woody/Gen4_R-Car_Trace32
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
main
Gen4_R-Car_Trace32/2_Trunk/perda1470x.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

12659 lines
888 KiB
Plaintext
Raw Permalink Blame History

; --------------------------------------------------------------------------------
; @Title: DA1470x On-Chip Peripherals
; @Props: Released
; @Author: JDU
; @Changelog: 2023-02-13 JDU
; @Manufacturer: DIALOG - Dialog Semiconductor
; @Doc: SVD generated (SVD2PER 1.8.6), based on: da1470x.svd (Ver. 1.2)
; @Core: Cortex-M33F, Cortex-M0+
; @Chip: DA14701-CM33, DA14701-CM0+-SNC, DA14701-CM0+-CMAC,
; DA14705-CM33, DA14705-CM0+-SNC, DA14705-CM0+-CMAC,
; DA14706-CM33, DA14706-CM0+-SNC, DA14706-CM0+-CMAC,
; DA14708-CM33, DA14708-CM0+-SNC, DA14708-CM0+-CMAC
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perda1470x.per 15769 2023-02-17 15:01:03Z kwisniewski $
sif (CORENAME()=="CORTEXM33F")
tree.close "Core Registers (Cortex-M33F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
textline " "
bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline " "
bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
textline " "
bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
textline " "
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline " "
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline " "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
textline " "
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
textline " "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
textline " "
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline " "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
textline " "
bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
textline " "
bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
textline " "
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
textline " "
bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
textline " "
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
textline " "
eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
textline " "
eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline " "
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
textline " "
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
textline " "
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
textline " "
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline " "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
textline " "
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline " "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline " "
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline " "
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline " "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline " "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline " "
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline " "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline " "
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline " "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline " "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline " "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline " "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline " "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline " "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline " "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline " "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline " "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline " "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline " "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline " "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline " "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld " "
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline " "
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline " "
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline " "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline " "
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
elif (CORENAME()=="CORTEXM0+")
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
autoindent.on center tree
tree "AES_HASH"
base ad:0x30040000
group.long 0x18++0x03
line.long 0x00 "CRYPTO_CLRIRQ_REG,Crypto Clear interrupt request"
bitfld.long 0x00 0. "CRYPTO_CLRIRQ,Write 1 to clear a pending interrupt request" "0,1"
group.long 0x00++0x03
line.long 0x00 "CRYPTO_CTRL_REG,Crypto Control register"
bitfld.long 0x00 17. "CRYPTO_AES_KEXP,It forces (active high) the execution of the key expansion process with the starting of the AES encryption/decryption process" "0,1"
bitfld.long 0x00 16. "CRYPTO_MORE_IN," "0,1"
newline
bitfld.long 0x00 10.--15. "CRYPTO_HASH_OUT_LEN,The number of bytes minus one of the hash result which will be saved at the memory by the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 9. "CRYPTO_HASH_SEL,Selects the type of the algorithm" "0: The encryption algorithm (AES),1: A hash algorithm"
newline
bitfld.long 0x00 8. "CRYPTO_IRQ_EN,Interrupt Request Enable" "0: The interrupt generation ability is disabled,1: The interrupt generation ability is enabled"
bitfld.long 0x00 7. "CRYPTO_ENCDEC,Encryption/Decryption" "0: Decryption,1: Encryption"
newline
bitfld.long 0x00 5.--6. "CRYPTO_AES_KEY_SZ,The size of AES Key" "0: 128 bits AES Key,1: 192 bits AES Key,2: 256 bits AES Key,3: 256 bits AES Key"
bitfld.long 0x00 4. "CRYPTO_OUT_MD,Output Mode" "0: Write back to memory all the resulting data,1: Write back to memory only the final block of.."
newline
bitfld.long 0x00 2.--3. "CRYPTO_ALG_MD,It defines the mode of operation of the AES algorithm when the controller is configured for an encryption/decryption processing (CRYPTO_HASH_SEL = 0)" "0: HASH algorithms that are based on 32 bits,1: HASH algorithms that are based on 64 bits,2: Reserved,3: Reserved See also the CRYPTO_ALG field"
bitfld.long 0x00 0.--1. "CRYPTO_ALG,Algorithm selection" "0: SHA-384,1: SHA-512,2: SHA-512/224,3: SHA-512/256"
group.long 0x10++0x03
line.long 0x00 "CRYPTO_DEST_ADDR_REG,Crypto DMA destination memory"
hexmask.long 0x00 0.--31. 1. "CRYPTO_DEST_ADDR,Destination address at where the result of the processing is stored"
group.long 0x08++0x03
line.long 0x00 "CRYPTO_FETCH_ADDR_REG,Crypto DMA fetch register"
hexmask.long 0x00 0.--31. 1. "CRYPTO_FETCH_ADDR,The memory address from where will be retrieved the data that will be processed"
group.long 0x100++0x03
line.long 0x00 "CRYPTO_KEYS_START,Crypto First position of the AES keys storage memory"
hexmask.long 0x00 0.--31. 1. "CRYPTO_KEY_X,CRYPTO_KEY_(0-63) This is the AES keys storage memory"
group.long 0x0C++0x03
line.long 0x00 "CRYPTO_LEN_REG,Crypto Length of the input block in bytes"
hexmask.long.tbyte 0x00 0.--23. 1. "CRYPTO_LEN,It contains the number of bytes of input data"
group.long 0x1C++0x03
line.long 0x00 "CRYPTO_MREG0_REG,Crypto Mode depended register 0"
hexmask.long 0x00 0.--31. 1. "CRYPTO_MREG0,It contains information that are depended by the mode of operation when is used the AES algorithm: CBC - IV[31:0] CTR - CTRBLK[31:0]"
group.long 0x20++0x03
line.long 0x00 "CRYPTO_MREG1_REG,Crypto Mode depended register 1"
hexmask.long 0x00 0.--31. 1. "CRYPTO_MREG1,It contains information that are depended by the mode of operation when is used the AES algorithm: CBC - IV[63:32] CTR - CTRBLK[63:32] At any other mode the contents of this register has no meaning"
group.long 0x24++0x03
line.long 0x00 "CRYPTO_MREG2_REG,Crypto Mode depended register 2"
hexmask.long 0x00 0.--31. 1. "CRYPTO_MREG2,It contains information that are depended by the mode of operation when is used the AES algorithm: CBC - IV[95:64] CTR - CTRBLK[95:64] At any other mode the contents of this register has no meaning"
group.long 0x28++0x03
line.long 0x00 "CRYPTO_MREG3_REG,Crypto Mode depended register 3"
hexmask.long 0x00 0.--31. 1. "CRYPTO_MREG3,It contains information that are depended by the mode of operation when is used the AES algorithm: CBC - IV[127:96] CTR - CTRBLK[127:96] At any other mode the contents of this register has no meaning"
group.long 0x04++0x03
line.long 0x00 "CRYPTO_START_REG,Crypto Start calculation"
bitfld.long 0x00 0. "CRYPTO_START,Write 1 to initiate the processing of the input data" "0,1"
group.long 0x14++0x03
line.long 0x00 "CRYPTO_STATUS_REG,Crypto Status register"
rbitfld.long 0x00 2. "CRYPTO_IRQ_ST,The status of the interrupt request line of the CRYPTO block" "0: There is no active interrupt request,1: An interrupt request is pending"
rbitfld.long 0x00 1. "CRYPTO_WAIT_FOR_IN,Indicates the situation where the engine waits for more input data" "0: The crypto is not waiting for more input data,1: The crypto waits for more input data"
newline
rbitfld.long 0x00 0. "CRYPTO_INACTIVE," "0,1"
tree.end
tree "ANAMISC_BIF"
base ad:0x50050600
group.long 0x1C++0x03
line.long 0x00 "CLK_CAL_IRQ_REG,Select clock for oscillator calibration"
bitfld.long 0x00 2. "CLK_CAL_IRQ_CLR,Clear the IRQ" "0: No effect,1: Clear the IRQ"
rbitfld.long 0x00 1. "CLK_CAL_IRQ_STATUS,Shows the IRQ bit status" "0,1"
bitfld.long 0x00 0. "CLK_CAL_IRQ_EN,Enable clk calibration IRQ" "0,1"
group.long 0x14++0x03
line.long 0x00 "CLK_REF_CNT_REG,Count value for oscillator calibration"
hexmask.long.word 0x00 0.--15. 1. "REF_CNT_VAL,Indicates the calibration time with a decrement counter to 1"
group.long 0x10++0x03
line.long 0x00 "CLK_REF_SEL_REG,Select clock for oscillator calibration"
bitfld.long 0x00 5.--7. "CAL_CLK_SEL,Select calibration clock input to be used in calibration" "0: DIVN clock,1: RCLP,2: RCHS,3: XTAL32K,4: RCOSC 0x5 0x6 and,?,?,7: Reserved"
bitfld.long 0x00 4. "EXT_CNT_EN_SEL," "0,1"
bitfld.long 0x00 3. "REF_CAL_START,Writing a '1' starts a calibration" "0,1"
bitfld.long 0x00 0.--2. "REF_CLK_SEL,Select reference clock input for calibration" "0: RCLP,1: RCHS,2: XTAL32K,3: RCX,4: RCOSC,5: DIVN clock,?..."
group.long 0x18++0x03
line.long 0x00 "CLK_REF_VAL_REG,DIVN reference cycles lower 16 bits"
hexmask.long 0x00 0.--31. 1. "XTAL_CNT_VAL,Returns the number of DIVN clock cycles counted during the calibration time defined with REF_CNT_VAL"
tree.end
tree "CACHE"
base ad:0x100C0000
group.long 0x20++0x03
line.long 0x00 "CACHE_CTRL2_REG,Cache control register 2 (only Word (32-bits) access supported)"
rbitfld.long 0x00 21. "CACHE_READY,Cache Controller RO status bit" "0: Default,1: Set to '1' when"
newline
rbitfld.long 0x00 20. "CACHE_RAM_INIT,Cache Controller RO status bit" "0: Default,1: Set to '1' when"
newline
bitfld.long 0x00 19. "CACHE_FLUSHED," "0,1"
newline
bitfld.long 0x00 18. "CACHE_FLUSH_DISABLE," "0,1"
newline
bitfld.long 0x00 16.--17. "CACHE_USE_FULL_DB_RANGE," "?,1: SYS_CTRL_REG[CACHERAM_MUX] must be set to '0',2: For all 3 settings max,3: Reserved"
newline
bitfld.long 0x00 15. "CACHE_MHCLKEN_DISABLE," "0,1"
newline
bitfld.long 0x00 14. "CACHE_CWF_DISABLE," "0,1"
newline
bitfld.long 0x00 13. "CACHE_CGEN," "0,1"
newline
bitfld.long 0x00 12. "CACHE_WEN," "0,1"
newline
abitfld.long 0x00 0.--11. "CACHE_LEN,Length of OQSPI FLASH cacheable memory" "0x001=1: The max,0x002=2: The first block (CACHE_LEN=1) includes.."
group.long 0x40++0x03
line.long 0x00 "CACHE_FLASH_REG,Cache QSPI Flash program size and base address register (only Word (32-bits) access supported)"
hexmask.long.word 0x00 16.--31. 1. "FLASH_REGION_BASE,These bits corresponds with the Flash region base address bits [31:16]"
newline
hexmask.long.word 0x00 4.--15. 1. "FLASH_REGION_OFFSET,Flash region offset address (in words)"
newline
bitfld.long 0x00 0.--3. "FLASH_REGION_SIZE,Flash region size" "0: 0.25 MBytes,1: The updated value takes effect only after a,2: See for the max,3: 2 MBytes,4: 4 MBytes,5: 8 MBytes,6: 16 MBytes,7: 32 MBytes,8: 64 MBytes,9: 128 MBytes,?..."
group.long 0x30++0x03
line.long 0x00 "CACHE_MRM_CTRL_REG,Cache MRM (Miss Rate Monitor) CONTROL register (only Word (32-bits) access supported)"
bitfld.long 0x00 4. "MRM_IRQ_HITS_THRES_STATUS," "0,1"
newline
bitfld.long 0x00 3. "MRM_IRQ_MISSES_THRES_STATUS," "0,1"
newline
bitfld.long 0x00 2. "MRM_IRQ_TINT_STATUS," "0,1"
newline
bitfld.long 0x00 1. "MRM_IRQ_MASK," "0,1"
newline
bitfld.long 0x00 0. "MRM_START," "0,1"
group.long 0x48++0x03
line.long 0x00 "CACHE_MRM_HITS1WS_REG,Cache MRM (Miss Rate Monitor) HITS with 1 Wait State register (only Word (32-bits) access supported)"
hexmask.long 0x00 0.--31. 1. "MRM_HITS1WS,Contains the amount of cache hits"
group.long 0x28++0x03
line.long 0x00 "CACHE_MRM_HITS_REG,Cache MRM (Miss Rate Monitor) HITS register (only Word (32-bits) access supported)"
hexmask.long 0x00 0.--31. 1. "MRM_HITS,Contains the amount of cache hits"
group.long 0x3C++0x03
line.long 0x00 "CACHE_MRM_HITS_THRES_REG,Cache MRM (Miss Rate Monitor) HITS THRESHOLD register (only Word (32-bits) access supported)"
hexmask.long 0x00 0.--31. 1. "MRM_HITS_THRES,Defines the hits threshold to trigger the interrupt generation"
group.long 0x2C++0x03
line.long 0x00 "CACHE_MRM_MISSES_REG,Cache MRM (Miss Rate Monitor) MISSES register (only Word (32-bits) access supported)"
hexmask.long 0x00 0.--31. 1. "MRM_MISSES,Contains the amount of cache misses"
group.long 0x38++0x03
line.long 0x00 "CACHE_MRM_MISSES_THRES_REG,Cache MRM (Miss Rate Monitor) THRESHOLD register (only Word (32-bits) access supported)"
hexmask.long 0x00 0.--31. 1. "MRM_MISSES_THRES,Defines the misses threshold to trigger the interrupt generation"
group.long 0x34++0x03
line.long 0x00 "CACHE_MRM_TINT_REG,Cache MRM (Miss Rate Monitor) TIME INTERVAL register (only Word (32-bits) access supported)"
hexmask.long.tbyte 0x00 0.--18. 1. "MRM_TINT,Defines the time interval for the monitoring in 32 MHz clock cycles"
group.long 0x50++0x03
line.long 0x00 "SWD_RESET_REG,SWD HW reset control register (only Word (32-bits) access supported)"
bitfld.long 0x00 0. "SWD_HW_RESET_REQ," "0,1"
tree.end
tree "CHARGER"
base ad:0x51000600
group.long 0x28++0x03
line.long 0x00 "CHARGER_CC_CHARGE_TIMER_REG,Maximum CC-charge time limit register"
hexmask.long.word 0x00 16.--30. 1. "CC_CHARGE_TIMER,Returns the current value of the CC-Charge timeout counter running at a 1Hz clock"
newline
hexmask.long.word 0x00 0.--14. 1. "MAX_CC_CHARGE_TIME,This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the CC (Constant Current) charging stage"
group.long 0x00++0x03
line.long 0x00 "CHARGER_CTRL_REG,Charger main control register"
bitfld.long 0x00 28. "EOC_TRIGGER," "0,1"
newline
rbitfld.long 0x00 22.--27. "EOC_INTERVAL_CHECK_TIMER,The specific bit-field determines the current state of the timer used to periodically check the End-of-Charge signal as soon as the Charger's FSM is either in CC_CHARGE or CV_CHARGE state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16.--21. "EOC_INTERVAL_CHECK_THRES,This bit-field determines the periodic interval of checking the End-of-Charge signal when the Charger's FSM is either in CC_CHARGE or in CV_CHARGE state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15. "REPLENISH_MODE,When this bit-field is set and the Charger's FSM is in the BYPASSED state (thus in Bypass mode) the internal multiplexer inside the digital part of the charger selects the Replenish instead of the Pre-charge setting to be driven to the.." "0,1"
newline
bitfld.long 0x00 14. "PRE_CHARGE_MODE,When set this bit-field enables a signal of the same name with the bit-field driven from the Charger's digital part towards the analogue circuitry in order to determine the current in Pre-Charge mode" "0,1"
newline
bitfld.long 0x00 13. "CHARGE_LOOP_HOLD,When set this bit-field disables charging provided that the Charger's FSM has switched to the BYPASSED state" "0,1"
newline
bitfld.long 0x00 12. "JEITA_SUPPORT_DISABLED," "0,1"
newline
bitfld.long 0x00 10.--11. "TBAT_MONITOR_MODE,Battery temperature pack monitoring modes according to the following encoding" "0: Battery temperature state checked and updated,1: Battery temperature state checked periodically,2: Battery temperature state checked periodically,3: When selected it freezes the Battery.."
newline
bitfld.long 0x00 9. "CHARGE_TIMERS_HALT_ENABLE," "0,1"
newline
bitfld.long 0x00 8. "STOP_CHARGE_TIMERS," "0,1"
newline
bitfld.long 0x00 7. "NTC_LOW_DISABLE," "0,1"
newline
bitfld.long 0x00 6. "TBAT_PROT_ENABLE," "0,1"
newline
bitfld.long 0x00 5. "TDIE_ERROR_RESUME," "0,1"
newline
bitfld.long 0x00 4. "TDIE_PROT_ENABLE," "0,1"
newline
bitfld.long 0x00 3. "CHARGER_RESUME," "0,1"
newline
bitfld.long 0x00 2. "CHARGER_BYPASS," "0,1"
newline
bitfld.long 0x00 1. "CHARGE_START," "0,1"
newline
bitfld.long 0x00 0. "CHARGER_ENABLE," "0,1"
group.long 0x10++0x03
line.long 0x00 "CHARGER_CURRENT_PARAM_REG,Charger current settings register"
bitfld.long 0x00 15. "I_EOC_DOUBLE_RANGE,When set the specific bit-field enables an increase of the (%) range of End-of-Charge current setting" "0,1"
newline
bitfld.long 0x00 12.--14. "I_END_OF_CHARGE,End-of-Charge current setting ranging from 6%( 000 ) to 20% ( 111 ) of the charge current setting with a step size of 2% as follows (when I_EOC_DOUBLE_RANGE = 0)" "0: 12%,1: 16%,2: 20%,3: 24%,4: 28%,5: 32%,6: 36%,7: 40%"
newline
bitfld.long 0x00 6.--11. "I_PRECHARGE,This bit-field determines the Pre-Charge current in mA ranging from 0.5 to 72mA according to the following encoding" "0: 0.5 mA,1: 1 mA,2: 1.5mA,3: 2 mA,4: 2.5mA,5: 3 mA,6: 3.5mA,7: 4 mA,8: 4.5mA,9: 5 mA,10: 5.5mA,11: 6 mA,12: 6.5mA,13: 7 mA,14: 7.5mA,15: 8 mA,16: 9 mA,17: 10 mA,18: 11 mA,19: 12 mA,20: 13 mA,21: 14 mA,22: 15 mA,23: 16 mA,24: 17 mA,25: 18 mA,26: 19 mA,27: 20 mA,28: 21 mA,29: 22 mA,30: 23 mA,31: 24 mA,32: 27 mA,33: 30 mA,34: 33 mA,35: 36 mA,36: 39 mA,37: 42 mA,38: 45 mA,39: 48 mA,40: 51 mA,41: 54 mA,42: 57 mA,43: 60 mA,44: 63 mA,45: 66 mA,46: 69 mA,47: 72 mA,48: 72 mA,49: 72 mA,50: 72 mA,51: 72 mA,52: 72 mA,53: 72 mA,54: 72 mA,55: 72 mA,56: 72 mA,57: 72 mA,58: 72 mA,59: 72 mA,60: 72 mA,61: 72 mA,62: 72 mA,63: 72 mA"
newline
bitfld.long 0x00 0.--5. "I_CHARGE,This bit-field determines the charge current range in mA" "0: 5 mA,1: 10 mA,2: 15 mA,3: 20 mA,4: 25 mA,5: 30 mA,6: 35 mA,7: 40 mA,8: 45 mA,9: 50 mA,10: 55 mA,11: 60 mA,12: 65 mA,13: 70 mA,14: 75 mA,15: 80 mA,16: 90 mA,17: 100 mA,18: 110 mA,19: 120 mA,20: 130 mA,21: 140 mA,22: 150 mA,23: 160 mA,24: 170 mA,25: 180 mA,26: 190 mA,27: 200 mA,28: 210 mA,29: 220 mA,30: 230 mA,31: 240 mA,32: 270 mA,33: 300 mA,34: 330 mA,35: 360 mA,36: 390 mA,37: 420 mA,38: 450 mA,39: 480 mA,40: 510 mA,41: 540 mA,42: 570 mA,43: 600 mA,44: 630 mA,45: 660 mA,46: 690 mA,47: 720 mA,48: 720 mA,49: 720 mA,50: 720 mA,51: 720 mA,52: 720 mA,53: 720 mA,54: 720 mA,55: 720 mA,56: 720 mA,57: 720 mA,58: 720 mA,59: 720 mA,60: 720 mA,61: 720 mA,62: 720 mA,63: 720 mA"
group.long 0x18++0x03
line.long 0x00 "CHARGER_CURRENT_STATUS_REG,Charger current status register"
rbitfld.long 0x00 6.--11. "I_PRECHARGE_SET,This bit-field returns the applied Pre-Charge current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 0.--5. "I_CHARGE_SET,This bit-field returns the applied CC current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2C++0x03
line.long 0x00 "CHARGER_CV_CHARGE_TIMER_REG,Maximum CV-charge time limit register"
hexmask.long.word 0x00 16.--30. 1. "CV_CHARGE_TIMER,Returns the current value of the CV-Charge timeout counter running at a 1Hz clock"
newline
hexmask.long.word 0x00 0.--14. 1. "MAX_CV_CHARGE_TIME,This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the CV (Constant Voltage) charging stage"
group.long 0x7C++0x03
line.long 0x00 "CHARGER_ERROR_IRQ_CLR_REG,Interrupt clear register of Charger Error IRQs"
bitfld.long 0x00 6. "TBAT_ERROR_IRQ_CLR,Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 5. "TDIE_ERROR_IRQ_CLR,Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 4. "VBAT_OVP_ERROR_IRQ_CLR,Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 3. "TOTAL_CHARGE_TIMEOUT_IRQ_CLR,Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 2. "CV_CHARGE_TIMEOUT_IRQ_CLR,Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 1. "CC_CHARGE_TIMEOUT_IRQ_CLR,Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 0. "PRECHARGE_TIMEOUT_IRQ_CLR,Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect" "0,1"
group.long 0x6C++0x03
line.long 0x00 "CHARGER_ERROR_IRQ_MASK_REG,Mask register of Charger Error IRQs"
bitfld.long 0x00 6. "TBAT_ERROR_IRQ_EN,When set it enables the generation of Battery temperature IRQs.The IRQ is generated as soon as the JEITA FSM detects that the battery temperature is either in the Hot or in the Cold temperature region by sampling the respective.." "0,1"
newline
bitfld.long 0x00 5. "TDIE_ERROR_IRQ_EN,When set it enables the generation of Die temperature error IRQs" "0,1"
newline
bitfld.long 0x00 4. "VBAT_OVP_ERROR_IRQ_EN,When set it enables the generation of VBAT_OVP IRQs" "0,1"
newline
bitfld.long 0x00 3. "TOTAL_CHARGE_TIMEOUT_IRQ_EN,When set it enables the total charge timeout IRQs" "0,1"
newline
bitfld.long 0x00 2. "CV_CHARGE_TIMEOUT_IRQ_EN,When set it enables the CV charge timeout IRQs" "0,1"
newline
bitfld.long 0x00 1. "CC_CHARGE_TIMEOUT_IRQ_EN,When set it enables the CC charge timeout IRQs" "0,1"
newline
bitfld.long 0x00 0. "PRECHARGE_TIMEOUT_IRQ_EN,When set it enables the Pre-Charge timeout IRQs" "0,1"
group.long 0x74++0x03
line.long 0x00 "CHARGER_ERROR_IRQ_STATUS_REG,Status register of Charger Error IRQs"
rbitfld.long 0x00 6. "TBAT_ERROR_IRQ," "0,1"
newline
rbitfld.long 0x00 5. "TDIE_ERROR_IRQ," "0,1"
newline
rbitfld.long 0x00 4. "VBAT_OVP_ERROR_IRQ," "0,1"
newline
rbitfld.long 0x00 3. "TOTAL_CHARGE_TIMEOUT_IRQ," "0,1"
newline
rbitfld.long 0x00 2. "CV_CHARGE_TIMEOUT_IRQ," "0,1"
newline
rbitfld.long 0x00 1. "CC_CHARGE_TIMEOUT_IRQ," "0,1"
newline
rbitfld.long 0x00 0. "PRECHARGE_TIMEOUT_IRQ," "0,1"
group.long 0x48++0x03
line.long 0x00 "CHARGER_JEITA_CURRENT2_REG,JEITA-compliant current settings register for Cooler and Warmer zones"
bitfld.long 0x00 18.--23. "I_PRECHARGE_TWARMER,Pre-charge current settings bit-field for the WARMER battery temperature pack zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "I_PRECHARGE_TCOOLER,Pre-charge current settings bit-field for the COOLER battery temperature pack zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "I_CHARGE_TWARMER,Charge current settings bit-field for the WARMER battery temperature pack zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "I_CHARGE_TCOOLER,Charge current settings bit-field for the COOLER battery temperature pack zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x44++0x03
line.long 0x00 "CHARGER_JEITA_CURRENT_REG,JEITA-compliant current settings register"
bitfld.long 0x00 18.--23. "I_PRECHARGE_TWARM,Pre-Charge current setting for the Warm battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "I_PRECHARGE_TCOOL,Pre-Charge current setting for the Cool battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "I_CHARGE_TWARM,Charge current setting for the Warm battery temperature pack zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "I_CHARGE_TCOOL,Charge current setting for the COOL battery temperature level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x34++0x03
line.long 0x00 "CHARGER_JEITA_V_CHARGE_REG,JEITA-compliant Charge voltage settings register"
bitfld.long 0x00 18.--23. "V_CHARGE_TWARMER,Charge voltage setting for the Warmer battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "V_CHARGE_TCOOLER,Charge voltage setting for the Cooler battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "V_CHARGE_TWARM,Charge voltage setting for the Warm battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "V_CHARGE_TCOOL,Charge voltage setting for the Cool battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x40++0x03
line.long 0x00 "CHARGER_JEITA_V_OVP_REG,JEITA-compliant OVP settings register"
bitfld.long 0x00 18.--23. "V_OVP_TWARMER,VBAT Over-voltage Protection (OVP) setting for the Warmer battery temperature zone.Regarding the range of values of this bit-field see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "V_OVP_TCOOLER,VBAT Over-voltage Protection (OVP) setting for the Cooler battery temperature zone.Regarding the range of values of this bit-field see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "V_OVP_TWARM,VBAT Over-voltage Protection (OVP) setting for the Warm battery temperature zone.Regarding the range of values of this bit-field see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "V_OVP_TCOOL,VBAT Over-voltage Protection (OVP) setting for the Cool battery temperature zone.Regarding the range of values of this bit-field see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "CHARGER_JEITA_V_PRECHARGE_REG,JEITA-compliant Pre-Charge voltage settings register"
bitfld.long 0x00 18.--23. "V_PRECHARGE_TWARMER,Pre-Charge voltage setting for the Warmer battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "V_PRECHARGE_TCOOLER,Pre-Charge voltage setting for the Cooler battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "V_PRECHARGE_TWARM,Pre-Charge voltage setting for the Warm battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "V_PRECHARGE_TCOOL,Pre-Charge current setting for the Cool battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3C++0x03
line.long 0x00 "CHARGER_JEITA_V_REPLENISH_REG,JEITA-compliant Replenish settings register"
bitfld.long 0x00 18.--23. "V_REPLENISH_TWARMER,Replenish voltage setting for the Warmer battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "V_REPLENISH_TCOOLER,Replenish voltage setting for the Cooler battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "V_REPLENISH_TWARM,Replenish voltage setting for the Warm battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "V_REPLENISH_TCOOL,Replenish voltage setting for the Cool battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "CHARGER_LOCK_REG,Charger HW lock register"
bitfld.long 0x00 15. "CHARGER_SWLOCK_EN," "0,1"
newline
bitfld.long 0x00 14. "JEITA_I_CHARGE2_LOCK," "0,1"
newline
bitfld.long 0x00 13. "JEITA_I_CHARGE_LOCK," "0,1"
newline
bitfld.long 0x00 12. "JEITA_V_OVP_LOCK," "0,1"
newline
bitfld.long 0x00 11. "JEITA_V_PRECHARGE_LOCK," "0,1"
newline
bitfld.long 0x00 10. "JEITA_V_CHARGE_LOCK," "0,1"
newline
bitfld.long 0x00 9. "TOTAL_CHARGE_TIMEOUT_LOCK," "0,1"
newline
bitfld.long 0x00 8. "CV_CHARGE_TIMEOUT_LOCK," "0,1"
newline
bitfld.long 0x00 7. "CC_CHARGE_TIMEOUT_LOCK," "0,1"
newline
bitfld.long 0x00 6. "PRECHARGE_TIMEOUT_LOCK," "0,1"
newline
bitfld.long 0x00 5. "TEMPSET2_PARAM_LOCK," "0,1"
newline
bitfld.long 0x00 4. "TEMPSET_PARAM_LOCK," "0,1"
newline
bitfld.long 0x00 3. "CURRENT_PARAM_LOCK," "0,1"
newline
bitfld.long 0x00 2. "VOLTAGE_PARAM_LOCK," "0,1"
newline
bitfld.long 0x00 1. "CHARGER_TEST_CTRL_LOCK," "0,1"
newline
bitfld.long 0x00 0. "CHARGER_CTRL_LOCK," "0,1"
group.long 0x24++0x03
line.long 0x00 "CHARGER_PRE_CHARGE_TIMER_REG,Maximum pre-charge time limit register"
hexmask.long.word 0x00 16.--30. 1. "PRE_CHARGE_TIMER,Returns the current value of the Pre-Charge timeout counter running at a 1Hz clock"
newline
hexmask.long.word 0x00 0.--14. 1. "MAX_PRE_CHARGE_TIME,This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the Pre-Charge stage"
group.long 0x64++0x03
line.long 0x00 "CHARGER_PWR_UP_TIMER_REG,Charger power-up settling timer register"
rbitfld.long 0x00 16.--20. "CHARGER_PWR_UP_TIMER,Returns the current value of the charger's power-up timer running with the 1Khz clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "CHARGER_PWR_UP_SETTLING,This bit-field determines the charger's power-up (settling) time required for the analogue circuitry of the charger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x78++0x03
line.long 0x00 "CHARGER_STATE_IRQ_CLR_REG,Interrupt clear register of Charger FSM IRQs"
bitfld.long 0x00 11. "CV_TO_PRECHARGE_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 10. "CC_TO_PRECHARGE_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 9. "CV_TO_CC_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 8. "TBAT_STATUS_UPDATE_IRQ_CLR,Writing a 1 will reset the Battery temperature status update IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 7. "TBAT_PROT_TO_PRECHARGE_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 6. "TDIE_PROT_TO_PRECHARGE_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 5. "EOC_TO_PRECHARGE_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 4. "CV_TO_EOC_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 3. "CC_TO_EOC_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 2. "CC_TO_CV_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 1. "PRECHARGE_TO_CC_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 0. "DISABLED_TO_PRECHARGE_IRQ_CLR,Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect" "0,1"
group.long 0x68++0x03
line.long 0x00 "CHARGER_STATE_IRQ_MASK_REG,Mask register of Charger FSM IRQs"
bitfld.long 0x00 11. "CV_TO_PRECHARGE_IRQ_EN,When set this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to PRE_CHARGE state" "0,1"
newline
bitfld.long 0x00 10. "CC_TO_PRECHARGE_IRQ_EN,When set this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to PRE_CHARGE state" "0,1"
newline
bitfld.long 0x00 9. "CV_TO_CC_IRQ_EN,When set this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to CC_CHARGE state" "0,1"
newline
bitfld.long 0x00 8. "TBAT_STATUS_UPDATE_IRQ_EN,When set this bit-field enables the generation of the Charger's state IRQ as soon as the battery temperature status is refreched by the Charger's Battery temperature monitor (JEITA) FSM" "0,1"
newline
bitfld.long 0x00 7. "TBAT_PROT_TO_PRECHARGE_IRQ_EN,When set this bit-field enables the Charger's state IRQ generation as soon as the Charger's FSM switches from the Battery temperature protection state (TBAT_PROT) to PRE_CHARGE resuming charging" "0,1"
newline
bitfld.long 0x00 6. "TDIE_PROT_TO_PRECHARGE_IRQ_EN,When set this bit-field enables the Charger's state IRQ generation as soon as the Charger's FSM switches from the Die temperature protection state (TDIE_PROT) to PRE_CHARGE resuming charging" "0,1"
newline
bitfld.long 0x00 5. "EOC_TO_PRECHARGE_IRQ_EN,When set this bit-field enables the Charger's State IRQ generation as soon as the Charger's FSM switches from END_OF_CHARGE again to PRE_CHARGE state" "0,1"
newline
bitfld.long 0x00 4. "CV_TO_EOC_IRQ_EN,When set this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to END_OF_CHARGE state" "0,1"
newline
bitfld.long 0x00 3. "CC_TO_EOC_IRQ_EN,When set this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to END_OF_CHARGE state" "0,1"
newline
bitfld.long 0x00 2. "CC_TO_CV_IRQ_EN,When set this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to CV_CHARGE state" "0,1"
newline
bitfld.long 0x00 1. "PRECHARGE_TO_CC_IRQ_EN,When set this bit-field enables the IRQ generation as soon as the Charger's FSM switches from PRE_CHARGE to CC_CHARGE state" "0,1"
newline
bitfld.long 0x00 0. "DISABLED_TO_PRECHARGE_IRQ_EN,When set this bit-field enables the IRQ generation as soon as the Charger's FSM switches from DISABLED to PRE_CHARGE state" "0,1"
group.long 0x70++0x03
line.long 0x00 "CHARGER_STATE_IRQ_STATUS_REG,Status register of Charger FSM IRQs"
rbitfld.long 0x00 11. "CV_TO_PRECHARGE_IRQ," "0,1"
newline
rbitfld.long 0x00 10. "CC_TO_PRECHARGE_IRQ," "0,1"
newline
rbitfld.long 0x00 9. "CV_TO_CC_IRQ," "0,1"
newline
rbitfld.long 0x00 8. "TBAT_STATUS_UPDATE_IRQ," "0,1"
newline
rbitfld.long 0x00 7. "TBAT_PROT_TO_PRECHARGE_IRQ," "0,1"
newline
rbitfld.long 0x00 6. "TDIE_PROT_TO_PRECHARGE_IRQ," "0,1"
newline
rbitfld.long 0x00 5. "EOC_TO_PRECHARGE_IRQ," "0,1"
newline
rbitfld.long 0x00 4. "CV_TO_EOC_IRQ," "0,1"
newline
rbitfld.long 0x00 3. "CC_TO_EOC_IRQ," "0,1"
newline
rbitfld.long 0x00 2. "CC_TO_CV_IRQ," "0,1"
newline
rbitfld.long 0x00 1. "PRECHARGE_TO_CC_IRQ," "0,1"
newline
rbitfld.long 0x00 0. "DISABLED_TO_PRECHARGE_IRQ," "0,1"
group.long 0x08++0x03
line.long 0x00 "CHARGER_STATUS_REG,Charger main status register"
rbitfld.long 0x00 26.--28. "OVP_EVENTS_DEBOUNCE_CNT,The specific bit-field returns the consecutive number of times Vbat has exceeded the programmed Over-Voltage Protection (OVP) level" "?,1: By default as soon as the counter reaches 4 the,2: See also the OVP_INTERVAL_CHECK_TIMER,?..."
newline
rbitfld.long 0x00 23.--25. "EOC_EVENTS_DEBOUNCE_CNT,The specific bit-field returns the number of times the End-of-Charge signal has been consecutively found to be high" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 20.--22. "TDIE_ERROR_DEBOUNCE_CNT,The specific bit-field returns the consecutive number of times the Die temperature is seen either above (for the case of an error) or below (for the case of recovering from an error) the set Die temperature level.This is.." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 16.--19. "CHARGER_JEITA_STATE,Returns the state of the Charger's JEITA FSM" "0: CHECK_IDLE,1: CHECK_THOT,2: CHECK_TCOLD,3: CHECK_TWARMER,4: CHECK_TWARM,5: CHECK_TCOOLER,6: CHECK_TCOOL,7: CHECK_TNORMAL,8: UPDATE_TBAT The FSM initially is,?..."
newline
rbitfld.long 0x00 12.--15. "CHARGER_STATE,Indicating the state of the Charger's main FSM based on the following encoding" "0: POWER_UP (Charger's power-up not yet set),1: INIT (Charger is being power-up FSM waiting for,2: DISABLED (Charger powered-up but charging not,3: PRE_CHARGE (Pre-Charge state),4: CC_CHARGE (Constant Current state),5: CV_CHARGE (Constant Voltage state),6: END_OF_CHARGE (End-of-Charge state),7: TDIE_PROT (Die temperature protection state,8: TBAT_PROT (Battery temperature protection state,9: BYPASSED (Bypassed state visited only when the,10: ERROR (Error state visited when a charge,?..."
newline
rbitfld.long 0x00 9.--11. "TBAT_STATUS,Battery pack temperature status according to the following encoding" "0: Battery temperature in COLD zone (default),1: Battery temperature in COOLER zone (above COLD),2: Battery temperature in COOL zone (above COOLER),3: Battery temperature in NORMAL zone (above COOL,4: Battery temperature in WARM zone (above NORMAL),5: Battery temperature in WARMER zone (above WARM,6: Battery temperature in HOT zone It is noted..,?..."
newline
rbitfld.long 0x00 8. "MAIN_TBAT_COMP_OUT,Returns the status of the main battery temperature comparator" "0: Battery temperature pack is found to be below,1: Battery temperature pack is found to be above"
newline
rbitfld.long 0x00 7. "TBAT_HOT_COMP_OUT,Returns the status of the battery temperature comparator dedicated to the Hot temperature zone" "0: Battery temperature pack is found to be below,1: Battery temperature pack is found to be in the"
newline
rbitfld.long 0x00 6. "TDIE_COMP_OUT," "0,1"
newline
rbitfld.long 0x00 5. "VBAT_OVP_COMP_OUT," "0,1"
newline
rbitfld.long 0x00 4. "MAIN_VBAT_COMP_OUT,This bit-field reflects the status of the main Vbat comparator residing in the analogue circuitry of the Charger" "0: Vbat has dropped below the set Replenish level,1: Vbat is still greater or equal to the set"
newline
rbitfld.long 0x00 3. "END_OF_CHARGE," "0,1"
newline
rbitfld.long 0x00 2. "CHARGER_CV_MODE," "0,1"
newline
rbitfld.long 0x00 1. "CHARGER_CC_MODE," "0,1"
newline
rbitfld.long 0x00 0. "CHARGER_IS_POWERED_UP," "0,1"
group.long 0x84++0x03
line.long 0x00 "CHARGER_SWLOCK_REG,Charger SW lock register"
rbitfld.long 0x00 1.--2. "SWLOCK_FSM_STATE,Returns the state of the FSM detecting the sequence of writes that either enable (lock) or disable (un-lock) the protection to the Charger registers/register bit-fields protected also through CHARGER_LOCK_REG (bits [14:0])" "0,1,2,3"
newline
rbitfld.long 0x00 0. "SWLOCK_STATUS," "0,1"
group.long 0x5C++0x03
line.long 0x00 "CHARGER_TBAT_COMP_TIMER_REG,Battery temperature (main) comparator timer register"
hexmask.long.word 0x00 16.--25. 1. "TBAT_COMP_TIMER,Returns the main battery temperature comparator's timer used for the latching of the comparator's output"
newline
hexmask.long.word 0x00 0.--9. 1. "TBAT_COMP_SETTLING,Settling time (specified in us) for the main battery temperature comparator checking for the COOL COLD and WARM levels"
group.long 0x58++0x03
line.long 0x00 "CHARGER_TBAT_MON_TIMER_REG,Battery temperature monitor interval timer register"
hexmask.long.word 0x00 16.--25. 1. "TBAT_MON_TIMER,This is the battery temperature monitoring timer counting with the Charger's 1KHz clock"
newline
hexmask.long.word 0x00 0.--9. 1. "TBAT_MON_INTERVAL,Timing interval (in ms) for the Battery temperature monitoring"
group.long 0x54++0x03
line.long 0x00 "CHARGER_TDIE_COMP_TIMER_REG,Die temperature comparator timer register"
hexmask.long.word 0x00 16.--25. 1. "TDIE_COMP_TIMER,Returns the current value of the timer used to determine when the Die temperature comparator's output must be sampled by the digital"
newline
hexmask.long.word 0x00 0.--9. 1. "TDIE_COMP_SETTLING,Settling time threshold (in us) for the Die temperature comparator"
group.long 0x20++0x03
line.long 0x00 "CHARGER_TEMPSET2_PARAM_REG,Charger battery temperature settings register (Cooler Warmer)"
bitfld.long 0x00 18.--23. "TBAT_WARMER,This bit-field determines the battery temperature threshold above which the WARMER zone is defined (between WARM and HOT)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "TBAT_WARM,This bit-field determines the battery temperature above which the charge current is reduced defining the Warm temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "TBAT_COOL,This bit-field determines the battery temperature below which the charge current is reduced defining the Cool temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "TBAT_COOLER,This bit-field determines the battery temperature below which the charge current is reduced defining the COOLER temperature zone (between COLD and COOL)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1C++0x03
line.long 0x00 "CHARGER_TEMPSET_PARAM_REG,Charger battery temperature settings register"
bitfld.long 0x00 12.--14. "TDIE_MAX,This bit-field determines the maximum Die temperature level limit ranging from 0C to 130C according to the following encoding" "0: 0 C (mainly,1: 50 C,2: 80 C,3: 90 C,4: 100 C,5: 110 C,6: 120 C,7: 130 C"
newline
bitfld.long 0x00 6.--11. "TBAT_HOT,This bit-field determines the battery temperature above which the charge current is zero defining the Hot battery temperature zone" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "TBAT_COLD,This bit-field determines the battery temperature below which the charge current is zero defining the Cold temperature zone" "0: -10C/0.741,1: -9C/0.733,2: -8C/0.724,3: -7C/0.715,4: -6C/0.706,5: -5C/0.695,6: -4C/0.686,7: -3C/0.677,8: -2C/0.668,9: -1C/0.657,10: 0C/0.647,11: 1C/0.638,12: 2C/0.628,13: 3C/0.618,14: 4C/0.608,15: 5C/0.596,16: 6C/0.587,17: 7C/0.578,18: 8C/0.567,19: 9C/0.557,20: 10C/0.546,21: 11C/0.536,22: 12C/0.527,23: 13C/0.517,24: 14C/0.506,25: 15C/0.495,26: 16C/0.486,27: 17C/0.477,28: 18C/0.467,29: 19C/0.457,30: 20C/0.446,31: 21C/0.438,32: 22C/0.429,33: 23C/0.419,34: 24C/0.410,35: 25C/0.400,36: 26C/0.392,37: 27C/0.383,38: 28C/0.375,39: 29C/0.366,40: 30C/0.356,41: 31C/0.349,42: 32C/0.341,43: 33C/0.333,44: 34C/0.325,45: 35C/0.316,46: 36C/0.309,47: 37C/0.302,48: 38C/0.295,49: 39C/0.287,50: 40C/0.280,51: 41C/0.273,52: 42C/0.267,53: 43C/0.260,54: 44C/0.253,55: 45C/0.247,56: 46C/0.241,57: 47C/0.235,58: 48C/0.229,59: 49C/0.223,60: 50C/0.217,61: 51C/0.212,62: 52C/0.207,63: 53C/0.202"
group.long 0x60++0x03
line.long 0x00 "CHARGER_THOT_COMP_TIMER_REG,Battery temperature comparator timer register for Hot zone"
hexmask.long.word 0x00 16.--25. 1. "THOT_COMP_TIMER,Returns the battery temperature comparator's timer dedicated for the Hot level"
newline
hexmask.long.word 0x00 0.--9. 1. "THOT_COMP_SETTLING,Charger's battery temperature comparator settling time (specified in us) specifically for the Hot temperature zone"
group.long 0x30++0x03
line.long 0x00 "CHARGER_TOTAL_CHARGE_TIMER_REG,Maximum total charge time limit register"
hexmask.long.word 0x00 16.--31. 1. "TOTAL_CHARGE_TIMER,Returns the current value of the overall charge timeout counter running at a 1Hz clock"
newline
hexmask.long.word 0x00 0.--15. 1. "MAX_TOTAL_CHARGE_TIME,This bit-field determines the maximum overall charging time allowed (measured in ticks of the 1Hz clock)"
group.long 0x4C++0x03
line.long 0x00 "CHARGER_VBAT_COMP_TIMER_REG,Main Vbat comparator timer register"
hexmask.long.word 0x00 16.--25. 1. "VBAT_COMP_TIMER,Returns the current value of the timer used to determine when the output of the Vbat comparator (checking Vbat vs Pre_Charge and Replenish levels) must be sampled by the digital"
newline
hexmask.long.word 0x00 0.--9. 1. "VBAT_COMP_SETTLING,Settling time threshold (in us) for the Vbat comparator checking Vbat vs the programmed Pre-Charge and Replenish levels"
group.long 0x0C++0x03
line.long 0x00 "CHARGER_VOLTAGE_PARAM_REG,Charger voltage settings register"
bitfld.long 0x00 18.--23. "V_OVP,This bit-field determines the VBAT Over-voltage protection limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. "V_REPLENISH,This bit-field determines the absolute value (in V) of the Replenish voltage threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--11. "V_PRECHARGE,This bit-field determines the voltage level at which the battery is considered as Pre-charged and therefore the Charger's FSM should move to the CC_CHARGE state entering the Constant Current charging phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "V_CHARGE,This bit-field determines the charge voltage levels supported" "0: 2.80V,1: 2.85V,2: 2.90V,3: 2.95V,4: 3.00V,5: 3.05V,6: 3.10V,7: 3.15V,8: 3.20V,9: 3.25V,10: 3.30V,11: 3.35V,12: 3.40V,13: 3.45V,14: 3.50V,15: 3.55V,16: 3.60V,17: 3.65V,18: 3.70V,19: 3.75V,20: 3.80V,21: 3.82V,22: 3.84V,23: 3.86V,24: 3.88V,25: 3.90V,26: 3.92V,27: 3.94V,28: 3.96V,29: 3.98V,30: 4.00V,31: 4.02V,32: 4.04V,33: 4.06V,34: 4.08V,35: 4.10V,36: 4.12V,37: 4.14V,38: 4.16V,39: 4.18V,40: 4.20V,41: 4.22V,42: 4.24V,43: 4.26V,44: 4.28V,45: 4.30V,46: 4.32V,47: 4.34V,48: 4.36V,49: 4.38V,50: 4.40V,51: 4.42V,52: 4.44V,53: 4.46V,54: 4.48V,55: 4.50V,56: 4.52V,57: 4.54V,58: 4.56V,59: 4.58V,60: 4.60V,61: 4.70V,62: 4.80V,63: 4.90V* It has"
group.long 0x14++0x03
line.long 0x00 "CHARGER_VOLTAGE_STATUS_REG,Charger voltage status register"
rbitfld.long 0x00 18.--23. "V_OVP_SET,This bit-field returns the applied V_OVP setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 12.--17. "V_REPLENISH_SET,This bit-field returns the applied V_REPLENISH setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 6.--11. "V_PRECHARGE_SET,This bit-field returns the applied V_PRECHARGE setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 0.--5. "V_CHARGE_SET,This bit-field returns the applied V_CHARGE setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50++0x03
line.long 0x00 "CHARGER_VOVP_COMP_TIMER_REG,Vbat OVP comparator timer register"
rbitfld.long 0x00 26.--31. "OVP_INTERVAL_CHECK_TIMER,The specific bit-field determines the current state of the timer used to periodically check the output of the Over-Voltage Protection comparator's output signal as soon as the Charger's FSM reaches any of the charging states.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 16.--25. 1. "VBAT_OVP_COMP_TIMER,Returns the current value of the timer used to determine when the Vbat Over-Voltage protection (OVP) comparator's output must be sampled by the digital"
newline
bitfld.long 0x00 10.--15. "OVP_INTERVAL_CHECK_THRES,This bit-field determines the periodic interval of checking the dedicated Vbat OVP comparator's output when the Charger's FSM is in any of the charging states (PRE/CC/CV_CHARGE)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--9. 1. "VBAT_OVP_COMP_SETTLING,Settling time threshold (in us) for the Vbat comparator checking Vbat vs the programmed Over-Voltage level"
tree.end
tree "CHG_DET"
base ad:0x50040300
group.long 0x10++0x03
line.long 0x00 "CHG_DET_ADC_CTRL_REG,Charge detection ADC control register"
bitfld.long 0x00 2. "ADC_V30_SEL,This bit-field determines the mode to be used when the intention is to measure the USB Dp/Dm levels with the GP_ADC" "0: Should be used when the V30 rail is at 3.0V,1: Should be used when the V30 rail is at 3.3V"
bitfld.long 0x00 1. "USB_DM_TO_ADC_EN," "0,1"
bitfld.long 0x00 0. "USB_DP_TO_ADC_EN," "0,1"
group.long 0x18++0x03
line.long 0x00 "CHG_DET_DCD_TIMER_REG,Charge detection DCD time-out timer register (used in the FSM)"
hexmask.long.word 0x00 16.--25. 1. "DCD_TIMER,This bit-field returns the current value of the DCD time-out timer also ticking with the 1KHz clock same as the shared 8-bit timer"
hexmask.long.word 0x00 0.--9. 1. "DCD_TIMEOUT_THRES,This bit-field determines the value from which the Data Contact Detection (DCD) time-out timer starts down-counting until expiring to zero"
group.long 0x00++0x03
line.long 0x00 "CHG_DET_FSM_CTRL_REG,Charge detection FSM control register"
bitfld.long 0x00 0. "CHG_DET_EN," "0,1"
group.long 0x04++0x03
line.long 0x00 "CHG_DET_FSM_STATUS_REG,Charge detection FSM status register"
rbitfld.long 0x00 9.--12. "CHG_DET_STATE,This bit-field returns the current state of the charge detection block's FSM" "0: WAIT_FOR_ATTACH (starting state),1: NODE_ATTACHED (USB_DP_VAL first check),2: WAIT_FOR_DCD (Data Contact Detection - first,3: CHECK_FOR_DCD (Data Contact Detection - second,4: WAIT_FOR_PCD (Primary Contact Detection - first,5: CHECK_FOR_PCD (Primary Contact Detection,6: WAIT_FOR_SCD (Secondary Contact Detection,7: CHECK_FOR_SCD (Secondary Contact Detection,8: CHG_PORT_DETECTED (terminal state indicating..,?..."
rbitfld.long 0x00 8. "NO_CONTACT_DETECTED," "0,1"
rbitfld.long 0x00 7. "PORT_2P4AMP_DETECTED," "0,1"
newline
rbitfld.long 0x00 6. "PORT_2AMP_DETECTED," "0,1"
rbitfld.long 0x00 5. "PORT_1AMP_DETECTED," "0,1"
rbitfld.long 0x00 4. "PS2_PROP_PORT_DETECTED," "0,1"
newline
rbitfld.long 0x00 3. "DCP_PORT_DETECTED," "0,1"
rbitfld.long 0x00 2. "CDP_PORT_DETECTED," "0,1"
rbitfld.long 0x00 1. "SDP_PORT_DETECTED," "0,1"
newline
rbitfld.long 0x00 0. "DETECTION_COMPLETED," "0,1"
group.long 0x24++0x03
line.long 0x00 "CHG_DET_IRQ_CLEAR_REG,Charge detection IRQ clear register"
bitfld.long 0x00 0. "CHG_DET_IRQ_CLR,Writing any value to this register clears the charge detection IRQ reading always returns zero" "0,1"
group.long 0x1C++0x03
line.long 0x00 "CHG_DET_IRQ_MASK_REG,Charge detection IRQ mask register"
bitfld.long 0x00 0. "CHG_DET_IRQ_EN," "0,1"
group.long 0x20++0x03
line.long 0x00 "CHG_DET_IRQ_STATUS_REG,Charge detection IRQ status register"
rbitfld.long 0x00 0. "CHG_DET_IRQ," "0,1"
group.long 0x0C++0x03
line.long 0x00 "CHG_DET_STATUS_REG,Charge detection status register holding the comparator outputs"
rbitfld.long 0x00 5. "USB_DM_VAL2," "0,1"
rbitfld.long 0x00 4. "USB_DP_VAL2," "0,1"
rbitfld.long 0x00 3. "USB_DM_VAL," "0,1"
newline
rbitfld.long 0x00 2. "USB_DP_VAL," "0,1"
rbitfld.long 0x00 1. "USB_CHG_DET," "0,1"
rbitfld.long 0x00 0. "USB_DCP_DET," "0,1"
group.long 0x08++0x03
line.long 0x00 "CHG_DET_SW_CTRL_REG,Charge detection manual (SW-based) mode control register"
bitfld.long 0x00 5. "IDM_SINK_ON," "0,1"
bitfld.long 0x00 4. "IDP_SINK_ON," "0,1"
bitfld.long 0x00 3. "VDM_SRC_ON," "0,1"
newline
bitfld.long 0x00 2. "VDP_SRC_ON," "0,1"
bitfld.long 0x00 1. "IDP_SRC_ON," "0,1"
bitfld.long 0x00 0. "USB_CHARGE_ON," "0,1"
group.long 0x14++0x03
line.long 0x00 "CHG_DET_TIMER_REG,Charge detection timer register (used in the FSM)"
hexmask.long.byte 0x00 16.--23. 1. "CHG_DET_TIMER,This bit-field returns the current value of the charge detection timer which is used by the FSM and which down-counts with a clock of 1KHz"
hexmask.long.byte 0x00 0.--7. 1. "CHG_DET_TIMER_THRES,This bit-field determines the value from which the charge detection timer starts down-counting until expiring to zero"
tree.end
tree "CRG"
tree "CRG_AUD"
base ad:0x50030000
group.long 0x40++0x03
line.long 0x00 "PCM_DIV_REG,PCM divider and enables"
bitfld.long 0x00 13. "PCM_SRC_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 12. "CLK_PCM_EN,Enable for the internally generated PCM clock The PCM_DIV must be set before or together with CLK_PCM_EN" "0,1"
hexmask.long.word 0x00 0.--11. 1. "PCM_DIV,PCM clock divider"
group.long 0x44++0x03
line.long 0x00 "PCM_FDIV_REG,PCM fractional division register"
hexmask.long.word 0x00 0.--15. 1. "PCM_FDIV,These bits define the fractional division part of the PCM clock"
group.long 0x48++0x03
line.long 0x00 "PDM_DIV_REG,PDM divider and enables"
bitfld.long 0x00 9. "PDM_MASTER_MODE,Master mode selection" "0: slave mode,1: master mode"
bitfld.long 0x00 8. "CLK_PDM_EN,Enable for the internally generated PDM clock The PDM_DIV must be set before or together with CLK_PDM_EN" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "PDM_DIV,PDM clock divider"
group.long 0x4C++0x03
line.long 0x00 "SRC_DIV_REG,SRC divider and enables"
bitfld.long 0x00 17. "CLK_SRC2_EN,Enable for the internally generated SRC2 clock The SRC2_DIV must be set before or together with CLK_SRC2_EN" "0,1"
bitfld.long 0x00 16. "CLK_SRC_EN,Enable for the internally generated SRC clock The SRC_DIV must be set before or together with CLK_SRC_EN" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "SRC2_DIV,SRC2 clock divider"
hexmask.long.byte 0x00 0.--7. 1. "SRC_DIV,SRC clock divider"
tree.end
tree "CRG_CTRL"
base ad:0x50060000
group.long 0x04++0x03
line.long 0x00 "CLK_PDCTRL_REG,Clock control settings for PD_CTRL"
bitfld.long 0x00 13. "EMMC_INV_TX_CLK,Inverts the clock in the TX path" "0,1"
bitfld.long 0x00 12. "EMMC_INV_RX_CLK,Invert the clock in the RX path cascaded with INV_TX_CLK" "0,1"
bitfld.long 0x00 11. "EMMC_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 7.--10. "EMMC_CLK_DIV,clock divider setting" "0: divide by 16,1: divide by 1,2: divide by 2,?,4: divide by 4,?,?,?,8: divide by 8,?..."
bitfld.long 0x00 6. "SDIO_INV_TX_CLK,Inverts the clock in the TX path" "0,1"
newline
bitfld.long 0x00 5. "SDIO_INV_RX_CLK,Invert the clock in the RX path cascaded with INV_TX_CLK" "0,1"
bitfld.long 0x00 4. "SDIO_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 0.--3. "SDIO_CLK_DIV,clock divider setting" "0: divide by 16,1: divide by 1,2: divide by 2,?,4: divide by 4,?,?,?,8: divide by 8,?..."
tree.end
tree "CRG_GPU"
base ad:0x51001000
group.long 0x04++0x03
line.long 0x00 "CLK_GPU_REG,Control register for clocks in PD_GPU"
bitfld.long 0x00 3. "MIPI_D_PHY_EN," "0,1"
bitfld.long 0x00 2. "MIPI_PHY_EN," "0,1"
bitfld.long 0x00 1. "MIPI_DSI_EN," "0,1"
bitfld.long 0x00 0. "GPU_ENABLE," "0,1"
tree.end
tree "CRG_SNC"
base ad:0x50020900
group.long 0x04++0x03
line.long 0x00 "CLK_SNC_REG,Peripheral divider register"
bitfld.long 0x00 17. "I3C_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 16. "I3C_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 15. "I2C3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 14. "I2C3_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 13. "I2C2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 12. "I2C2_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 11. "I2C_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 10. "I2C_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 9. "SPI2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 8. "SPI2_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 7. "SPI_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 6. "SPI_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 5. "UART3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 4. "UART3_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 3. "UART2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 2. "UART2_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 1. "UART_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 0. "UART_ENABLE,Enables the clock" "0,1"
group.long 0x0C++0x03
line.long 0x00 "RESET_CLK_SNC_REG,Peripheral divider register RESET register"
bitfld.long 0x00 17. "I3C_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 16. "I3C_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 15. "I2C3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 14. "I2C3_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 13. "I2C2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 12. "I2C2_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 11. "I2C_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 10. "I2C_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 9. "SPI2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 8. "SPI2_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 7. "SPI_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 6. "SPI_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 5. "UART3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 4. "UART3_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 3. "UART2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 2. "UART2_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 1. "UART_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 0. "UART_ENABLE,Enables the clock" "0,1"
group.long 0x08++0x03
line.long 0x00 "SET_CLK_SNC_REG,Peripheral divider register SET register"
bitfld.long 0x00 17. "I3C_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 16. "I3C_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 15. "I2C3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 14. "I2C3_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 13. "I2C2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 12. "I2C2_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 11. "I2C_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 10. "I2C_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 9. "SPI2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 8. "SPI2_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 7. "SPI_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 6. "SPI_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 5. "UART3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 4. "UART3_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 3. "UART2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 2. "UART2_ENABLE,Enables the clock" "0,1"
newline
bitfld.long 0x00 1. "UART_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 0. "UART_ENABLE,Enables the clock" "0,1"
tree.end
tree "CRG_SYS"
base ad:0x50040400
group.long 0x10++0x03
line.long 0x00 "BATCHECK_REG,"
bitfld.long 0x00 7. "BATCHECK_LOAD_ENABLE,Enable a current load on the battery" "0,1"
bitfld.long 0x00 4.--6. "BATCHECK_ILOAD,Set the current load to (ILOAD+1) mA" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "BATCHECK_TRIM,Trim the current load with steps of 2.7% from -19.1% to +19.1%" "0: +0.0%,1: +2.7%,2: +5.5%,3: +8.2%,4: +10.9%,5: +13.6%,6: +16.4%,7: +19.1%,8: -0%,9: -2.7%,10: -5.5%,11: -8.2%,12: -10.9%,13: -13.6%,14: -16.4%,15: -19.1%"
group.long 0x00++0x03
line.long 0x00 "CLK_SYS_REG,Peripheral divider register"
bitfld.long 0x00 7. "SPI3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 6. "SPI3_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 5. "CLK_CHG_EN,Enables the clocks for the charger FSM block" "0,1"
newline
bitfld.long 0x00 4. "LCD_RESET_REQ,Generates a SW reset towards the LCD controller" "0,1"
bitfld.long 0x00 3. "LCD_DPHYCLK_SEL,This bitfield selects the clock source for the LCD controller" "0: source as selected by LCD_SYSCLK_DIV2 bit,1: DPHY byte clock"
bitfld.long 0x00 1. "LCD_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
newline
bitfld.long 0x00 0. "LCD_ENABLE,Enables the clock" "0,1"
group.long 0x0C++0x03
line.long 0x00 "RESET_CLK_SYS_REG,Peripheral divider RESET register"
bitfld.long 0x00 7. "SPI3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 6. "SPI3_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 5. "CLK_CHG_EN,Enables the clocks for the charger FSM block" "0,1"
newline
bitfld.long 0x00 4. "LCD_RESET_REQ,Generates a SW reset towards the LCD controller" "0,1"
bitfld.long 0x00 3. "LCD_DPHYCLK_SEL,This bitfield selects the clock source for the LCD controller" "0: source as selected by LCD_SYSCLK_DIV2 bit,1: DPHY byte clock"
bitfld.long 0x00 1. "LCD_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
newline
bitfld.long 0x00 0. "LCD_ENABLE,Enables the clock" "0,1"
group.long 0x08++0x03
line.long 0x00 "SET_CLK_SYS_REG,Peripheral divider SET register"
bitfld.long 0x00 7. "SPI3_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.long 0x00 6. "SPI3_ENABLE,Enables the clock" "0,1"
bitfld.long 0x00 5. "CLK_CHG_EN,Enables the clocks for the charger FSM block" "0,1"
newline
bitfld.long 0x00 4. "LCD_RESET_REQ,Generates a SW reset towards the LCD controller" "0,1"
bitfld.long 0x00 3. "LCD_DPHYCLK_SEL,This bitfield selects the clock source for the LCD controller" "0: source as selected by LCD_SYSCLK_DIV2 bit,1: DPHY byte clock"
bitfld.long 0x00 1. "LCD_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
newline
bitfld.long 0x00 0. "LCD_ENABLE,Enables the clock" "0,1"
tree.end
tree "CRG_TOP"
base ad:0x50000000
group.long 0xEC++0x03
line.long 0x00 "ANA_STATUS_REG,Analog Signals Status Register"
rbitfld.long 0x00 29. "FLAG_LDO_V30_COMBINED_OK," "0,1"
newline
rbitfld.long 0x00 28. "XOR_DOUT_WAKEUP_PADS,Will be the result of XOR operation of the hibernation wakeup pads outputs combined" "0,1"
newline
rbitfld.long 0x00 27. "VBUS_AVAILABLE,High when VBUS > ( VBAT + 150 mV)" "0,1"
newline
rbitfld.long 0x00 26. "FLAG_ADC_LDO_OK,When high ldo_adc is active" "0,1"
newline
rbitfld.long 0x00 25. "FLAG_IBIAS_TRIM,10nA Iref trimming high when on-chip current is larger than reference current" "0,1"
newline
rbitfld.long 0x00 24. "BOD_VIN_NOK,General output of the BOD to indicate that one of the monitored inputs is below the trigger-level" "0,1"
newline
rbitfld.long 0x00 23. "BG_OK,When high bandgap is active" "0,1"
newline
rbitfld.long 0x00 22. "BOOST_DCDC_VLED_OK,When high boost dcdc vled is active" "0,1"
newline
rbitfld.long 0x00 21. "LDO_VSYS_HIGH_TEMP,If 1 indicates that temperature of LDO_VSYS is above operating conditions" "0,1"
newline
rbitfld.long 0x00 19.--20. "VBAT_VSYS_STATE," "?,1: Test mode ( sysbat switch closed),2: Ideal diode enabled (with VBAT-only or VBUS and,3: Sleep mode (with VBAT-only sysbat switch.."
newline
rbitfld.long 0x00 18. "LDO_VSYS_HEAD_LIM,When high the headroom loop is controlling VSYS" "0,1"
newline
rbitfld.long 0x00 17. "LDO_VSYS_CURR_LIM,When high the current limiter is controlling VSYS" "0,1"
newline
rbitfld.long 0x00 16. "LDO_VSYS_LIM,When high the voltage loop is controlling VSYS" "0,1"
newline
rbitfld.long 0x00 15. "LDO_VSYS_OK,When high LDO_VSYS is in regulating mode" "0,1"
newline
rbitfld.long 0x00 14. "LDO_MIPI_OK,When high ldo_mipi is active" "0,1"
newline
rbitfld.long 0x00 13. "LDO_V30_OK,When high ldo_v30 is active" "0,1"
newline
rbitfld.long 0x00 12. "SWITCH_V18F_OK,V18F switch completely closed" "0,1"
newline
rbitfld.long 0x00 11. "BUCK_DCDC_V18P_OK,V18P Rail ok based on DCDC V18P programmed level" "0,1"
newline
rbitfld.long 0x00 10. "BUCK_DCDC_V18_OK,V18 Rail ok based on DCDC V18 programmed level" "0,1"
newline
rbitfld.long 0x00 9. "BUCK_DCDC_V14_OK,V14 Rail ok based on DCDC V14 programmed level" "0,1"
newline
rbitfld.long 0x00 8. "BUCK_DCDC_V12_OK,V12 Rail ok based on DCDC V12 programmed level" "0,1"
newline
rbitfld.long 0x00 7. "COMP_VBUS_PLUGIN,VBUS is connected (VBUS > 2.5V)" "0,1"
newline
rbitfld.long 0x00 6. "COMP_VSYS_NEAR_VLED,BOOST_VLED_SEL=0x0 : VSYS>4.3 BOOST_VLED_SEL=0x1 : VSYS>4.55 BOOST_VLED_SEL=0x2 : VSYS>4.8 BOOST_VLED_SEL=0x3 : VSYS>4.8" "0,1"
newline
rbitfld.long 0x00 5. "COMP_VBUS_ABOVE_VSYS,VBUS>VSYS+0.05V" "0,1"
newline
rbitfld.long 0x00 4. "COMP_VSYS_OK,VSYS> 2.45V" "0,1"
newline
rbitfld.long 0x00 3. "COMP_VBAT_OK,VBAT> 2.7V" "0,1"
newline
rbitfld.long 0x00 2. "COMP_VBUS_OK," "0,1"
newline
rbitfld.long 0x00 1. "POR_VSYS_OK," "0,1"
newline
rbitfld.long 0x00 0. "POR_V30_OK," "0,1"
group.long 0x50++0x03
line.long 0x00 "BANDGAP_REG,bandgap trimming"
bitfld.long 0x00 15. "EN_BGR_TCCOMP,Enable Temperature compensation in the reference current for Charger and LED module" "0: Disabled original currents from BGR are used,1: enabled ( = default setting)"
newline
bitfld.long 0x00 12. "BANDGAP_ENABLE_CLAMP,Enables a supply clamp inside the bandgap that improves PSRR" "0,1"
newline
bitfld.long 0x00 6.--11. "BGR_TRIM,Trim register for bandgap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 5. "SYSRAM_LPMX,RAM Transparent Light Sleep (TLS) Core Enable for System RAMs and Cache RAM" "0,1"
newline
bitfld.long 0x00 0.--4. "BGR_ITRIM,Current trimming for bias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xE8++0x03
line.long 0x00 "BIAS_VREF_SEL_REG,"
bitfld.long 0x00 4.--7. "BIAS_VREF_RF2_SEL,same coding as BIAS_VREF_RF1_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "BIAS_VREF_RF1_SEL,Vref_code | Vref_Voltage (mV) 0:900 1:930 2:960 3:990 4:1020 5:1050 6:1080 7:1110 8:1140 9:1170 10:1200 11:1230 12:1260 13:1290 14:1320 15:1350" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60++0x03
line.long 0x00 "BOD_CTRL_REG,Brown Out Detection control register"
bitfld.long 0x00 18. "BOD_VBUS_RST_EN,If set generate power-on reset on channel VBUS" "0,1"
newline
bitfld.long 0x00 17. "BOD_VBAT_RST_EN,If set generate power-on reset on channel VBAT" "0,1"
newline
bitfld.long 0x00 16. "BOD_MIPI_RST_EN,If set generate power-on reset on channel VMIPI" "0,1"
newline
bitfld.long 0x00 15. "BOD_VSYS_RST_EN,If set generate power-on reset on channel VSYS" "0,1"
newline
bitfld.long 0x00 14. "BOD_V18F_RST_EN,If set generate power-on reset on channel V18F" "0,1"
newline
bitfld.long 0x00 13. "BOD_V18P_RST_EN,If set generate power-on reset on channel V18P" "0,1"
newline
bitfld.long 0x00 12. "BOD_V18_RST_EN,If set generate power-on reset on channel V18" "0,1"
newline
bitfld.long 0x00 11. "BOD_V14_RST_EN,If set generate power-on reset on channel V14" "0,1"
newline
bitfld.long 0x00 10. "BOD_V12_RST_EN,If set generate power-on reset on channel V12" "0,1"
newline
bitfld.long 0x00 9. "BOD_VBUS_EN,Enable brown-out detection for channel VBUS" "0,1"
newline
bitfld.long 0x00 8. "BOD_VBAT_EN,Enable brown-out detection for channel VBAT" "0,1"
newline
bitfld.long 0x00 7. "BOD_MIPI_EN,Enable brown-out detection for channel VMIPI" "0,1"
newline
bitfld.long 0x00 6. "BOD_VSYS_EN,Enable brown-out detection for channel VSYS" "0,1"
newline
bitfld.long 0x00 5. "BOD_V18F_EN,Enable brown-out detection for channel V18F" "0,1"
newline
bitfld.long 0x00 4. "BOD_V18P_EN,Enable brown-out detection for channel V18P" "0,1"
newline
bitfld.long 0x00 3. "BOD_V18_EN,Enable brown-out detection for channel V18" "0,1"
newline
bitfld.long 0x00 2. "BOD_V14_EN,Enable brown-out detection for channel V14" "0,1"
newline
bitfld.long 0x00 1. "BOD_V12_EN,Enable brown-out detection for channel VDD (V12)" "0,1"
newline
bitfld.long 0x00 0. "BOD_STATUS_CLEAR,Clears BOD_STATUS_REG when this bit is 1 for more than 2us" "0,1"
group.long 0x64++0x03
line.long 0x00 "BOD_STATUS_REG,"
rbitfld.long 0x00 8. "BOD_VBUS," "0,1"
newline
rbitfld.long 0x00 7. "BOD_VBAT," "0,1"
newline
rbitfld.long 0x00 6. "BOD_VMIPI," "0,1"
newline
rbitfld.long 0x00 5. "BOD_VSYS," "0,1"
newline
rbitfld.long 0x00 4. "BOD_V18F," "0,1"
newline
rbitfld.long 0x00 3. "BOD_V18P," "0,1"
newline
rbitfld.long 0x00 2. "BOD_V18," "0,1"
newline
rbitfld.long 0x00 1. "BOD_V14," "0,1"
newline
rbitfld.long 0x00 0. "BOD_V12," "0,1"
group.long 0x00++0x03
line.long 0x00 "CLK_AMBA_REG,HCLK PCLK divider and clock gates"
bitfld.long 0x00 20. "OQSPI_PULLUP_ENABLE,Selects pull value when OQSPIF_D* pads are not output" "0: The pads are pull-down,1: The pads are pull-up (to V18F)"
newline
bitfld.long 0x00 19. "OQSPI_GPIO_MODE,If this bit is set the upper 4 pins of the OQSPIF controller can be used as GPIO P2_07 to P2_04" "0,1"
newline
bitfld.long 0x00 18. "QSPIC2_ENABLE,Clock enable for QSPI RAM controller" "0,1"
newline
bitfld.long 0x00 16.--17. "QSPIC2_DIV,Clock divider setting" "0,1,2,3"
newline
bitfld.long 0x00 15. "QSPIC_ENABLE,Clock enable for QSPI FLASH2 controller" "0,1"
newline
bitfld.long 0x00 13.--14. "QSPIC_DIV,Clock divider setting" "0,1,2,3"
newline
bitfld.long 0x00 12. "OQSPIF_ENABLE,Clock enable for Octal SPI controller" "0,1"
newline
bitfld.long 0x00 10.--11. "OQSPIF_DIV,Clock divider setting" "0,1,2,3"
newline
bitfld.long 0x00 9. "OTP_ENABLE,Clock enable for OTP controller" "0,1"
newline
bitfld.long 0x00 8. "AES_CLK_ENABLE,Clock enable for AES crypto block" "0,1"
newline
bitfld.long 0x00 5.--7. "SLOW_PCLK_DIV,Slow-APB interface clock derived from DIVN_CLK: 0b000: divide divn_clk by 1 0b001: divide divn_clk by 2 0b010: divide divn_clk by 4 0b011: divide divn_clk by 8 0b1xx: divide divn_clk by 16" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--4. "PCLK_DIV,Fast-APB interface clock Cascaded with HCLK: 0b00: divide hclk by 1 0b01: divide hclk by 2 0b10: divide hclk by 4 0b11: divide hclk by 8" "0,1,2,3"
newline
bitfld.long 0x00 0.--2. "HCLK_DIV,AHB interface and microprocessor clock" "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "CLK_CMAC_SWITCH_REG,Clock switching register for CMAC clock domain"
rbitfld.long 0x00 2. "CMAC_RUNNING_ON_XTAL,This bit is '1' when the CMAC_CLK is enabled and the switch is set in the XTAL32M position" "0,1"
newline
rbitfld.long 0x00 1. "CMAC_RUNNING_ON_DIVN,This bit is '1' when the CMAC_CLK is enabled and the switch is set in the DIVN_CLK position" "0,1"
newline
bitfld.long 0x00 0. "CMAC_CLK_SEL,Selects the clock source of the CMAC_CLK" "0: DIVN_CLK is selected,1: XTAL32M is selected"
group.long 0x14++0x03
line.long 0x00 "CLK_CTRL_REG,Clock control register"
rbitfld.long 0x00 15. "RUNNING_AT_PLL,Indicates that the PLL clock is used as clock and may not be switched off" "0,1"
newline
rbitfld.long 0x00 14. "RUNNING_AT_XTAL32M,Indicates that the XTAL32M clock is used as clock and may not be switched off" "0,1"
newline
rbitfld.long 0x00 13. "RUNNING_AT_RCHS,Indicates that the RCHS clock is used as clock" "0,1"
newline
rbitfld.long 0x00 12. "RUNNING_AT_RCLP,Indicates that the RCLP_CLK is being used as clock" "0,1"
newline
bitfld.long 0x00 6. "VAD_CLK_SEL,Selects the clock for the VAD" "0: Select RCLP clock (normalized for ~32KHz),1: Select XTAL32K"
newline
bitfld.long 0x00 2.--3. "LP_CLK_SEL,Sets the clock source of the LowerPower clock" "0: RC32K,1: RCX,2: XTAL32K through the oscillator with an external,3: XTAL32K through an external square wave"
newline
bitfld.long 0x00 0.--1. "SYS_CLK_SEL,Selects the clock source" "0: XTAL32M,1: RCHS,2: The Low Power clock is used,3: The PLL160Mhz is used"
group.long 0x10++0x03
line.long 0x00 "CLK_RADIO_REG,Radio PLL control register"
bitfld.long 0x00 6. "RAD_REG_RESET_REQ,Reset request for registers of the radio PHY" "0,1"
newline
bitfld.long 0x00 5. "RFCU_ENABLE,Enable the RF control Unit clock" "0,1"
newline
bitfld.long 0x00 4. "CMAC_SYNCH_RESET,Force synchronous reset to CMAC core and Sleep Timer" "0,1"
newline
bitfld.long 0x00 2. "CMAC_CLK_ENABLE,Enables the clock" "0,1"
group.long 0x44++0x03
line.long 0x00 "CLK_RCHS_REG,Fast RC control register"
bitfld.long 0x00 22.--23. "RCHS_SPEED,Selects speed of RCHS output 0b00: 32MHz by dividing 96 / 3" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "RCHS_INIT_RANGE,Course frequency adjustment" "0,1,2,3"
newline
hexmask.long.byte 0x00 12.--19. 1. "RCHS_INIT_DEL,Fine frequency adjustment"
newline
bitfld.long 0x00 9.--11. "RCHS_INIT_DTCF,Fine duty-cycle adjustment" "0: minimum,?,2: default,?,4: maximum 0x5 until,?,?,7: oscillator does not work"
newline
bitfld.long 0x00 5.--8. "RCHS_INIT_DTC,Course duty-cycle adjustment" "0: minimum,?,?,?,?,5: default,?,?,?,?,10: maximum 0xB until,?,?,?,?,15: oscillator does not work"
newline
bitfld.long 0x00 1.--4. "RCHS_BIAS,Bias adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "RCHS_ENABLE,Enables the HighSpeed RC oscillator" "0,1"
group.long 0x3C++0x03
line.long 0x00 "CLK_RCLP_REG,32/512 kHz RC oscillator register"
bitfld.long 0x00 5. "RCLP_LOW_SPEED_FORCE,Forces RCLP in 32kHz mode" "0,1"
newline
bitfld.long 0x00 1.--4. "RCLP_TRIM," "?,?,?,?,?,?,?,7: default,?,?,?,?,?,?,?,15: highest frequency"
newline
bitfld.long 0x00 0. "RCLP_ENABLE,Enables the 32kHz RC oscillator" "0,1"
group.long 0x48++0x03
line.long 0x00 "CLK_RCX_REG,RCX-oscillator control register"
bitfld.long 0x00 8.--11. "RCX_BIAS,LDO bias current" "0: minimum,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: maximum"
newline
bitfld.long 0x00 7. "RCX_C0,Add unit capacitance to RC-time delay" "0,1"
newline
bitfld.long 0x00 2.--6. "RCX_CADJUST,Adjust capacitance part of RC-time delay" "0: minimum capacitance,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: maximum capacitance"
newline
bitfld.long 0x00 0. "RCX_ENABLE," "0,1"
group.long 0x4C++0x03
line.long 0x00 "CLK_RTCDIV_REG,Divisor for RTC 100Hz clock"
bitfld.long 0x00 21. "RTC_RESET_REQ,Reset request for the RTC module" "0,1"
newline
bitfld.long 0x00 20. "RTC_DIV_ENABLE,Enable for the 100 Hz generation for the RTC block" "0,1"
newline
bitfld.long 0x00 19. "RTC_DIV_DENOM,Selects the denominator for the fractional division: 0b0: 1000 0b1: 1024" "0,1"
newline
hexmask.long.word 0x00 10.--18. 1. "RTC_DIV_INT,Integer divisor part for RTC 100Hz generation"
newline
hexmask.long.word 0x00 0.--9. 1. "RTC_DIV_FRAC,Fractional divisor part for RTC 100Hz generation"
group.long 0x2C++0x03
line.long 0x00 "CLK_SNC_CTRL_REG,"
bitfld.long 0x00 2. "SNC_STATE_RETAINED,A flag which can be used from FW to indicate that the CPU state has been retained and should be restored during the wakeup sequence (at the beginning of Reset Handler)" "0,1"
newline
bitfld.long 0x00 1. "SNC_CLK_ENABLE,Clock-enable for the CM0plus in the SNC" "0,1"
newline
bitfld.long 0x00 0. "SNC_RESET_REQ,Force the SNC microprocessor in reset" "0,1"
group.long 0x1C++0x03
line.long 0x00 "CLK_SWITCH2XTAL_REG,Switches clock from RC32M to XTAL32M"
bitfld.long 0x00 0. "SWITCH2XTAL,When writing to this register the clock switch will happen from RC32M to XTAL32M" "0,1"
group.long 0x18++0x03
line.long 0x00 "CLK_TMR_REG,Clock control for the timers"
bitfld.long 0x00 2. "TMR2_PWM_AON_MODE,Maps Timer2_pwm onto P1_17" "0,1"
newline
bitfld.long 0x00 1. "TMR_PWM_AON_MODE,Maps Timer1_pwm onto P1_00 This state is preserved during deep sleep to allow PWM output on the pad during deep sleep" "0,1"
newline
bitfld.long 0x00 0. "WAKEUPCT_ENABLE,Enables the clock" "0,1"
group.long 0x40++0x03
line.long 0x00 "CLK_XTAL32K_REG,32 kHz XTAL oscillator register"
bitfld.long 0x00 9. "XTAL32K_DISABLE_OUTPUT,Disables output buffer test only" "0,1"
newline
bitfld.long 0x00 7. "XTAL32K_DISABLE_AMPREG,Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator" "0,1"
newline
bitfld.long 0x00 3.--6. "XTAL32K_CUR,Bias current for the 32kHz XTAL oscillator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--2. "XTAL32K_RBIAS,Setting for the bias resistor" "0,1,2,3"
newline
bitfld.long 0x00 0. "XTAL32K_ENABLE,Enables the 32kHz XTAL oscillator" "0,1"
group.long 0xD4++0x03
line.long 0x00 "DISCHARGE_RAIL_REG,Immediate rail resetting"
bitfld.long 0x00 4. "RESET_V30," "0,1"
newline
bitfld.long 0x00 3. "RESET_VPOD," "0,1"
newline
bitfld.long 0x00 2. "RESET_V18P," "0,1"
newline
bitfld.long 0x00 1. "RESET_V18," "0,1"
newline
bitfld.long 0x00 0. "RESET_V14," "0,1"
group.long 0x34++0x03
line.long 0x00 "LCD_EXT_CTRL_REG,"
bitfld.long 0x00 10. "LCD_EXT_CLK_EN," "0,1"
newline
hexmask.long.word 0x00 0.--9. 1. "LCD_EXT_CNT_RELOAD,Reload value for LCD_EXT_CLK generation"
group.long 0x70++0x03
line.long 0x00 "P0_PAD_LATCH_REG,Control the state retention of the GPIO ports"
abitfld.long 0x00 0.--31. "P0_LATCH_EN,Direct write to the individual pad latching signals" "0x00000000=0: Control signals are retained,0x00000001=1: Latch is transparant pad can be.."
group.long 0x78++0x03
line.long 0x00 "P0_RESET_PAD_LATCH_REG,Control the state retention of the GPIO ports"
hexmask.long 0x00 0.--31. 1. "P0_RESET_LATCH_EN,Direct Reset of the marked bits"
group.long 0x74++0x03
line.long 0x00 "P0_SET_PAD_LATCH_REG,Control the state retention of the GPIO ports"
hexmask.long 0x00 0.--31. 1. "P0_SET_LATCH_EN,Direct Set of the marked bits"
group.long 0x7C++0x03
line.long 0x00 "P1_PAD_LATCH_REG,Control the state retention of the GPIO ports"
abitfld.long 0x00 0.--31. "P1_LATCH_EN,Direct write to the individual pad latching signals" "0x00000000=0: Control signals are retained,0x00000001=1: Latch is transparant pad can be.."
group.long 0x84++0x03
line.long 0x00 "P1_RESET_PAD_LATCH_REG,Control the state retention of the GPIO ports"
hexmask.long 0x00 0.--31. 1. "P1_RESET_LATCH_EN,Direct Reset of the marked bits"
group.long 0x80++0x03
line.long 0x00 "P1_SET_PAD_LATCH_REG,Control the state retention of the GPIO ports"
hexmask.long 0x00 0.--31. 1. "P1_SET_LATCH_EN,Direct Set of the marked bits"
group.long 0x88++0x03
line.long 0x00 "P2_PAD_LATCH_REG,Control the state retention of the GPIO ports"
abitfld.long 0x00 0.--14. "P2_LATCH_EN,Direct write to the individual pad latching signals" "0x0000=0: Control signals are retained,0x0001=1: Latch is transparant pad can be.."
group.long 0x90++0x03
line.long 0x00 "P2_RESET_PAD_LATCH_REG,Control the state retention of the GPIO ports"
hexmask.long.word 0x00 0.--14. 1. "P2_RESET_LATCH_EN,Direct Reset of the marked bits"
group.long 0x8C++0x03
line.long 0x00 "P2_SET_PAD_LATCH_REG,Control the state retention of the GPIO ports"
hexmask.long.word 0x00 0.--14. 1. "P2_SET_LATCH_EN,Direct Set of the marked bits"
group.long 0x20++0x03
line.long 0x00 "PMU_CTRL_REG,Power Management Unit control register"
bitfld.long 0x00 13. "RETAIN_RGP_RAM,Retain the R-G-B RAMs inside the LCD display controller" "0,1"
newline
bitfld.long 0x00 12. "RETAIN_GPU_CLUT,Retain the GPU CLUT memory" "0,1"
newline
bitfld.long 0x00 11. "RETAIN_DCACHE,Selects the retainability of the dcache block while PD_CTRL is off" "0,1"
newline
bitfld.long 0x00 10. "GPU_SLEEP,Put the GPU power domain (PD_GPU) in powerdown" "0,1"
newline
bitfld.long 0x00 9. "CTRL_SLEEP,Put the Controller power domain (PD_CTRL) in powerdown" "0,1"
newline
bitfld.long 0x00 8. "ENABLE_CLKLESS,Selects the clockless sleep mode" "0,1"
newline
bitfld.long 0x00 7. "RETAIN_CACHE,Selects the retainability of the cache block during deep sleep" "0,1"
newline
bitfld.long 0x00 6. "SYS_SLEEP,Put the System powerdomain (PD_SYS) in powerdown" "0,1"
newline
bitfld.long 0x00 5. "RESET_ON_WAKEUP,Perform a Hardware Reset after waking up" "0,1"
newline
bitfld.long 0x00 3. "SNC_SLEEP,Put the Communications powerdomain (PD_SNC) in powerdown" "0,1"
newline
bitfld.long 0x00 2. "TIM_SLEEP,Put the Timers Powerdomain (PD_TIM) in powerdown" "0,1"
newline
bitfld.long 0x00 1. "RADIO_SLEEP,Put the digital part of the radio including CMAC (PD_RAD) in powerdown" "0,1"
newline
bitfld.long 0x00 0. "AUD_SLEEP,Put the audio power domain (PD_AUD) in powerdown" "0,1"
group.long 0xF4++0x03
line.long 0x00 "PMU_SLEEP_REG,Configures the sleep/wakeup strategy"
bitfld.long 0x00 31. "ULTRA_FAST_WAKEUP,Allows the core to start running on the RC32M while the PMU is still waiting for supplies to settle to the final value" "0,1"
newline
bitfld.long 0x00 30. "ENABLE_FAST_SWITCH,Enables early clock switching upon event detection to speed up wakeup time" "0,1"
newline
hexmask.long.byte 0x00 23.--29. 1. "VLED_BYPASS_REFRESH_TIME,This setting determines how long the VLED bypass switch is closed when VSYS near VLED flag and VLED VNOK flag are asserted in sleep"
newline
bitfld.long 0x00 19.--22. "BOD_SLEEP_INTERVAL,This is the interval at which the BOD comparators/POR will be checked during sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 5.--18. 1. "RAILS_REFRESH_INTERVAL,This is the interval at which the power rails reference voltage will be refreshed during sleep"
newline
bitfld.long 0x00 0.--4. "BASE_REFRESH_INTERVAL,This sets the base time for calculating the intervals at which PMU refreshes during sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xD0++0x03
line.long 0x00 "PMU_TRIM_REG,"
bitfld.long 0x00 8.--10. "IBIAS_10N_TRIM," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--7. "LDO_RET_V30_TRIM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LDO_V30_TRIM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x94++0x03
line.long 0x00 "POR_CTRL_REG,Controls the POR on VBAT"
bitfld.long 0x00 11. "POR_VSYS_SLEEP_CYCLE_EN,Enables POR_VSYS during BOD check cycles in sleep (If POR_VSYS_DISABLE = 0)" "0,1"
newline
bitfld.long 0x00 10. "POR_VSYS_HYST_SEL,Selects POR_VSYS threshold level when hysteresis is disabled (see POR_VSYS_DISABLE)" "0: Vthres = VTH_L (low level),1: Vthres = VTH_H (high level)"
newline
bitfld.long 0x00 9. "POR_VSYS_HYST_DISABLE,Disable POR_VSYS hysteresis" "0,1"
newline
bitfld.long 0x00 8. "POR_VSYS_FORCE_ON,FORCE POR_VSYS to be ON (also in SLEEP)" "0,1"
newline
bitfld.long 0x00 7. "POR_VSYS_MASK,Mask POR on VSYS" "0,1"
newline
bitfld.long 0x00 6. "POR_VSYS_DISABLE,Disable POR_VSYS" "0,1"
newline
bitfld.long 0x00 5. "POR_V30_SLEEP_CYCLE_EN,Enables POR_V30 during BOD check cycles in sleep (If POR_V30_DISABLE = 0)" "0,1"
newline
bitfld.long 0x00 4. "POR_V30_HYST_SEL,Selects POR_VDDA_3V0 threshold level when hysteresis is disabled (see POR_VDDA_3V0_HYST_DISABLE)" "0: Vthres = VTH_L (low level),1: Vthres = VTH_H (high level)"
newline
bitfld.long 0x00 3. "POR_V30_HYST_DISABLE,Disable POR_VDDA_3V0 hysteresis select level with POR_VDDA_3V0_HYST_SEL" "0,1"
newline
bitfld.long 0x00 2. "POR_V30_FORCE_ON,Force POR_VDDA_3V0 always ON (also in SLEEP)" "0,1"
newline
bitfld.long 0x00 1. "POR_V30_MASK,Mask POR_VDDA_3V0" "0,1"
newline
bitfld.long 0x00 0. "POR_V30_DISABLE,Disable POR_VDDA_3V0" "0,1"
group.long 0x98++0x03
line.long 0x00 "POR_PIN_REG,Selects a GPIO pin for POR generation"
bitfld.long 0x00 7. "POR_PIN_POLARITY," "0,1"
newline
abitfld.long 0x00 0.--6. "POR_PIN_SELECT," "0x1F=31: P0_31,0x20=32: P1_00,0x3F=63: P1_31,0x40=64: P2_00,0x4E=78: P2_14 0x4F to,0x7E=126: reserved,0x7F=127: POR generation disabled"
group.long 0x9C++0x03
line.long 0x00 "POR_TIMER_REG,Time for POR to happen"
hexmask.long.byte 0x00 0.--6. 1. "POR_TIME,Time for the POReset to happen"
group.long 0xF0++0x03
line.long 0x00 "POWER_CTRL_REG,Power control register"
bitfld.long 0x00 19. "SW_V18F_SLEEP_ON,Closes the V18F switch in sleep when DCDC_V18P_SLEEP_EN is 1" "0,1"
newline
bitfld.long 0x00 18. "SW_V18F_ON,Closes the V18F switch when DCDC_V18P_EN is 1" "0,1"
newline
bitfld.long 0x00 17. "DCDC_VLED_SLEEP_EN,Enables boost dcdc led rail in sleep mode" "0,1"
newline
bitfld.long 0x00 16. "DCDC_VLED_EN,Enables boost dcdc led rail in active mode" "0,1"
newline
bitfld.long 0x00 15. "DCDC_V18P_SLEEP_EN,Enables buck dcdc V18p rail in sleep mode" "0,1"
newline
bitfld.long 0x00 14. "DCDC_V18P_EN,Enables buck dcdc V18p rail in active mode" "0,1"
newline
bitfld.long 0x00 13. "DCDC_V18_SLEEP_EN,Enables buck dcdc V18 rail in sleep mode" "0,1"
newline
bitfld.long 0x00 12. "DCDC_V18_EN,Enables buck dcdc V18 rail in active mode" "0,1"
newline
bitfld.long 0x00 11. "DCDC_V14_SLEEP_EN,Enables buck dcdc V14 rail in sleep mode" "0,1"
newline
bitfld.long 0x00 10. "DCDC_V14_EN,Enables buck dcdc V14 rail in active mode" "0,1"
newline
bitfld.long 0x00 9. "DCDC_V12_SLEEP_EN,Enables buck dcdc V12 rail in sleep mode" "0,1"
newline
bitfld.long 0x00 8. "DCDC_V12_EN,Enables buck dcdc V12 rail in active mode" "0,1"
newline
bitfld.long 0x00 7. "CLAMP_V12_DIS,Disables V12 clamp" "0,1"
newline
bitfld.long 0x00 6. "CLAMP_V30_EN,Enables V30 clamp" "0,1"
newline
bitfld.long 0x00 5. "LDO_MIPI_EN,Enables ldo MIPI when DCDC_V18P_EN is 1" "0,1"
newline
bitfld.long 0x00 4. "LDO_RET_V30_SLEEP_EN,Enables ldo V30 ret in sleep mode" "0,1"
newline
bitfld.long 0x00 3. "LDO_RET_V30_EN,Enables ldo V30 ret in active mode" "0,1"
newline
bitfld.long 0x00 2. "LDO_V30_SLEEP_EN,Enables ldo V30 in sleep mode" "0,1"
newline
bitfld.long 0x00 1. "LDO_V30_EN,Enables ldo V30 in active mode" "0,1"
newline
bitfld.long 0x00 0. "LDO_START_EN,Enables ldo start" "0,1"
group.long 0xF8++0x03
line.long 0x00 "POWER_LVL_REG,"
bitfld.long 0x00 17.--18. "VSYS_LEVEL,Level setting for VSYS rail when ldo_vsys is enabled (COMP_VBUS_OK & COMP_VBUS_ABOVE_VSYS)" "0,1,2,3"
newline
bitfld.long 0x00 16. "V18_LEVEL,Level setting for V18 rail" "0,1"
newline
bitfld.long 0x00 14.--15. "V14_LEVEL,Level setting for V14 rail" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "V12_SLEEP_LEVEL,Level setting for V12 rail in sleep" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "V12_LEVEL,Level setting for V12 rail" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "V30_SLEEP_LEVEL,Level setting for V30 in sleep" "0: 3.0V,1: reserved,2: 3.3V,3: 3.3V"
newline
bitfld.long 0x00 6.--7. "V30_LEVEL,Level setting for V30" "0: 3.0V,1: reserved,2: 3.3V,3: 3.3V"
newline
bitfld.long 0x00 3.--5. "VMIPI_LEVEL,LDO MIPI level: 0.9V+0.05V*LDO_MIPI_LEVEL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "CLAMP_V12_LEVEL,Level setting for V12 clamp retained in hibernation (only V12 source in Hibernation)" "0,1,2,3,4,5,6,7"
group.long 0xC0++0x03
line.long 0x00 "RAM_PWR_CTRL_REG,Control power state of System RAMS"
bitfld.long 0x00 26.--27. "RAM13_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 24.--25. "RAM12_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "RAM11_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "RAM10_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "RAM9_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "RAM8_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "RAM7_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "RAM6_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "RAM5_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "RAM4_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "RAM3_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "RAM2_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "RAM1_PWR_CTRL,See description of RAM0_PWR_CTRL" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "RAM0_PWR_CTRL,Power state control of the individual RAMs" "0: Retained,1: Off (memory content,2: Retained,3: Off (memory content"
group.long 0xBC++0x03
line.long 0x00 "RESET_STAT_REG,Reset status register"
bitfld.long 0x00 6. "SNC_WDOGRESET_STAT,Indicates that a SNC-Watchdog timeout has happened" "0,1"
newline
bitfld.long 0x00 5. "CMAC_WDOGRESET_STAT,Indicates that a CMAC-Watchdog timeout has happened" "0,1"
newline
bitfld.long 0x00 4. "SWD_HWRESET_STAT,Indicates that a write to SWD_RESET_REG has happened" "0,1"
newline
bitfld.long 0x00 3. "WDOGRESET_STAT,Indicates that a Watchdog timeout has happened" "0,1"
newline
bitfld.long 0x00 2. "SWRESET_STAT,Indicates that a SW Reset has happened" "0,1"
newline
bitfld.long 0x00 1. "HWRESET_STAT,Indicates that a HW Reset has happened" "0,1"
newline
bitfld.long 0x00 0. "PORESET_STAT,Indicates that a PowerOn Reset has happened" "0,1"
group.long 0x0C++0x03
line.long 0x00 "RST_CTRL_REG,Reset control register"
bitfld.long 0x00 0. "SYS_CACHE_FLUSH_WITH_SW_RESET," "0,1"
group.long 0xCC++0x03
line.long 0x00 "SECURE_BOOT_REG,Controls secure booting"
bitfld.long 0x00 9. "PROT_OTP_CS_WRITE,This bit will permanentlly disable any write action to the CS inside the OTP" "0,1"
newline
bitfld.long 0x00 8. "FORCE_SNC_DEBUGGER_OFF,This bit will permanently disable the SNC debugger" "0,1"
newline
bitfld.long 0x00 7. "PROT_OQSPIF_KEY_READ,This bit will permanently disable CPU read capability at OTP offset 0x00000B00 and for the complete segment" "0,1"
newline
bitfld.long 0x00 6. "PROT_OQSPIF_KEY_WRITE,This bit will permanently disable ANY write capability at OTP offset 0x00000B00 and for the complete segment" "0,1"
newline
bitfld.long 0x00 5. "PROT_AES_KEY_READ,This bit will permanently disable CPU read capability at OTP offset 0x00000A00 and for the complete segment" "0,1"
newline
bitfld.long 0x00 4. "PROT_AES_KEY_WRITE,This bit will permanently disable ANY write capability at OTP offset 0x00000A00 and for the complete segment" "0,1"
newline
bitfld.long 0x00 3. "PROT_SIG_KEY_WRITE,This bit will permanently disable ANY write capability at OTP offset 0x000008C0 and for the complete segment" "0,1"
newline
bitfld.long 0x00 2. "FORCE_CMAC_DEBUGGER_OFF,This bit will permanently disable the CMAC debugger" "0,1"
newline
bitfld.long 0x00 1. "FORCE_DEBUGGER_OFF,Follows the respective OTP flag value" "0: The system debugger is enabled with,1: The system debugger SWD is totally disabled"
newline
bitfld.long 0x00 0. "SECURE_BOOT,Follows the respective OTP flag value" "0: system is not supporting secure boot,1: system is a secure system supporting secure.."
group.long 0x30++0x03
line.long 0x00 "SLP_MAP_REG,Map signals on GPIOs during sleep"
bitfld.long 0x00 8. "LCD_INV_EXT_CLK_SLP_MAP,Maps inverted LCD_EXT_CLK on P0_10 for LCD XFRP function This state is preserved during deep sleep to allow pin output toggle on the pad during deep sleep" "0,1"
newline
bitfld.long 0x00 7. "LCD_EXT_CLK_SLP_MAP,Maps LCD_EXT_CLK on P0_19 for LCD VCOM/FRP/EXTCOMIN function This state is preserved during deep sleep to allow pin output toggle on the pad during deep sleep" "0,1"
newline
bitfld.long 0x00 6. "BANDGAP_SLP_MAP,Setting this bit will: -map bandgap_enable to P0_13 -map (wokenup OR cmac_slp_timer_expire) to P1_06" "0,1"
newline
bitfld.long 0x00 5. "RCLP_SLP_MAP,Maps RCLP onto P1_23" "0,1"
newline
bitfld.long 0x00 4. "XTAL32K_SLP_MAP,Maps XTA32k onto P0_31" "0,1"
newline
bitfld.long 0x00 3. "RCX_SLP_MAP,Maps RCX onto P1_22" "0,1"
newline
bitfld.long 0x00 2. "TMR4_PWM_SLP_MAP,Maps Timer4_pwm onto P1_31 This state is preserved during deep sleep to allow pin output toggle on the pad during deep sleep" "0,1"
newline
bitfld.long 0x00 1. "TMR3_PWM_SLP_MAP,Maps Timer3_pwm onto P1_30 This state is preserved during deep sleep to allow pin output toggle on the pad during deep sleep" "0,1"
newline
bitfld.long 0x00 0. "TMR_PWM_SLP_MAP,Maps Timer1_pwm onto P0_30 This state is preserved during deep sleep to allow pin output toggle on the pad during deep sleep" "0,1"
group.long 0xE4++0x03
line.long 0x00 "SW_V18F_REG,"
bitfld.long 0x00 2.--3. "DELAY_TRIM,Soft start delay trim" "0,1,2,3"
newline
bitfld.long 0x00 1. "SKIP_SOFT_START,Skip soft start routine" "0,1"
newline
bitfld.long 0x00 0. "FORCE_SW_ON,Forces closing sw_V18f independent of v18p state" "0,1"
group.long 0x24++0x03
line.long 0x00 "SYS_CTRL_REG,System Control register"
bitfld.long 0x00 15. "SW_RESET,Writing a '1' to this bit will generate a SW_RESET" "0,1"
newline
bitfld.long 0x00 10. "CACHERAM_MUX,Controls accessiblity of Cache RAM" "0: the cache controller is bypassed the cacheRAM..,1: the cache controller is enabled the cacheRAM is"
newline
bitfld.long 0x00 9. "TIMEOUT_DISABLE,Disables timeout in Power statemachine" "0,1"
newline
bitfld.long 0x00 7. "DEBUGGER_ENABLE,Enable the debugger" "0,1"
newline
bitfld.long 0x00 5. "SNC_DEBUGGER_ENABLE,Enable the CMAC debugger" "0,1"
newline
bitfld.long 0x00 3. "REMAP_INTVECT," "0,1"
newline
bitfld.long 0x00 0.--2. "REMAP_ADR0,Controls which memory is located at address 0x0000 for execution" "0: ROM,1: DWord (64 bits) access is not supported by the,2: DMA access is not supported by the Cache Data,3: RAMS un-cached,4: OQSPI FLASH un-cached (for verification only),5: SYSRAM3 (for SNC-based applications where SNC,6: Cache Data RAM un-cached (CACHERAM_MUX=0 for,?..."
group.long 0x28++0x03
line.long 0x00 "SYS_STAT_REG,System status register"
rbitfld.long 0x00 17. "GPU_IS_UP,Indicates that PD_GPU is functional" "0,1"
newline
rbitfld.long 0x00 16. "GPU_IS_DOWN,Indicates that PD_GPU is in power down" "0,1"
newline
rbitfld.long 0x00 15. "CTRL_IS_UP,Indicates that PD_CTRL is functional" "0,1"
newline
rbitfld.long 0x00 14. "CTRL_IS_DOWN,Indicates that PD_CTRL is in power down" "0,1"
newline
rbitfld.long 0x00 13. "POWER_IS_UP,Indicates that the Startup statemachine is finished and all power regulation is in order" "0,1"
newline
rbitfld.long 0x00 12. "DBG_IS_ACTIVE,Indicates that a debugger is attached" "0,1"
newline
rbitfld.long 0x00 11. "SNC_IS_UP,Indicates that PD_SNC is functional" "0,1"
newline
rbitfld.long 0x00 10. "SNC_IS_DOWN,Indicates that PD_SNC is in power down" "0,1"
newline
rbitfld.long 0x00 9. "TIM_IS_UP,Indicates that PD_TIM is functional" "0,1"
newline
rbitfld.long 0x00 8. "TIM_IS_DOWN,Indicates that PD_TIM is in power down" "0,1"
newline
rbitfld.long 0x00 7. "MEM_IS_UP,Indicates that PD_MEM is functional" "0,1"
newline
rbitfld.long 0x00 6. "MEM_IS_DOWN,Indicates that PD_MEM is in power down" "0,1"
newline
rbitfld.long 0x00 5. "SYS_IS_UP,Indicates that PD_SYS is functional" "0,1"
newline
rbitfld.long 0x00 4. "SYS_IS_DOWN,Indicates that PD_SYS is in power down" "0,1"
newline
rbitfld.long 0x00 3. "AUD_IS_UP,Indicates that PD_AUD is functional" "0,1"
newline
rbitfld.long 0x00 2. "AUD_IS_DOWN,Indicates that PD_AUD is in power down" "0,1"
newline
rbitfld.long 0x00 1. "RAD_IS_UP,Indicates that PD_RAD is functional" "0,1"
newline
rbitfld.long 0x00 0. "RAD_IS_DOWN,Indicates that PD_RAD is in power down" "0,1"
group.long 0x58++0x03
line.long 0x00 "VBUS_IRQ_CLEAR_REG,Clear pending IRQ register"
hexmask.long.word 0x00 0.--15. 1. "VBUS_IRQ_CLEAR,Writing any value to this register will reset the VBUS_IRQ line"
group.long 0x54++0x03
line.long 0x00 "VBUS_IRQ_MASK_REG,IRQ masking"
bitfld.long 0x00 2. "VBUS_WAKEUP_CLKLESS,Enables waking up from CLKLESS mode when VBUS becomes available" "0,1"
newline
bitfld.long 0x00 1. "VBUS_IRQ_EN_RISE,Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to ramp above threshold" "0,1"
newline
bitfld.long 0x00 0. "VBUS_IRQ_EN_FALL,Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to fall below threshold" "0,1"
group.long 0xE0++0x03
line.long 0x00 "WAKEUP_HIBERN_REG,"
bitfld.long 0x00 12. "HIBERNATION_ENABLE,Enable hibernation mode" "0,1"
newline
bitfld.long 0x00 6.--9. "WAKEUP_PD_EN,Enables pulldown for GPIO[n] during hibernation Bit" "0: P0_20 Bit,1: P0_29 Bit,2: P1_04 Bit,3: P0_28,?..."
newline
bitfld.long 0x00 0.--3. "WAKEUP_EN,Enables GPIO[n] to wake up from hibernation Bit" "0: P0_20 Bit,1: P0_29 Bit,2: P1_04 Bit,3: P0_28,?..."
tree.end
tree "CRG_VSYS"
base ad:0x50000B00
group.long 0x00++0x03
line.long 0x00 "VSYS_GEN_CTRL_REG,"
bitfld.long 0x00 23.--24. "FORCE_VBAT_VSYS_SW,0x0" "?,1: VBAT_VSYS set to ideal diode,2: Forces VBAT_VSYS switch to be opened,3: Forces VBAT_VSYS switch to be closed"
newline
bitfld.long 0x00 21.--22. "FORCE_LDO_ENABLE,0x0" "?,1: LDO VSYS will be enabled when COMP_VBUS_OK &,2: LDO_VSYS will be disabled regardless of VBUS..,3: LDO_VSYS will be enabled regardless of VBUS.."
newline
bitfld.long 0x00 19.--20. "LDO_TEMP_PROTECT_MODE," "?,1: LDO_VSYS is muted (disabled) when temperature..,2: LDO_VSYS is not muted (disabled) when,3: Force LDO_VSYS mute"
newline
bitfld.long 0x00 18. "EN_HEADROOM,Enables the voltage headroom loop in the LDO_VSYS" "0,1"
newline
bitfld.long 0x00 13.--17. "CURLIM_OFFSET_TRIM,For adjusting the offset of the curlim range ( +/- 78 mA)" "0: maximum positive offset,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: minimal offset ( reset value),?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: maximum negative offset"
newline
bitfld.long 0x00 8.--12. "CURLIM_GAIN_TRIM,For adjusting the gain of the curlim range ( +/- 20%)" "0: maximum gain,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: nominal gain ( reset value),?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: minimum gain"
newline
abitfld.long 0x00 1.--7. "CURLIM_SET,Sets the level of the LDO_VSYS current limiter in 10 mA steps" "0x00=0: 1270 mA,0x01=1: 1260 mA,0x76=118: 90 mA ( reset value)"
newline
bitfld.long 0x00 0. "EN_CURLIM,Enables the current limiter in the LDO_VSYS" "0,1"
group.long 0x08++0x03
line.long 0x00 "VSYS_GEN_IRQ_CLEAR_REG,"
bitfld.long 0x00 1. "VBUS_LOW_DRIVE_IRQ_CLEAR,Clears VBUS_LOW_DRIVE_IRQ" "0,1"
newline
bitfld.long 0x00 0. "LDO_VSYS_HIGH_TEMP_IRQ_CLEAR,Clears LDO_VSYS_HIGH_TEMP_IRQ" "0,1"
group.long 0x0C++0x03
line.long 0x00 "VSYS_GEN_IRQ_MASK_REG,"
bitfld.long 0x00 1. "VBUS_LOW_DRIVE_IRQ_MASK,Masks VBUS_LOW_DRIVE_IRQ interrupt" "0,1"
newline
bitfld.long 0x00 0. "LDO_VSYS_HIGH_TEMP_IRQ_MASK,Masks LDO_VSYS_HIGH_TEMP_IRQ interrupt" "0,1"
group.long 0x04++0x03
line.long 0x00 "VSYS_GEN_IRQ_STATUS_REG,"
bitfld.long 0x00 1. "VBUS_LOW_DRIVE_IRQ_STATUS,Indicates vbus drive strength is not enough to keep vbus up with the set limit of ldo_vbus" "0,1"
newline
bitfld.long 0x00 0. "LDO_VSYS_HIGH_TEMP_IRQ_STATUS,Indicates that a high temperature has been detected at ldo_vsys" "0,1"
tree.end
tree "CRG_XTAL"
base ad:0x50050400
group.long 0x60++0x03
line.long 0x00 "PLL_SYS_CTRL1_REG,System PLL control register 1"
bitfld.long 0x00 15. "PLL_OUT_DIV," "0,1"
bitfld.long 0x00 14. "PLL_SEL_MIN_CUR_INT," "0,1"
newline
bitfld.long 0x00 11. "PLL_PRE_DIV,PLL input divider (1: Indicates divide by 2)" "0,1"
hexmask.long.byte 0x00 4.--10. 1. "PLL_N_DIV,PLL loop divider N (x means divide by x 0 means divide by 1)"
newline
bitfld.long 0x00 3. "LDO_PLL_VREF_HOLD," "0,1"
bitfld.long 0x00 2. "LDO_PLL_ENABLE," "0,1"
newline
bitfld.long 0x00 1. "PLL_RST_N," "0,1"
bitfld.long 0x00 0. "PLL_EN," "0,1"
group.long 0x64++0x03
line.long 0x00 "PLL_SYS_CTRL2_REG,System PLL control register 2"
bitfld.long 0x00 15. "PLL_RECALIB,Recalibrate" "0,1"
group.long 0x68++0x03
line.long 0x00 "PLL_SYS_CTRL3_REG,System PLL control register 3"
bitfld.long 0x00 1.--6. "PLL_MIN_CURRENT,VCO current trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x70++0x03
line.long 0x00 "PLL_SYS_STATUS_REG,System PLL status register"
rbitfld.long 0x00 15. "LDO_PLL_OK," "0,1"
rbitfld.long 0x00 11. "PLL_CALIBRATION_END,Indicates that calibration has finished" "0,1"
newline
rbitfld.long 0x00 5.--10. "PLL_BEST_MIN_CUR,Calibrated VCO current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 0. "PLL_LOCK_FINE," "0,1"
group.long 0x74++0x03
line.long 0x00 "PLL_USB_CTRL1_REG,USB PLL control register 1"
bitfld.long 0x00 15. "PLL_OUT_DIV," "0,1"
bitfld.long 0x00 14. "PLL_SEL_MIN_CUR_INT," "0,1"
newline
bitfld.long 0x00 11. "PLL_PRE_DIV,PLL input divider (1: Indicates divide by 2)" "0,1"
hexmask.long.byte 0x00 4.--10. 1. "PLL_N_DIV,PLL loop divider N (x means divide by x 0 means divide by 1)"
newline
bitfld.long 0x00 3. "LDO_PLL_VREF_HOLD," "0,1"
bitfld.long 0x00 2. "LDO_PLL_ENABLE," "0,1"
newline
bitfld.long 0x00 1. "PLL_RST_N," "0,1"
bitfld.long 0x00 0. "PLL_EN," "0,1"
group.long 0x78++0x03
line.long 0x00 "PLL_USB_CTRL2_REG,USB PLL control register 2"
bitfld.long 0x00 15. "PLL_RECALIB,Recalibrate" "0,1"
group.long 0x7C++0x03
line.long 0x00 "PLL_USB_CTRL3_REG,USB PLL control register 3"
bitfld.long 0x00 1.--6. "PLL_MIN_CURRENT,VCO current trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "PLL_USB_STATUS_REG,USB PLL status register"
rbitfld.long 0x00 15. "LDO_PLL_OK," "0,1"
rbitfld.long 0x00 11. "PLL_CALIBRATION_END,Indicates that calibration has finished" "0,1"
newline
rbitfld.long 0x00 5.--10. "PLL_BEST_MIN_CUR,Calibrated VCO current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 0. "PLL_LOCK_FINE," "0,1"
group.long 0x98++0x03
line.long 0x00 "RESET_SYS_IRQ_CTRL_REG,System IRQ RESET register"
bitfld.long 0x00 5. "CMAC2SNC_IRQ_BIT," "0,1"
bitfld.long 0x00 4. "CMAC2SYS_IRQ_BIT," "0,1"
newline
bitfld.long 0x00 3. "SNC2SYS_IRQ_BIT," "0,1"
bitfld.long 0x00 2. "SNC2CMAC_IRQ_BIT," "0,1"
newline
bitfld.long 0x00 1. "SYS2SNC_IRQ_BIT," "0,1"
bitfld.long 0x00 0. "SYS2CMAC_IRQ_BIT," "0,1"
group.long 0x94++0x03
line.long 0x00 "SET_SYS_IRQ_CTRL_REG,System IRQ SET register"
bitfld.long 0x00 5. "CMAC2SNC_IRQ_BIT," "0,1"
bitfld.long 0x00 4. "CMAC2SYS_IRQ_BIT," "0,1"
newline
bitfld.long 0x00 3. "SNC2SYS_IRQ_BIT," "0,1"
bitfld.long 0x00 2. "SNC2CMAC_IRQ_BIT," "0,1"
newline
bitfld.long 0x00 1. "SYS2SNC_IRQ_BIT," "0,1"
bitfld.long 0x00 0. "SYS2CMAC_IRQ_BIT," "0,1"
group.long 0x90++0x03
line.long 0x00 "SYS_IRQ_CTRL_REG,System IRQ control register"
bitfld.long 0x00 5. "CMAC2SNC_IRQ_BIT," "0,1"
bitfld.long 0x00 4. "CMAC2SYS_IRQ_BIT," "0,1"
newline
bitfld.long 0x00 3. "SNC2SYS_IRQ_BIT," "0,1"
bitfld.long 0x00 2. "SNC2CMAC_IRQ_BIT," "0,1"
newline
bitfld.long 0x00 1. "SYS2SNC_IRQ_BIT," "0,1"
bitfld.long 0x00 0. "SYS2CMAC_IRQ_BIT," "0,1"
group.long 0x0C++0x03
line.long 0x00 "XTAL32M_CAP_MEAS_REG,Capacitance measure circuit control"
bitfld.long 0x00 6.--8. "XTAL32M_MEAS_TIME,Select measurement time (in DIVN clock-cycles)" "0: 32,1: 64,?,?,?,?,6: 2048,7: 4096"
bitfld.long 0x00 5. "XTAL32M_MEAS_START,Starts capacitance measurement" "0,1"
newline
bitfld.long 0x00 3.--4. "XTAL32M_MEAS_CUR,Select measurement current (minimum required capacitance)" "0: 100nA (0.44pF),1: 500nA (2.22pF),2: 1uA (4.44pF),3: 5uA (22.2pF)"
bitfld.long 0x00 0.--2. "XTAL32M_CAP_SELECT,Select measured capacitance" "0: disabled,1: hold capacitance,2: xtal_p,3: xtal_n,4: xtal_p + xtal_n,5: low reference on xtal_p,6: low reference on xtal_p,?..."
group.long 0x14++0x03
line.long 0x00 "XTAL32M_CTRL_REG,Xtal32m control register"
bitfld.long 0x00 9.--11. "XTAL32M_DRIVE_CYCLES,Number of drive clock-cycles" "0: Drive,1: 4,2: 8,3: 16,4: 32,5: 64 0x6:128,?..."
bitfld.long 0x00 8. "XTAL32M_ENABLE,Enables xtal32m (testing purposes)" "0,1"
newline
bitfld.long 0x00 6.--7. "XTAL32M_BIASPROT,Bias startup circuit" "0: enable during startup,1: always enabled,2: always disabled,?..."
bitfld.long 0x00 4.--5. "XTAL32M_LDO_SAH,Controls amplitude regulator sample-and-hold" "0: set to HOLD when IRQ fires,1: always TRACK 2'b1x,?..."
newline
bitfld.long 0x00 2.--3. "XTAL32M_AMPREG_SAH,Controls amplitude regulator sample-and-hold" "0: set to HOLD when IRQ fires,1: always TRACK 2'b1x,?..."
bitfld.long 0x00 0.--1. "XTAL32M_BIAS_SAH,Controls bias sample-and-hold" "0: set to HOLD when IRQ fires,1: always TRACK 2'b1x,?..."
group.long 0x10++0x03
line.long 0x00 "XTAL32M_FSM_REG,Startup state machine configuration"
bitfld.long 0x00 5. "XTAL32M_BOOST_MODE,Boost mode configuration" "0: Only allow BOOST mode in START state,1: Allow BOOST mode in SETTLE and START state"
bitfld.long 0x00 4. "XTAL32M_FSM_APPLY_CONFIG,CUR_SET AMPL_SET CMP_LVL and TRIM from XTAL32M_TRIM_REG are" "0: applied at next startup,1: immediately applied"
newline
bitfld.long 0x00 3. "XTAL32M_FSM_FORCE_IDLE,Forces FSM in IDLE state allows for software control" "0,1"
bitfld.long 0x00 2. "XTAL32M_CMP_MODE,Use following comparator trim settings in SETTLE state" "0: XTAL32M_TRIM_REG.CMP_LVL,1: XTAL32M_SETTLE_REG.CMP_LVL"
newline
bitfld.long 0x00 1. "XTAL32M_TRIM_MODE,Use following trimsetting in the SETTLE state" "0: XTAL32M_TRIM_REG.TRIM,1: XTAL32M_SETTLE_REG.TRIM"
bitfld.long 0x00 0. "XTAL32M_CUR_MODE,Use the following current setting in the SETTLE state" "0: XTAL32M_START_REG.CUR_SET,1: XTAL32M_SETTLE_REG.CUR_SET"
group.long 0x18++0x03
line.long 0x00 "XTAL32M_IRQ_CTRL_REG,Xtal32m Interrupt control register"
bitfld.long 0x00 10.--11. "XTAL32M_IRQ_CAP_CTRL,The IRQ counter is captured in the XTAL32M_IRQ_STATUS_REG.IRQ_COUNT_CAP when leaving the following state" "0: START,1: SETTLE,2: RUN,?..."
bitfld.long 0x00 9. "XTAL32M_IRQ_ENABLE,Enable xtal interrupt generation" "0,1"
newline
bitfld.long 0x00 8. "XTAL32M_IRQ_CLK,Clock divider for IRQ counter" "0: 4us,1: 32us"
hexmask.long.byte 0x00 0.--7. 1. "XTAL32M_IRQ_CNT,IRQ counter start value"
group.long 0x28++0x03
line.long 0x00 "XTAL32M_IRQ_STAT_REG,XTAL32M IRQ status register"
hexmask.long.byte 0x00 8.--15. 1. "XTAL32M_IRQ_COUNT_CAP,Captured IRQ counter"
hexmask.long.byte 0x00 0.--7. 1. "XTAL32M_IRQ_COUNT_STAT,Current IRQ counter value"
group.long 0x04++0x03
line.long 0x00 "XTAL32M_SETTLE_REG,Trim values for XTAL32M in SETTLE state of startup"
abitfld.long 0x00 22.--28. "XTAL32M_TIMEOUT,Timeout" "0x00=0: disabled,0x01=1: 4us,0x02=2: 8us,0x3F=63: 252us,0x40=64: 268us,0x7F=127: 1260us"
bitfld.long 0x00 19.--21. "XTAL32M_CMP_BLANK,Blanking time for comparator output" "0: disabled,1: 4us,2: 8us,3: 16us,4: 32us,5: 64us,?..."
newline
bitfld.long 0x00 17.--18. "XTAL32M_CMP_LVL,Comparator triplevel" "0: 30%,1: 35%,2: 45%,3: 60%"
bitfld.long 0x00 14.--16. "XTAL32M_AMPL_SET,Amplitude Regulator input level setting (peak-peak) in SETTLE phase of startup" "0: 300mV,1: 350mV,?,?,?,?,?,7: 900mV"
newline
bitfld.long 0x00 10.--13. "XTAL32M_CUR_SET,Current setting (units of 16uA) in SETTLE phase of startup" "0: OFF,1: 1x,2: 2x,3: 3x,4: 4x,5: 6x,6: 8x,7: 12x,8: 16x,9: 24x,10: 32x,11: 48x,12: 64x,13: 96x,14: 128x,15: 192x"
hexmask.long.word 0x00 0.--9. 1. "XTAL32M_TRIM,Capacitance bank seting in SETLLE phase of startup CL = 3.5pF + 50fF/LSB"
group.long 0x00++0x03
line.long 0x00 "XTAL32M_START_REG,Trim values for XTAL32M in START state of startup"
abitfld.long 0x00 22.--28. "XTAL32M_TIMEOUT,Timeout" "0x00=0: disabled,0x01=1: 4us,0x02=2: 8us,0x3F=63: 252us,0x40=64: 268us,0x7F=127: 1260us"
bitfld.long 0x00 19.--21. "XTAL32M_CMP_BLANK,Blanking time for comparator output" "0: disabled,1: 4us,2: 8us,3: 16us,4: 32us,5: 64us,?..."
newline
bitfld.long 0x00 17.--18. "XTAL32M_CMP_LVL,Comparator triplevel" "0: 30%,1: 35%,2: 45%,3: 60%"
bitfld.long 0x00 14.--16. "XTAL32M_AMPL_SET,Amplitude Regulator input level setting (peak-peak) in START phase of startup" "0: 300mV,1: 350mV,?,?,?,?,?,7: 900mV"
newline
bitfld.long 0x00 10.--13. "XTAL32M_CUR_SET,Current setting (units of 16uA) in START phase of startup" "0: OFF,1: 1x,2: 2x,3: 3x,4: 4x,5: 6x,6: 8x,7: 12x,8: 16x,9: 24x,10: 32x,11: 48x,12: 64x,13: 96x,14: 128x,15: 192x"
hexmask.long.word 0x00 0.--9. 1. "XTAL32M_TRIM,Capacitance bank seting in START phase of startup CL = 3.5pF + 50fF/LSB"
group.long 0x24++0x03
line.long 0x00 "XTAL32M_STAT0_REG,XTAL32M status register"
rbitfld.long 0x00 29. "XTAL32M_OVERLOAD,Indicates xtal is overloaded" "0,1"
rbitfld.long 0x00 27.--28. "XTAL32M_CMP_LVL_STAT,Current value for amplitude regulator comparator setting" "0,1,2,3"
newline
rbitfld.long 0x00 24.--26. "XTAL32M_AMPL_TRIM,Current value for amplitude trim" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 14.--23. 1. "XTAL32M_TRIM_VAL,Current value for oscillator trimming"
newline
rbitfld.long 0x00 10.--13. "XTAL32M_CUR_SET_STAT,Current value for cur_set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 9. "XTAL32M_LDO_OK,Indicates LDO voltage level is ok" "0,1"
newline
rbitfld.long 0x00 7.--8. "XTAL32M_CMP_OUT,Amplitude regulator comparator output state" "0,1,2,3"
rbitfld.long 0x00 3.--6. "XTAL32M_STATE,State of xtal startup FSM" "0: IDLE,1: WAIT_LDO,2: WAIT_BIAS,3: XTAL_DRIVE,4: START_BLANK,5: START,6: SETTLE_BLANK,7: SETTLE,8: RUN,9: CAP_TEST_IDLE,10: CAP_TEST_MEAS,11: CAP_TEST_END,?..."
newline
rbitfld.long 0x00 1.--2. "XTAL32M_CMP_OUT_HOLD,Captured state of amplitude regulator comparators at IRQ fire" "0,1,2,3"
rbitfld.long 0x00 0. "XTAL32M_READY,Indicates xtal startup FSM has reached the RUNNIG state and is ready for use (sysclk)" "0,1"
group.long 0x08++0x03
line.long 0x00 "XTAL32M_TRIM_REG,Trim values for XTAL32M in RUNNING state"
bitfld.long 0x00 19.--24. "XTAL32M_BOOST_TRIM,Boost trimming set accordingly to shunt capacitance" "0: Boost Disabled,1: 250fF,2: 375fF,3: 500fF,4: 625fF,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: 7.875pF,63: 8pF"
bitfld.long 0x00 17.--18. "XTAL32M_CMP_LVL,Comparator triplevel" "0: 30%,1: 35%,2: 45%,3: 60%"
newline
bitfld.long 0x00 14.--16. "XTAL32M_AMPL_SET,Amplitude Regulator input level setting (peak-peak) in running phase" "0: 300mV,1: 350mV,?,?,?,?,?,7: 900mV"
bitfld.long 0x00 10.--13. "XTAL32M_CUR_SET,Current setting (units of 16uA) in running phase" "0: OFF,1: 1x,2: 2x,3: 3x,4: 4x,5: 6x,6: 8x,7: 12x,8: 16x,9: 24x,10: 32x,11: 48x,12: 64x,13: 96x,14: 128x,15: 192x"
newline
hexmask.long.word 0x00 0.--9. 1. "XTAL32M_TRIM,Capacitance bank seting in running phase use to trim the xtal32m output frequency CL = 3.5pF + 50fF/LSB"
tree.end
tree.end
tree "DCACHE"
base ad:0x30100000
group.long 0x04++0x03
line.long 0x00 "DCACHE_BASE_ADDR_REG,Dcache base address for cacheable region"
hexmask.long.tbyte 0x00 0.--16. 1. "DCACHE_BASE_ADDR,Base of PSRAM cacheable memory N*1kByte"
group.long 0x00++0x03
line.long 0x00 "DCACHE_CTRL_REG,Dcache Control register"
bitfld.long 0x00 25. "DCACHE_DISABLE_CLKGATE,Disable the clockgating for the DCACHE" "0: Enable clockgating (default),1: Disable clockgating"
newline
bitfld.long 0x00 24. "DCACHE_WBUFFER_FLUSH,Write buffer flush" "0: Write buffer isn't flushed (default),1: Write buffer is flushed"
newline
rbitfld.long 0x00 23. "DCACHE_WBUFFER_EMPTY,Status of the write buffer" "0: Write buffer isn't empty,1: Write buffer is empty"
newline
bitfld.long 0x00 22. "DCACHE_WFLUSHED," "0,1"
newline
rbitfld.long 0x00 21. "DCACHE_READY," "0,1"
newline
bitfld.long 0x00 20. "DCACHE_WFLUSH,Write a '1' to this field will trigger a write flush of the 'dirty' lines" "0,1"
newline
bitfld.long 0x00 19. "DCACHE_INIT,Write a '1' to this field will trigger an initialization of the cache ('0's are written in the TAG area)" "0,1"
newline
bitfld.long 0x00 18. "DCACHE_ENABLE,Enable the dcache controller HW block" "0: Disabled all AHB accesses towards the QSPI are,1: Enabled all AHB access towards the QSPI within"
newline
hexmask.long.tbyte 0x00 0.--17. 1. "DCACHE_LEN,Length of PSRAM cacheable memory N*1kByte"
group.long 0x14++0x03
line.long 0x00 "DCACHE_MRM_CTRL_REG,Dcache MRM (Miss Rate Monitor) CONTROL register"
bitfld.long 0x00 5. "MRM_IRQ_EVICTS_THRES_STATUS," "0,1"
newline
bitfld.long 0x00 4. "MRM_IRQ_HITS_THRES_STATUS," "0,1"
newline
bitfld.long 0x00 3. "MRM_IRQ_MISSES_THRES_STATUS," "0,1"
newline
bitfld.long 0x00 2. "MRM_IRQ_TINT_STATUS," "0,1"
newline
bitfld.long 0x00 1. "MRM_IRQ_MASK," "0,1"
newline
bitfld.long 0x00 0. "MRM_START," "0,1"
group.long 0x10++0x03
line.long 0x00 "DCACHE_MRM_EVICTS_REG,Dcache MRM (Miss Rate Monitor) EVICTS register"
hexmask.long 0x00 0.--31. 1. "MRM_EVICTS,Contains the amount of cache evicts"
group.long 0x24++0x03
line.long 0x00 "DCACHE_MRM_EVICTS_THRES_REG,Dcache MRM (Miss Rate Monitor) EVICTS THRESHOLD register"
hexmask.long 0x00 0.--31. 1. "MRM_EVICTS_THRES,Defines the hits threshold to trigger the interrupt generation"
group.long 0x08++0x03
line.long 0x00 "DCACHE_MRM_HITS_REG,Dcache MRM (Miss Rate Monitor) HITS register"
hexmask.long 0x00 0.--31. 1. "MRM_HITS,Contains the amount of cache hits"
group.long 0x20++0x03
line.long 0x00 "DCACHE_MRM_HITS_THRES_REG,Dcache MRM (Miss Rate Monitor) HITS THRESHOLD register"
hexmask.long 0x00 0.--31. 1. "MRM_HITS_THRES,Defines the hits threshold to trigger the interrupt generation"
group.long 0x0C++0x03
line.long 0x00 "DCACHE_MRM_MISSES_REG,Dcache MRM (Miss Rate Monitor) MISSES register"
hexmask.long 0x00 0.--31. 1. "MRM_MISSES,Contains the amount of cache misses"
group.long 0x1C++0x03
line.long 0x00 "DCACHE_MRM_MISSES_THRES_REG,Dcache MRM (Miss Rate Monitor) THRESHOLD register"
hexmask.long 0x00 0.--31. 1. "MRM_MISSES_THRES,Defines the misses threshold to trigger the interrupt generation"
group.long 0x18++0x03
line.long 0x00 "DCACHE_MRM_TINT_REG,Dcache MRM (Miss Rate Monitor) TIME INTERVAL register"
hexmask.long.tbyte 0x00 0.--18. 1. "MRM_TINT,Defines the time interval for the monitoring in 32 MHz clock cycles"
tree.end
tree "DCDC"
base ad:0x50000300
group.long 0x00++0x03
line.long 0x00 "BUCK_CTRL_REG,"
bitfld.long 0x00 14.--15. "CFG_TIMEOUT,Sets maximum switch on-time" "0: Disabled,1: 0.5 ms,2: 1.0 ms (Default),3: 1.5 ms"
bitfld.long 0x00 13. "EN_FREEWHEEL,Enables freewheel switch when converter is idle" "0,1"
bitfld.long 0x00 10.--12. "TRIM_BIAS,Bias current trim" "0: -21 %,1: -14 %,2: -7 %,3: +0 % (Default),4: +7 %,5: +14 %,6: +21 %,7: +28 %"
bitfld.long 0x00 5.--7. "CFG_IMAX_UPPER,Sets upper value of inductor peak current limit control" "0: 260 mA,1: 400 mA,2: 530 mA,3: 660 mA,4: 790 mA,5: 920 mA,6: 1060 mA (Default),7: 1190 mA"
newline
bitfld.long 0x00 2.--4. "CFG_IMAX_LOWER,Sets lower value of inductor peak current limit control" "0: 260 mA (Default),1: 400 mA,2: 530 mA,3: 660 mA,4: 790 mA,5: 920 mA,6: 1060 mA,7: 1190 mA"
bitfld.long 0x00 0.--1. "CFG_HYST,Controls hysteresis on output comparator" "0: 6 mV (Default),1: 9 mV,2: 12 mV,3: 15 mV"
tree.end
tree "DCDC_BOOST"
base ad:0x50000500
group.long 0x08++0x03
line.long 0x00 "BOOST_CTRL_REG0,"
bitfld.long 0x00 17.--20. "BOOST_TIMEOUT_TRIG_DELAY,Delay before generating next comparator clock after a timeout event on the P switch allows inductor current to drop to zero" "0: Disabled,1: 250 ns,2: 500 ns,3: 750 ns,4: 1000 ns (default),5: 1250 ns,6: 1500 ns,7: 1750 ns,8: 2000 ns,9: 2250 ns,10: 2500 ns,11: 2750 ns,12: 3000 ns,13: 3250 ns,14: 3500 ns,15: 3750 ns"
bitfld.long 0x00 13.--16. "BOOST_PSW_TIMEOUT,P switch timeout if switch is closed longer than this a timeout is generated and the FSM is forced to the next state" "0: Disabled,1: 250 ns,2: 500 ns,3: 750 ns,4: 1000 ns,5: 1250 ns,6: 1500 ns,7: 1750 ns,8: 2000 ns (default),9: 2250 ns,10: 2500 ns,11: 2750 ns,12: 3000 ns,13: 3250 ns,14: 3500 ns,15: 3750 ns"
newline
bitfld.long 0x00 9.--12. "BOOST_NSW_TIMEOUT,N switch timeout if switch is closed longer than this a timeout is generated and the FSM is forced to the next state" "0: Disabled,1: 125 ns,2: 250 ns,3: 375 ns,4: 500 ns,5: 625 ns,6: 750 ns (default),7: 875 ns,8: 1000 ns,9: 1125 ns,10: 1250 ns,11: 1375 ns,12: 1500 ns,13: 1625 ns,14: 1750 ns,15: 1875 ms"
bitfld.long 0x00 7.--8. "BOOST_OK_CLR_COUNT,Number of subsequent V_NOK events before BOOST_VLED_OK is reset" "0: 2,1: 4,2: 8,3: 15"
newline
bitfld.long 0x00 5.--6. "BOOST_IDLE_CLK_DIV,Determines times between comparator samples when converter is idle" "0: 250 ns,1: 500 ns (default),2: 1000 ns,3: 2000 ns"
bitfld.long 0x00 2.--4. "BOOST_VLED_TRIM,Trim setting for boost converter sets deviation from nominal output voltage (4 V)" "0: -75 mV,1: -50 mV,2: -25 mV,3: 0 mV (default),4: 25 mV,5: 50 mV,6: 75 mV,7: 100 mV"
newline
bitfld.long 0x00 0.--1. "BOOST_VLED_SEL,Voltage selection for boost converter sets nominal output voltage" "0: 4.50V (default),1: 4.75V,2: 5.00V,3: 5.00V"
group.long 0x0C++0x03
line.long 0x00 "BOOST_CTRL_REG1,"
bitfld.long 0x00 17. "BOOST_CUR_LIM_SLEEP_FIXED,Enable fixed current iso dynamic current in sleep mode" "0: Use dynamic current control,1: Use fixed current as defined in"
bitfld.long 0x00 12.--16. "BOOST_CUR_LIM_SLEEP,Fixed inductor peak current limit in sleep mode I = 30 mA * (1 + N) default 960 mA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--11. "BOOST_CUR_LIM_STEP,Step size taken by automatic inductor peak current limit control" "0: 0 (disabled),1: 1,2: 2 (default),3: 3"
bitfld.long 0x00 5.--9. "BOOST_CUR_LIM_MAX,Maximum inductor peak current limit I = 30 mA * (1 + N) default 960 mA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "BOOST_CUR_LIM_MIN,Minimum inductor peak current limit I = 30 mA * (1 + N) default 150 mA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "BOOST_STATUS_REG,"
rbitfld.long 0x00 18.--23. "BOOST_COMP_TRIM,Actual P side comparator trim value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 17. "BOOST_IDLE,Converter idle" "0,1"
newline
rbitfld.long 0x00 12.--16. "BOOST_CUR_LIM,Actual inductor peak current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 11. "BOOST_COMP_P_DYN_P,P output of P side dynamic comparator" "0,1"
newline
rbitfld.long 0x00 10. "BOOST_COMP_P_DYN_N,N output of P side dynamic comparator" "0,1"
rbitfld.long 0x00 9. "BOOST_COMP_P_CONT,Output of P side continuous time comparator" "0,1"
newline
rbitfld.long 0x00 8. "BOOST_COMP_N_CONT,Output of N side continuous time comparator" "0,1"
rbitfld.long 0x00 7. "BOOST_TIMEOUT_PSW,Timeout on P switch occurred" "0,1"
newline
rbitfld.long 0x00 6. "BOOST_TIMEOUT_NSW,Timeout on N switch occurred" "0,1"
rbitfld.long 0x00 5. "BOOST_VOUT_NOK,NOK output of output voltage comparator" "0,1"
newline
rbitfld.long 0x00 4. "BOOST_VOUT_OK,OK output of output voltage comparator" "0,1"
rbitfld.long 0x00 2.--3. "BOOST_SW_STATE,State of boost converter switches" "0: Both off,1: P switch on,2: N switch on,3: Undefined"
newline
rbitfld.long 0x00 1. "BOOST_STARTUP_COMPLETE,Indicates if the converter is enabled and the startup counter has expired (internal biasing settled)" "0,1"
rbitfld.long 0x00 0. "BOOST_VLED_OK,Indicates that V_LED is above its threshold reset after too many subsequent V_NOK events" "0,1"
group.long 0x10++0x03
line.long 0x00 "BOOST_TEST_CTRL_REG,"
bitfld.long 0x00 27.--28. "BOOST_ILOAD_SEL_TEST,Test mode control for 20mA test-mux" "0: All switches open (Default),1: Sink 20mA from LX for testing PMOS,2: Sink 20mA from V_LED,3: Source 20mA into LX for testing NMOS"
bitfld.long 0x00 22.--23. "BOOST_LSSUP_TRIM,Trim low side supply voltage V = 2 V + 300 mV * N default 2.9 V" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "BOOST_HSGND_TRIM,Trim high side ground V = VBAT - (2 V + 400 mV * N) default VBAT - 3.2 V" "0,1,2,3"
group.long 0x00++0x03
line.long 0x00 "VLED_PWR_CTRL_REG,"
bitfld.long 0x00 11.--12. "VLED_PWR_FORCE,Manual selection of VLED supply source requires that VLED_PWR_MANUAL = 0x1" "0: VLED not powered,1: VLED powered by VSYS,2: VLED powered by boost converter,3: N.A"
bitfld.long 0x00 10. "VLED_PWR_MANUAL," "0,1"
newline
bitfld.long 0x00 9. "VLED_PWR_USE_VSYS_LVL,Sets the condition for powering VLED from VSYS" "0: VLED always powered from VSYS,1: VLED powered form VSYS if VSYS is near VLED"
bitfld.long 0x00 8. "VLED_PWR_ENABLE," "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "VSYS_OK_DEBOUNCE,Sets debounce time on VSYS comparator in steps of 1.024 ms Note: actual delay can be up to one period of 1.024 ms clock shorter than programmed depending on alignment of comparator trip event and clock edge"
group.long 0x04++0x03
line.long 0x00 "VLED_PWR_STATUS_REG,"
rbitfld.long 0x00 5. "VLED_PWR_ALLOW_BOOST,Indicates whether boost converter is blocked or not" "0,1"
rbitfld.long 0x00 4. "VLED_PWR_VSYS_CONNECTED,Indicates that VSYS switch is closed" "0,1"
newline
rbitfld.long 0x00 2.--3. "VLED_PWR_SWITCH_CTRL_STATE,State of the VLED power control FSM" "0: Disabled,1: VSYS,2: Boost,3: N.A"
rbitfld.long 0x00 1. "VSYS_OK_DEBOUNCED,Output of VSYS OK debounce logic" "0,1"
newline
rbitfld.long 0x00 0. "VSYS_OK,Output of VSYS OK logic" "0,1"
tree.end
tree "DMA"
base ad:0x51000400
group.long 0x00++0x03
line.long 0x00 "DMA0_A_START_REG,Source address register of DMA channel 0"
hexmask.long 0x00 0.--31. 1. "DMA0_A_START,Source start address of channel 0"
group.long 0x04++0x03
line.long 0x00 "DMA0_B_START_REG,Destination address register of DMA channel 0"
hexmask.long 0x00 0.--31. 1. "DMA0_B_START,Destination start address of channel 0"
group.long 0x10++0x03
line.long 0x00 "DMA0_CTRL_REG,Control register of DMA channel 0"
bitfld.long 0x00 16. "DMA_EXCLUSIVE_ACCESS," "0,1"
newline
bitfld.long 0x00 15. "BUS_ERROR_DETECT," "0,1"
newline
bitfld.long 0x00 13.--14. "BURST_MODE,Enables the DMA read/write bursts according to the following configuration" "0: Bursts are disabled,1: Bursts of 4 are enabled,2: Bursts of 8 are enabled,3: Reserved"
newline
bitfld.long 0x00 12. "REQ_SENSE," "0,1"
newline
bitfld.long 0x00 11. "DMA_INIT," "0,1"
newline
bitfld.long 0x00 10. "DMA_IDLE," "0,1"
newline
bitfld.long 0x00 7.--9. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
newline
bitfld.long 0x00 6. "CIRCULAR," "0,1"
newline
bitfld.long 0x00 5. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
newline
bitfld.long 0x00 4. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.long 0x00 3. "DREQ_MODE," "0,1"
newline
bitfld.long 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
newline
bitfld.long 0x00 0. "DMA_ON," "0,1"
group.long 0x14++0x03
line.long 0x00 "DMA0_IDX_REG,Index pointer register of DMA channel 0"
hexmask.long.word 0x00 0.--15. 1. "DMA0_IDX,This (read-only) register determines the data items already transferred by the DMA channel"
group.long 0x08++0x03
line.long 0x00 "DMA0_INT_REG,Interrupt length register of DMA channel 0"
hexmask.long.word 0x00 0.--15. 1. "DMA0_INT,Number of transfers until an interrupt is generated"
group.long 0x0C++0x03
line.long 0x00 "DMA0_LEN_REG,Transfer length register of DMA channel 0"
hexmask.long.word 0x00 0.--15. 1. "DMA0_LEN,DMA channel's transfer length"
group.long 0x20++0x03
line.long 0x00 "DMA1_A_START_REG,Source address register of DMA channel 1"
hexmask.long 0x00 0.--31. 1. "DMA1_A_START,Source start address of channel 1"
group.long 0x24++0x03
line.long 0x00 "DMA1_B_START_REG,Destination address register of DMA channel 1"
hexmask.long 0x00 0.--31. 1. "DMA1_B_START,Destination start address of channel 1"
group.long 0x30++0x03
line.long 0x00 "DMA1_CTRL_REG,Control register of DMA channel 1"
bitfld.long 0x00 16. "DMA_EXCLUSIVE_ACCESS," "0,1"
newline
bitfld.long 0x00 15. "BUS_ERROR_DETECT," "0,1"
newline
bitfld.long 0x00 13.--14. "BURST_MODE,Enables the DMA read/write bursts according to the following configuration" "0: Bursts are disabled,1: Bursts of 4 are enabled,2: Bursts of 8 are enabled,3: Reserved"
newline
bitfld.long 0x00 12. "REQ_SENSE," "0,1"
newline
bitfld.long 0x00 11. "DMA_INIT," "0,1"
newline
bitfld.long 0x00 10. "DMA_IDLE," "0,1"
newline
bitfld.long 0x00 7.--9. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
newline
bitfld.long 0x00 6. "CIRCULAR," "0,1"
newline
bitfld.long 0x00 5. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
newline
bitfld.long 0x00 4. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.long 0x00 3. "DREQ_MODE," "0,1"
newline
bitfld.long 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
newline
bitfld.long 0x00 0. "DMA_ON," "0,1"
group.long 0x34++0x03
line.long 0x00 "DMA1_IDX_REG,Index pointer register of DMA channel 1"
hexmask.long.word 0x00 0.--15. 1. "DMA1_IDX,This (read-only) register determines the data items already transferred by the DMA channel"
group.long 0x28++0x03
line.long 0x00 "DMA1_INT_REG,Interrupt length register of DMA channel 1"
hexmask.long.word 0x00 0.--15. 1. "DMA1_INT,Number of transfers until an interrupt is generated"
group.long 0x2C++0x03
line.long 0x00 "DMA1_LEN_REG,Transfer length register of DMA channel 1"
hexmask.long.word 0x00 0.--15. 1. "DMA1_LEN,DMA channel's transfer length"
group.long 0x40++0x03
line.long 0x00 "DMA2_A_START_REG,Source address register of DMA channel 2"
hexmask.long 0x00 0.--31. 1. "DMA2_A_START,Source start address of channel 2"
group.long 0x44++0x03
line.long 0x00 "DMA2_B_START_REG,Destination address register of DMA channel 2"
hexmask.long 0x00 0.--31. 1. "DMA2_B_START,Destination start address of channel 2"
group.long 0x50++0x03
line.long 0x00 "DMA2_CTRL_REG,Control register of DMA channel 2"
bitfld.long 0x00 16. "DMA_EXCLUSIVE_ACCESS," "0,1"
newline
bitfld.long 0x00 15. "BUS_ERROR_DETECT," "0,1"
newline
bitfld.long 0x00 13.--14. "BURST_MODE,Enables the DMA read/write bursts according to the following configuration" "0: Bursts are disabled,1: Bursts of 4 are enabled,2: Bursts of 8 are enabled,3: Reserved"
newline
bitfld.long 0x00 12. "REQ_SENSE," "0,1"
newline
bitfld.long 0x00 11. "DMA_INIT," "0,1"
newline
bitfld.long 0x00 10. "DMA_IDLE," "0,1"
newline
bitfld.long 0x00 7.--9. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
newline
bitfld.long 0x00 6. "CIRCULAR," "0,1"
newline
bitfld.long 0x00 5. "AINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.long 0x00 4. "BINC,Enable increment of destination address" "0: do not increment,1: increment according value of BW"
newline
bitfld.long 0x00 3. "DREQ_MODE," "0,1"
newline
bitfld.long 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
newline
bitfld.long 0x00 0. "DMA_ON," "0,1"
group.long 0x54++0x03
line.long 0x00 "DMA2_IDX_REG,Index pointer register of DMA channel 2"
hexmask.long.word 0x00 0.--15. 1. "DMA2_IDX,This (read-only) register determines the data items already transferred by the DMA channel"
group.long 0x48++0x03
line.long 0x00 "DMA2_INT_REG,Interrupt length register of DMA channel 2"
hexmask.long.word 0x00 0.--15. 1. "DMA2_INT,Number of transfers until an interrupt is generated"
group.long 0x4C++0x03
line.long 0x00 "DMA2_LEN_REG,Transfer length register of DMA channel 2"
hexmask.long.word 0x00 0.--15. 1. "DMA2_LEN,DMA channel's transfer length"
group.long 0x60++0x03
line.long 0x00 "DMA3_A_START_REG,Source address register of DMA channel 3"
hexmask.long 0x00 0.--31. 1. "DMA3_A_START,Source start address of channel 3"
group.long 0x64++0x03
line.long 0x00 "DMA3_B_START_REG,Destination address register of DMA channel 3"
hexmask.long 0x00 0.--31. 1. "DMA3_B_START,Destination start address of channel 3"
group.long 0x70++0x03
line.long 0x00 "DMA3_CTRL_REG,Control register of DMA channel 3"
bitfld.long 0x00 16. "DMA_EXCLUSIVE_ACCESS," "0,1"
newline
bitfld.long 0x00 15. "BUS_ERROR_DETECT," "0,1"
newline
bitfld.long 0x00 13.--14. "BURST_MODE,Enables the DMA read/write bursts according to the following configuration" "0: Bursts are disabled,1: Bursts of 4 are enabled,2: Bursts of 8 are enabled,3: Reserved"
newline
bitfld.long 0x00 12. "REQ_SENSE," "0,1"
newline
bitfld.long 0x00 11. "DMA_INIT," "0,1"
newline
bitfld.long 0x00 10. "DMA_IDLE," "0,1"
newline
bitfld.long 0x00 7.--9. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
newline
bitfld.long 0x00 6. "CIRCULAR," "0,1"
newline
bitfld.long 0x00 5. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
newline
bitfld.long 0x00 4. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.long 0x00 3. "DREQ_MODE," "0,1"
newline
bitfld.long 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
newline
bitfld.long 0x00 0. "DMA_ON," "0,1"
group.long 0x74++0x03
line.long 0x00 "DMA3_IDX_REG,Index pointer register of DMA channel 3"
hexmask.long.word 0x00 0.--15. 1. "DMA3_IDX,This (read-only) register determines the data items already transferred by the DMA channel"
group.long 0x68++0x03
line.long 0x00 "DMA3_INT_REG,Interrupt length register of DMA channel 3"
hexmask.long.word 0x00 0.--15. 1. "DMA3_INT,Number of transfers until an interrupt is generated"
group.long 0x6C++0x03
line.long 0x00 "DMA3_LEN_REG,Transfer length register of DMA channel 3"
hexmask.long.word 0x00 0.--15. 1. "DMA3_LEN,DMA channel's transfer length"
group.long 0x80++0x03
line.long 0x00 "DMA4_A_START_REG,Source address register of DMA channel 4"
hexmask.long 0x00 0.--31. 1. "DMA4_A_START,Source start address of channel 4"
group.long 0x84++0x03
line.long 0x00 "DMA4_B_START_REG,Destination address register of DMA channel 4"
hexmask.long 0x00 0.--31. 1. "DMA4_B_START,Destination start address of channel 4"
group.long 0x90++0x03
line.long 0x00 "DMA4_CTRL_REG,Control register of DMA channel 4"
bitfld.long 0x00 16. "DMA_EXCLUSIVE_ACCESS," "0,1"
newline
bitfld.long 0x00 15. "BUS_ERROR_DETECT," "0,1"
newline
bitfld.long 0x00 13.--14. "BURST_MODE,Enables the DMA read/write bursts according to the following configuration" "0: Bursts are disabled,1: Bursts of 4 are enabled,2: Bursts of 8 are enabled,3: Reserved"
newline
bitfld.long 0x00 12. "REQ_SENSE," "0,1"
newline
bitfld.long 0x00 11. "DMA_INIT," "0,1"
newline
bitfld.long 0x00 10. "DMA_IDLE," "0,1"
newline
bitfld.long 0x00 7.--9. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
newline
bitfld.long 0x00 6. "CIRCULAR," "0,1"
newline
bitfld.long 0x00 5. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
newline
bitfld.long 0x00 4. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.long 0x00 3. "DREQ_MODE," "0,1"
newline
bitfld.long 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
newline
bitfld.long 0x00 0. "DMA_ON," "0,1"
group.long 0x94++0x03
line.long 0x00 "DMA4_IDX_REG,Index pointer register of DMA channel 4"
hexmask.long.word 0x00 0.--15. 1. "DMA4_IDX,This (read-only) register determines the data items already transferred by the DMA channel"
group.long 0x88++0x03
line.long 0x00 "DMA4_INT_REG,Interrupt length register of DMA channel 4"
hexmask.long.word 0x00 0.--15. 1. "DMA4_INT,Number of transfers until an interrupt is generated"
group.long 0x8C++0x03
line.long 0x00 "DMA4_LEN_REG,Transfer length register of DMA channel 4"
hexmask.long.word 0x00 0.--15. 1. "DMA4_LEN,DMA channel's transfer length"
group.long 0xA0++0x03
line.long 0x00 "DMA5_A_START_REG,Source address register of DMA channel 5"
hexmask.long 0x00 0.--31. 1. "DMA5_A_START,Source start address of channel 5"
group.long 0xA4++0x03
line.long 0x00 "DMA5_B_START_REG,Destination address register of DMA channel 5"
hexmask.long 0x00 0.--31. 1. "DMA5_B_START,Destination start address of channel 5"
group.long 0xB0++0x03
line.long 0x00 "DMA5_CTRL_REG,Control register of DMA channel 5"
bitfld.long 0x00 16. "DMA_EXCLUSIVE_ACCESS," "0,1"
newline
bitfld.long 0x00 15. "BUS_ERROR_DETECT," "0,1"
newline
bitfld.long 0x00 13.--14. "BURST_MODE,Enables the DMA read/write bursts according to the following configuration" "0: Bursts are disabled,1: Bursts of 4 are enabled,2: Bursts of 8 are enabled,3: Reserved"
newline
bitfld.long 0x00 12. "REQ_SENSE," "0,1"
newline
bitfld.long 0x00 11. "DMA_INIT," "0,1"
newline
bitfld.long 0x00 10. "DMA_IDLE," "0,1"
newline
bitfld.long 0x00 7.--9. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
newline
bitfld.long 0x00 6. "CIRCULAR," "0,1"
newline
bitfld.long 0x00 5. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
newline
bitfld.long 0x00 4. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.long 0x00 3. "DREQ_MODE," "0,1"
newline
bitfld.long 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
newline
bitfld.long 0x00 0. "DMA_ON," "0,1"
group.long 0xB4++0x03
line.long 0x00 "DMA5_IDX_REG,Index pointer register of DMA channel 5"
hexmask.long.word 0x00 0.--15. 1. "DMA5_IDX,This (read-only) register determines the data items already transferred by the DMA channel"
group.long 0xA8++0x03
line.long 0x00 "DMA5_INT_REG,Interrupt length register of DMA channel 5"
hexmask.long.word 0x00 0.--15. 1. "DMA5_INT,Number of transfers until an interrupt is generated"
group.long 0xAC++0x03
line.long 0x00 "DMA5_LEN_REG,Transfer length register of DMA channel 5"
hexmask.long.word 0x00 0.--15. 1. "DMA5_LEN,DMA channel's transfer length"
group.long 0xC0++0x03
line.long 0x00 "DMA6_A_START_REG,Source address register of DMA channel 6"
hexmask.long 0x00 0.--31. 1. "DMA6_A_START,Source start address of channel 6"
group.long 0xC4++0x03
line.long 0x00 "DMA6_B_START_REG,Destination address register of DMA channel 6"
hexmask.long 0x00 0.--31. 1. "DMA6_B_START,Destination start address of channel 6"
group.long 0xD0++0x03
line.long 0x00 "DMA6_CTRL_REG,Control register of DMA channel 6"
bitfld.long 0x00 16. "DMA_EXCLUSIVE_ACCESS," "0,1"
newline
bitfld.long 0x00 15. "BUS_ERROR_DETECT," "0,1"
newline
bitfld.long 0x00 13.--14. "BURST_MODE,Enables the DMA read/write bursts according to the following configuration" "0: Bursts are disabled,1: Bursts of 4 are enabled,2: Bursts of 8 are enabled,3: Reserved"
newline
bitfld.long 0x00 12. "REQ_SENSE," "0,1"
newline
bitfld.long 0x00 11. "DMA_INIT," "0,1"
newline
bitfld.long 0x00 10. "DMA_IDLE," "0,1"
newline
bitfld.long 0x00 7.--9. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
newline
bitfld.long 0x00 6. "CIRCULAR," "0,1"
newline
bitfld.long 0x00 5. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
newline
bitfld.long 0x00 4. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.long 0x00 3. "DREQ_MODE," "0,1"
newline
bitfld.long 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
newline
bitfld.long 0x00 0. "DMA_ON," "0,1"
group.long 0xD4++0x03
line.long 0x00 "DMA6_IDX_REG,Index pointer register of DMA channel 6"
hexmask.long.word 0x00 0.--15. 1. "DMA6_IDX,This (read-only) register determines the data items already transferred by the DMA channel"
group.long 0xC8++0x03
line.long 0x00 "DMA6_INT_REG,Interrupt length register of DMA channel 6"
hexmask.long.word 0x00 0.--15. 1. "DMA6_INT,Number of transfers until an interrupt is generated"
group.long 0xCC++0x03
line.long 0x00 "DMA6_LEN_REG,Transfer length register of DMA channel 6"
hexmask.long.word 0x00 0.--15. 1. "DMA6_LEN,DMA channel's transfer length"
group.long 0xE0++0x03
line.long 0x00 "DMA7_A_START_REG,Source address register of DMA channel 7"
hexmask.long 0x00 0.--31. 1. "DMA7_A_START,Source start address of channel 7"
group.long 0xE4++0x03
line.long 0x00 "DMA7_B_START_REG,Destination address register of DMA channel 7"
hexmask.long 0x00 0.--31. 1. "DMA7_B_START,Destination start address of channel 7"
group.long 0xF0++0x03
line.long 0x00 "DMA7_CTRL_REG,Control register of DMA channel 7"
bitfld.long 0x00 16. "DMA_EXCLUSIVE_ACCESS," "0,1"
newline
bitfld.long 0x00 15. "BUS_ERROR_DETECT," "0,1"
newline
bitfld.long 0x00 13.--14. "BURST_MODE,Enables the DMA read/write bursts according to the following configuration" "0: Bursts are disabled,1: Bursts of 4 are enabled,2: Bursts of 8 are enabled,3: Reserved"
newline
bitfld.long 0x00 12. "REQ_SENSE," "0,1"
newline
bitfld.long 0x00 11. "DMA_INIT," "0,1"
newline
bitfld.long 0x00 10. "DMA_IDLE," "0,1"
newline
bitfld.long 0x00 7.--9. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
newline
bitfld.long 0x00 6. "CIRCULAR," "0,1"
newline
bitfld.long 0x00 5. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
newline
bitfld.long 0x00 4. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.long 0x00 3. "DREQ_MODE," "0,1"
newline
bitfld.long 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
newline
bitfld.long 0x00 0. "DMA_ON," "0,1"
group.long 0xF4++0x03
line.long 0x00 "DMA7_IDX_REG,Index pointer register of DMA channel 7"
hexmask.long.word 0x00 0.--15. 1. "DMA7_IDX,This (read-only) register determines the data items already transferred by the DMA channel"
group.long 0xE8++0x03
line.long 0x00 "DMA7_INT_REG,Interrupt length register of DMA channel 7"
hexmask.long.word 0x00 0.--15. 1. "DMA7_INT,Number of transfers until an interrupt is generated"
group.long 0xEC++0x03
line.long 0x00 "DMA7_LEN_REG,Transfer length register of DMA channel 7"
hexmask.long.word 0x00 0.--15. 1. "DMA7_LEN,DMA channel's transfer length"
group.long 0x108++0x03
line.long 0x00 "DMA_CLEAR_INT_REG,DMA Interrupt clear register"
bitfld.long 0x00 7. "DMA_RST_IRQ_CH7,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 7 writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 6. "DMA_RST_IRQ_CH6,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 6 writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 5. "DMA_RST_IRQ_CH5,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 5 writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 4. "DMA_RST_IRQ_CH4,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 4 writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 3. "DMA_RST_IRQ_CH3,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 3 writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 2. "DMA_RST_IRQ_CH2,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 2 writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 1. "DMA_RST_IRQ_CH1,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 1 writing a 0 will have no effect" "0,1"
newline
bitfld.long 0x00 0. "DMA_RST_IRQ_CH0,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 0 writing a 0 will have no effect" "0,1"
group.long 0x10C++0x03
line.long 0x00 "DMA_INT_MASK_REG,DMA Interrupt mask register"
bitfld.long 0x00 7. "DMA_IRQ_ENABLE7," "0,1"
newline
bitfld.long 0x00 6. "DMA_IRQ_ENABLE6," "0,1"
newline
bitfld.long 0x00 5. "DMA_IRQ_ENABLE5," "0,1"
newline
bitfld.long 0x00 4. "DMA_IRQ_ENABLE4," "0,1"
newline
bitfld.long 0x00 3. "DMA_IRQ_ENABLE3," "0,1"
newline
bitfld.long 0x00 2. "DMA_IRQ_ENABLE2," "0,1"
newline
bitfld.long 0x00 1. "DMA_IRQ_ENABLE1," "0,1"
newline
bitfld.long 0x00 0. "DMA_IRQ_ENABLE0," "0,1"
group.long 0x104++0x03
line.long 0x00 "DMA_INT_STATUS_REG,DMA Interrupt status register"
rbitfld.long 0x00 15. "DMA_BUS_ERR7," "0,1"
newline
rbitfld.long 0x00 14. "DMA_BUS_ERR6," "0,1"
newline
rbitfld.long 0x00 13. "DMA_BUS_ERR5," "0,1"
newline
rbitfld.long 0x00 12. "DMA_BUS_ERR4," "0,1"
newline
rbitfld.long 0x00 11. "DMA_BUS_ERR3," "0,1"
newline
rbitfld.long 0x00 10. "DMA_BUS_ERR2," "0,1"
newline
rbitfld.long 0x00 9. "DMA_BUS_ERR1," "0,1"
newline
rbitfld.long 0x00 8. "DMA_BUS_ERR0," "0,1"
newline
rbitfld.long 0x00 7. "DMA_IRQ_CH7," "0,1"
newline
rbitfld.long 0x00 6. "DMA_IRQ_CH6," "0,1"
newline
rbitfld.long 0x00 5. "DMA_IRQ_CH5," "0,1"
newline
rbitfld.long 0x00 4. "DMA_IRQ_CH4," "0,1"
newline
rbitfld.long 0x00 3. "DMA_IRQ_CH3," "0,1"
newline
rbitfld.long 0x00 2. "DMA_IRQ_CH2," "0,1"
newline
rbitfld.long 0x00 1. "DMA_IRQ_CH1," "0,1"
newline
rbitfld.long 0x00 0. "DMA_IRQ_CH0," "0,1"
group.long 0x100++0x03
line.long 0x00 "DMA_REQ_MUX_REG,DMA channels peripherals mapping register"
bitfld.long 0x00 12.--15. "DMA67_SEL,Select which combination of peripherals are mapped on the DMA channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "DMA45_SEL,Select which combination of peripherals are mapped on the DMA channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "DMA23_SEL,Select which combination of peripherals are mapped on the DMA channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DMA01_SEL,Select which combination of peripherals are mapped on the DMA channels" "0: SPI_rx / SPI_tx,1: SP2_rx / SPI2_tx,2: UART_rx / UART_tx,3: UART2_rx / UART2_tx,4: I2C_rx / I2C_tx,5: I2C2_rx / I2C2_tx,6: USB_rx / USB_tx,7: UART3_rx / UART3_tx,8: PCM / PCM,9: SRC_rx / SRC_tx,10: SPI3_rx / SPI3_tx,11: I2C3_rx / I2C3_tx,12: GP_ADC / APP_ADC,13: SRC2_rx / SRC2_tx,14: I3C_rx / I3C_tx,15: None"
group.long 0x114++0x03
line.long 0x00 "DMA_RESET_INT_MASK_REG,DMA Reset Interrupt mask register"
bitfld.long 0x00 7. "DMA_RESET_IRQ_ENABLE7,Writing a '1' will disable the IRQs in the DMA channel 7 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 6. "DMA_RESET_IRQ_ENABLE6,Writing a '1' will disable the IRQs in the DMA channel 6 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 5. "DMA_RESET_IRQ_ENABLE5,Writing a '1' will disable the IRQs in the DMA channel 5 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 4. "DMA_RESET_IRQ_ENABLE4,Writing a '1' will disable the IRQs in the DMA channel 4 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 3. "DMA_RESET_IRQ_ENABLE3,Writing a '1' will disable the IRQs in the DMA channel 3 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 2. "DMA_RESET_IRQ_ENABLE2,Writing a '1' will disable the IRQs in the DMA channel 2 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 1. "DMA_RESET_IRQ_ENABLE1,Writing a '1' will disable the IRQs in the DMA channel 1 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 0. "DMA_RESET_IRQ_ENABLE0,Writing a '1' will disable the IRQs in the DMA channel 0 writing a '0' has no effect" "0,1"
group.long 0x110++0x03
line.long 0x00 "DMA_SET_INT_MASK_REG,DMA Set Interrupt mask register"
bitfld.long 0x00 7. "DMA_SET_IRQ_ENABLE7,Writing a '1' will enable the IRQs in the DMA channel 7 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 6. "DMA_SET_IRQ_ENABLE6,Writing a '1' will enable the IRQs in the DMA channel 6 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 5. "DMA_SET_IRQ_ENABLE5,Writing a '1' will enable the IRQs in the DMA channel 5 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 4. "DMA_SET_IRQ_ENABLE4,Writing a '1' will enable the IRQs in the DMA channel 4 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 3. "DMA_SET_IRQ_ENABLE3,Writing a '1' will enable the IRQs in the DMA channel 3 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 2. "DMA_SET_IRQ_ENABLE2,Writing a '1' will enable the IRQs in the DMA channel 2 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 1. "DMA_SET_IRQ_ENABLE1,Writing a '1' will enable the IRQs in the DMA channel 1 writing a '0' has no effect" "0,1"
newline
bitfld.long 0x00 0. "DMA_SET_IRQ_ENABLE0,Writing a '1' will enable the IRQs in the DMA channel 0 writing a '0' has no effect" "0,1"
tree.end
tree "DSI2"
base ad:0x51001300
group.long 0x14++0x03
line.long 0x00 "DSI2_CFG_AUTOINSERT_EOTP_REG,"
bitfld.long 0x00 0. "AUTOINSERT_EOTP,Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode" "0,1"
group.long 0x28++0x03
line.long 0x00 "DSI2_CFG_BTA_H_TO_COUNT_REG,"
hexmask.long.tbyte 0x00 0.--23. 1. "BTA_H_TO_COUNT,Host Bust Turn Around (BTA) Timout"
group.long 0x60++0x03
line.long 0x00 "DSI2_CFG_CLK_LANE_EN_REG,"
bitfld.long 0x00 0. "CLK_LANE_EN,Forces PHY Enable n signals to 1'b1 when register is set to 1" "0,1"
group.long 0x04++0x03
line.long 0x00 "DSI2_CFG_CONTINUOUS_HS_CLK_REG,"
bitfld.long 0x00 0. "CONTINUOUS_HS_CLK,Sets the Host Controller into non-continuous MIPI clock mode" "0: Non-Continuous high speed clock,1: Continuous high speed clock"
group.long 0x64++0x03
line.long 0x00 "DSI2_CFG_DATA_LANE_EN_REG,"
bitfld.long 0x00 0.--1. "DATA_LANE_EN,Forces PHY Enable n signals to 1'b1 when register is set to 1" "0,1,2,3"
group.long 0x30++0x03
line.long 0x00 "DSI2_CFG_DISABLE_BURST_REG,"
bitfld.long 0x00 0. "DISABLE_BURST,Disables packets combined into a burst" "0,1"
group.long 0x1C++0x03
line.long 0x00 "DSI2_CFG_DISBL_RX_CRC_CHECK_REG,"
bitfld.long 0x00 0. "DISABLE_RX_CRC_CHECK,Prevents the Host from checking the payload CRC in long packets sent from the Peripheral" "0,1"
group.long 0x18++0x03
line.long 0x00 "DSI2_CFG_EXT_CMDS_AFT_EOTP_REG,"
hexmask.long.byte 0x00 0.--7. 1. "EXTRA_CMDS_AFTER_EOTP,Configures the DSI-2 Host Controller to send extra End Of Transmission Packets after the end of a packet"
group.long 0x20++0x03
line.long 0x00 "DSI2_CFG_HTX_TO_COUNT_REG,"
hexmask.long.tbyte 0x00 0.--23. 1. "HTX_TO_COUNT,Host HS TX Timeout count HS TX Timeout"
group.long 0x1A8++0x03
line.long 0x00 "DSI2_CFG_IRQ_MASK,Status of APB to packet interface reading will clear IRQ status 1 and 2"
bitfld.long 0x00 31. "IRQ_HS_TX_TIMEOUT,host bta timeout host controller host bta timeout port" "0,1"
bitfld.long 0x00 30. "IRQ_LP_RX_TIMEOUT,low power rx timeout host controller lp rx timeout port" "0,1"
newline
bitfld.long 0x00 29. "IRQ_HOST_BTA_TIMEOUT,high speed tx timeout host controller hs tx timeout port" "0,1"
hexmask.long.tbyte 0x00 9.--28. 1. "IRQ_MAP_DIRECTORY,map directory to dsi host controller status out port bit descriptions"
newline
bitfld.long 0x00 8. "IRQ_RX_PACKET_RCVD,All RX packet payload data has been received" "0,1"
bitfld.long 0x00 7. "IRQ_RX_HEADER_RCVD,RX packet header has been received" "0,1"
newline
bitfld.long 0x00 6. "IRQ_RX_FIFO_UNDERFLOW,RX fifo underflow" "0,1"
bitfld.long 0x00 5. "IRQ_RX_FIFO_OVERFLOW,RX fifo overflow" "0,1"
newline
bitfld.long 0x00 4. "IRQ_TX_FIFO_UNDERFLOW,TX fifo underflow" "0,1"
bitfld.long 0x00 3. "IRQ_TX_FIFO_OVERFLOW,TX fifo overflow" "0,1"
newline
bitfld.long 0x00 2. "IRQ_DPHY_DIRECTION,DPHY direction" "0: TX had control,1: RX has control"
bitfld.long 0x00 1. "IRQ_TX_DONE,TX packet done" "0,1"
newline
bitfld.long 0x00 0. "IRQ_STATE_NOT_IDLE,State machine not idle" "0,1"
group.long 0x1AC++0x03
line.long 0x00 "DSI2_CFG_IRQ_MASK2,Status of APB to packet interface part 2 read part 2 first then dsi2 host irq 2"
bitfld.long 0x00 2. "IRQ_CRC_ERROR,CRC error" "0,1"
bitfld.long 0x00 1. "IRQ_MULTI_BIT_ECC_ERROR,TX packet done" "0,1"
newline
bitfld.long 0x00 0. "IRQ_SINGLE_BIT_ECC_ERROR,Single bit ecc error" "0,1"
group.long 0x1A0++0x03
line.long 0x00 "DSI2_CFG_IRQ_STATUS,Status of APB to packet interface reading will clear IRQ status 1 and 2"
rbitfld.long 0x00 31. "IRQ_HS_TX_TIMEOUT,host bta timeout host controller host bta timeout port" "0,1"
rbitfld.long 0x00 30. "IRQ_LP_RX_TIMEOUT,low power rx timeout host controller lp rx timeout port" "0,1"
newline
rbitfld.long 0x00 29. "IRQ_HOST_BTA_TIMEOUT,high speed tx timeout host controller hs tx timeout port" "0,1"
hexmask.long.tbyte 0x00 9.--28. 1. "IRQ_MAP_DIRECTORY,map directory to dsi host controller status out port bit descriptions"
newline
rbitfld.long 0x00 8. "IRQ_RX_PACKET_RCVD,All RX packet payload data has been received" "0,1"
rbitfld.long 0x00 7. "IRQ_RX_HEADER_RCVD,RX packet header has been received" "0,1"
newline
rbitfld.long 0x00 6. "IRQ_RX_FIFO_UNDERFLOW,RX fifo underflow" "0,1"
rbitfld.long 0x00 5. "IRQ_RX_FIFO_OVERFLOW,RX fifo overflow" "0,1"
newline
rbitfld.long 0x00 4. "IRQ_TX_FIFO_UNDERFLOW,TX fifo underflow" "0,1"
rbitfld.long 0x00 3. "IRQ_TX_FIFO_OVERFLOW,TX fifo overflow" "0,1"
newline
rbitfld.long 0x00 2. "IRQ_DPHY_DIRECTION,DPHY direction" "0: TX had control,1: RX has control"
rbitfld.long 0x00 1. "IRQ_TX_DONE,TX packet done" "0,1"
newline
rbitfld.long 0x00 0. "IRQ_STATE_NOT_IDLE,State machine not idle" "0,1"
group.long 0x1A4++0x03
line.long 0x00 "DSI2_CFG_IRQ_STATUS2,Status of APB to packet interface part 2 read part 2 first then dsi2 host irq 2"
rbitfld.long 0x00 2. "IRQ_CRC_ERROR,CRC error" "0,1"
rbitfld.long 0x00 1. "IRQ_MULTI_BIT_ECC_ERROR,TX packet done" "0,1"
newline
rbitfld.long 0x00 0. "IRQ_SINGLE_BIT_ECC_ERROR,Single bit ecc error" "0,1"
group.long 0x24++0x03
line.long 0x00 "DSI2_CFG_LRX_H_TO_COUNT_REG,"
hexmask.long.tbyte 0x00 0.--23. 1. "LRX_H_TO_COUNT,Host Low Power RX Timeout LP_RX-H Timeout"
group.long 0x00++0x03
line.long 0x00 "DSI2_CFG_NUM_LANES_REG,configure numer of active lanes"
bitfld.long 0x00 0.--3. "NUM_LANES,Sets the number of active lanes that are to be used for transmitting data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x184++0x03
line.long 0x00 "DSI2_CFG_PACKET_CONTROL,Tx packet control register"
bitfld.long 0x00 26. "PKT_BTA_ONLY,Perform BTA only no packet tx" "0,1"
bitfld.long 0x00 25. "PKT_BTA_AFTER_SENT,Perform BTA after packet is sent" "0,1"
newline
bitfld.long 0x00 24. "PKT_LP_OR_HS,low power or high speed" "0,1"
bitfld.long 0x00 18.--23. "PKT_HEADER_DTYPE,Packet header DSI Data Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16.--17. "PKT_VC,Virtual channel" "0,1,2,3"
hexmask.long.word 0x00 0.--15. 1. "PKT_WC,Packet word count"
group.long 0x194++0x03
line.long 0x00 "DSI2_CFG_PKT_RD_LEVEL,Read level of APB to pkt interface fifo"
hexmask.long.word 0x00 0.--15. 1. "PKT_FIFO_RD_LEVEL,Read level of APB to pkt interface fifo"
group.long 0x19C++0x03
line.long 0x00 "DSI2_CFG_PKT_RX_HEADER,Packet 2 APB RX header"
rbitfld.long 0x00 18.--23. "PKT_RX_HEADER_DTYPE,Packet header DSI Data Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 16.--17. "PKT_RX_VC,Virtual channel" "0,1,2,3"
newline
hexmask.long.word 0x00 0.--15. 1. "PKT_RX_WC,Packet word count"
group.long 0x198++0x03
line.long 0x00 "DSI2_CFG_PKT_RX_PAYLOAD,Packet 2 APB RX payload"
hexmask.long 0x00 0.--31. 1. "PKT_PKT_RX_PAYLOAD,APB to pkt interface RX payload"
group.long 0x18C++0x03
line.long 0x00 "DSI2_CFG_PKT_STATUS,Status of APB to packet interface"
rbitfld.long 0x00 8. "PKT_RX_PACKET_RCVD,All RX packet payload data has been received" "0,1"
rbitfld.long 0x00 7. "PKT_RX_HEADER_RCVD,RX packet header has been received" "0,1"
newline
rbitfld.long 0x00 6. "PKT_RX_FIFO_UNDERFLOW,RX fifo underflow" "0,1"
rbitfld.long 0x00 5. "PKT_RX_FIFO_OVERFLOW,RX fifo overflow" "0,1"
newline
rbitfld.long 0x00 4. "PKT_TX_FIFO_UNDERFLOW,TX fifo underflow" "0,1"
rbitfld.long 0x00 3. "PKT_TX_FIFO_OVERFLOW,TX fifo overflow" "0,1"
newline
rbitfld.long 0x00 2. "PKT_DPHY_DIRECTION,DPHY direction" "0: TX had control,1: RX has control"
rbitfld.long 0x00 1. "PKT_TX_DONE,TX packet done" "0,1"
newline
rbitfld.long 0x00 0. "PKT_STATE_NOT_IDLE,State machine not idle" "0,1"
group.long 0x190++0x03
line.long 0x00 "DSI2_CFG_PKT_WR_LEVEL,Write level of APB to pkt interface fifo"
hexmask.long.word 0x00 0.--15. 1. "PKT_FIFO_WR_LEVEL,Write level of APB to pkt interface fifo"
group.long 0x44++0x03
line.long 0x00 "DSI2_CFG_RX_ERROR_STATUS_REG,"
rbitfld.long 0x00 10. "BTA_TIMEOUT,BTA timeout" "0,1"
rbitfld.long 0x00 9. "REV_LP_DATA_RX_TIMEOUT,Reverse Low Power Data receive timeout" "0,1"
newline
rbitfld.long 0x00 8. "HS_FWD_TX_TIMEOUT,High Speed forward TX timeout" "0,1"
rbitfld.long 0x00 7. "CRC_ERR,CRC error" "0,1"
newline
rbitfld.long 0x00 3.--6. "ECC_SINGLE_BIT_ERR_POS,Bit position for ECC single bit error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 1. "ECC_MULTI_BIT_ERR,ECC multi bit error" "0,1"
newline
rbitfld.long 0x00 0. "ECC_SINGLE_BIT_ERR,ECC single bit error" "0,1"
group.long 0x188++0x03
line.long 0x00 "DSI2_CFG_SEND_PACKET,Tx send packet"
bitfld.long 0x00 0. "CFG_SEND_PACKET,Tx send packet writing to this register causes the packet described in dsi2 host pkt control to be sent" "0,1"
group.long 0x40++0x03
line.long 0x00 "DSI2_CFG_STATUS_OUT_REG,Contains the status of the status register"
rbitfld.long 0x00 16.--19. "LAST_RCVD_TRIGGER,Last received Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 15. "DSI2_PROT_VIOLATION,Protocol violation error from peripheral error report cleared upon read" "0,1"
newline
rbitfld.long 0x00 13. "INVALID_TRANS_LENGTH,Transmission length error from peripheral error report cleared upon read" "0,1"
rbitfld.long 0x00 12. "DSI2_VC_ID_INVALID,Invalid VC from peripheral error report cleared upon read" "0,1"
newline
rbitfld.long 0x00 11. "DSI2_DT_NOT_RECOGNIZED,Invalid data type from peripheral error report cleared upon read" "0,1"
rbitfld.long 0x00 10. "LP_CHECKSUM_ERROR,Checksum error (long packet only) from peripheral error report cleared upon read" "0,1"
newline
rbitfld.long 0x00 9. "ECC_MULTI_BIT_ERROR,ECC multi-bit error from peripheral error report (not corrected) cleared upon read" "0,1"
rbitfld.long 0x00 8. "ECC_1BIT_ERROR,ECC single bit error from peripheral error report (and corrected) cleared upon read" "0,1"
newline
rbitfld.long 0x00 7. "CONTENTION_DETECTED,Contention Detection from peripheral error report cleared upon read" "0,1"
rbitfld.long 0x00 6. "FALSE_CTRL_ERROR,False Control Error from peripheral error report cleared upon read" "0,1"
newline
rbitfld.long 0x00 5. "PERIPH_TIMEOUT_ERROR,Peripheral Timeout error from peripheral error report cleared upon read" "0,1"
rbitfld.long 0x00 4. "LP_TRANS_SYNC_ERROR,Low Power Transmit Sync error from peripheral error report cleared upon read" "0,1"
newline
rbitfld.long 0x00 3. "ESC_MODE_ENTRY_CMD_ERROR,Escape Mode Entry Command Error from peripheral error report cleared upon read" "0,1"
rbitfld.long 0x00 2. "EOT_SYNC_ERROR,End of Transmission Sync Error from peripheral error report cleared upon read" "0,1"
newline
rbitfld.long 0x00 1. "SOT_SYNC_ERROR,Start of Transmission Sync Error from peripheral error report cleared upon read" "0,1"
rbitfld.long 0x00 0. "SOT_ERROR,Start of Transmission Error from peripheral error report cleared upon read" "0,1"
group.long 0x2C++0x03
line.long 0x00 "DSI2_CFG_TWAKEUP_REG,"
hexmask.long.tbyte 0x00 0.--18. 1. "TWAKEUP,PHY Twakeup timing parameter"
group.long 0x10++0x03
line.long 0x00 "DSI2_CFG_TX_GAP_REG,"
hexmask.long.byte 0x00 0.--7. 1. "TX_GAP,Sets the number of byte clock periods (clk input) that the controller will wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode again"
group.long 0x180++0x03
line.long 0x00 "DSI2_CFG_TX_PAYLOAD,TX Payload data write register"
hexmask.long 0x00 0.--31. 1. "CFG_TX_PAYLOAD,Tx Payload data write register"
group.long 0x0C++0x03
line.long 0x00 "DSI2_CFG_T_POST_REG,"
hexmask.long.byte 0x00 0.--7. 1. "T_POST,Sets the number of byte clock periods (clk input) to wait before putting the clock lane into LP mode after the data lanes have been put into LP mode"
group.long 0x08++0x03
line.long 0x00 "DSI2_CFG_T_PRE_REG,"
hexmask.long.byte 0x00 0.--7. 1. "T_PRE,Sets the number of byte clock periods (clk input) that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation"
group.long 0x140++0x03
line.long 0x00 "DSI2_CFG_VID_BLLP_MODE,"
bitfld.long 0x00 0. "VID_BLLP_MODE,Optimize bllp periods to Low Power mode when possible 0 blanking packets are sent during BLLP periods 1 LP mode is used for BLLP periods" "0,1"
group.long 0x100++0x03
line.long 0x00 "DSI2_CFG_VID_ENABLE,"
bitfld.long 0x00 0. "VID_ENABLE,Enables the video interface" "0: video interface off all packets go through rx,1: video interface on video packets routed out"
group.long 0x12C++0x03
line.long 0x00 "DSI2_CFG_VID_HBP,"
hexmask.long.word 0x00 0.--15. 1. "VID_HBP,Sets the DSI-2 packet payload size in bytes of the horizontal back porch blanking packet"
group.long 0x128++0x03
line.long 0x00 "DSI2_CFG_VID_HFP,"
hexmask.long.word 0x00 0.--15. 1. "VID_HFP,Sets the DSI-2 packet payload size in bytes of the horizontal front porch blanking packet"
group.long 0x130++0x03
line.long 0x00 "DSI2_CFG_VID_HSA,"
hexmask.long.word 0x00 0.--15. 1. "VID_HSA,Sets the DSI-2 packet payload size in bytes of the horizontal sync width filler blanking packet"
group.long 0x118++0x03
line.long 0x00 "DSI2_CFG_VID_HSYNC_POLARITY,"
bitfld.long 0x00 0. "VID_HSYNC_POLARITY,Sets Polarity of vid_hsync input 0 active low 1 active high" "0,1"
group.long 0x120++0x03
line.long 0x00 "DSI2_CFG_VID_OVERRIDE,"
bitfld.long 0x00 0. "VID_OVERRIDE,Overrides internal counters and uses values on configuration inputs" "0,1"
group.long 0x134++0x03
line.long 0x00 "DSI2_CFG_VID_PACKETS_P_LINE,"
bitfld.long 0x00 0.--2. "VID_PACKETS_P_LINE,Sets the number of packets that will be sent for a video line" "0,1,2,3,4,5,6,7"
group.long 0x10C++0x03
line.long 0x00 "DSI2_CFG_VID_PIX_ALIGNMENT,"
bitfld.long 0x00 0. "VID_PIX_ALIGNMENT,Some RGB modes can be aligned either MSB or LSB onto the video_pX[35:0] inputs" "0,1"
group.long 0x110++0x03
line.long 0x00 "DSI2_CFG_VID_PIX_FORMAT,"
bitfld.long 0x00 0.--5. "VID_PIX_FORMAT,Sets the DSI-2 packet type of the pixels" "?,?,?,?,?,?,?,?,?,?,?,?,12: Loosely Packed Pixel Stream 20-bit YCbCr 4:2:2,13: Packed Pixel Stream 30-bit RGB 10-10-10 format,14: Packed Pixel Stream 16-bit RGB 5-6-5 format,?,?,?,?,?,?,?,?,?,?,?,?,?,28: Packed Pixel Stream 24-bit YCbCr 4:2:2 format,29: Packed Pixel Stream 36-bit RGB 12-12-12 format,30: Packed Pixel Stream 18-bit RGB 6-6-6,?,?,?,?,?,?,?,?,?,?,?,?,?,44: Packed Pixel Stream 16-bit YCbCr 4:2:2 format,?,46: Loosely Packed Pixel Stream 18-bit RGB 6-6-6,?,?,?,?,?,?,?,?,?,?,?,?,?,?,61: Packed Pixel Stream 12-bit YCbCr 4:2:0 format,62: Packed Pixel Stream 24-bit RGB 8-8-8,?..."
group.long 0x108++0x03
line.long 0x00 "DSI2_CFG_VID_PIX_PAYLOAD_SIZE,"
hexmask.long.word 0x00 0.--15. 1. "VID_PIX_PAYLOAD_SIZE,The number of bytes in a video payload packet"
group.long 0x104++0x03
line.long 0x00 "DSI2_CFG_VID_PIX_P_PACKET,"
hexmask.long.word 0x00 0.--15. 1. "VID_PIX_P_PACKET,Sets the number of pixels that are sent in a packet for each video line"
group.long 0x124++0x03
line.long 0x00 "DSI2_CFG_VID_START_DELAY,"
hexmask.long.word 0x00 0.--15. 1. "VID_START_DELAY,In order to optimize DSI-2 utility the video interface buffers a certain number of pixels before initiating a DSI-2 packet"
group.long 0x144++0x03
line.long 0x00 "DSI2_CFG_VID_USE_NULL_PKT_BLLP,"
bitfld.long 0x00 0. "VID_USE_NULL_PKT_BLLP,Selects type of blanking packet to be sent during bllp region" "0: Blanking packet used in bllp region,1: Null packet used in bllp region"
group.long 0x148++0x03
line.long 0x00 "DSI2_CFG_VID_VACTIVE,"
hexmask.long.word 0x00 0.--15. 1. "VID_VACTIVE,Sets the number of lines in the vertical active area"
group.long 0x138++0x03
line.long 0x00 "DSI2_CFG_VID_VBP,"
hexmask.long.word 0x00 0.--15. 1. "VID_VBP,Sets the number of lines in the vertical back porch"
group.long 0x14C++0x03
line.long 0x00 "DSI2_CFG_VID_VC,"
bitfld.long 0x00 0.--1. "VID_VC,Sets the Virtual Channel (VC) of packets that will be sent to the receive packet interface" "0,1,2,3"
group.long 0x13C++0x03
line.long 0x00 "DSI2_CFG_VID_VFP,"
hexmask.long.word 0x00 0.--15. 1. "VID_VFP,Sets the number of lines in the vertical front porch"
group.long 0x11C++0x03
line.long 0x00 "DSI2_CFG_VID_VIDEO_MODE,"
bitfld.long 0x00 0.--1. "VID_VID_VIDEO_MODE,Select DSI-2 video mode that the host VID module should generate packets for" "0,1,2,3"
group.long 0x114++0x03
line.long 0x00 "DSI2_CFG_VID_VSYNC_POLARITY,"
bitfld.long 0x00 0. "VID_VSYNC_POLARITY,Sets polarity of vid_vsync input 0 active low 1 active high" "0,1"
tree.end
tree "DSIDPHY_REG"
base ad:0x51001500
group.long 0x18++0x03
line.long 0x00 "DPHY_BIST_DC_OUT_REG,"
rbitfld.long 0x00 0.--5. "DPHY_BIST_DC_OUT,Output signal used in the DC test modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "DPHY_BIST_ENBL_REG,"
bitfld.long 0x00 0.--5. "DPHY_BIST_ENBL,Six-bit signal that enables the testing modes [000000] Testing Disabled [000001] HS-TX Sequence Test (1) [000010] HS-TX Sequence Test (2) [000011] HS-TX Sequence PRBS Test (1) [000100] HS-TX Sequence PRBS Test (2) [001001] HS-TX Test (1).." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x03
line.long 0x00 "DPHY_BIST_PATTERN_REG,"
hexmask.long 0x00 0.--31. 1. "DPHY_BIST_PATTERN,This is the programmable test pattern used by BIST pattern generator and pattern matcher"
group.long 0x0C++0x03
line.long 0x00 "DPHY_CLK_DATA_LANE_PROG_REG,"
bitfld.long 0x00 21.--25. "UC_PRG_HS_TRAIL,Clock Lane: Bits used to program T_CLK_TRAIL time in the end of high speed transmission mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 14.--20. 1. "UC_PRG_HS_ZERO,Clock Lane: Bits used to program T_CLK_ZERO time in the beginning of high speed transmission mode"
bitfld.long 0x00 13. "UC_PRG_HS_PREPARE,Clock Lane: Bit used to program T_CLK_PREPARE time in the beginning of high speed transmission mode" "0,1"
newline
bitfld.long 0x00 8.--12. "U_PRG_HS_TRAIL,Data Lane: Bits used to program T_HS_TRAIL time in the end of high speed transmission mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2.--7. "U_PRG_HS_ZERO,Data Lane: Bits used to program T_HS_ZERO time in the beginning of high speed transmission mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "U_PRG_HS_PREPARE,Data Lane: Bits used to program T_HS_PREPARE time in the beginning of high speed transmission mode" "0,1,2,3"
group.long 0x00++0x03
line.long 0x00 "DPHY_GLOBAL_CTRL_REG,"
bitfld.long 0x00 5. "ULPS_PLL_CTRL,When the PHY enters ULPS this input determines if the PLL will be powered down or not" "0,1"
bitfld.long 0x00 4. "ULPS_PHY_CTRL,When the PHY enters ULPS this input determines if the PHY will be powered down or not" "0,1"
bitfld.long 0x00 3. "LOCK_BYP,When clock lane exits from ULPS this input determines if the PLL LOCK signal will be used to gate the TxByteClkHS 1b0: PLL LOCK signal will gate TxByteClkHS clock [Default] 1b1: PLL LOCK signal will not gate TxByteClkHS clock CIL based counter.." "0,1"
newline
bitfld.long 0x00 2. "AUTO_PD_EN,Powers down inactive lanes reported by CFG_NUM_LANES input bus" "0,1"
bitfld.long 0x00 1. "PHY_PD,Power Down input for PHY" "0,1"
bitfld.long 0x00 0. "PLL_PD,Power-down signal When high the PLL is powered down" "0,1"
group.long 0x04++0x03
line.long 0x00 "DPHY_PLL_CONTROL_REG,PLL control"
bitfld.long 0x00 20. "PLL_LOCK_LATCH,Enable signal to use latched LOCK signal 1b0: LOCK<= Normal LOCK signal [Default] 1b1: LOCK<= Latched LOCK signal" "0,1"
bitfld.long 0x00 19. "PLL_BYPASS,Enable signal to bypass PLL: 1b0: CLKOUT<= CLKREF * ( M / ( N * O )) 1b1: CLKOUT<= CLKEXT" "0,1"
bitfld.long 0x00 15.--18. "PLL_TST,Test Pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 7.--14. 1. "PLL_CM,Control M (feedback) divider"
bitfld.long 0x00 2.--6. "PLL_CN,Control N (input) divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--1. "PLL_CO,Control O (output) divider" "0,1,2,3"
group.long 0x08++0x03
line.long 0x00 "DPHY_STATUS_REG,"
rbitfld.long 0x00 0. "PLL_LOCK,Lock Detect output" "0,1"
group.long 0x1C++0x03
line.long 0x00 "DPHY_TX_RCAL_REG,On-chip termination control"
bitfld.long 0x00 0. "TX_RCAL,On-chip termination control bits for manual calibration of HS-TX" "0,1"
group.long 0x20++0x03
line.long 0x00 "DSI2_DPHY_CLK_RST_N_CTRL_REG,"
bitfld.long 0x00 1. "DPHY_TX_ESC_CLK_DIV," "0,1"
bitfld.long 0x00 0. "DSI2_RESET_N,Hold the DSI2 in reset" "0,1"
group.long 0x24++0x03
line.long 0x00 "DSI2_ERROR_STATUS_REG,"
bitfld.long 0x00 11. "ROW_ACCESS_ERROR,There was a row access error in the memory" "0,1"
bitfld.long 0x00 10. "HOST_BTA_TIMEOUT,Host BTA timeout has occurred" "0,1"
bitfld.long 0x00 9. "LS_RX_TIMEOUT,Low Power RX timeout has occurred" "0,1"
newline
bitfld.long 0x00 8. "HS_TX_TIMEOUT,High Speed transmit has timed out" "0,1"
bitfld.long 0x00 7. "CRC_ERROR,CRC calculated on the received data does not match the CRC the transmitter sent at the end of the packet" "0,1"
bitfld.long 0x00 6. "ECC_TWO_BIT_ERROR,Single bit error in the packet header was detected and corrected" "0,1"
newline
bitfld.long 0x00 5. "ECC_ONE_BIT_ERROR,Two packet header bit errors were detected and not corrected" "0,1"
bitfld.long 0x00 4. "VID_ERROR_BLANKING,Only asserted if cfg_vid_video_mode is set to Burst Mode and cfg_vid_bllp_mode is set to 1b1" "0,1"
bitfld.long 0x00 3. "VID_ERROR_FIFO_UNDERFLOW,Asserted if internal video FIFO underflows" "0,1"
newline
bitfld.long 0x00 2. "VID_ERROR_FIFO_OVERFLOW,Asserted if internal video FIFO overflows" "0,1"
bitfld.long 0x00 1. "VID_ERROR_SYNC_PULSE,Only asserted if cfg_vid_video_mode is set to Non-Burst mode with Sync Pulses" "0,1"
bitfld.long 0x00 0. "VID_ERROR,Asserted if an error occurs during operation" "0,1"
group.long 0x28++0x03
line.long 0x00 "DSI2_INTERRUPT_EN_REG,"
bitfld.long 0x00 11. "ROW_ACCESS_ERROR_IRQ_EN,Enable Row Access Error IRQ" "0,1"
bitfld.long 0x00 10. "HOST_BTA_TIMEOUT_IRQ_EN,Enable BTA timeout IRQ" "0,1"
bitfld.long 0x00 9. "LP_RX_TIMEOUT_IRQ_EN,Enable Low Power RX timeout IRQ" "0,1"
newline
bitfld.long 0x00 8. "HS_TX_TIMEOUT_IRQ_EN,Enable High Speed TX timeout IRQ" "0,1"
bitfld.long 0x00 7. "CRC_ERROR_IRQ_EN,Enable CRC error IRQ" "0,1"
bitfld.long 0x00 6. "ECC_TWO_BIT_ERROR_IRQ_EN,Enable ECC 2 bit error IRQ" "0,1"
newline
bitfld.long 0x00 5. "ECC_ONE_BIT_ERROR_IRQ_EN,Enable ECC 1 bit error IRQ" "0,1"
bitfld.long 0x00 4. "VID_ERROR_BLANKING_IRQ_EN,Enable VID blanking error IRQ" "0,1"
bitfld.long 0x00 3. "VID_ERROR_FIFO_UNDERFLOW_IRQ_EN,Enable VID FIFO underflow IRQ" "0,1"
newline
bitfld.long 0x00 2. "VID_ERROR_FIFO_OVERFLOW_IRQ_EN,Enable VID FIFO overflow IRQ" "0,1"
bitfld.long 0x00 1. "VID_ERROR_SYNC_PULSE_IRQ_EN,Enable VID sync pulse error IRQ" "0,1"
bitfld.long 0x00 0. "VID_ERROR_IRQ_EN,Enable VID error IRQ" "0,1"
group.long 0x34++0x03
line.long 0x00 "DSI2_MEMCTRL_REG,"
bitfld.long 0x00 1.--4. "DSI2_MS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DSI2_MSE," "0,1"
group.long 0x30++0x03
line.long 0x00 "DSI2_TRIGGER_REG,"
bitfld.long 0x00 0.--1. "TRIGGER_DATA,Transmit trigger" "0,1,2,3"
group.long 0x2C++0x03
line.long 0x00 "DSI2_ULPS_CFG_REG,"
rbitfld.long 0x00 4.--5. "ULPS_ACTIVE,Ultra Low Power State status" "0,1,2,3"
rbitfld.long 0x00 3. "ULPS_CLK_ACTIVE,Ultra Low Power State clock lane status" "0,1"
bitfld.long 0x00 1.--2. "ULPS_ENABLE,Ultra-Low Power State enable" "0,1,2,3"
newline
bitfld.long 0x00 0. "ULPS_CLK_ENABLE,Ultra-Low Power State enable for clock lane" "0,1"
tree.end
tree "EMMC"
base ad:0x30058000
group.byte 0x54++0x00
line.byte 0x00 "EMMC_ADMA_ERR_STAT_R_REG,This register stores the ADMA state during an ADMA error"
rbitfld.byte 0x00 2. "ADMA_LEN_ERR,ADMA Length Mismatch Error States This error occurs in the following instances: - While the Block Count Enable is being set the total data length specified by the Descriptor table is different from that specified by the Block Count and.." "0,1"
newline
rbitfld.byte 0x00 0.--1. "ADMA_ERR_STATES,ADMA Error States These bits indicate the state of ADMA when an error occurs during ADMA data transfer" "0,1,2,3"
group.long 0x58++0x03
line.long 0x00 "EMMC_ADMA_SA_LOW_R_REG,This register holds the lower 32-bit system address for DMA transfer"
hexmask.long 0x00 0.--31. 1. "ADMA_SA_LOW,ADMA System Address These bits indicate the lower 32 bits of the ADMA system address"
group.long 0x08++0x03
line.long 0x00 "EMMC_ARGUMENT_R_REG,This register is used to configure the SD/eMMC command argument"
hexmask.long 0x00 0.--31. 1. "ARGUMENT,Command Argument"
group.long 0x540++0x03
line.long 0x00 "EMMC_AT_CTRL_R_REG,This register controls some aspects of tuning and auto-tuning features"
bitfld.long 0x00 24.--26. "SWIN_TH_VAL,Sampling window threshold value setting The maximum value that can be set here depends on the length of delayline used for tuning" "0: Threshold values is 0x1 windows of length 1 tap,1: Threshold values is 0x2 windows of length 2..,2: Threshold values is 0x1 windows of length 3..,?..."
newline
bitfld.long 0x00 19.--20. "POST_CHANGE_DLY,Time taken for phase switching and stable clock output" "0,1,2,3"
newline
bitfld.long 0x00 17.--18. "PRE_CHANGE_DLY,Maximum Latency specification between cclk_tx and cclk_rx" "0,1,2,3"
newline
bitfld.long 0x00 16. "TUNE_CLK_STOP_EN,Clock stopping control for Tuning and auto-tuning circuit" "0,1"
newline
bitfld.long 0x00 4. "SW_TUNE_EN,This fields enables software-managed tuning flow" "0,1"
newline
bitfld.long 0x00 3. "RPT_TUNE_ERR,Framing errors are not generated when executing tuning" "0,1"
newline
bitfld.long 0x00 2. "SWIN_TH_EN,Sampling window Threshold enable Selects the tuning mode Field should be programmed only when SAMPLE_CLK_SEL is '0' Values: 0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold set by.." "0,1"
group.long 0x544++0x03
line.long 0x00 "EMMC_AT_STAT_R_REG,Register to read the Center Left and Right codes used by tuning and auto-tuning engines"
hexmask.long.byte 0x00 16.--23. 1. "L_EDGE_PH_CODE,Left Edge Phase code"
newline
hexmask.long.byte 0x00 8.--15. 1. "R_EDGE_PH_CODE,Right Edge Phase code"
newline
hexmask.long.byte 0x00 0.--7. 1. "CENTER_PH_CODE,Centered Phase code"
group.word 0x3C++0x01
line.word 0x00 "EMMC_AUTO_CMD_STAT_R_REG,This register is used to indicate the CMD12 response error of Auto CMD12 and the CMD23 response error of Auto CMD23"
rbitfld.word 0x00 7. "CMD_NOT_ISSUED_AUTO_CMD12,Command Not Issued By Auto CMD12 Error If this bit is set to 1 CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register" "0,1"
newline
rbitfld.word 0x00 5. "AUTO_CMD_RESP_ERR,Auto CMD Response Error This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13" "0,1"
newline
rbitfld.word 0x00 4. "AUTO_CMD_IDX_ERR,Auto CMD Index Error This bit is set if the command index error occurs in response to a command" "0,1"
newline
rbitfld.word 0x00 3. "AUTO_CMD_EBIT_ERR,Auto CMD End Bit Error This bit is set when detecting that the end bit of command response is 0" "0,1"
newline
rbitfld.word 0x00 2. "AUTO_CMD_CRC_ERR,Auto CMD CRC Error This bit is set when detecting a CRC error in the command response" "0,1"
newline
rbitfld.word 0x00 1. "AUTO_CMD_TOUT_ERR,Auto CMD Timeout Error This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command" "0,1"
newline
rbitfld.word 0x00 0. "AUTO_CMD12_NOT_EXEC,Auto CMD12 Not Executed If multiple memory block data transfer is not started due to a command error this bit is not set because it is not necessary to issue an Auto CMD12" "0,1"
group.byte 0x2A++0x00
line.byte 0x00 "EMMC_BGAP_CTRL_R_REG,This register is used by the host driver to control any operation related to Block Gap"
bitfld.byte 0x00 3. "INT_AT_BGAP,Interrupt At Block Gap" "0,1"
newline
bitfld.byte 0x00 2. "RD_WAIT_CTRL,Read Wait Control" "0,1"
newline
bitfld.byte 0x00 1. "CONTINUE_REQ,Continue Request" "0,1"
newline
bitfld.byte 0x00 0. "STOP_BG_REQ,Stop At Block Gap Request" "0,1"
group.word 0x06++0x01
line.word 0x00 "EMMC_BLOCKCOUNT_R_REG,This register is used to configure the number of data blocks"
abitfld.word 0x00 0.--15. "BLOCK_CNT,16-bit Block Count" "0x0000=0: Stop Count,0x0001=1: 1 Block,0x0002=2: 2 Blocks,0xFFFF=65535: 65535 Blocks"
group.word 0x04++0x01
line.word 0x00 "EMMC_BLOCKSIZE_R_REG,This register is used to configure an SDMA buffer boundary and the number of bytes in a data block"
bitfld.word 0x00 12.--14. "SDMA_BUF_BDARY,SDMA Buffer Boundary" "0,1,2,3,4,5,6,7"
newline
abitfld.word 0x00 0.--11. "XFER_BLOCK_SIZE,Transfer Block Size" "0x001=1: 1 byte,0x002=2: 2 bytes,0x003=3: 3 bytes,0x1FF=511: 511 byte,0x200=512: 512 bytes,0x800=2048: 2048 bytes"
group.word 0x52E++0x01
line.word 0x00 "EMMC_BOOT_CTRL_R_REG,This register is used to control the eMMC Boot operation"
bitfld.word 0x00 12.--15. "BOOT_TOUT_CNT,Boot Ack Timeout Counter Value" "0: TMCLK x 2^13,1: TMCLK x 2^14,?,?,?,?,?,?,?,?,?,?,?,?,14: TMCLK x 2^27,15: Reserved"
newline
bitfld.word 0x00 8. "BOOT_ACK_ENABLE,Boot Acknowledge Enable When this bit set DWC_mshc checks for boot acknowledge start pattern of 0-1-0 during boot operation" "0,1"
newline
bitfld.word 0x00 7. "VALIDATE_BOOT,Validate Mandatory Boot Enable bit This bit is used to validate the MAN_BOOT_EN bit" "0,1"
newline
bitfld.word 0x00 0. "MAN_BOOT_EN,Mandatory Boot Enable This bit is used to initiate the mandatory boot operation" "0,1"
group.long 0x20++0x03
line.long 0x00 "EMMC_BUF_DATA_R_REG,This register is used to access the packet buffer"
hexmask.long 0x00 0.--31. 1. "BUF_DATA,Buffer Data"
group.long 0x40++0x03
line.long 0x00 "EMMC_CAPABILITIES1_R_REG,This register provides the Host Driver with information specific to the Host Controller implementation"
rbitfld.long 0x00 30.--31. "SLOT_TYPE_R,Slot Type These bits indicate usage of a slot by a specific Host System" "0,1,2,3"
newline
rbitfld.long 0x00 29. "ASYNC_INT_SUPPORT,Asynchronous Interrupt Support (SD Mode only) Values: 0x0 (FALSE): Asynchronous Interrupt Not Supported 0x1 (TRUE): Asynchronous Interrupt Supported" "0,1"
newline
rbitfld.long 0x00 28. "SYS_ADDR_64_V3,64-bit System Address Support for V3 This bit sets the Host controller to support 64-bit System Addressing of V3 mode" "0,1"
newline
rbitfld.long 0x00 27. "SYS_ADDR_64_V4,64-bit System Address Support for V4 This bit sets the Host Controller to support 64-bit System Addressing of V4 mode" "0,1"
newline
rbitfld.long 0x00 26. "VOLT_18,Voltage Support for 1.8V Values: 0x0 (FALSE): 1.8V Not Supported 0x1 (TRUE): 1.8V Supported" "0,1"
newline
rbitfld.long 0x00 25. "VOLT_30,Voltage Support for SD 3.0V or Embedded 1.2V Values: 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported 0x1 (TRUE): SD 3.0V or Embedded Supported" "0,1"
newline
rbitfld.long 0x00 24. "VOLT_33,Voltage Support for 3.3V Values: 0x0 (FALSE): 3.3V Not Supported 0x1 (TRUE): 3.3V Supported" "0,1"
newline
rbitfld.long 0x00 23. "SUS_RES_SUPPORT,Suspense/Resume Support This bit indicates whether the Host Controller supports Suspend/Resume functionality" "0,1"
newline
rbitfld.long 0x00 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly" "0,1"
newline
rbitfld.long 0x00 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz" "0,1"
newline
rbitfld.long 0x00 19. "ADMA2_SUPPORT,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2" "0,1"
newline
rbitfld.long 0x00 18. "EMBEDDED_8_BIT,8-bit Support for Embedded Device This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode" "0,1"
newline
rbitfld.long 0x00 16.--17. "MAX_BLK_LEN,Maximum Block Length This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller" "0,1,2,3"
newline
abitfld.long 0x00 8.--15. "BASE_CLK_FREQ,Base Clock Frequency for SD clock These bits indicate the base (maximum) clock frequency for the SD Clock" "0x00=0: Get information through another method,0x01=1: 1 MHz,0x02=2: 2 MHz,0x3F=63: 63 MHz -- 0x40-0xFF,0xFF=255: 255 MHz If the frequency is 16.5 MHz.."
newline
rbitfld.long 0x00 7. "TOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data TImeout Error" "0,1"
newline
rbitfld.long 0x00 0.--5. "TOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error" "0: Get information through another method,1: 1KHz / 1MHz,2: 2KHz / 2MHz,3: 3KHz / 3MHz,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: 63KHz / 63MHz"
group.long 0x44++0x03
line.long 0x00 "EMMC_CAPABILITIES2_R_REG,This register provides the Host Driver with information specific to the Host Controller implementation"
rbitfld.long 0x00 28. "VDD2_18V_SUPPORT,1.8V VDD2 Support This bit indicates support of VDD2 for the Host System" "0,1"
newline
rbitfld.long 0x00 27. "ADMA3_SUPPORT,ADMA3 Support This bit indicates whether the Host Controller is capable of using ADMA3" "0,1"
newline
abitfld.long 0x00 16.--23. "CLK_MUL,Clock Multiplier These bits indicate the clock multiplier of the programmable clock generator" "0x00=0: Clock Multiplier is not Supported,0x01=1: Clock Multiplier M =,0x02=2: Clock Multiplier M =,0x03=3: ,0xFF=255: Clock Multiplier M = 256"
newline
rbitfld.long 0x00 14.--15. "RE_TUNING_MODES,Re-Tuning Modes (UHS-I only) These bits select the re-tuning method and limit the maximum data length" "0,1,2,3"
newline
rbitfld.long 0x00 13. "USE_TUNING_SDR50,Use Tuning for SDR50 (UHS-I only)" "0,1"
newline
rbitfld.long 0x00 8.--11. "RETUNE_CNT,Timer Count for Re-Tuning (UHS-I only)" "0: Re-Tuning Timer disabled,1: 1 seconds,2: 2 seconds,3: 4 seconds,?,?,?,?,?,?,?,11: 1024 seconds,12: Reserved,13: Reserved,14: Reserved,15: Get information from other source"
newline
rbitfld.long 0x00 6. "DRV_TYPED,Driver Type D Support (UHS-I only) This bit indicates support of Driver Type D for 1.8 Signaling" "0,1"
newline
rbitfld.long 0x00 5. "DRV_TYPEC,Driver Type C Support (UHS-I only) This bit indicates support of Driver Type C for 1.8 Signaling" "0,1"
newline
rbitfld.long 0x00 4. "DRV_TYPEA,Driver Type A Support (UHS-I only) This bit indicates support of Driver Type A for 1.8 Signaling" "0,1"
newline
rbitfld.long 0x00 3. "UHS2_SUPPORT,UHS-II Support (UHS-II only) This bit indicates whether Host Controller supports UHS-II" "0,1"
newline
rbitfld.long 0x00 2. "DDR50_SUPPORT,DDR50 Support (UHS-I only) Values: 0x0 (FALSE): DDR50 is not supported 0x1 (TRUE): DDR50 is supported" "0,1"
newline
rbitfld.long 0x00 1. "SDR104_SUPPORT,SDR104 Support (UHS-I only) This bit mentions that SDR104 requires tuning" "0,1"
newline
rbitfld.long 0x00 0. "SDR50_SUPPORT,SDR50 Support (UHS-I only) Thsi bit indicates that SDR50 is supported" "0,1"
group.word 0x2C++0x01
line.word 0x00 "EMMC_CLK_CTRL_R_REG,This register controls SDCLK (card clock) in an SD/eMMC mode and RCLK in the UHS-II mode"
abitfld.word 0x00 8.--15. "FREQ_SEL,SDCLK/RCLK Frequency Select" "0x00=0: Base clock * M,0x01=1: Base clock * M /2,0x02=2: Base clock * M /3"
newline
bitfld.word 0x00 6.--7. "UPPER_FREQ_SEL,These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control" "0,1,2,3"
newline
bitfld.word 0x00 5. "CLK_GEN_SELECT,Clock Generator Select" "0,1"
newline
bitfld.word 0x00 3. "PLL_ENABLE,PLL Enable" "0,1"
newline
bitfld.word 0x00 2. "SD_CLK_EN,SD/eMMC Clock Enable" "0,1"
newline
rbitfld.word 0x00 1. "INTERNAL_CLK_STABLE,Internal Clock Stable This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set" "0,1"
newline
bitfld.word 0x00 0. "INTERNAL_CLK_EN,Internal Clock Enable" "0,1"
group.word 0x0E++0x01
line.word 0x00 "EMMC_CMD_R_REG,This register is used to provide the information related to a command and a response packet"
bitfld.word 0x00 8.--13. "CMD_INDEX,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.word 0x00 6.--7. "CMD_TYPE,Command Type" "0,1,2,3"
newline
bitfld.word 0x00 5. "DATA_PRESENT_SEL,Data Present Select" "0,1"
newline
bitfld.word 0x00 4. "CMD_IDX_CHK_ENABLE,Command Index Check Enable" "0,1"
newline
bitfld.word 0x00 3. "CMD_CRC_CHK_ENABLE,Command CRC Check Enable" "0,1"
newline
bitfld.word 0x00 2. "SUB_CMD_FLAG,Sub Command Flag" "0,1"
newline
bitfld.word 0x00 0.--1. "RESP_TYPE_SELECT,Response Type Select" "0,1,2,3"
group.long 0x184++0x03
line.long 0x00 "EMMC_CQCAP_REG,This register indicates the capabilities of the command queuing engine"
rbitfld.long 0x00 28. "CRYPTO_SUPPORT,Crypto Support This bit indicates whether the Host Controller supports cryptographic operations" "0,1"
newline
hexmask.long.word 0x00 16.--27. 1. "CQCCAP_RSVD2,These bits [27:16] of the CQCAP register are reserved"
newline
rbitfld.long 0x00 12.--15. "ITCFMUL,Internal Timer Clock Frequency Multiplier (ITCFMUL) This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--9. 1. "ITCFVAL,Internal Timer Clock Frequency Value (ITCFVAL) This field scales the frequency of the timer clock provided by ITCFMUL"
group.long 0x48++0x03
line.long 0x00 "EMMC_CURR_CAPABILITIES1_R_REG,This register indicate the maximum current capability for each voltage for VDD1"
abitfld.long 0x00 16.--23. "MAX_CUR_18V,Maximum Current for 1.8V This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card" "0x00=0: Get information,0x01=1: 4mA,0x02=2: 8mA,0x03=3: 13mA,0xFF=255: 1020mA"
newline
abitfld.long 0x00 8.--15. "MAX_CUR_30V,Maximum Current for 3.0V This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card" "0x00=0: Get information,0x01=1: 4mA,0x02=2: 8mA,0x03=3: 13mA,0xFF=255: 1020mA"
newline
abitfld.long 0x00 0.--7. "MAX_CUR_33V,Maximum Current for 3.3V This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card" "0x00=0: Get information,0x01=1: 4mA,0x02=2: 8mA,0x03=3: 13mA,0xFF=255: 1020mA"
group.long 0x4C++0x03
line.long 0x00 "EMMC_CURR_CAPABILITIES2_R_REG,This register indicates the maximum current capability for each voltage (for VDD2)"
abitfld.long 0x00 0.--7. "MAX_CUR_VDD2_18V,Maximum Current for 1.8V VDD2 This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card" "0x00=0: Get information,0x01=1: 4mA,0x02=2: 8mA,0x03=3: 13mA,0xFF=255: 1020mA"
group.long 0xF6C++0x03
line.long 0x00 "EMMC_EMBEDDED_CTRL_R_REG,This register controls the embedded device"
abitfld.long 0x00 24.--30. "BACK_END_PWR_CTRL,Back-End Power Control (SD Mode) Each bit of this field controls back-end power supply for an embedded device" "0x00=0: Back-End Power is off,0x01=1: Back-End Power is supplied D24"
newline
bitfld.long 0x00 20.--22. "INT_PIN_SEL,Interrupt Pin Select These bits enable the interrupt pin inputs" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "CLK_PIN_SEL,Clock Pin Select (SD Mode) This bit is selected by one of clock pin outputs" "0: Clock pins are disabled,1: CLK[1] is selected,2: CLK[2] is selected,?,?,?,?,7: CLK[7] is selected"
newline
abitfld.long 0x00 8.--14. "BUS_WIDTH_PRESET,Bus Width Preset (SD Mode) Each bit of this field specifies the bus width for each embedded device" "0x00=0: 4-bit bus width mode,0x01=1: 8-bit bus width mode,0x02=2: D10,0x03=3: D11,0x04=4: D12,0x05=5: D13,0x06=6: D14"
newline
rbitfld.long 0x00 4.--5. "NUM_INT_PIN,Number of Interrupt Input Pins This field indicates support of interrupt input pins for an embedded system" "0,1,2,3"
newline
rbitfld.long 0x00 0.--2. "NUM_CLK_PIN,Number of Clock Pins (SD Mode) This field indicates support of clock pins to select one of devices for shared bus system" "0: Shared bus is not supported,1: 1 SDCLK is supported - 0x2 - 2 SDCLK is..,?,?,?,?,?,7: 7 SDCLK is supported"
group.word 0x52C++0x01
line.word 0x00 "EMMC_EMMC_CTRL_R_REG,This register is used to control the eMMC operation"
bitfld.word 0x00 3. "EMMC_RST_N_OE,Output Enable control for EMMC Device Reset signal PAD control" "0,1"
newline
bitfld.word 0x00 2. "EMMC_RST_N,EMMC Device Reset signal control" "0,1"
newline
bitfld.word 0x00 1. "DISABLE_DATA_CRC_CHK,Disable Data CRC Check This bit controls masking of CRC16 error for Card Write in eMMC mode" "0,1"
newline
bitfld.word 0x00 0. "CARD_IS_EMMC,eMMC Card present This bit indicates the type of card connected" "0,1"
group.word 0x3A++0x01
line.word 0x00 "EMMC_ERROR_INT_SIGNAL_EN_R_REG,This register is used to select the interrupt status that is notified to the Host System as an interrupt"
bitfld.word 0x00 15. "VENDOR_ERR_SIGNAL_EN3,The 16th bit of Error Interrupt Signal Enable is reserved" "0,1"
newline
bitfld.word 0x00 14. "VENDOR_ERR_SIGNAL_EN2,The 15th bit of Error Interrupt Signal Enable is reserved" "0,1"
newline
bitfld.word 0x00 13. "VENDOR_ERR_SIGNAL_EN1,The 14th bit of Error Interrupt Signal Enable is reserved" "0,1"
newline
bitfld.word 0x00 12. "BOOT_ACK_ERR_SIGNAL_EN,Boot Acknowledgment Error (eMMC Mode only)" "0,1"
newline
bitfld.word 0x00 11. "RESP_ERR_SIGNAL_EN,Response Error Signal Enable (SD Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 10. "TUNING_ERR_SIGNAL_EN,Tuning Error Signal Enable (UHS-I Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 9. "ADMA_ERR_SIGNAL_EN,ADMA Error Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 8. "AUTO_CMD_ERR_SIGNAL_EN,Auto CMD Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 7. "CUR_LMT_ERR_SIGNAL_EN,Current Limit Error Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 6. "DATA_END_BIT_ERR_SIGNAL_EN,Data End Bit Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 5. "DATA_CRC_ERR_SIGNAL_EN,Data CRC Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 4. "DATA_TOUT_ERR_SIGNAL_EN,Data Timeout Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 3. "CMD_IDX_ERR_SIGNAL_EN,Command Index Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 2. "CMD_END_BIT_ERR_SIGNAL_EN,Command End Bit Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 1. "CMD_CRC_ERR_SIGNAL_EN,Command CRC Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 0. "CMD_TOUT_ERR_SIGNAL_EN,Command Timeout Error Signal Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
group.word 0x36++0x01
line.word 0x00 "EMMC_ERROR_INT_STAT_EN_R_REG,This register sets the Interrupt Status for Error Interrupt Status register (ERROR_INT_STAT_R) when ERROR_INT_STAT_EN_R is set"
bitfld.word 0x00 15. "VENDOR_ERR_STAT_EN3,The 15th bit of Error Interrupt Status Enable register is reserved" "0,1"
newline
bitfld.word 0x00 14. "VENDOR_ERR_STAT_EN2,The 14th bit of Error Interrupt Status Enable register is reserved" "0,1"
newline
bitfld.word 0x00 13. "VENDOR_ERR_STAT_EN1,The 13th bit of Error Interrupt Status Enable register is reserved" "0,1"
newline
bitfld.word 0x00 12. "BOOT_ACK_ERR_STAT_EN,Boot Acknowledgment Error (eMMC Mode only) Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R)" "0,1"
newline
bitfld.word 0x00 11. "RESP_ERR_STAT_EN,Response Error Status Enable (SD Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 10. "TUNING_ERR_STAT_EN,Tuning Error Status Enable (UHS-I Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 9. "ADMA_ERR_STAT_EN,ADMA Error Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 8. "AUTO_CMD_ERR_STAT_EN,Auto CMD Error Status Enable (SD/eMMC Mode only)" "0,1"
newline
bitfld.word 0x00 7. "CUR_LMT_ERR_STAT_EN,Current Limit Error Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 6. "DATA_END_BIT_ERR_STAT_EN,Data End Bit Error Status Enable (SD/eMMC Mode only)" "0,1"
newline
bitfld.word 0x00 5. "DATA_CRC_ERR_STAT_EN,Data CRC Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 4. "DATA_TOUT_ERR_STAT_EN,Data Timeout Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 3. "CMD_IDX_ERR_STAT_EN,Command Index Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 2. "CMD_END_BIT_ERR_STAT_EN,Command End Bit Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 1. "CMD_CRC_ERR_STAT_EN,Command CRC Error Status Enable (SD/eMMC Mode only) Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 0. "CMD_TOUT_ERR_STAT_EN,Command Timeout Error Status Enable (SD/eMMC Mode only)" "0,1"
group.word 0x32++0x01
line.word 0x00 "EMMC_ERROR_INT_STAT_R_REG,This register enables an interrupt when the Error Interrupt Status Enable is enabled and at least one of the statuses is set to"
bitfld.word 0x00 12. "BOOT_ACK_ERR,Boot Acknowledgement Error" "0,1"
newline
bitfld.word 0x00 11. "RESP_ERR,Response Error" "0,1"
newline
bitfld.word 0x00 10. "TUNING_ERR,Tuning Error" "0,1"
newline
bitfld.word 0x00 9. "ADMA_ERR,ADMA Error" "0,1"
newline
bitfld.word 0x00 8. "AUTO_CMD_ERR,Auto CMD Error" "0,1"
newline
bitfld.word 0x00 7. "CUR_LMT_ERR,Current Limit Error" "0,1"
newline
bitfld.word 0x00 6. "DATA_END_BIT_ERR,Data End Bit Error" "0,1"
newline
bitfld.word 0x00 5. "DATA_CRC_ERR,Data CRC Error" "0,1"
newline
bitfld.word 0x00 4. "DATA_TOUT_ERR,Data Timeout Error" "0,1"
newline
bitfld.word 0x00 3. "CMD_IDX_ERR,Command Index Error" "0,1"
newline
bitfld.word 0x00 2. "CMD_END_BIT_ERR,Command End Bit Error" "0,1"
newline
bitfld.word 0x00 1. "CMD_CRC_ERR,Command CRC Error" "0,1"
newline
bitfld.word 0x00 0. "CMD_TOUT_ERR,Command Timeout Error" "0,1"
group.word 0x50++0x01
line.word 0x00 "EMMC_FORCE_AUTO_CMD_STAT_R_REG,The register is not a physically implemented but is an address at which the Auto CMD Error Status register can be written.This"
bitfld.word 0x00 7. "FORCE_CMD_NOT_ISSUED_AUTO_CMD12,Force Event for Command Not Issued By Auto CMD12 Error Values: 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set 0x0 (FALSE): Not Affected" "0,1"
newline
bitfld.word 0x00 5. "FORCE_AUTO_CMD_RESP_ERR,Force Event for Auto CMD Response Error Values: 0x1 (TRUE): Auto CMD Response Error Status is set 0x0 (FALSE): Not Affected" "0,1"
newline
bitfld.word 0x00 4. "FORCE_AUTO_CMD_IDX_ERR,Force Event for Auto CMD Index Error Values: 0x1 (TRUE): Auto CMD Index Error Status is set 0x0 (FALSE): Not Affected" "0,1"
newline
bitfld.word 0x00 3. "FORCE_AUTO_CMD_EBIT_ERR,Force Event for Auto CMD End Bit Error Values: 0x1 (TRUE): Auto CMD End Bit Error Status is set 0x0 (FALSE): Not Affected" "0,1"
newline
bitfld.word 0x00 2. "FORCE_AUTO_CMD_CRC_ERR,Force Event for Auto CMD CRC Error Values: 0x1 (TRUE): Auto CMD CRC Error Status is set 0x0 (FALSE): Not Affected" "0,1"
newline
bitfld.word 0x00 1. "FORCE_AUTO_CMD_TOUT_ERR,Force Event for Auto CMD Timeout Error Values: 0x1 (TRUE): Auto CMD Timeout Error Status is set 0x0 (FALSE): Not Affected" "0,1"
newline
bitfld.word 0x00 0. "FORCE_AUTO_CMD12_NOT_EXEC,Force Event for Auto CMD12 Not Executed Values: 0x1 (TRUE): Auto CMD12 Not Executed Status is set 0x0 (FALSE): Not Affected" "0,1"
group.word 0x52++0x01
line.word 0x00 "EMMC_FORCE_ERROR_INT_STAT_R_REG,This register is not physically implemented but is an address at which the Error Interrupt Status register can be written"
bitfld.word 0x00 15. "FORCE_VENDOR_ERR3,This bit (FORCE_VENDOR_ERR3) of the FORCE_ERROR_INT_STAT_R register is reserved" "0,1"
newline
bitfld.word 0x00 14. "FORCE_VENDOR_ERR2,This bit (FORCE_VENDOR_ERR2) of the FORCE_ERROR_INT_STAT_R register is reserved" "0,1"
newline
bitfld.word 0x00 13. "FORCE_VENDOR_ERR1,This bit (FORCE_VENDOR_ERR1) of the FORCE_ERROR_INT_STAT_R register is reserved" "0,1"
newline
bitfld.word 0x00 12. "FORCE_BOOT_ACK_ERR,Force Event for Boot Ack error Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Boot ack Error Status is set" "0,1"
newline
bitfld.word 0x00 11. "FORCE_RESP_ERR,Force Event for Response Error (SD Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Response Error Status is set" "0,1"
newline
bitfld.word 0x00 10. "FORCE_TUNING_ERR,Force Event for Tuning Error (UHS-I Mode only)" "0,1"
newline
bitfld.word 0x00 9. "FORCE_ADMA_ERR,Force Event for ADMA Error Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): ADMA Error Status is set" "0,1"
newline
bitfld.word 0x00 8. "FORCE_AUTO_CMD_ERR,Force Event for Auto CMD Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): ADMA Error Status is set" "0,1"
newline
bitfld.word 0x00 7. "FORCE_CUR_LMT_ERR,Force Event for Current Limit Error Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Current Limit Error Status is set" "0,1"
newline
bitfld.word 0x00 6. "FORCE_DATA_END_BIT_ERR,Force Event for Data End Bit Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Data End Bit Error Status is set" "0,1"
newline
bitfld.word 0x00 5. "FORCE_DATA_CRC_ERR,Force Event for Data CRC Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Data CRC Error Status is set" "0,1"
newline
bitfld.word 0x00 4. "FORCE_DATA_TOUT_ERR,Force Event for Data Timeout Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Data Timeout Error Status is set" "0,1"
newline
bitfld.word 0x00 3. "FORCE_CMD_IDX_ERR,Force Event for Command Index Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Command Index Error Status is set" "0,1"
newline
bitfld.word 0x00 2. "FORCE_CMD_END_BIT_ERR,Force Event for Command End Bit Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Command End Bit Error Status is set" "0,1"
newline
bitfld.word 0x00 1. "FORCE_CMD_CRC_ERR,Force Event for Command CRC Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Command CRC Error Status is set" "0,1"
newline
bitfld.word 0x00 0. "FORCE_CMD_TOUT_ERR,Force Event for Command Timeout Error (SD/eMMC Mode only) Values: 0x0 (FALSE): Not Affected 0x1 (TRUE): Command Timeout Error Status is set" "0,1"
group.word 0xFE++0x01
line.word 0x00 "EMMC_HOST_CNTRL_VERS_R_REG,This register is used to indicate the Host Controller Version number"
hexmask.word.byte 0x00 8.--15. 1. "VENDOR_VERSION_NUM,Vendor Version Number This field is reserved for the vendor version number"
newline
hexmask.word.byte 0x00 0.--7. 1. "SPEC_VERSION_NUM,Specification Version Number These bits indicate the Host controller specification version"
group.byte 0x28++0x00
line.byte 0x00 "EMMC_HOST_CTRL1_R_REG,This register is used to control the operation of the Host Controller"
bitfld.byte 0x00 7. "CARD_DETECT_SIG_SEL,Card Detect Signal Selection" "0,1"
newline
bitfld.byte 0x00 6. "CARD_DETECT_TEST_LVL,Card Detect Test Level" "0,1"
newline
bitfld.byte 0x00 5. "EXT_DAT_XFER,Extended Data Transfer Width" "0,1"
newline
bitfld.byte 0x00 3.--4. "DMA_SEL,DMA Select" "0: SDMA is selected,1: Reserved,2: 32-bit Address ADMA2 is selected,3: 64-bit Address ADMA2 is selected Values"
newline
bitfld.byte 0x00 2. "HIGH_SPEED_EN,High Speed Enable (SD/eMMC Mode only)" "0,1"
newline
bitfld.byte 0x00 1. "DAT_XFER_WIDTH,Data Transfer Width" "0,1"
newline
bitfld.byte 0x00 0. "LED_CTRL,LED Control" "0,1"
group.word 0x3E++0x01
line.word 0x00 "EMMC_HOST_CTRL2_R_REG,This register is used to control how the Host Controller operates"
bitfld.word 0x00 15. "PRESET_VAL_ENABLE,Preset Value Enable This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers" "0,1"
newline
bitfld.word 0x00 14. "ASYNC_INT_ENABLE,Asynchronous Interrupt Enable This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register" "0,1"
newline
bitfld.word 0x00 13. "ADDRESSING,64-bit Addressing This bit is effective when Host Version 4 Enable is set to 1" "0,1"
newline
bitfld.word 0x00 12. "HOST_VER4_ENABLE,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4 mode" "0,1"
newline
bitfld.word 0x00 11. "CMD23_ENABLE,CMD23 Enable If the card supports CMD23 this bit is set to 1" "0,1"
newline
bitfld.word 0x00 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects ADMA2 Length mode to be either 16-bit or 26-bit" "0,1"
newline
bitfld.word 0x00 8. "UHS2_IF_ENABLE,UHS-II Interface Enable This bit is used to enable the UHS-II Interface" "0,1"
newline
bitfld.word 0x00 7. "SAMPLE_CLK_SEL,Sampling Clock Select This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT" "0,1"
newline
bitfld.word 0x00 6. "EXEC_TUNING,Execute Tuning This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed" "0,1"
newline
bitfld.word 0x00 4.--5. "DRV_STRENGTH_SEL,Driver Strength Select This bit is used to select the Host Controller output driver in 1.8V signaling UHS-I/eMMC speed modes" "0,1,2,3"
newline
bitfld.word 0x00 3. "SIGNALING_EN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes" "0,1"
newline
bitfld.word 0x00 0.--2. "UHS_MODE_SEL,UHS Mode/eMMC Speed Mode Select These bits are used to select UHS mode in the SD mode of operation" "0: Legacy,1: High Speed SDR,2: Reserved,3: HS200,4: High Speed DDR,5: Reserved,6: Reserved,7: HS400 Values"
group.byte 0x510++0x00
line.byte 0x00 "EMMC_MBIU_CTRL_R_REG,This register is used to select the valid burst types that the AHB Master bus interface can generate"
bitfld.byte 0x00 3. "BURST_INCR16_EN,INCR16 Burst Controls generation of INCR16 transfers on Master interface" "0,1"
newline
bitfld.byte 0x00 2. "BURST_INCR8_EN,INCR8 Burst Controls generation of INCR8 transfers on Master interface" "0,1"
newline
bitfld.byte 0x00 1. "BURST_INCR4_EN,INCR4 Burst Controls generation of INCR4 transfers on Master interface" "0,1"
newline
bitfld.byte 0x00 0. "UNDEFL_INCR_EN,Undefined INCR Burst Controls generation of undefined length INCR transfer on Master interface" "0,1"
group.byte 0x508++0x00
line.byte 0x00 "EMMC_MSHC_CTRL_R_REG,This register is used to control the operation of MSHC Host Controller"
bitfld.byte 0x00 4. "SW_CG_DIS,Internal clock gating disable control This bit must be used to disable IP's internal clock gating when required" "0,1"
newline
bitfld.byte 0x00 0. "CMD_CONFLICT_CHECK,Command conflict check This bit enables command conflict check" "0,1"
group.long 0x500++0x03
line.long 0x00 "EMMC_MSHC_VER_ID_R_REG,This register reflects the current release number of DWC_mshc/DWC_mshc_lite"
hexmask.long 0x00 0.--31. 1. "MSHC_VER_ID,Current release number This field indicates the Synopsys DesignWare Cores DWC_mshc/DWC_mshc_lite current release number that is read by an application"
group.long 0x504++0x03
line.long 0x00 "EMMC_MSHC_VER_TYPE_R_REG,This register reflects the current release type of DWC_mshc/DWC_mshc_lite"
hexmask.long 0x00 0.--31. 1. "MSHC_VER_TYPE,Current release type This field indicates the Synopsys DesignWare Cores DWC_mshc/DWC_mshc_lite current release type that is read by an application"
group.word 0x38++0x01
line.word 0x00 "EMMC_NORMAL_INT_SIGNAL_EN_R_REG,This register is used to select the interrupt status that is indicated to the Host System as the interrupt"
bitfld.word 0x00 14. "CQE_EVENT_SIGNAL_EN,Command Queuing Engine Event Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 13. "FX_EVENT_SIGNAL_EN,FX Event Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 12. "RE_TUNE_EVENT_SIGNAL_EN,Re-Tuning Event (UHS-I only) Signal Enable" "0,1"
newline
bitfld.word 0x00 11. "INT_C_SIGNAL_EN,INT_C (Embedded) Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 10. "INT_B_SIGNAL_EN,INT_B (Embedded) Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 9. "INT_A_SIGNAL_EN,INT_A (Embedded) Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 8. "CARD_INTERRUPT_SIGNAL_EN,Card Interrupt Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 7. "CARD_REMOVAL_SIGNAL_EN,Card Removal Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 6. "CARD_INSERTION_SIGNAL_EN,Card Insertion Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 5. "BUF_RD_READY_SIGNAL_EN,Buffer Read Ready Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 4. "BUF_WR_READY_SIGNAL_EN,Buffer Write Ready Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 3. "DMA_INTERRUPT_SIGNAL_EN,DMA Interrupt Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 2. "BGAP_EVENT_SIGNAL_EN,Block Gap Event Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 1. "XFER_COMPLETE_SIGNAL_EN,Transfer Complete Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 0. "CMD_COMPLETE_SIGNAL_EN,Command Complete Signal Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
group.word 0x34++0x01
line.word 0x00 "EMMC_NORMAL_INT_STAT_EN_R_REG,This register enables the Interrupt Status for Normal Interrupt Status register (NORMAL_INT_STAT_R) when NORMAL_INT_STAT_R is s"
bitfld.word 0x00 14. "CQE_EVENT_STAT_EN,CQE Event Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 13. "FX_EVENT_STAT_EN,FX Event Status Enable This bit is added from Version 4.10" "0,1"
newline
bitfld.word 0x00 12. "RE_TUNE_EVENT_STAT_EN,Re-Tuning Event (UHS-I only) Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 11. "INT_C_STAT_EN,INT_C (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System" "0,1"
newline
bitfld.word 0x00 10. "INT_B_STAT_EN,INT_B (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System" "0,1"
newline
bitfld.word 0x00 9. "INT_A_STAT_EN,INT_A (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System" "0,1"
newline
bitfld.word 0x00 8. "CARD_INTERRUPT_STAT_EN,Card Interrupt Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System" "0,1"
newline
bitfld.word 0x00 7. "CARD_REMOVAL_STAT_EN,Card Removal Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 6. "CARD_INSERTION_STAT_EN,Card Insertion Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 5. "BUF_RD_READY_STAT_EN,Buffer Read Ready Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 4. "BUF_WR_READY_STAT_EN,Buffer Write Ready Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 3. "DMA_INTERRUPT_STAT_EN,DMA Interrupt Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 2. "BGAP_EVENT_STAT_EN,Block Gap Event Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 1. "XFER_COMPLETE_STAT_EN,Transfer Complete Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
newline
bitfld.word 0x00 0. "CMD_COMPLETE_STAT_EN,Command Complete Status Enable Values: 0x0 (FALSE): Masked 0x1 (TRUE): Enabled" "0,1"
group.word 0x30++0x01
line.word 0x00 "EMMC_NORMAL_INT_STAT_R_REG,This register reflects the status of the Normal Interrupt"
rbitfld.word 0x00 15. "ERR_INTERRUPT,Error Interrupt" "0,1"
newline
bitfld.word 0x00 14. "CQE_EVENT,Command Queuing Event This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode" "0,1"
newline
rbitfld.word 0x00 13. "FX_EVENT,FX Event" "0,1"
newline
rbitfld.word 0x00 12. "RE_TUNE_EVENT,Re-tuning Event" "0,1"
newline
rbitfld.word 0x00 11. "INT_C,INT_C (Embedded)" "0,1"
newline
rbitfld.word 0x00 10. "INT_B,INT_B (Embedded)" "0,1"
newline
rbitfld.word 0x00 9. "INT_A,INT_A (Embedded)" "0,1"
newline
rbitfld.word 0x00 8. "CARD_INTERRUPT,Card Interrupt" "0,1"
newline
bitfld.word 0x00 7. "CARD_REMOVAL_STAT_R,Card Removal" "0,1"
newline
bitfld.word 0x00 6. "CARD_INSERTION,Card Insertion This bit is set if the Card Inserted in the Present State register changes from 0 to 1" "0,1"
newline
bitfld.word 0x00 5. "BUF_RD_READY,Buffer Read Ready" "0,1"
newline
bitfld.word 0x00 4. "BUF_WR_READY,Buffer Write Ready" "0,1"
newline
bitfld.word 0x00 3. "DMA_INTERRUPT,DMA Interrupt" "0,1"
newline
bitfld.word 0x00 2. "BGAP_EVENT,Block Gap Event" "0,1"
newline
bitfld.word 0x00 1. "XFER_COMPLETE,Transfer Complete" "0,1"
newline
bitfld.word 0x00 0. "CMD_COMPLETE,Command Complete" "0,1"
group.word 0x6E++0x01
line.word 0x00 "EMMC_PRESET_DDR50_R_REG,This register defines the Preset Value for DDR50 and High Speed DDR speed modes in the SD and eMMC modes respectively"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for DDR50 bus speed mode" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify a 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register as described by a Host System"
group.word 0x62++0x01
line.word 0x00 "EMMC_PRESET_DS_R_REG,This register defines Preset Value for Default Speed mode in SD mode"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System"
group.word 0x64++0x01
line.word 0x00 "EMMC_PRESET_HS_R_REG,This register defines Preset Value for High Speed mode in SD mode"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System"
group.word 0x60++0x01
line.word 0x00 "EMMC_PRESET_INIT_R_REG,This register defines Preset Value for Initialization in SD/eMMC mode"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate that the Driver strength is supported by 1.8V signaling bus speed modes" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when the Host Controller supports a programmable clock generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System"
group.word 0x6C++0x01
line.word 0x00 "EMMC_PRESET_SDR104_R_REG,This register defines Preset Value for SDR104 and HS200 speed modes in the SD and eMMC modes respectively"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for SDR104 bus speed mode" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify a 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System"
group.word 0x66++0x01
line.word 0x00 "EMMC_PRESET_SDR12_R_REG,This register defines Preset Value for SDR12 and Legacy speed mode in SD and eMMC mode respectively"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported for the SDR12 bus speed mode" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator Values: 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator 0x1 (PROG): Programmable Clock Generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System"
group.word 0x68++0x01
line.word 0x00 "EMMC_PRESET_SDR25_R_REG,This register defines Preset Value for SDR25 and High Speed SDR speed mode in SD and eMMC mode respectively"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported for the SDR25 bus speed mode" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System"
group.word 0x6A++0x01
line.word 0x00 "EMMC_PRESET_SDR50_R_REG,This register defines Preset Value for SDR50 speed mode in SD mode"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for SDR50 bus speed mode" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System"
group.word 0x74++0x01
line.word 0x00 "EMMC_PRESET_UHS2_R_REG,This register is used to hold the preset value for UHS-II and HS400 speed modes in the SD and eMMC modes respectively"
rbitfld.word 0x00 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes in the SD mode" "0,1,2,3"
newline
rbitfld.word 0x00 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when the Host Controller supports a programmable clock generator" "0,1"
newline
hexmask.word 0x00 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify the 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register as described by a Host System"
group.long 0x24++0x03
line.long 0x00 "EMMC_PSTATE_REG,This register indicates the present status of the Host Controller"
rbitfld.long 0x00 31. "UHS2_IF_DETECT,UHS-II Interface Detection" "0,1"
newline
rbitfld.long 0x00 30. "LANE_SYNC,Lane Synchronization" "0,1"
newline
rbitfld.long 0x00 29. "IN_DORMANT_ST,In Dormant Status For SD/eMMC mode this bit always returns 0" "0,1"
newline
rbitfld.long 0x00 28. "SUB_CMD_STAT,Sub Command Status" "0,1"
newline
rbitfld.long 0x00 27. "CMD_ISSUE_ERR,Command Not Issued by Error" "0,1"
newline
rbitfld.long 0x00 25. "HOST_REG_VOL,Host Regulator Voltage Stable" "0,1"
newline
rbitfld.long 0x00 24. "CMD_LINE_LVL,Command-Line Signal Level" "0,1"
newline
rbitfld.long 0x00 20.--23. "DAT_3_0,DAT[3:0] Line Signal Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 19. "WR_PROTECT_SW_LVL,Write Protect Switch Pin Level" "0,1"
newline
rbitfld.long 0x00 18. "CARD_DETECT_PIN_LEVEL,Card Detect Pin Level" "0,1"
newline
rbitfld.long 0x00 17. "CARD_STABLE,Card Stable" "0,1"
newline
rbitfld.long 0x00 16. "CARD_INSERTED,Card Inserted" "0,1"
newline
rbitfld.long 0x00 11. "BUF_RD_ENABLE,Buffer Read Enable" "0,1"
newline
rbitfld.long 0x00 10. "BUF_WR_ENABLE,Buffer Write Enable" "0,1"
newline
rbitfld.long 0x00 9. "RD_XFER_ACTIVE,Read Transfer Active" "0,1"
newline
rbitfld.long 0x00 8. "WR_XFER_ACTIVE,Write Transfer Active" "0,1"
newline
rbitfld.long 0x00 4.--7. "DAT_7_4,DAT[7:4] Line Signal Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 3. "RE_TUNE_REQ,Re-Tuning Request" "0,1"
newline
rbitfld.long 0x00 2. "DAT_LINE_ACTIVE,DAT Line Active (SD/eMMC Mode only)" "0,1"
newline
rbitfld.long 0x00 1. "CMD_INHIBIT_DAT,Command Inhibit (DAT)" "0,1"
newline
rbitfld.long 0x00 0. "CMD_INHIBIT,Command Inhibit (CMD)" "0,1"
group.byte 0x29++0x00
line.byte 0x00 "EMMC_PWR_CTRL_R_REG,This register is used to control the bus power for the Card"
bitfld.byte 0x00 5.--7. "SD_BUS_VOL_VDD2,SD Bus Voltage Select for VDD2" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "SD_BUS_PWR_VDD2,SD Bus Power for VDD2" "0,1"
newline
bitfld.byte 0x00 1.--3. "SD_BUS_VOL_VDD1,SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD" "0: Reserved Values,?,?,?,?,5: 1.2V(Typical),6: 1.8V(Typical),7: 3.3V(Typical)"
newline
bitfld.byte 0x00 0. "SD_BUS_PWR_VDD1,SD Bus Power for VDD1" "0,1"
group.word 0xE6++0x01
line.word 0x00 "EMMC_P_EMBEDDED_CNTRL_REG,This register points to the location of UHS-II embedded control registers"
hexmask.word 0x00 0.--11. 1. "REG_OFFSET_EMBEDDED_CNTRL_ADDR,Offset Address of Embedded Control register"
group.word 0xE8++0x01
line.word 0x00 "EMMC_P_VENDOR_SPECIFIC_AREA_REG,This register used as a pointer for the Vendor Specific Area 1"
hexmask.word 0x00 0.--11. 1. "REG_OFFSET_ADDR_VENDOR,Base offset Address for Vendor-Specific registers"
group.word 0xEA++0x01
line.word 0x00 "EMMC_P_VNDR2_SPECIFIC_AREA_REG,This register is used as a pointer for the Vendor Specific Area 2"
hexmask.word 0x00 0.--15. 1. "REG_OFFSET_ADDR_VNDR2,Base offset Address for Command Queuing registers"
group.long 0x10++0x03
line.long 0x00 "EMMC_RESP01_R_REG,This register stores 39-08 bits of the Response Field for an SD/eMMC mode"
hexmask.long 0x00 0.--31. 1. "RESP01,Command Response"
group.long 0x14++0x03
line.long 0x00 "EMMC_RESP23_R_REG,This register stores 71-40 bits of the Response Field for an SD/eMMC mode"
hexmask.long 0x00 0.--31. 1. "RESP23,Command Response"
group.long 0x18++0x03
line.long 0x00 "EMMC_RESP45_R_REG,This register stores 103-72 bits of the Response Field for an SD/eMMC mode"
hexmask.long 0x00 0.--31. 1. "RESP45,Command Response"
group.long 0x1C++0x03
line.long 0x00 "EMMC_RESP67_R_REG,This register stores 135-104 bits of the Response Field for an SD/eMMC mode"
hexmask.long 0x00 0.--31. 1. "RESP67,Command Response"
group.long 0x00++0x03
line.long 0x00 "EMMC_SDMASA_R_REG,This register is used to configure a 32-bit Block Count or an SDMA System Address based on the Host Version 4 Enable bit in"
hexmask.long 0x00 0.--31. 1. "BLOCKCNT_SDMASA,32-bit Block Count (SDMA System Address)"
group.word 0xFC++0x01
line.word 0x00 "EMMC_SLOT_INTR_STATUS_R_REG,This register indicates the Interrupt status of each slot"
abitfld.word 0x00 0.--7. "INTR_SLOT,Interrupt signal for each Slot These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot" "0x00=0: Slot,0x01=1: Slot,0x02=2: Slot,0x03=3: ,0x07=7: Slot 8"
group.byte 0x2F++0x00
line.byte 0x00 "EMMC_SW_RST_R_REG,This register is used to generate a reset pulse by writing 1 to each bit of this register"
bitfld.byte 0x00 2. "SW_RST_DAT,Software Reset For DAT line" "0,1"
newline
bitfld.byte 0x00 1. "SW_RST_CMD,Software Reset For CMD line" "0,1"
newline
bitfld.byte 0x00 0. "SW_RST_ALL,Software Reset For All" "0,1"
group.byte 0x2E++0x00
line.byte 0x00 "EMMC_TOUT_CTRL_R_REG,This register is used to set the Data Timeout Counter value for an SD/eMMC mode according to the timer clock defined by the Cap"
bitfld.byte 0x00 0.--3. "TOUT_CNT,Data Timeout Counter Value" "0: TMCLK x 2^13,1: TMCLK x 2^14,?,?,?,?,?,?,?,?,?,?,?,?,14: TMCLK x 2^27,15: Reserved"
group.byte 0x2B++0x00
line.byte 0x00 "EMMC_WUP_CTRL_R_REG,This register is mandatory for the Host Controller but the wakeup functionality depends on the Host Controller system hardware"
bitfld.byte 0x00 2. "CARD_REMOVAL,Wakeup Event Enable on SD Card Removal" "0,1"
newline
bitfld.byte 0x00 1. "CARD_INSERT,Wakeup Event Enable on SD Card Insertion" "0,1"
newline
bitfld.byte 0x00 0. "CARD_INT,Wakeup Event Enable on Card Interrupt" "0,1"
group.word 0x0C++0x01
line.word 0x00 "EMMC_XFER_MODE_R_REG,This register is used to control the operation of data transfers for an SD/eMMC mode"
bitfld.word 0x00 8. "RESP_INT_DISABLE,Response Interrupt Disable" "0,1"
newline
bitfld.word 0x00 7. "RESP_ERR_CHK_ENABLE,Response Error Check Enable" "0,1"
newline
bitfld.word 0x00 6. "RESP_TYPE,Response Type R1/R5" "0,1"
newline
bitfld.word 0x00 5. "MULTI_BLK_SEL,Multi/Single Block Select" "0,1"
newline
bitfld.word 0x00 4. "DATA_XFER_DIR,Data Transfer Direction Select" "0,1"
newline
bitfld.word 0x00 2.--3. "AUTO_CMD_ENABLE,Auto Command Enable" "0,1,2,3"
newline
bitfld.word 0x00 1. "BLOCK_COUNT_ENABLE,Block Count Enable" "0,1"
newline
bitfld.word 0x00 0. "DMA_EN_EMMC,DMA Enable" "0,1"
tree.end
tree "GPADC"
base ad:0x50020800
group.long 0x1C++0x03
line.long 0x00 "GP_ADC_CLEAR_INT_REG,General Purpose ADC Clear Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "GP_ADC_CLR_INT,Writing any value to this register will clear the ADC_INT interrupt"
group.long 0x04++0x03
line.long 0x00 "GP_ADC_CTRL2_REG,General Purpose ADC Second Control Register"
bitfld.long 0x00 13.--15. "GP_ADC_STORE_DEL," "?,1: Data is stored 2 ADC_CLK cycles after internal,?,?,?,?,?,7: Data is stored 8 ADC_CLK cycles after internal"
newline
bitfld.long 0x00 9.--12. "GP_ADC_SMPL_TIME," "?,1: The sample time is 1*8 ADC_CLK cycles,2: The sample time is 2*8 ADC_CLK cycles,?,?,?,?,?,?,?,?,?,?,?,?,15: The sample time is 15*8 ADC_CLK cycles"
newline
bitfld.long 0x00 6.--8. "GP_ADC_CONV_NRS," "?,1: 2 samples are taken,2: 4 samples are taken,?,?,?,?,7: 128 samples are taken"
newline
bitfld.long 0x00 2. "GP_ADC_I20U," "0,1"
newline
bitfld.long 0x00 0.--1. "GP_ADC_ATTN," "?,1: Enabling 2x attenuator (input voltages up to,2: Enabling 3x attenuator (input voltages up to,3: Enabling 4x attenuator (input voltages up to"
group.long 0x08++0x03
line.long 0x00 "GP_ADC_CTRL3_REG,General Purpose ADC Third Control Register"
abitfld.long 0x00 8.--15. "GP_ADC_INTERVAL,Defines the interval between two ADC conversions in case GP_ADC_CONT is set" "0x00=0: No extra delay between two conversions,0x01=1: 1.024 ms interval between two conversions,0x02=2: 2.048 ms interval between two conversions,0xFF=255: 261.12 ms interval between two.."
newline
abitfld.long 0x00 0.--7. "GP_ADC_EN_DEL,Defines the delay for enabling the ADC after enabling the LDO" "0x00=0: Not allowed,0x01=1: 4x ADC_CLK period"
group.long 0x00++0x03
line.long 0x00 "GP_ADC_CTRL_REG,General Purpose ADC Control Register"
bitfld.long 0x00 15.--16. "GP_ADC_RESULT_MODE,Sample mode" "0: Sample extention the result is aligned on the..,1: Sample truncation the result is aligned on..,2: Normal mode the result is aligned on the MSBs,3: N.A"
newline
bitfld.long 0x00 14. "GP_ADC_DIE_TEMP_EN,Enables the die-temperature sensor" "0,1"
newline
bitfld.long 0x00 12.--13. "GP_ADC_DIFF_TEMP_SEL," "?,1: Z,2: V(ntc) from charger,3: V(temp) from charger"
newline
bitfld.long 0x00 11. "GP_ADC_DIFF_TEMP_EN," "0,1"
newline
bitfld.long 0x00 10. "GP_ADC_LDO_HOLD," "0,1"
newline
bitfld.long 0x00 9. "GP_ADC_CHOP," "0,1"
newline
bitfld.long 0x00 8. "GP_ADC_SIGN," "0,1"
newline
bitfld.long 0x00 7. "GP_ADC_MUTE," "0,1"
newline
bitfld.long 0x00 6. "GP_ADC_SE," "0,1"
newline
bitfld.long 0x00 5. "GP_ADC_MINT," "0,1"
newline
rbitfld.long 0x00 4. "GP_ADC_INT," "0,1"
newline
bitfld.long 0x00 3. "GP_ADC_DMA_EN," "0,1"
newline
bitfld.long 0x00 2. "GP_ADC_CONT," "0,1"
newline
bitfld.long 0x00 1. "GP_ADC_START," "0,1"
newline
bitfld.long 0x00 0. "GP_ADC_EN," "0,1"
group.long 0x14++0x03
line.long 0x00 "GP_ADC_OFFN_REG,General Purpose ADC Negative Offset Register"
hexmask.long.word 0x00 0.--9. 1. "GP_ADC_OFFN,Offset adjust of 'negative' array of ADC-network (effective if GP_ADC_SE=0 or GP_ADC_SE=1 AND GP_ADC_SIGN=1 OR GP_ADC_CHOP=1 )"
group.long 0x10++0x03
line.long 0x00 "GP_ADC_OFFP_REG,General Purpose ADC Positive Offset Register"
hexmask.long.word 0x00 0.--9. 1. "GP_ADC_OFFP,Offset adjust of 'positive' array of ADC-network (effective if GP_ADC_SE=0 or GP_ADC_SE=1 AND GP_ADC_SIGN=0 OR GP_ADC_CHOP=1 )"
group.long 0x20++0x03
line.long 0x00 "GP_ADC_RESULT_REG,General Purpose ADC Result Register"
hexmask.long.word 0x00 0.--15. 1. "GP_ADC_VAL,Returns the 10 up to 16 bits linear value of the last AD conversion"
group.long 0x0C++0x03
line.long 0x00 "GP_ADC_SEL_REG,General Purpose ADC Input Selection Register"
bitfld.long 0x00 14.--16. "GP_ADC_LDO_SENSE_SEL,Enable and select the current sensing logic for one of the LDO's" "0: LDO current sense disabled,1: Sense current of LDO_SUPPLY_VBUS (V33),2: Sense current of LDO_1V4,3: Sense current of LDO_1V8,4: Sense current of LDO_CORE (VDD1V2),5: Sense current of LDO_1V8P,6: Sense current of LDO_SUPPLY_VBAT (V33),7: Reserved"
newline
bitfld.long 0x00 11.--13. "GP_ADC_SEL_MUX2," "?,1: V18P,2: V18,3: V14,4: V12,5: VSYS,6: VBUS,7: VBAT"
newline
bitfld.long 0x00 8.--10. "GP_ADC_SEL_MUX1," "?,1: NC,2: Reserved,3: I_sense_bus,4: Reserved,5: V30,6: VMIPI,7: V18F"
newline
bitfld.long 0x00 7. "GP_ADC_SEL_P_TST,When set to 1 GP_ADC_SEL_P selection becomes" "0: VSSA,1: VDDA_CONT"
newline
bitfld.long 0x00 4.--6. "GP_ADC_SEL_P,ADC positive input selection" "0: ADC0 (P1[0]),1: ADC1 (P1[1]),2: ADC2 (P1[2]),3: ADC3 (P0[10]),4: Temperature Sensor,5: VBAT_HIGH,6: VBAT_LOW,7: VDDD"
newline
bitfld.long 0x00 0.--2. "GP_ADC_SEL_N,ADC negative input selection" "0: ADC0 (P1[0]),1: ADC1 (P1[1]),2: ADC2 (P1[2]),3: ADC3 (P0[10]) All other,?..."
group.long 0x18++0x03
line.long 0x00 "GP_ADC_TRIM_REG,General Purpose ADC Trim Register"
bitfld.long 0x00 0.--2. "GP_ADC_LDO_LEVEL,GPADC LDO level" "0: 825mV,1: 850mV,2: 875mV,3: 900mV (reset),4: 925mV (default),5: 950mV,6: 975mV 7:1000mV,?..."
tree.end
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
base ad:0x50050100
group.long 0x16C++0x03
line.long 0x00 "GPIO_CLK_SEL_REG,Select which clock to map on ports P0/P1"
bitfld.long 0x00 9. "DIVN_OUTPUT_EN,DIVN output enable bit-field" "0,1"
bitfld.long 0x00 7. "XTAL32M_OUTPUT_EN,XTAL32M output enable bit-field" "0,1"
newline
bitfld.long 0x00 6. "RCX_OUTPUT_EN,RCX output enable bit-field" "0,1"
bitfld.long 0x00 5. "RCLP_OUTPUT_EN,RCLP output enable bit-field" "0,1"
newline
bitfld.long 0x00 4. "XTAL32K_OUTPUT_EN,XTAL32K output enable bit-field" "0,1"
bitfld.long 0x00 3. "FUNC_CLOCK_EN,If set it enables the mapping of the selected clock signal according to FUNC_CLOCK_SEL bit-field" "0,1"
newline
bitfld.long 0x00 0.--2. "FUNC_CLOCK_SEL,Select which clock to map when PID = FUNC_CLOCK" "0: XTAL32K,1: RCLP,2: RCX,3: XTAL32M,4: DIVN,5: Reserved,6: Reserved,7: Reserved"
group.long 0x17C++0x03
line.long 0x00 "LCDC_MAP_CTRL_REG,LCDC mapping control Register"
bitfld.long 0x00 14. "MAP_ON_P1_07_EN," "0,1"
bitfld.long 0x00 13. "MAP_ON_P1_01_EN," "0,1"
newline
bitfld.long 0x00 12. "MAP_ON_P1_00_EN," "0,1"
bitfld.long 0x00 11. "MAP_ON_P0_24_EN," "0,1"
newline
bitfld.long 0x00 10. "MAP_ON_P0_23_EN," "0,1"
bitfld.long 0x00 9. "MAP_ON_P0_22_EN," "0,1"
newline
bitfld.long 0x00 8. "MAP_ON_P0_21_EN," "0,1"
bitfld.long 0x00 7. "MAP_ON_P0_19_EN," "0,1"
newline
bitfld.long 0x00 6. "MAP_ON_P0_18_EN," "0,1"
bitfld.long 0x00 5. "MAP_ON_P0_17_EN," "0,1"
newline
bitfld.long 0x00 4. "MAP_ON_P0_16_EN," "0,1"
bitfld.long 0x00 3. "MAP_ON_P0_15_EN," "0,1"
newline
bitfld.long 0x00 2. "MAP_ON_P0_14_EN," "0,1"
bitfld.long 0x00 1. "MAP_ON_P0_10_EN," "0,1"
newline
bitfld.long 0x00 0. "MAP_ON_P0_09_EN," "0,1"
group.long 0x24++0x03
line.long 0x00 "P0_00_MODE_REG,P0_00 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,Function of port" "0: GPIO,1: UART_RX,2: UART_TX,3: UART2_RX,4: UART2_TX,5: UART2_CTSN,6: UART2_RTSN,7: UART3_RX,8: UART3_TX,9: UART3_CTSN / ISO_RST,10: UART3_RTSN / ISO_CARDINSERT,11: ISO_CLK,12: ISO_DATA,13: SPI_DI,14: SPI_DO,15: SPI_CLK,16: SPI_EN,17: SPI_EN2,18: SPI2_DI,19: SPI2_DO,20: SPI2_CLK,21: SPI2_EN,22: SPI2_EN2,23: SPI3_EN,24: SPI3_EN2,25: I2C_SCL,26: I2C_SDA,27: I2C2_SCL,28: I2C2_SDA,29: I2C3_SCL,30: I2C3_SDA,31: I3C_SCL,32: I3C_SDA,33: USB_SOF,34: ADC (Analog),35: USB (P2_10 and P2_11),36: PCM_DI,37: PCM_DO,38: PCM_FSC,39: PCM_CLK,40: PDM_DATA,41: PDM_CLK,42: COEX_EXT_ACT,43: COEX_SMART_ACT,44: COEX_SMART_PRI,45: PORT0_DCF,46: PORT1_DCF,47: PORT2_DCF,48: PORT3_DCF,49: PORT4_DCF,50: CLOCK (see also,51: TIM_PWM,52: TIM2_PWM,53: TIM3_PWM,54: TIM4_PWM,55: TIM5_PWM,56: TIM6_PWM,57: TIM_1SHOT,58: TIM2_1SHOT,59: TIM3_1SHOT,60: TIM4_1SHOT,61: TIM5_1SHOT,62: TIM6_1SHOT,63: CMAC_DIAG (Dedicated Pins)"
group.long 0x28++0x03
line.long 0x00 "P0_01_MODE_REG,P0_01 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2C++0x03
line.long 0x00 "P0_02_MODE_REG,P0_02 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x30++0x03
line.long 0x00 "P0_03_MODE_REG,P0_03 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x34++0x03
line.long 0x00 "P0_04_MODE_REG,P0_04 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "P0_05_MODE_REG,P0_05 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3C++0x03
line.long 0x00 "P0_06_MODE_REG,P0_06 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x40++0x03
line.long 0x00 "P0_07_MODE_REG,P0_07 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x44++0x03
line.long 0x00 "P0_08_MODE_REG,P0_08 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x48++0x03
line.long 0x00 "P0_09_MODE_REG,P0_09 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4C++0x03
line.long 0x00 "P0_10_MODE_REG,P0_10 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50++0x03
line.long 0x00 "P0_11_MODE_REG,P0_11 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x03
line.long 0x00 "P0_12_MODE_REG,P0_12 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x58++0x03
line.long 0x00 "P0_13_MODE_REG,P0_13 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5C++0x03
line.long 0x00 "P0_14_MODE_REG,P0_14 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x60++0x03
line.long 0x00 "P0_15_MODE_REG,P0_15 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x64++0x03
line.long 0x00 "P0_16_MODE_REG,P0_16 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x68++0x03
line.long 0x00 "P0_17_MODE_REG,P0_17 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x6C++0x03
line.long 0x00 "P0_18_MODE_REG,P0_18 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x70++0x03
line.long 0x00 "P0_19_MODE_REG,P0_19 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x74++0x03
line.long 0x00 "P0_20_MODE_REG,P0_20 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x78++0x03
line.long 0x00 "P0_21_MODE_REG,P0_21 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x7C++0x03
line.long 0x00 "P0_22_MODE_REG,P0_22 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "P0_23_MODE_REG,P0_23 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x84++0x03
line.long 0x00 "P0_24_MODE_REG,P0_24 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x88++0x03
line.long 0x00 "P0_25_MODE_REG,P0_25 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8C++0x03
line.long 0x00 "P0_26_MODE_REG,P0_26 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x90++0x03
line.long 0x00 "P0_27_MODE_REG,P0_27 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x94++0x03
line.long 0x00 "P0_28_MODE_REG,P0_28 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x03
line.long 0x00 "P0_29_MODE_REG,P0_29 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x9C++0x03
line.long 0x00 "P0_30_MODE_REG,P0_30 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA0++0x03
line.long 0x00 "P0_31_MODE_REG,P0_31 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x00++0x03
line.long 0x00 "P0_DATA_REG,P0 Data input / output Register"
hexmask.long 0x00 0.--31. 1. "P0_DATA,Set P0 output register when written Returns the value of P0 port when"
group.long 0x160++0x03
line.long 0x00 "P0_PADPWR_CTRL_REG,P0 Output Power Control Register"
bitfld.long 0x00 31. "P0_31_OUT_CTRL," "0,1"
bitfld.long 0x00 30. "P0_30_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 29. "P0_29_OUT_CTRL," "0,1"
bitfld.long 0x00 28. "P0_28_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 27. "P0_27_OUT_CTRL," "0,1"
bitfld.long 0x00 24. "P0_24_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 23. "P0_23_OUT_CTRL," "0,1"
bitfld.long 0x00 22. "P0_22_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 21. "P0_21_OUT_CTRL," "0,1"
bitfld.long 0x00 20. "P0_20_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 19. "P0_19_OUT_CTRL," "0,1"
bitfld.long 0x00 18. "P0_18_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 17. "P0_17_OUT_CTRL," "0,1"
bitfld.long 0x00 16. "P0_16_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 15. "P0_15_OUT_CTRL," "0,1"
bitfld.long 0x00 14. "P0_14_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 11. "P0_11_OUT_CTRL," "0,1"
bitfld.long 0x00 10. "P0_10_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 9. "P0_09_OUT_CTRL," "0,1"
bitfld.long 0x00 8. "P0_08_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 7. "P0_07_OUT_CTRL," "0,1"
bitfld.long 0x00 6. "P0_06_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 5. "P0_05_OUT_CTRL," "0,1"
bitfld.long 0x00 4. "P0_04_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 3. "P0_03_OUT_CTRL," "0,1"
bitfld.long 0x00 2. "P0_02_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 1. "P0_01_OUT_CTRL," "0,1"
bitfld.long 0x00 0. "P0_00_OUT_CTRL," "0,1"
group.long 0x18++0x03
line.long 0x00 "P0_RESET_DATA_REG,P0 Reset port pins Register"
hexmask.long 0x00 0.--31. 1. "P0_RESET,Writing a 1 to P0[y] sets P0[y] to 0"
group.long 0x0C++0x03
line.long 0x00 "P0_SET_DATA_REG,P0 Set port pins Register"
hexmask.long 0x00 0.--31. 1. "P0_SET,Writing a 1 to P0[y] sets P0[y] to 1"
group.long 0x170++0x03
line.long 0x00 "P0_WEAK_CTRL_REG,P0 Weak Pads Control Register"
bitfld.long 0x00 31. "P0_31_LOWDRV," "0,1"
bitfld.long 0x00 30. "P0_30_LOWDRV," "0,1"
newline
bitfld.long 0x00 29. "P0_29_LOWDRV," "0,1"
bitfld.long 0x00 28. "P0_28_LOWDRV," "0,1"
newline
bitfld.long 0x00 27. "P0_27_LOWDRV," "0,1"
bitfld.long 0x00 24. "P0_24_LOWDRV," "0,1"
newline
bitfld.long 0x00 23. "P0_23_LOWDRV," "0,1"
bitfld.long 0x00 22. "P0_22_LOWDRV," "0,1"
newline
bitfld.long 0x00 21. "P0_21_LOWDRV," "0,1"
bitfld.long 0x00 20. "P0_20_LOWDRV," "0,1"
newline
bitfld.long 0x00 19. "P0_19_LOWDRV," "0,1"
bitfld.long 0x00 18. "P0_18_LOWDRV," "0,1"
newline
bitfld.long 0x00 17. "P0_17_LOWDRV," "0,1"
bitfld.long 0x00 16. "P0_16_LOWDRV," "0,1"
newline
bitfld.long 0x00 15. "P0_15_LOWDRV," "0,1"
bitfld.long 0x00 14. "P0_14_LOWDRV," "0,1"
newline
bitfld.long 0x00 11. "P0_11_LOWDRV," "0,1"
bitfld.long 0x00 10. "P0_10_LOWDRV," "0,1"
newline
bitfld.long 0x00 9. "P0_09_LOWDRV," "0,1"
bitfld.long 0x00 8. "P0_08_LOWDRV," "0,1"
newline
bitfld.long 0x00 7. "P0_07_LOWDRV," "0,1"
bitfld.long 0x00 6. "P0_06_LOWDRV," "0,1"
newline
bitfld.long 0x00 5. "P0_05_LOWDRV," "0,1"
bitfld.long 0x00 4. "P0_04_LOWDRV," "0,1"
newline
bitfld.long 0x00 3. "P0_03_LOWDRV," "0,1"
bitfld.long 0x00 2. "P0_02_LOWDRV," "0,1"
newline
bitfld.long 0x00 1. "P0_01_LOWDRV," "0,1"
bitfld.long 0x00 0. "P0_00_LOWDRV," "0,1"
group.long 0xA4++0x03
line.long 0x00 "P1_00_MODE_REG,P1_00 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA8++0x03
line.long 0x00 "P1_01_MODE_REG,P1_01 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAC++0x03
line.long 0x00 "P1_02_MODE_REG,P1_02 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB0++0x03
line.long 0x00 "P1_03_MODE_REG,P1_03 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB4++0x03
line.long 0x00 "P1_04_MODE_REG,P1_04 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xB8++0x03
line.long 0x00 "P1_05_MODE_REG,P1_05 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBC++0x03
line.long 0x00 "P1_06_MODE_REG,P1_06 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC0++0x03
line.long 0x00 "P1_07_MODE_REG,P1_07 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC4++0x03
line.long 0x00 "P1_08_MODE_REG,P1_08 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC8++0x03
line.long 0x00 "P1_09_MODE_REG,P1_09 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCC++0x03
line.long 0x00 "P1_10_MODE_REG,P1_10 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD0++0x03
line.long 0x00 "P1_11_MODE_REG,P1_11 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD4++0x03
line.long 0x00 "P1_12_MODE_REG,P1_12 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD8++0x03
line.long 0x00 "P1_13_MODE_REG,P1_13 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xDC++0x03
line.long 0x00 "P1_14_MODE_REG,P1_14 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE0++0x03
line.long 0x00 "P1_15_MODE_REG,P1_15 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE4++0x03
line.long 0x00 "P1_16_MODE_REG,P1_16 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE8++0x03
line.long 0x00 "P1_17_MODE_REG,P1_17 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xEC++0x03
line.long 0x00 "P1_18_MODE_REG,P1_18 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF0++0x03
line.long 0x00 "P1_19_MODE_REG,P1_19 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF4++0x03
line.long 0x00 "P1_20_MODE_REG,P1_20 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF8++0x03
line.long 0x00 "P1_21_MODE_REG,P1_21 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xFC++0x03
line.long 0x00 "P1_22_MODE_REG,P1_22 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x100++0x03
line.long 0x00 "P1_23_MODE_REG,P1_23 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x104++0x03
line.long 0x00 "P1_24_MODE_REG,P1_24 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x108++0x03
line.long 0x00 "P1_25_MODE_REG,P1_25 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10C++0x03
line.long 0x00 "P1_26_MODE_REG,P1_26 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x110++0x03
line.long 0x00 "P1_27_MODE_REG,P1_27 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x114++0x03
line.long 0x00 "P1_28_MODE_REG,P1_28 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x118++0x03
line.long 0x00 "P1_29_MODE_REG,P1_29 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x11C++0x03
line.long 0x00 "P1_30_MODE_REG,P1_30 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x120++0x03
line.long 0x00 "P1_31_MODE_REG,P1_31 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "P1_DATA_REG,P1 Data input / output Register"
hexmask.long 0x00 0.--31. 1. "P1_DATA,Set P1 output register when written Returns the value of P1 port when"
group.long 0x164++0x03
line.long 0x00 "P1_PADPWR_CTRL_REG,P1 Output Power Control Register"
bitfld.long 0x00 31. "P1_31_OUT_CTRL," "0,1"
bitfld.long 0x00 30. "P1_30_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 27. "P1_27_OUT_CTRL," "0,1"
bitfld.long 0x00 26. "P1_26_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 25. "P1_25_OUT_CTRL," "0,1"
bitfld.long 0x00 24. "P1_24_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 23. "P1_23_OUT_CTRL," "0,1"
bitfld.long 0x00 22. "P1_22_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 20. "P1_20_OUT_CTRL," "0,1"
bitfld.long 0x00 19. "P1_19_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 15. "P1_15_OUT_CTRL," "0,1"
bitfld.long 0x00 14. "P1_14_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 13. "P1_13_OUT_CTRL," "0,1"
bitfld.long 0x00 12. "P1_12_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 11. "P1_11_OUT_CTRL," "0,1"
bitfld.long 0x00 7. "P1_07_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 6. "P1_06_OUT_CTRL," "0,1"
bitfld.long 0x00 5. "P1_05_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 4. "P1_04_OUT_CTRL," "0,1"
bitfld.long 0x00 3. "P1_03_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 1. "P1_01_OUT_CTRL," "0,1"
bitfld.long 0x00 0. "P1_00_OUT_CTRL," "0,1"
group.long 0x1C++0x03
line.long 0x00 "P1_RESET_DATA_REG,P1 Reset port pins Register"
hexmask.long 0x00 0.--31. 1. "P1_RESET,Writing a 1 to P1[y] sets P1[y] to 0"
group.long 0x10++0x03
line.long 0x00 "P1_SET_DATA_REG,P1 Set port pins Register"
hexmask.long 0x00 0.--31. 1. "P1_SET,Writing a 1 to P1[y] sets P1[y] to 1"
group.long 0x174++0x03
line.long 0x00 "P1_WEAK_CTRL_REG,P1 Weak Pads Control Register"
bitfld.long 0x00 31. "P1_31_LOWDRV," "0,1"
bitfld.long 0x00 30. "P1_30_LOWDRV," "0,1"
newline
bitfld.long 0x00 27. "P1_27_LOWDRV," "0,1"
bitfld.long 0x00 26. "P1_26_LOWDRV," "0,1"
newline
bitfld.long 0x00 25. "P1_25_LOWDRV," "0,1"
bitfld.long 0x00 24. "P1_24_LOWDRV," "0,1"
newline
bitfld.long 0x00 23. "P1_23_LOWDRV," "0,1"
bitfld.long 0x00 22. "P1_22_LOWDRV," "0,1"
newline
bitfld.long 0x00 20. "P1_20_LOWDRV," "0,1"
bitfld.long 0x00 19. "P1_19_LOWDRV," "0,1"
newline
bitfld.long 0x00 15. "P1_15_LOWDRV," "0,1"
bitfld.long 0x00 14. "P1_14_LOWDRV," "0,1"
newline
bitfld.long 0x00 13. "P1_13_LOWDRV," "0,1"
bitfld.long 0x00 12. "P1_12_LOWDRV," "0,1"
newline
bitfld.long 0x00 11. "P1_11_LOWDRV," "0,1"
bitfld.long 0x00 7. "P1_07_LOWDRV," "0,1"
newline
bitfld.long 0x00 6. "P1_06_LOWDRV," "0,1"
bitfld.long 0x00 5. "P1_05_LOWDRV," "0,1"
newline
bitfld.long 0x00 4. "P1_04_LOWDRV," "0,1"
bitfld.long 0x00 3. "P1_03_LOWDRV," "0,1"
newline
bitfld.long 0x00 1. "P1_01_LOWDRV," "0,1"
bitfld.long 0x00 0. "P1_00_LOWDRV," "0,1"
group.long 0x124++0x03
line.long 0x00 "P2_00_MODE_REG,P2_00 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x128++0x03
line.long 0x00 "P2_01_MODE_REG,P2_01 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x12C++0x03
line.long 0x00 "P2_02_MODE_REG,P2_02 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x130++0x03
line.long 0x00 "P2_03_MODE_REG,P2_03 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x134++0x03
line.long 0x00 "P2_04_MODE_REG,P2_04 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x138++0x03
line.long 0x00 "P2_05_MODE_REG,P2_05 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x13C++0x03
line.long 0x00 "P2_06_MODE_REG,P2_06 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x140++0x03
line.long 0x00 "P2_07_MODE_REG,P2_07 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x144++0x03
line.long 0x00 "P2_08_MODE_REG,P2_08 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x148++0x03
line.long 0x00 "P2_09_MODE_REG,P2_09 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14C++0x03
line.long 0x00 "P2_10_MODE_REG,P2_10 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x150++0x03
line.long 0x00 "P2_11_MODE_REG,P2_11 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x154++0x03
line.long 0x00 "P2_12_MODE_REG,P2_12 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x158++0x03
line.long 0x00 "P2_13_MODE_REG,P2_13 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x15C++0x03
line.long 0x00 "P2_14_MODE_REG,P2_14 Mode Register"
bitfld.long 0x00 10. "PPOD," "0,1"
bitfld.long 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.long 0x00 0.--5. "PID,See P0_00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "P2_DATA_REG,P1 Data input / output Register"
hexmask.long.word 0x00 0.--14. 1. "P2_DATA,Set P2 output register when written Returns the value of P2 port when"
group.long 0x168++0x03
line.long 0x00 "P2_PADPWR_CTRL_REG,P2 Output Power Control Register"
bitfld.long 0x00 11. "P2_11_OUT_CTRL," "0,1"
bitfld.long 0x00 10. "P2_10_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 9. "P2_09_OUT_CTRL," "0,1"
bitfld.long 0x00 8. "P2_08_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 7. "P2_07_OUT_CTRL," "0,1"
bitfld.long 0x00 6. "P2_06_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 5. "P2_05_OUT_CTRL," "0,1"
bitfld.long 0x00 4. "P2_04_OUT_CTRL," "0,1"
newline
bitfld.long 0x00 1. "P2_01_OUT_CTRL," "0,1"
group.long 0x20++0x03
line.long 0x00 "P2_RESET_DATA_REG,P0 Reset port pins Register"
hexmask.long.word 0x00 0.--14. 1. "P2_RESET,Writing a 1 to P2[y] sets P2[y] to 0"
group.long 0x14++0x03
line.long 0x00 "P2_SET_DATA_REG,P1 Set port pins Register"
hexmask.long.word 0x00 0.--14. 1. "P2_SET,Writing a 1 to P2[y] sets P2[y] to 1"
group.long 0x178++0x03
line.long 0x00 "P2_WEAK_CTRL_REG,P2 Weak Pads Control Register"
bitfld.long 0x00 11. "P2_11_LOWDRV," "0,1"
bitfld.long 0x00 10. "P2_10_LOWDRV," "0,1"
newline
bitfld.long 0x00 9. "P2_09_LOWDRV," "0,1"
bitfld.long 0x00 8. "P2_08_LOWDRV," "0,1"
newline
bitfld.long 0x00 7. "P2_07_LOWDRV," "0,1"
bitfld.long 0x00 6. "P2_06_LOWDRV," "0,1"
newline
bitfld.long 0x00 5. "P2_05_LOWDRV," "0,1"
bitfld.long 0x00 4. "P2_04_LOWDRV," "0,1"
newline
bitfld.long 0x00 1. "P2_01_LOWDRV," "0,1"
group.long 0x180++0x03
line.long 0x00 "PAD_DRIVE_CTRL_REG,Pad drive control for SPI3/SDIO/eMMC"
bitfld.long 0x00 10.--11. "EMMC_DRIVE,pads drive current" "0: 4 mA,1: 8 mA,2: 12 mA,3: 16 mA"
bitfld.long 0x00 8.--9. "EMMC_SLEW,pads slew rate control" "0: Rise=1.7 V/ns Fall=1.9 V/ns (weak),1: Rise=2.0 V/ns Fall=2.3 V/ns,2: Rise=2.3 V/ns Fall=2.6 V/ns,3: Rise=2.4 V/ns Fall=2.7 V/ns (strong) Conditions"
newline
bitfld.long 0x00 6.--7. "SDIO_DRIVE,pads drive current" "0: 4 mA,1: 8 mA,2: 12 mA,3: 16 mA"
bitfld.long 0x00 4.--5. "SDIO_SLEW,QSPI pads slew rate control" "0: Rise=1.7 V/ns Fall=1.9 V/ns (weak),1: Rise=2.0 V/ns Fall=2.3 V/ns,2: Rise=2.3 V/ns Fall=2.6 V/ns,3: Rise=2.4 V/ns Fall=2.7 V/ns (strong) Conditions"
newline
bitfld.long 0x00 2.--3. "SPI3_DRIVE,pads drive current" "0: 4 mA,1: 8 mA,2: 12 mA,3: 16 mA"
bitfld.long 0x00 0.--1. "SPI3_SLEW,QSPI pads slew rate control" "0: Rise=1.7 V/ns Fall=1.9 V/ns (weak),1: Rise=2.0 V/ns Fall=2.3 V/ns,2: Rise=2.3 V/ns Fall=2.6 V/ns,3: Rise=2.4 V/ns Fall=2.7 V/ns (strong) Conditions"
tree.end
tree "GPREG"
base ad:0x50040100
group.long 0x08++0x03
line.long 0x00 "DEBUG_REG,Various debug information register"
bitfld.long 0x00 12. "ETM_TRACE_MAP_ON_PINS_EN," "0,1"
rbitfld.long 0x00 11. "SNC_CPU_IS_HALTED," "0,1"
bitfld.long 0x00 10. "HALT_SNC_CPU_EN," "0,1"
bitfld.long 0x00 9. "SNC_CPU_FREEZE_EN," "0,1"
newline
bitfld.long 0x00 8. "CROSS_CPU_HALT_SENSITIVITY,Select the cross CPU halt sensitivity" "0: Level triggered,1: Pulse triggered"
bitfld.long 0x00 7. "SYS_CPUWAIT_ON_JTAG," "0,1"
bitfld.long 0x00 6. "SYS_CPUWAIT," "0,1"
rbitfld.long 0x00 5. "CMAC_CPU_IS_HALTED," "0,1"
newline
rbitfld.long 0x00 4. "SYS_CPU_IS_HALTED," "0,1"
bitfld.long 0x00 3. "HALT_SYS_CPU_EN," "0,1"
bitfld.long 0x00 2. "HALT_CMAC_CPU_EN," "0,1"
bitfld.long 0x00 1. "CMAC_CPU_FREEZE_EN," "0,1"
newline
bitfld.long 0x00 0. "SYS_CPU_FREEZE_EN," "0,1"
group.long 0x0C++0x03
line.long 0x00 "GP_STATUS_REG,General purpose system status register"
bitfld.long 0x00 0. "CAL_PHASE,If '1' it designates that the chip is in Calibration Phase i.e" "0,1"
group.long 0x04++0x03
line.long 0x00 "RESET_FREEZE_REG,Controls unfreezing of various timers/counters (incl. DMA and USB)"
bitfld.long 0x00 13. "FRZ_SWTIM6,If '1' the SW Timer6 continues '0' is discarded" "0,1"
bitfld.long 0x00 12. "FRZ_SWTIM5,If '1' the SW Timer5 continues '0' is discarded" "0,1"
bitfld.long 0x00 11. "FRZ_SNC_WDOG,If '1' the SNC SW Watchdog Timer continues '0' is discarded" "0,1"
bitfld.long 0x00 10. "FRZ_CMAC_WDOG,If '1' the CMAC SW Watchdog Timer continues '0' is discarded" "0,1"
newline
bitfld.long 0x00 9. "FRZ_SWTIM4,If '1' the SW Timer4 continues '0' is discarded" "0,1"
bitfld.long 0x00 8. "FRZ_SWTIM3,If '1' the SW Timer3 continues '0' is discarded" "0,1"
bitfld.long 0x00 7. "FRZ_PWMLED,If '1' the PWM LED continues '0' is discarded" "0,1"
bitfld.long 0x00 6. "FRZ_SWTIM2,If '1' the SW Timer2 continues '0' is discarded" "0,1"
newline
bitfld.long 0x00 5. "FRZ_DMA,If '1' the DMA continues '0' is discarded" "0,1"
bitfld.long 0x00 4. "FRZ_USB,If '1' the USB continues '0' is discarded" "0,1"
bitfld.long 0x00 3. "FRZ_SYS_WDOG,If '1' the SYS SW Watchdog Timer continues '0' is discarded" "0,1"
bitfld.long 0x00 2. "FRZ_RESERVED," "0,1"
newline
bitfld.long 0x00 1. "FRZ_SWTIM,If '1' the SW Timer continues '0' is discarded" "0,1"
bitfld.long 0x00 0. "FRZ_WKUPTIM,If '1' the Wake Up Timer continues '0' is discarded" "0,1"
group.long 0x00++0x03
line.long 0x00 "SET_FREEZE_REG,Controls freezing of various timers/counters (incl. DMA and USB)"
bitfld.long 0x00 13. "FRZ_SWTIM6,If '1' the SW Timer6 is frozen '0' is discarded" "0,1"
bitfld.long 0x00 12. "FRZ_SWTIM5,If '1' the SW Timer5 is frozen '0' is discarded" "0,1"
bitfld.long 0x00 11. "FRZ_SNC_WDOG,If '1' the SNC SW Watchdog Timer is frozen '0' is discarded" "0,1"
bitfld.long 0x00 10. "FRZ_CMAC_WDOG,If '1' the CMAC SW Watchdog Timer is frozen '0' is discarded" "0,1"
newline
bitfld.long 0x00 9. "FRZ_SWTIM4,If '1' the SW Timer4 is frozen '0' is discarded" "0,1"
bitfld.long 0x00 8. "FRZ_SWTIM3,If '1' the SW Timer3 is frozen '0' is discarded" "0,1"
bitfld.long 0x00 7. "FRZ_PWMLED,If '1' the PWM LED is frozen '0' is discarded" "0,1"
bitfld.long 0x00 6. "FRZ_SWTIM2,If '1' the SW Timer2 is frozen '0' is discarded" "0,1"
newline
bitfld.long 0x00 5. "FRZ_DMA,If '1' the DMA is frozen '0' is discarded" "0,1"
bitfld.long 0x00 4. "FRZ_USB,If '1' the USB is frozen '0' is discarded" "0,1"
bitfld.long 0x00 3. "FRZ_SYS_WDOG,If '1' the SYS SW Watchdog Timer is frozen '0' is discarded" "0,1"
bitfld.long 0x00 2. "FRZ_RESERVED," "0,1"
newline
bitfld.long 0x00 1. "FRZ_SWTIM,If '1' the SW Timer is frozen '0' is discarded" "0,1"
bitfld.long 0x00 0. "FRZ_WKUPTIM,If '1' the Wake Up Timer is frozen '0' is discarded" "0,1"
group.long 0x18++0x03
line.long 0x00 "USBPAD_REG,USB pads control register"
bitfld.long 0x00 2. "USBPHY_FORCE_SW2_ON," "0,1"
bitfld.long 0x00 1. "USBPHY_FORCE_SW1_OFF," "0,1"
bitfld.long 0x00 0. "USBPAD_EN," "0,1"
tree.end
tree "GPU_CORE"
base ad:0x51001200
group.long 0xC4++0x03
line.long 0x00 "D2_CACHECTL,#49: cache control register Internal caches can be enabled/disabled and flushed using this register"
bitfld.long 0x00 3. "D2C_CACHECTL_FLUSH_TX,Flush texture cache" "0,1"
bitfld.long 0x00 2. "D2C_CACHECTL_ENABLE_TX,Texture cache enable" "0,1"
bitfld.long 0x00 1. "D2C_CACHECTL_FLUSH_FB,Flush framebuffer cache" "0,1"
bitfld.long 0x00 0. "D2C_CACHECTL_ENABLE_FB,Framebuffer cache enable" "0,1"
group.long 0xE8++0x03
line.long 0x00 "D2_COLKEY,#58: Color key value The R G and B components of the internal color representation of a texel is compared with the color key"
hexmask.long.tbyte 0x00 0.--23. 1. "COLKEY_RGB,Color Key Value RGB888"
group.long 0x64++0x03
line.long 0x00 "D2_COLOR1,#25: Base color register All color registers are *write only* reading will return undefined results"
hexmask.long 0x00 0.--31. 1. "COLOR1,"
group.long 0x68++0x03
line.long 0x00 "D2_COLOR2,#26: Secondary color register Secondary color is relevant only when rendering patterns textures or using a D2C_BC2 blendmod"
hexmask.long 0x00 0.--31. 1. "COLOR2,"
group.long 0x00++0x03
line.long 0x00 "D2_CONTROL,#0: geometry control register This register controls the pixel enumeration and selection units deciding which pixels are"
bitfld.long 0x00 27.--31. "RESERVED,reserved for SoftDave internal use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "D2C_LIMITERPRECISION,increase precision of limiters from 16.16 to 10.22" "0,1"
bitfld.long 0x00 23. "D2C_SPANSTORE,nextline span start is always equal or left to current-line span start" "0,1"
bitfld.long 0x00 22. "D2C_SPANABORT,shape is horizontally convex" "0,1"
newline
bitfld.long 0x00 21. "D2C_UNIONCD,combine outputs C & D as union (output is final)" "0,1"
bitfld.long 0x00 20. "D2C_UNIONAB,combine outputs A & B as union (output is called C)" "0,1"
bitfld.long 0x00 19. "D2C_UNION56,combine limter 5 & 6 as union (output is called D)" "0,1"
bitfld.long 0x00 18. "D2C_UNION34,combine limter 3 & 4 as union (output is called B)" "0,1"
newline
bitfld.long 0x00 17. "D2C_UNION12,combine limter 1 & 2 as union (output is called A)" "0,1"
bitfld.long 0x00 16. "D2C_BAND2ENABLE,enable band postprocess for limiter 2 (see <D2_L2BAND>)" "0,1"
bitfld.long 0x00 15. "D2C_BAND1ENABLE,enable band postprocess for limiter 1 (see <D2_L1BAND>)" "0,1"
bitfld.long 0x00 14. "D2C_LIM6THRESHOLD,enable limiter 6 threshold mode" "0,1"
newline
bitfld.long 0x00 13. "D2C_LIM5THRESHOLD,enable limiter 5 threshold mode" "0,1"
bitfld.long 0x00 12. "D2C_LIM4THRESHOLD,enable limiter 4 threshold mode" "0,1"
bitfld.long 0x00 11. "D2C_LIM3THRESHOLD,enable limiter 3 threshold mode" "0,1"
bitfld.long 0x00 10. "D2C_LIM2THRESHOLD,enable limiter 2 threshold mode" "0,1"
newline
bitfld.long 0x00 9. "D2C_LIM1THRESHOLD,enable limiter 1 threshold mode" "0,1"
bitfld.long 0x00 8. "D2C_QUAD3ENABLE,enable quadratic coupling of limiters 5 and 6" "0,1"
bitfld.long 0x00 7. "D2C_QUAD2ENABLE,enable quadratic coupling of limiters 3 and 4" "0,1"
bitfld.long 0x00 6. "D2C_QUAD1ENABLE,enable quadratic coupling of limiters 1 and 2" "0,1"
newline
bitfld.long 0x00 5. "D2C_LIM6ENABLE,enable limiter 6" "0,1"
bitfld.long 0x00 4. "D2C_LIM5ENABLE,enable limiter 5" "0,1"
bitfld.long 0x00 3. "D2C_LIM4ENABLE,enable limiter 4" "0,1"
bitfld.long 0x00 2. "D2C_LIM3ENABLE,enable limiter 3" "0,1"
newline
bitfld.long 0x00 1. "D2C_LIM2ENABLE,enable limiter 2" "0,1"
bitfld.long 0x00 0. "D2C_LIM1ENABLE,enable limiter 1" "0,1"
group.long 0x04++0x03
line.long 0x00 "D2_CONTROL2,#1: surface control register This register controls the colorization texturing and blending units deciding what color a p"
bitfld.long 0x00 31. "D2C_RLEFORMAT2,bit1 of RLE texel format" "0,1"
bitfld.long 0x00 30. "D2C_RLEFORMAT1,bit0 of RLE texel format" "0,1"
bitfld.long 0x00 29. "D2C_BDIA,dst factor for alpha channel will be inverted (meaning 1-a or 1-1 depending on BDFA)" "0,1"
bitfld.long 0x00 28. "D2C_BSIA,src factor for alpha channel will be inverted (meaning 1-a or 1-1 depending on BSFA)" "0,1"
newline
bitfld.long 0x00 27. "D2C_CLUTFORMAT1,bit0 of the CLUT entry format" "0,1"
bitfld.long 0x00 26. "D2C_COLKEY_ENABLE,enable color keying (see also <D2_COLKEY> and feature bits of <D2_HWREVISION>)" "0,1"
bitfld.long 0x00 25. "D2C_CLUT_ENABLE,enable the use of the CLUT (see also feature bits of <D2_HWREVISION>) if disabled the texture indices are written to FB" "0,1"
bitfld.long 0x00 24. "D2C_RLE_ENABLE,enable RLE decoder (see also feature bits of <D2_HWREVISION>)" "0,1"
newline
bitfld.long 0x00 23. "D2C_WRITEALPHA2,bit1 of the 'alpha source' (depends on USE_ACB)" "0,1"
bitfld.long 0x00 22. "D2C_WRITEALPHA1,bit0 of the 'alpha source' (depends on USE_ACB)" "0,1"
bitfld.long 0x00 21. "D2C_WRITEFORMAT2,bit1 of the framebuffer format descriptor" "0,1"
bitfld.long 0x00 20. "D2C_WRITEFORMAT1,bit0 of the framebuffer format descriptor" "0,1"
newline
bitfld.long 0x00 19. "D2C_READFORMAT2,bit1 of the texture format descriptor" "0,1"
bitfld.long 0x00 18. "D2C_READFORMAT1,bit0 of the texture format descriptor" "0,1"
bitfld.long 0x00 17. "D2C_TEXTUREFILTERY,linear filtering on texture v axis" "0,1"
bitfld.long 0x00 16. "D2C_TEXTUREFILTERX,linear filtering on texture u axis" "0,1"
newline
bitfld.long 0x00 15. "D2C_TEXTURECLAMPY,clamp instead of mask v coordinate" "0,1"
bitfld.long 0x00 14. "D2C_TEXTURECLAMPX,clamp instead of mask u coordinate" "0,1"
bitfld.long 0x00 13. "D2C_BC2,blending for color channels is done with <D2_COLOR2> instead of the real dst value" "0,1"
bitfld.long 0x00 12. "D2C_BDI,dst factor for color channels will be inverted (meaning 1-a or 1-1 depending on BDF)" "0,1"
newline
bitfld.long 0x00 11. "D2C_BSI,src factor for color channels will be inverted (meaning 1-a or 1-1 depending on BSF)" "0,1"
bitfld.long 0x00 10. "D2C_BDF,dst factor for color channels is alpha (factor is 1 per default)" "0,1"
bitfld.long 0x00 9. "D2C_BSF,src factor for color channels is alpha (factor is 1 per default)" "0,1"
bitfld.long 0x00 8. "D2C_WRITEFORMAT3,bit2 of the framebuffer format descriptor" "0,1"
newline
bitfld.long 0x00 7. "D2C_BDFA,dst factor for alpha channel is alpha (factor is 1 per default)" "0,1"
bitfld.long 0x00 6. "D2C_BSFA,src factor for alpha channel is alpha (factor is 1 per default)" "0,1"
bitfld.long 0x00 5. "D2C_READFORMAT4,bit3 of the texture format descriptor" "0,1"
bitfld.long 0x00 4. "D2C_READFORMAT3,bit2 of the texture format descriptor" "0,1"
newline
bitfld.long 0x00 3. "USE_ACB,use full alpha channel blending else use write-alpha mode" "0,1"
bitfld.long 0x00 2. "D2C_PATTERNSOURCEL5,Limiter 5 is used as pattern index instead of the default U-Limiter" "0,1"
bitfld.long 0x00 1. "D2C_TEXTUREENABLE,Pixel source is read from texture and used as an alpha to blend between <D2_COLOR1> and <D2_COLOR2>" "0,1"
bitfld.long 0x00 0. "D2C_PATTERNENABLE,Pixel source is a pattern color (blend of <D2_COLOR1> and <D2_COLOR2> depending on <D2_PATTERN> and pattern index)" "0,1"
group.long 0x08++0x03
line.long 0x00 "D2_CONTROL3,#2: burst length limit control register This register controls the burst length limit for the master bus interfaces Log2 of"
bitfld.long 0x00 24.--26. "BURSTLENGTH_MDL,Log2 of the burst length limit for MDL" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "BURSTLENGTH_MTX,Log2 of the burst length limit for MTX" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "BURSTLENGTH_MFBW,Log2 of the burst length limit for MFB" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "BURSTLENGTH_MFBR,Log2 of the burst length limit for MFB" "0,1,2,3,4,5,6,7"
group.long 0xC8++0x03
line.long 0x00 "D2_DLISTSTART,#50: Displaylist start address Setting a new displaylist base address (writing to D2_DLISTSTART) *triggers* execution of th"
hexmask.long 0x00 0.--31. 1. "DLISTSTART,"
group.long 0xF0++0x03
line.long 0x00 "D2_HWREVISION,#1: hardware version and feature set ID Read this (constant) register to identify the present hardware revision and feature"
rbitfld.long 0x00 28. "FB_BURSTSPLITTING,bursts can be split with respect to burst length limit" "0,1"
rbitfld.long 0x00 27. "FB_ALPHACHANNELBLENDING,full alpha channel blending available" "0,1"
rbitfld.long 0x00 26. "FB_HILIMITERPRECISION,increasable precision of limiters available" "0,1"
rbitfld.long 0x00 25. "FB_COLORKEY,color keying available" "0,1"
newline
rbitfld.long 0x00 24. "FB_TEXCLUT256,extend CLUT to 256x32bit ARGB8888" "0,1"
rbitfld.long 0x00 23. "FB_RLEUNIT,RLE texture decoder available" "0,1"
rbitfld.long 0x00 22. "FB_FBPREFETCH,Framebuffer prefetch available" "0,1"
rbitfld.long 0x00 21. "FB_TEXCLUT,Color Lookup Table 16x24bit for indexed textureformat available" "0,1"
newline
rbitfld.long 0x00 20. "FB_PERFCOUNT,Two performance counters available" "0,1"
rbitfld.long 0x00 19. "FB_TXCACHE,Texture Cache available" "0,1"
rbitfld.long 0x00 18. "FB_FBCACHE,Framebuffer Cache available" "0,1"
rbitfld.long 0x00 17. "FB_DLR,DisplayListReader available" "0,1"
newline
rbitfld.long 0x00 16. "FB_SWDAVE,Software D/AVE" "0,1"
rbitfld.long 0x00 12.--15. "HWTYPE,D/AVE Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 8.--11. "HWBRANCH,Branch number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "HWREVISION,Revision number"
group.long 0xC0++0x03
line.long 0x00 "D2_IRQCTL,#48: interrupt control register DAVE2 features three sources for interrupts"
bitfld.long 0x00 5. "D2IRQCTL_CLR_BUS_ERROR,Clear Interrupt 'Bus error'" "0,1"
bitfld.long 0x00 4. "D2IRQCTL_ENABLE_BUS_ERROR,Interruptmask enable 'Bus error'" "0,1"
bitfld.long 0x00 3. "D2IRQCTL_CLR_FINISH_DLIST,Clear Interrupt 'Displaylist is finished'" "0,1"
bitfld.long 0x00 2. "D2IRQCTL_CLR_FINISH_ENUM,Clear Interrupt 'Enumeration is finished'" "0,1"
newline
bitfld.long 0x00 1. "D2IRQCTL_ENABLE_FINISH_DLIST,Interruptmask enable 'Displaylist is finished'" "0,1"
bitfld.long 0x00 0. "D2IRQCTL_ENABLE_FINISH_ENUM,Interruptmask enable 'Enumeration is finished'" "0,1"
group.long 0x58++0x03
line.long 0x00 "D2_L1BAND,#22: Limiter1 band width parameter Postfilter First two limiter outputs can be routed through an additional unit before cla"
hexmask.long 0x00 0.--31. 1. "L1BAND,"
group.long 0x10++0x03
line.long 0x00 "D2_L1START,#4: Limiter1 start value All limiter registers are *write only* reading will return undefined results"
hexmask.long 0x00 0.--31. 1. "L1START,"
group.long 0x28++0x03
line.long 0x00 "D2_L1XADD,#10: Limiter1 X-Axis increment The xadd value is the 16:16 fixedpoint difference between two samples with a distance of 1 pix"
hexmask.long 0x00 0.--31. 1. "L1XADD,"
group.long 0x40++0x03
line.long 0x00 "D2_L1YADD,#16: Limiter1 Y-Axis increment The yadd value is the 16:16 fixedpoint difference between two samples with a distance of 1 pix"
hexmask.long 0x00 0.--31. 1. "L1YADD,"
group.long 0x5C++0x03
line.long 0x00 "D2_L2BAND,#23: Limiter2 band width parameter see &lt D2_L1BAND&gt"
hexmask.long 0x00 0.--31. 1. "L2BAND,"
group.long 0x14++0x03
line.long 0x00 "D2_L2START,#5: Limiter2 start value see &lt D2_L1START&gt"
hexmask.long 0x00 0.--31. 1. "L2START,"
group.long 0x2C++0x03
line.long 0x00 "D2_L2XADD,#11: Limiter2 X-Axis increment see &lt D2_L1XADD&gt"
hexmask.long 0x00 0.--31. 1. "L2XADD,"
group.long 0x44++0x03
line.long 0x00 "D2_L2YADD,#17: Limiter2 Y-Axis increment see &lt D2_L1YADD&gt"
hexmask.long 0x00 0.--31. 1. "L2YADD,"
group.long 0x18++0x03
line.long 0x00 "D2_L3START,#6: Limiter3 start value see &lt D2_L1START&gt"
hexmask.long 0x00 0.--31. 1. "L3START,"
group.long 0x30++0x03
line.long 0x00 "D2_L3XADD,#12: Limiter3 X-Axis increment"
hexmask.long 0x00 0.--31. 1. "L3XADD,"
group.long 0x48++0x03
line.long 0x00 "D2_L3YADD,#18: Limiter3 Y-Axis increment see &lt D2_L1YADD&gt"
hexmask.long 0x00 0.--31. 1. "L3YADD,"
group.long 0x1C++0x03
line.long 0x00 "D2_L4START,#7: Limiter4 start value see &lt D2_L1START&gt"
hexmask.long 0x00 0.--31. 1. "L4START,"
group.long 0x34++0x03
line.long 0x00 "D2_L4XADD,#13: Limiter4 X-Axis increment see &lt D2_L1XADD&gt"
hexmask.long 0x00 0.--31. 1. "L4XADD,"
group.long 0x4C++0x03
line.long 0x00 "D2_L4YADD,#19: Limiter4 Y-Axis increment see &lt D2_L1YADD&gt"
hexmask.long 0x00 0.--31. 1. "L4YADD,"
group.long 0x20++0x03
line.long 0x00 "D2_L5START,#8: Limiter5 start value see &lt D2_L1START&gt"
hexmask.long 0x00 0.--31. 1. "L5START,"
group.long 0x38++0x03
line.long 0x00 "D2_L5XADD,#14: Limiter5 X-Axis increment see &lt D2_L1XADD&gt"
hexmask.long 0x00 0.--31. 1. "L5XADD,"
group.long 0x50++0x03
line.long 0x00 "D2_L5YADD,#20: Limiter5 Y-Axis increment see &lt D2_L1YADD&gt"
hexmask.long 0x00 0.--31. 1. "L5YADD,"
group.long 0x24++0x03
line.long 0x00 "D2_L6START,#9: Limiter6 start value see &lt D2_L1START&gt"
hexmask.long 0x00 0.--31. 1. "L6START,"
group.long 0x3C++0x03
line.long 0x00 "D2_L6XADD,#15: Limiter6 X-Axis increment see &lt D2_L1XADD&gt"
hexmask.long 0x00 0.--31. 1. "L6XADD,"
group.long 0x54++0x03
line.long 0x00 "D2_L6YADD,#21: Limiter6 Y-Axis increment see &lt D2_L1YADD&gt"
hexmask.long 0x00 0.--31. 1. "L6YADD,"
group.long 0x90++0x03
line.long 0x00 "D2_LUSTART,#36: U Limiter start value The start value is a 16:16 fixedpoint number valid at the first pixel of the bounding box"
hexmask.long 0x00 0.--31. 1. "LUSTART,"
group.long 0x94++0x03
line.long 0x00 "D2_LUXADD,#37: U Limiter X-Axis increment The add value for U is the 16:16 fixedpoint difference between two samples with a distance o"
hexmask.long 0x00 0.--31. 1. "LUXADD,"
group.long 0x98++0x03
line.long 0x00 "D2_LUYADD,#38: U Limiter Y-Axis increment The add value for U is the 16:16 fixedpoint difference between two samples with a distance o"
hexmask.long 0x00 0.--31. 1. "LUYADD,"
group.long 0xA0++0x03
line.long 0x00 "D2_LVSTARTF,#40: V Limiter start value fractional part The start value is a 32:16 fixedpoint number valid at the first pixel of the boun"
hexmask.long.word 0x00 0.--15. 1. "LVSTARTF,fractional part"
group.long 0x9C++0x03
line.long 0x00 "D2_LVSTARTI,#39: V Limiter start value integer part"
hexmask.long 0x00 0.--31. 1. "LVSTARTI,"
group.long 0xA4++0x03
line.long 0x00 "D2_LVXADDI,#41: V Limiter X-Axis increment integer part The add value for V is the 32:16 fixedpoint difference between two samples with"
hexmask.long 0x00 0.--31. 1. "LVXADDI,"
group.long 0xA8++0x03
line.long 0x00 "D2_LVYADDI,#42: V Limiter Y-Axis increment integer part The add value for V is the 32:16 fixedpoint difference between two samples with"
hexmask.long 0x00 0.--31. 1. "LVYADDI,"
group.long 0xAC++0x03
line.long 0x00 "D2_LVYXADDF,#43: V Limiter X and Y increment fractional parts"
hexmask.long.word 0x00 16.--31. 1. "D2_LVYADDI_FRAC,Y increment fractional part for <D2_LVYADDI>"
hexmask.long.word 0x00 0.--15. 1. "D2_LVXADDI_FRAC,X increment fractional part for <D2_LVXADDI>"
group.long 0x80++0x03
line.long 0x00 "D2_ORIGIN,#32: address of the first pixel in framebuffer Writing to &lt D2_ORIGIN&gt will *trigger* DAVE2 to start rendering"
hexmask.long 0x00 0.--31. 1. "ORIGIN,"
group.long 0x74++0x03
line.long 0x00 "D2_PATTERN,#29: Pattern register Each bit in the pattern register is interpreted as a reference to one of the two color registers ( 0bi"
hexmask.long 0x00 0.--31. 1. "PATTERN,"
group.long 0xCC++0x03
line.long 0x00 "D2_PERFCOUNT1,#51: Performance counter Writing to the D2_PERFCOUNT1 register resets the first internal performance counter to the specifie"
hexmask.long 0x00 0.--31. 1. "PERFCOUNT1,"
group.long 0xD0++0x03
line.long 0x00 "D2_PERFCOUNT2,#52: Performance counter Writing to the D2_PERFCOUNT2 register resets the second internal performance counter to the specifi"
hexmask.long 0x00 0.--31. 1. "PERFCOUNT2,"
group.long 0xD4++0x03
line.long 0x00 "D2_PERFTRIGGER,#53: Performance counters control register Select the internal event that will increment &lt D2_PERFCOUNT1&gt respectively &"
hexmask.long.word 0x00 16.--31. 1. "PERFTRIGGER2,Select the internal event that will increment D2_PERFCOUNT2 register"
hexmask.long.word 0x00 0.--15. 1. "PERFTRIGGER1,Select the internal event that will increment D2_PERFCOUNT1 register"
group.long 0x7C++0x03
line.long 0x00 "D2_PITCH,#31: framebuffer pitch and spanstore delay"
hexmask.long.word 0x00 16.--31. 1. "SSD,spanstore delay the number of scanlines to delay spanstore operations"
hexmask.long.word 0x00 0.--15. 1. "PITCH,the width (in pixels) of one framebuffer scanline"
group.long 0x78++0x03
line.long 0x00 "D2_SIZE,#30: bounding box dimension"
hexmask.long.word 0x00 16.--31. 1. "SIZEY,the height (in pixels) of the primitives bounding box"
hexmask.long.word 0x00 0.--15. 1. "SIZEX,the width (in pixels) of the primitives bounding box"
group.long 0xF4++0x03
line.long 0x00 "D2_STATUS,#0: status control register The current dave status can be polled by reading this register"
rbitfld.long 0x00 8.--10. "D2C_IRQ_BUS_ERROR_SRC,source interface of bus error" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 6. "D2C_IRQ_BUS_ERROR,IRQ on bus error" "0,1"
rbitfld.long 0x00 5. "D2C_IRQ_DLIST,IRQ on display list finish" "0,1"
rbitfld.long 0x00 4. "D2C_IRQ_ENUM,IRQ on enumeration finish" "0,1"
newline
rbitfld.long 0x00 3. "D2C_DLISTACTIVE,display list active cant direct access hwregs" "0,1"
rbitfld.long 0x00 2. "D2C_CACHE_DIRTY,framebuffer cache dirty cant flip frame" "0,1"
rbitfld.long 0x00 1. "D2C_BUSY_WRITE,framebuffer writeback busy cant change framebuffer type" "0,1"
rbitfld.long 0x00 0. "D2C_BUSY_ENUM,enumeration unit busy cant start new primitive" "0,1"
group.long 0xD8++0x03
line.long 0x00 "D2_TEXCLUT,#54: Color Lookup Table for the indexed texture format 16x24bit Triggers a write into the CLUT if CLUT size is 16 x 24bit"
hexmask.long.byte 0x00 24.--31. 1. "TEXCLUT_INDEX,Index of the CLUT entry that shall be written"
hexmask.long.tbyte 0x00 0.--23. 1. "TEXCLUT_RGB,Color Value RGB888"
group.long 0xDC++0x03
line.long 0x00 "D2_TEXCLUT_ADDR,#55: Color Lookup Table write address for the indexed texture format 256x32bit Start address for consecutive writes to &lt D2"
hexmask.long.byte 0x00 0.--7. 1. "TEXCLUT_ADDR,write address"
group.long 0xE0++0x03
line.long 0x00 "D2_TEXCLUT_DATA,#56: Color Lookup Table write data for the indexed texture format 256x32bit Writes one 32 bit color value into the CLUT if CL"
hexmask.long 0x00 0.--31. 1. "TEXCLUT_ARGB,Color value ARGB8888 if CLUTFORMAT = argb8888"
group.long 0xE4++0x03
line.long 0x00 "D2_TEXCLUT_OFFSET,#57: Offset to the texture index for the indexed texture formats i8 i4 i2 and i1 The index offset is combined with the text"
hexmask.long.byte 0x00 0.--7. 1. "TEXCLUT_OFFSET,index offset"
group.long 0xB8++0x03
line.long 0x00 "D2_TEXMASK,#46: Texture size or texture address mask Depending on the clamping mode this register encodes the clamp limit or wrap mask"
hexmask.long.tbyte 0x00 11.--31. 1. "TEXVMASK,V mask"
hexmask.long.word 0x00 0.--10. 1. "TEXUMASK,U mask"
group.long 0xBC++0x03
line.long 0x00 "D2_TEXORIGIN,#47: Texture base address All texture registers are *write only* reading will return undefined results"
hexmask.long 0x00 0.--31. 1. "TEXORIGIN,"
group.long 0xB4++0x03
line.long 0x00 "D2_TEXPITCH,#45: Texels per texture line Pitch is equal or bigger than texture width"
hexmask.long 0x00 0.--31. 1. "TEXPITCH,"
tree.end
tree "GPU_REG"
base ad:0x51001100
group.long 0x00++0x03
line.long 0x00 "GPU_CTRL_REG,"
bitfld.long 0x00 6. "PWRS_B,Power save mode read port memories" "0: Disabled,1: Enabled"
bitfld.long 0x00 2.--5. "GPU_RAM_MS,Margin setting for GPU memories" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "GPU_RAM_MSE,Margin enable for GPU memories" "0,1"
bitfld.long 0x00 0. "GPU_EN,GPU enable" "0: Enable,1: Disable"
tree.end
tree "I2C (Inter-Integrated Circuit)"
tree "I2C"
base ad:0x50020600
group.long 0x98++0x03
line.long 0x00 "I2C_ACK_GENERAL_CALL_REG,I2C ACK General Call Register"
bitfld.long 0x00 0. "ACK_GEN_CALL,ACK General Call" "0: Generate NACK for General Call,1: Generate ACK for a General Call"
group.long 0x5C++0x03
line.long 0x00 "I2C_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register"
rbitfld.long 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.long 0x68++0x03
line.long 0x00 "I2C_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register"
rbitfld.long 0x00 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register" "0,1"
group.long 0x40++0x03
line.long 0x00 "I2C_CLR_INTR_REG,Clear Combined and Individual Interrupt Register"
rbitfld.long 0x00 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the I2C_TX_ABRT_SOURCE register" "0,1"
group.long 0x50++0x03
line.long 0x00 "I2C_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register"
rbitfld.long 0x00 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x58++0x03
line.long 0x00 "I2C_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x48++0x03
line.long 0x00 "I2C_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x44++0x03
line.long 0x00 "I2C_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x64++0x03
line.long 0x00 "I2C_CLR_START_DET_REG,Clear START_DET Interrupt Register"
rbitfld.long 0x00 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register" "0,1"
group.long 0x60++0x03
line.long 0x00 "I2C_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register"
rbitfld.long 0x00 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register" "0,1"
group.long 0x54++0x03
line.long 0x00 "I2C_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register"
rbitfld.long 0x00 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the I2C_TX_ABRT_SOURCE register" "0,1"
group.long 0x4C++0x03
line.long 0x00 "I2C_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register"
rbitfld.long 0x00 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x00++0x03
line.long 0x00 "I2C_CON_REG,I2C Control Register"
rbitfld.long 0x00 10. "I2C_STOP_DET_IF_MASTER_ACTIVE,In Master mode" "0: issues the STOP_DET irrespective of whether,1: issues the STOP_DET interrupt only when master"
newline
bitfld.long 0x00 9. "I2C_RX_FIFO_FULL_HLD_CTRL,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH" "0: Overflow when RX_FIFO is full,1: Hold bus when RX_FIFO is full"
newline
bitfld.long 0x00 8. "I2C_TX_EMPTY_CTRL,This bit controls the generation of the TX_EMPTY interrupt as described in the IC_RAW_INTR_STAT register" "0: Default behaviour of TX_EMPTY interrupt,1: Controlled generation of TX_EMPTY interrupt"
newline
bitfld.long 0x00 7. "I2C_STOP_DET_IFADDRESSED," "0,1"
newline
bitfld.long 0x00 6. "I2C_SLAVE_DISABLE,Slave enabled or disabled after reset is applied which means software does not have to configure the slave" "0: slave is enabled,1: slave is disabled Software should ensure that"
newline
bitfld.long 0x00 5. "I2C_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master" "0: disable,1: enable"
newline
bitfld.long 0x00 4. "I2C_10BITADDR_MASTER,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x00 3. "I2C_10BITADDR_SLAVE,When acting as a slave this bit controls whether the controller responds to 7- or 10-bit addresses" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x00 1.--2. "I2C_SPEED,These bits control at which speed the controller operates" "?,1: standard mode (100 kbit/s),2: fast mode (400 kbit/s),3: high speed mode"
newline
bitfld.long 0x00 0. "I2C_MASTER_MODE,This bit controls whether the controller master is enabled" "0: master disabled,1: master enabled Software should ensure that"
group.long 0x10++0x03
line.long 0x00 "I2C_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register"
bitfld.long 0x00 10. "I2C_RESTART,This bit controls whether a RESTART is issued before the byte is sent or received" "0: If IC_RESTART_EN is 1 a RESTART is issued only,1: If IC_RESTART_EN is 1 a RESTART is issued.."
newline
bitfld.long 0x00 9. "I2C_STOP,This bit controls whether a STOP is issued after the byte is sent or received" "0: STOP is not issued after this byte regardless..,1: STOP is issued after this byte regardless of"
newline
bitfld.long 0x00 8. "I2C_CMD,This bit controls whether a read or a write is performed" "0: Write When,1: "
newline
hexmask.long.byte 0x00 0.--7. 1. "I2C_DAT,This register contains the data to be transmitted or received on the I2C bus"
group.long 0x88++0x03
line.long 0x00 "I2C_DMA_CR_REG,DMA Control Register"
bitfld.long 0x00 1. "TDMAE,Transmit DMA Enable" "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x00 0. "RDMAE,Receive DMA Enable" "0: Receive DMA disabled,1: Receive DMA enabled"
group.long 0x90++0x03
line.long 0x00 "I2C_DMA_RDLR_REG,I2C Receive Data Level Register"
bitfld.long 0x00 0.--4. "DMARDL,Receive Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8C++0x03
line.long 0x00 "I2C_DMA_TDLR_REG,DMA Transmit Data Level Register"
bitfld.long 0x00 0.--4. "DMATDL,Transmit Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C++0x03
line.long 0x00 "I2C_ENABLE_REG,I2C Enable Register"
bitfld.long 0x00 2. "I2C_TX_CMD_BLOCK,In Master mode" "0,1"
newline
bitfld.long 0x00 1. "I2C_ABORT,The software can abort the I2C transfer in master mode by setting this bit" "0,1"
newline
bitfld.long 0x00 0. "I2C_EN,Controls whether the controller is enabled" "0: Disables the controller (TX and RX FIFOs are,1: Enables the controller Software can disable the"
group.long 0x9C++0x03
line.long 0x00 "I2C_ENABLE_STATUS_REG,I2C Enable Status Register"
rbitfld.long 0x00 2. "SLV_RX_DATA_LOST,Slave Received Data Lost" "0: Slave RX Data is not lost,1: Slave RX Data is lost"
newline
rbitfld.long 0x00 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive)" "0: Slave is disabled when it is idle,1: Slave is disabled when it is active"
newline
rbitfld.long 0x00 0. "IC_EN,ic_en Status" "0: I2C disabled,1: I2C enabled"
group.long 0x1C++0x03
line.long 0x00 "I2C_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x20++0x03
line.long 0x00 "I2C_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x0C++0x03
line.long 0x00 "I2C_HS_MADDR_REG,I2C High Speed Master Mode Code Address Register"
bitfld.long 0x00 0.--2. "I2C_IC_HS_MAR,This bit field holds the value of the I2C HS mode master code" "0,1,2,3,4,5,6,7"
group.long 0x24++0x03
line.long 0x00 "I2C_HS_SCL_HCNT_REG,High Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_HS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x28++0x03
line.long 0x00 "I2C_HS_SCL_LCNT_REG,High Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_HS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0xA0++0x03
line.long 0x00 "I2C_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size"
hexmask.long.byte 0x00 0.--7. 1. "I2C_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.long 0xA4++0x03
line.long 0x00 "I2C_IC_HS_SPKLEN_REG,I2C HS spike suppression limit Size"
hexmask.long.byte 0x00 0.--7. 1. "I2C_HS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.long 0x30++0x03
line.long 0x00 "I2C_INTR_MASK_REG,I2C Interrupt Mask Register"
rbitfld.long 0x00 14. "M_SCL_STUCK_AT_LOW,M_SCL_STUCK_AT_LOW Register field Reserved bits" "0,1"
newline
bitfld.long 0x00 13. "M_MASTER_ON_HOLD,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 12. "M_RESTART_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 11. "M_GEN_CALL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 10. "M_START_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 9. "M_STOP_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 8. "M_ACTIVITY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 7. "M_RX_DONE,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 6. "M_TX_ABRT,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 5. "M_RD_REQ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 4. "M_TX_EMPTY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 3. "M_TX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 2. "M_RX_FULL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 1. "M_RX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 0. "M_RX_UNDER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
group.long 0x2C++0x03
line.long 0x00 "I2C_INTR_STAT_REG,I2C Interrupt Status Register"
rbitfld.long 0x00 14. "R_SCL_STUCK_AT_LOW," "0,1"
newline
rbitfld.long 0x00 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty" "0,1"
newline
rbitfld.long 0x00 12. "R_RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed" "0,1"
newline
rbitfld.long 0x00 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
newline
rbitfld.long 0x00 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 9. "R_STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 8. "R_ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
newline
rbitfld.long 0x00 7. "R_RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.long 0x00 6. "R_TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
newline
rbitfld.long 0x00 5. "R_RD_REQ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
newline
rbitfld.long 0x00 4. "R_TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
newline
rbitfld.long 0x00 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
newline
rbitfld.long 0x00 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
newline
rbitfld.long 0x00 1. "R_RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
newline
rbitfld.long 0x00 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.long 0x34++0x03
line.long 0x00 "I2C_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register"
rbitfld.long 0x00 14. "SCL_STUCK_AT_LOW,CL_STUCK_AT_LOW Register field Reserved bits" "0,1"
newline
rbitfld.long 0x00 13. "MASTER_ON_HOLD,ndicates whether master is holding the bus and TX FIFO is empty" "0,1"
newline
rbitfld.long 0x00 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed" "0,1"
newline
rbitfld.long 0x00 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
newline
rbitfld.long 0x00 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 8. "ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
newline
rbitfld.long 0x00 7. "RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.long 0x00 6. "TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
newline
rbitfld.long 0x00 5. "RD_REQ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
newline
rbitfld.long 0x00 4. "TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
newline
rbitfld.long 0x00 3. "TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
newline
rbitfld.long 0x00 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
newline
rbitfld.long 0x00 1. "RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
newline
rbitfld.long 0x00 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.long 0x78++0x03
line.long 0x00 "I2C_RXFLR_REG,I2C Receive FIFO Level Register"
rbitfld.long 0x00 0.--5. "RXFLR,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "I2C_RX_TL_REG,I2C Receive FIFO Threshold Register"
bitfld.long 0x00 0.--4. "RX_TL,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "I2C_SAR_REG,I2C Slave Address Register"
hexmask.long.word 0x00 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave"
group.long 0x7C++0x03
line.long 0x00 "I2C_SDA_HOLD_REG,I2C SDA Hold Time Length Register"
hexmask.long.byte 0x00 16.--23. 1. "I2C_SDA_RX_HOLD,Sets the required SDA hold time in units of ic_clk period when receiver"
newline
hexmask.long.word 0x00 0.--15. 1. "I2C_SDA_TX_HOLD,Sets the required SDA hold time in units of ic_clk period when transmitter"
group.long 0x94++0x03
line.long 0x00 "I2C_SDA_SETUP_REG,I2C SDA Setup Register"
hexmask.long.byte 0x00 0.--7. 1. "SDA_SETUP,SDA Setup"
group.long 0x14++0x03
line.long 0x00 "I2C_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x18++0x03
line.long 0x00 "I2C_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x70++0x03
line.long 0x00 "I2C_STATUS_REG,I2C Status Register"
rbitfld.long 0x00 10. "LV_HOLD_RX_FIFO_FULL,This bit indicates the BUS Hold in Slave mode due to Rx FIFO is Full and an additional byte has been received" "0: Slave is not holding the bus or Bus hold is not,1: Slave holds the bus due to Rx FIFO is full"
newline
rbitfld.long 0x00 9. "SLV_HOLD_TX_FIFO_EMPTY,This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty" "0: Slave is not holding the bus or Bus hold is not,1: Slave holds the bus due to Tx FIFO is empty"
newline
rbitfld.long 0x00 8. "MST_HOLD_RX_FIFO_FULL,This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received" "0: Master is not holding the bus or Bus hold is..,1: Master holds the bus due to Rx FIFO is full"
newline
rbitfld.long 0x00 7. "MST_HOLD_TX_FIFO_EMPTY,the DW_apb_i2c master stalls the write transfer when Tx FIFO is empty and the the last byte does not have the Stop bit set" "0: Master is not holding the bus or Bus hold is..,1: Master holds the bus due to Tx FIFO is empty"
newline
rbitfld.long 0x00 6. "SLV_ACTIVITY,Slave FSM Activity Status" "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave.."
newline
rbitfld.long 0x00 5. "MST_ACTIVITY,Master FSM Activity Status" "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
newline
rbitfld.long 0x00 4. "RFF,Receive FIFO Completely Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.long 0x00 3. "RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
rbitfld.long 0x00 2. "TFE,Transmit FIFO Completely Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
rbitfld.long 0x00 1. "TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
newline
rbitfld.long 0x00 0. "I2C_ACTIVITY,I2C Activity Status" "0,1"
group.long 0x04++0x03
line.long 0x00 "I2C_TAR_REG,I2C Target Address Register"
bitfld.long 0x00 11. "SPECIAL,On read This bit indicates whether software performs a General Call or START BYTE command" "0: Disables programming of GENERAL_CALL or,1: Enables programming of GENERAL_CALL or"
newline
bitfld.long 0x00 10. "GC_OR_START,On read If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a General Call or START byte command is to be performed by the controller" "0: GENERAL_CALL byte transmission Writes to this,1: START byte transmission"
newline
hexmask.long.word 0x00 0.--9. 1. "IC_TAR,This is the target address for any master transaction"
group.long 0x74++0x03
line.long 0x00 "I2C_TXFLR_REG,I2C Transmit FIFO Level Register"
rbitfld.long 0x00 0.--5. "TXFLR,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "I2C_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register"
rbitfld.long 0x00 16. "ABRT_USER_ABRT,Master-Transmitter : This is a master-mode-only bit" "0,1"
newline
rbitfld.long 0x00 15. "ABRT_SLVRD_INTX,Slave-Transmitter : When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register" "0: Slave trying to transmit to remote master in,1: Slave trying to transmit to remote master in"
newline
rbitfld.long 0x00 14. "ABRT_SLV_ARBLOST,Slave-Transmitter : Slave lost the bus while transmitting data to a remote master" "0: Slave lost arbitration to remote master,1: Slave lost arbitration to remote master"
newline
rbitfld.long 0x00 13. "ABRT_SLVFLUSH_TXFIFO,Slave-Transmitter : Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO" "0: Slave flushes existing data in TX-FIFO upon,1: Slave flushes existing data in TX-FIFO upon"
newline
rbitfld.long 0x00 12. "ARB_LOST,Master-Transmitter or Slave-Transmitter : Master has lost arbitration or if I2C_TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitration" "0: Master or Slave-Transmitter lost arbitration,1: Master or Slave-Transmitter lost arbitration"
newline
rbitfld.long 0x00 11. "ABRT_MASTER_DIS,Master-Transmitter or Master-Receiver : User tries to initiate a Master operation with the Master mode disabled" "0: User initiating master operation when MASTER,1: User intitating master operation when MASTER"
newline
rbitfld.long 0x00 10. "ABRT_10B_RD_NORSTRT,Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode" "0: Master not trying to read in 10Bit addressing,1: Master trying to read in 10Bit addressing mode"
newline
rbitfld.long 0x00 9. "ABRT_SBYTE_NORSTRT,Master : To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1) the SPECIAL bit must be cleared (I2C_TAR[11]) or the GC_OR_START bit must be cleared (I2C_TAR[10])" "0: User trying to send START byte when RESTART,1: User trying to send START byte when RESTART"
newline
rbitfld.long 0x00 8. "ABRT_HS_NORSTRT,Master-Transmitter or Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode" "0: User trying to switch Master to HS mode when,1: User trying to switch Master to HS mode when"
newline
rbitfld.long 0x00 7. "ABRT_SBYTE_ACKDET,Master : Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)" "0: ACK detected for START byte- scenario not..,1: ACK detected for START byte"
newline
rbitfld.long 0x00 6. "ABRT_HS_ACKDET,Master : Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior)" "0: HS Master code ACKed in HS Mode- scenario not,1: HS Master code ACKed in HS Mode"
newline
rbitfld.long 0x00 5. "ABRT_GCALL_READ,Master-Transmitter : The controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)" "0: GCALL is followed by read from bus-scenario not,1: GCALL is followed by read from bus"
newline
rbitfld.long 0x00 4. "ABRT_GCALL_NOACK,Master-Transmitter : the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call" "0: GCALL not ACKed by any slave-scenario not..,1: GCALL not ACKed by any slave"
newline
rbitfld.long 0x00 3. "ABRT_TXDATA_NOACK,Master-Transmitter : This is a master-mode only bit" "0: Transmitted data non-ACKed by addressed,1: Transmitted data not ACKed by addressed slave"
newline
rbitfld.long 0x00 2. "ABRT_10ADDR2_NOACK,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave" "0: This abort is not generated,1: Byte 2 of 10Bit Address not ACKed by any slave"
newline
rbitfld.long 0x00 1. "ABRT_10ADDR1_NOACK,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave" "0: This abort is not generated,1: Byte 1 of 10Bit Address not ACKed by any slave"
newline
rbitfld.long 0x00 0. "ABRT_7B_ADDR_NOACK,Master-Transmitter or Master-Receiver : Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave" "0: This abort is not generated,1: This abort is generated because of NOACK for"
group.long 0x3C++0x03
line.long 0x00 "I2C_TX_TL_REG,I2C Transmit FIFO Threshold Register"
bitfld.long 0x00 0.--4. "TX_TL,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "I2C2"
base ad:0x50020700
group.long 0x98++0x03
line.long 0x00 "I2C2_ACK_GENERAL_CALL_REG,I2C ACK General Call Register"
bitfld.long 0x00 0. "ACK_GEN_CALL,ACK General Call" "0: Generate NACK for General Call,1: Generate ACK for a General Call"
group.long 0x5C++0x03
line.long 0x00 "I2C2_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register"
rbitfld.long 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.long 0x68++0x03
line.long 0x00 "I2C2_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register"
rbitfld.long 0x00 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register" "0,1"
group.long 0x40++0x03
line.long 0x00 "I2C2_CLR_INTR_REG,Clear Combined and Individual Interrupt Register"
rbitfld.long 0x00 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the I2C_TX_ABRT_SOURCE register" "0,1"
group.long 0x50++0x03
line.long 0x00 "I2C2_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register"
rbitfld.long 0x00 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x58++0x03
line.long 0x00 "I2C2_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x48++0x03
line.long 0x00 "I2C2_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x44++0x03
line.long 0x00 "I2C2_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x64++0x03
line.long 0x00 "I2C2_CLR_START_DET_REG,Clear START_DET Interrupt Register"
rbitfld.long 0x00 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register" "0,1"
group.long 0x60++0x03
line.long 0x00 "I2C2_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register"
rbitfld.long 0x00 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register" "0,1"
group.long 0x54++0x03
line.long 0x00 "I2C2_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register"
rbitfld.long 0x00 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the I2C_TX_ABRT_SOURCE register" "0,1"
group.long 0x4C++0x03
line.long 0x00 "I2C2_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register"
rbitfld.long 0x00 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x00++0x03
line.long 0x00 "I2C2_CON_REG,I2C Control Register"
rbitfld.long 0x00 10. "I2C_STOP_DET_IF_MASTER_ACTIVE,In Master mode" "0: issues the STOP_DET irrespective of whether,1: issues the STOP_DET interrupt only when master"
newline
bitfld.long 0x00 9. "I2C_RX_FIFO_FULL_HLD_CTRL,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH" "0: Overflow when RX_FIFO is full,1: Hold bus when RX_FIFO is full"
newline
bitfld.long 0x00 8. "I2C_TX_EMPTY_CTRL,This bit controls the generation of the TX_EMPTY interrupt as described in the IC_RAW_INTR_STAT register" "0: Default behaviour of TX_EMPTY interrupt,1: Controlled generation of TX_EMPTY interrupt"
newline
bitfld.long 0x00 7. "I2C_STOP_DET_IFADDRESSED," "0,1"
newline
bitfld.long 0x00 6. "I2C_SLAVE_DISABLE,Slave enabled or disabled after reset is applied which means software does not have to configure the slave" "0: slave is enabled,1: slave is disabled Software should ensure that"
newline
bitfld.long 0x00 5. "I2C_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master" "0: disable,1: enable"
newline
bitfld.long 0x00 4. "I2C_10BITADDR_MASTER,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x00 3. "I2C_10BITADDR_SLAVE,When acting as a slave this bit controls whether the controller responds to 7- or 10-bit addresses" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x00 1.--2. "I2C_SPEED,These bits control at which speed the controller operates" "?,1: standard mode (100 kbit/s),2: fast mode (400 kbit/s),3: high speed mode"
newline
bitfld.long 0x00 0. "I2C_MASTER_MODE,This bit controls whether the controller master is enabled" "0: master disabled,1: master enabled Software should ensure that"
group.long 0x10++0x03
line.long 0x00 "I2C2_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register"
bitfld.long 0x00 10. "I2C_RESTART,This bit controls whether a RESTART is issued before the byte is sent or received" "0: If IC_RESTART_EN is 1 a RESTART is issued only,1: If IC_RESTART_EN is 1 a RESTART is issued.."
newline
bitfld.long 0x00 9. "I2C_STOP,This bit controls whether a STOP is issued after the byte is sent or received" "0: STOP is not issued after this byte regardless..,1: STOP is issued after this byte regardless of"
newline
bitfld.long 0x00 8. "I2C_CMD,This bit controls whether a read or a write is performed" "0: Write When,1: "
newline
hexmask.long.byte 0x00 0.--7. 1. "I2C_DAT,This register contains the data to be transmitted or received on the I2C bus"
group.long 0x88++0x03
line.long 0x00 "I2C2_DMA_CR_REG,DMA Control Register"
bitfld.long 0x00 1. "TDMAE,Transmit DMA Enable" "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x00 0. "RDMAE,Receive DMA Enable" "0: Receive DMA disabled,1: Receive DMA enabled"
group.long 0x90++0x03
line.long 0x00 "I2C2_DMA_RDLR_REG,I2C Receive Data Level Register"
bitfld.long 0x00 0.--4. "DMARDL,Receive Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8C++0x03
line.long 0x00 "I2C2_DMA_TDLR_REG,DMA Transmit Data Level Register"
bitfld.long 0x00 0.--4. "DMATDL,Transmit Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C++0x03
line.long 0x00 "I2C2_ENABLE_REG,I2C Enable Register"
bitfld.long 0x00 2. "I2C_TX_CMD_BLOCK,In Master mode" "0,1"
newline
bitfld.long 0x00 1. "I2C_ABORT,The software can abort the I2C transfer in master mode by setting this bit" "0,1"
newline
bitfld.long 0x00 0. "I2C_EN,Controls whether the controller is enabled" "0: Disables the controller (TX and RX FIFOs are,1: Enables the controller Software can disable the"
group.long 0x9C++0x03
line.long 0x00 "I2C2_ENABLE_STATUS_REG,I2C Enable Status Register"
rbitfld.long 0x00 2. "SLV_RX_DATA_LOST,Slave Received Data Lost" "0: Slave RX Data is not lost,1: Slave RX Data is lost"
newline
rbitfld.long 0x00 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive)" "0: Slave is disabled when it is idle,1: Slave is disabled when it is active"
newline
rbitfld.long 0x00 0. "IC_EN,ic_en Status" "0: I2C disabled,1: I2C enabled"
group.long 0x1C++0x03
line.long 0x00 "I2C2_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x20++0x03
line.long 0x00 "I2C2_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x0C++0x03
line.long 0x00 "I2C2_HS_MADDR_REG,I2C High Speed Master Mode Code Address Register"
bitfld.long 0x00 0.--2. "I2C_IC_HS_MAR,This bit field holds the value of the I2C HS mode master code" "0,1,2,3,4,5,6,7"
group.long 0x24++0x03
line.long 0x00 "I2C2_HS_SCL_HCNT_REG,High Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_HS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x28++0x03
line.long 0x00 "I2C2_HS_SCL_LCNT_REG,High Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_HS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0xA0++0x03
line.long 0x00 "I2C2_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size"
hexmask.long.byte 0x00 0.--7. 1. "I2C_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.long 0xA4++0x03
line.long 0x00 "I2C2_IC_HS_SPKLEN_REG,I2C HS spike suppression limit Size"
hexmask.long.byte 0x00 0.--7. 1. "I2C_HS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.long 0x30++0x03
line.long 0x00 "I2C2_INTR_MASK_REG,I2C Interrupt Mask Register"
rbitfld.long 0x00 14. "M_SCL_STUCK_AT_LOW,M_SCL_STUCK_AT_LOW Register field Reserved bits" "0,1"
newline
bitfld.long 0x00 13. "M_MASTER_ON_HOLD,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 12. "M_RESTART_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 11. "M_GEN_CALL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 10. "M_START_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 9. "M_STOP_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 8. "M_ACTIVITY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 7. "M_RX_DONE,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 6. "M_TX_ABRT,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 5. "M_RD_REQ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 4. "M_TX_EMPTY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 3. "M_TX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 2. "M_RX_FULL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 1. "M_RX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 0. "M_RX_UNDER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
group.long 0x2C++0x03
line.long 0x00 "I2C2_INTR_STAT_REG,I2C Interrupt Status Register"
rbitfld.long 0x00 14. "R_SCL_STUCK_AT_LOW," "0,1"
newline
rbitfld.long 0x00 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty" "0,1"
newline
rbitfld.long 0x00 12. "R_RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed" "0,1"
newline
rbitfld.long 0x00 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
newline
rbitfld.long 0x00 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 9. "R_STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 8. "R_ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
newline
rbitfld.long 0x00 7. "R_RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.long 0x00 6. "R_TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
newline
rbitfld.long 0x00 5. "R_RD_REQ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
newline
rbitfld.long 0x00 4. "R_TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
newline
rbitfld.long 0x00 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
newline
rbitfld.long 0x00 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
newline
rbitfld.long 0x00 1. "R_RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
newline
rbitfld.long 0x00 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.long 0x34++0x03
line.long 0x00 "I2C2_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register"
rbitfld.long 0x00 14. "SCL_STUCK_AT_LOW,CL_STUCK_AT_LOW Register field Reserved bits" "0,1"
newline
rbitfld.long 0x00 13. "MASTER_ON_HOLD,ndicates whether master is holding the bus and TX FIFO is empty" "0,1"
newline
rbitfld.long 0x00 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed" "0,1"
newline
rbitfld.long 0x00 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
newline
rbitfld.long 0x00 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 8. "ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
newline
rbitfld.long 0x00 7. "RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.long 0x00 6. "TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
newline
rbitfld.long 0x00 5. "RD_REQ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
newline
rbitfld.long 0x00 4. "TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
newline
rbitfld.long 0x00 3. "TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
newline
rbitfld.long 0x00 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
newline
rbitfld.long 0x00 1. "RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
newline
rbitfld.long 0x00 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.long 0x78++0x03
line.long 0x00 "I2C2_RXFLR_REG,I2C Receive FIFO Level Register"
rbitfld.long 0x00 0.--5. "RXFLR,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "I2C2_RX_TL_REG,I2C Receive FIFO Threshold Register"
bitfld.long 0x00 0.--4. "RX_TL,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "I2C2_SAR_REG,I2C Slave Address Register"
hexmask.long.word 0x00 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave"
group.long 0x7C++0x03
line.long 0x00 "I2C2_SDA_HOLD_REG,I2C SDA Hold Time Length Register"
hexmask.long.byte 0x00 16.--23. 1. "I2C_SDA_RX_HOLD,Sets the required SDA hold time in units of ic_clk period when receiver"
newline
hexmask.long.word 0x00 0.--15. 1. "I2C_SDA_TX_HOLD,Sets the required SDA hold time in units of ic_clk period when transmitter"
group.long 0x94++0x03
line.long 0x00 "I2C2_SDA_SETUP_REG,I2C SDA Setup Register"
hexmask.long.byte 0x00 0.--7. 1. "SDA_SETUP,SDA Setup"
group.long 0x14++0x03
line.long 0x00 "I2C2_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x18++0x03
line.long 0x00 "I2C2_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x70++0x03
line.long 0x00 "I2C2_STATUS_REG,I2C Status Register"
rbitfld.long 0x00 10. "LV_HOLD_RX_FIFO_FULL,This bit indicates the BUS Hold in Slave mode due to Rx FIFO is Full and an additional byte has been received" "0: Slave is not holding the bus or Bus hold is not,1: Slave holds the bus due to Rx FIFO is full"
newline
rbitfld.long 0x00 9. "SLV_HOLD_TX_FIFO_EMPTY,This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty" "0: Slave is not holding the bus or Bus hold is not,1: Slave holds the bus due to Tx FIFO is empty"
newline
rbitfld.long 0x00 8. "MST_HOLD_RX_FIFO_FULL,This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received" "0: Master is not holding the bus or Bus hold is..,1: Master holds the bus due to Rx FIFO is full"
newline
rbitfld.long 0x00 7. "MST_HOLD_TX_FIFO_EMPTY,the DW_apb_i2c master stalls the write transfer when Tx FIFO is empty and the the last byte does not have the Stop bit set" "0: Master is not holding the bus or Bus hold is..,1: Master holds the bus due to Tx FIFO is empty"
newline
rbitfld.long 0x00 6. "SLV_ACTIVITY,Slave FSM Activity Status" "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave.."
newline
rbitfld.long 0x00 5. "MST_ACTIVITY,Master FSM Activity Status" "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
newline
rbitfld.long 0x00 4. "RFF,Receive FIFO Completely Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.long 0x00 3. "RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
rbitfld.long 0x00 2. "TFE,Transmit FIFO Completely Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
rbitfld.long 0x00 1. "TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
newline
rbitfld.long 0x00 0. "I2C_ACTIVITY,I2C Activity Status" "0,1"
group.long 0x04++0x03
line.long 0x00 "I2C2_TAR_REG,I2C Target Address Register"
bitfld.long 0x00 11. "SPECIAL,On read This bit indicates whether software performs a General Call or START BYTE command" "0: Disables programming of GENERAL_CALL or,1: Enables programming of GENERAL_CALL or"
newline
bitfld.long 0x00 10. "GC_OR_START,On read If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a General Call or START byte command is to be performed by the controller" "0: GENERAL_CALL byte transmission Writes to this,1: START byte transmission"
newline
hexmask.long.word 0x00 0.--9. 1. "IC_TAR,This is the target address for any master transaction"
group.long 0x74++0x03
line.long 0x00 "I2C2_TXFLR_REG,I2C Transmit FIFO Level Register"
rbitfld.long 0x00 0.--5. "TXFLR,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "I2C2_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register"
rbitfld.long 0x00 16. "ABRT_USER_ABRT,Master-Transmitter : This is a master-mode-only bit" "0,1"
newline
rbitfld.long 0x00 15. "ABRT_SLVRD_INTX,Slave-Transmitter : When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register" "0: Slave trying to transmit to remote master in,1: Slave trying to transmit to remote master in"
newline
rbitfld.long 0x00 14. "ABRT_SLV_ARBLOST,Slave-Transmitter : Slave lost the bus while transmitting data to a remote master" "0: Slave lost arbitration to remote master,1: Slave lost arbitration to remote master"
newline
rbitfld.long 0x00 13. "ABRT_SLVFLUSH_TXFIFO,Slave-Transmitter : Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO" "0: Slave flushes existing data in TX-FIFO upon,1: Slave flushes existing data in TX-FIFO upon"
newline
rbitfld.long 0x00 12. "ARB_LOST,Master-Transmitter or Slave-Transmitter : Master has lost arbitration or if I2C_TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitration" "0: Master or Slave-Transmitter lost arbitration,1: Master or Slave-Transmitter lost arbitration"
newline
rbitfld.long 0x00 11. "ABRT_MASTER_DIS,Master-Transmitter or Master-Receiver : User tries to initiate a Master operation with the Master mode disabled" "0: User initiating master operation when MASTER,1: User intitating master operation when MASTER"
newline
rbitfld.long 0x00 10. "ABRT_10B_RD_NORSTRT,Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode" "0: Master not trying to read in 10Bit addressing,1: Master trying to read in 10Bit addressing mode"
newline
rbitfld.long 0x00 9. "ABRT_SBYTE_NORSTRT,Master : To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1) the SPECIAL bit must be cleared (I2C_TAR[11]) or the GC_OR_START bit must be cleared (I2C_TAR[10])" "0: User trying to send START byte when RESTART,1: User trying to send START byte when RESTART"
newline
rbitfld.long 0x00 8. "ABRT_HS_NORSTRT,Master-Transmitter or Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode" "0: User trying to switch Master to HS mode when,1: User trying to switch Master to HS mode when"
newline
rbitfld.long 0x00 7. "ABRT_SBYTE_ACKDET,Master : Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)" "0: ACK detected for START byte- scenario not..,1: ACK detected for START byte"
newline
rbitfld.long 0x00 6. "ABRT_HS_ACKDET,Master : Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior)" "0: HS Master code ACKed in HS Mode- scenario not,1: HS Master code ACKed in HS Mode"
newline
rbitfld.long 0x00 5. "ABRT_GCALL_READ,Master-Transmitter : The controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)" "0: GCALL is followed by read from bus-scenario not,1: GCALL is followed by read from bus"
newline
rbitfld.long 0x00 4. "ABRT_GCALL_NOACK,Master-Transmitter : the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call" "0: GCALL not ACKed by any slave-scenario not..,1: GCALL not ACKed by any slave"
newline
rbitfld.long 0x00 3. "ABRT_TXDATA_NOACK,Master-Transmitter : This is a master-mode only bit" "0: Transmitted data non-ACKed by addressed,1: Transmitted data not ACKed by addressed slave"
newline
rbitfld.long 0x00 2. "ABRT_10ADDR2_NOACK,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave" "0: This abort is not generated,1: Byte 2 of 10Bit Address not ACKed by any slave"
newline
rbitfld.long 0x00 1. "ABRT_10ADDR1_NOACK,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave" "0: This abort is not generated,1: Byte 1 of 10Bit Address not ACKed by any slave"
newline
rbitfld.long 0x00 0. "ABRT_7B_ADDR_NOACK,Master-Transmitter or Master-Receiver : Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave" "0: This abort is not generated,1: This abort is generated because of NOACK for"
group.long 0x3C++0x03
line.long 0x00 "I2C2_TX_TL_REG,I2C Transmit FIFO Threshold Register"
bitfld.long 0x00 0.--4. "TX_TL,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "I2C3"
base ad:0x50020500
group.long 0x98++0x03
line.long 0x00 "I2C3_ACK_GENERAL_CALL_REG,I2C ACK General Call Register"
bitfld.long 0x00 0. "ACK_GEN_CALL,ACK General Call" "0: Generate NACK for General Call,1: Generate ACK for a General Call"
group.long 0x5C++0x03
line.long 0x00 "I2C3_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register"
rbitfld.long 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.long 0x68++0x03
line.long 0x00 "I2C3_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register"
rbitfld.long 0x00 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register" "0,1"
group.long 0x40++0x03
line.long 0x00 "I2C3_CLR_INTR_REG,Clear Combined and Individual Interrupt Register"
rbitfld.long 0x00 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the I2C_TX_ABRT_SOURCE register" "0,1"
group.long 0x50++0x03
line.long 0x00 "I2C3_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register"
rbitfld.long 0x00 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x58++0x03
line.long 0x00 "I2C3_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x48++0x03
line.long 0x00 "I2C3_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x44++0x03
line.long 0x00 "I2C3_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register"
rbitfld.long 0x00 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x64++0x03
line.long 0x00 "I2C3_CLR_START_DET_REG,Clear START_DET Interrupt Register"
rbitfld.long 0x00 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register" "0,1"
group.long 0x60++0x03
line.long 0x00 "I2C3_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register"
rbitfld.long 0x00 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register" "0,1"
group.long 0x54++0x03
line.long 0x00 "I2C3_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register"
rbitfld.long 0x00 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the I2C_TX_ABRT_SOURCE register" "0,1"
group.long 0x4C++0x03
line.long 0x00 "I2C3_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register"
rbitfld.long 0x00 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register" "0,1"
group.long 0x00++0x03
line.long 0x00 "I2C3_CON_REG,I2C Control Register"
rbitfld.long 0x00 10. "I2C_STOP_DET_IF_MASTER_ACTIVE,In Master mode" "0: issues the STOP_DET irrespective of whether,1: issues the STOP_DET interrupt only when master"
newline
bitfld.long 0x00 9. "I2C_RX_FIFO_FULL_HLD_CTRL,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH" "0: Overflow when RX_FIFO is full,1: Hold bus when RX_FIFO is full"
newline
bitfld.long 0x00 8. "I2C_TX_EMPTY_CTRL,This bit controls the generation of the TX_EMPTY interrupt as described in the IC_RAW_INTR_STAT register" "0: Default behaviour of TX_EMPTY interrupt,1: Controlled generation of TX_EMPTY interrupt"
newline
bitfld.long 0x00 7. "I2C_STOP_DET_IFADDRESSED," "0,1"
newline
bitfld.long 0x00 6. "I2C_SLAVE_DISABLE,Slave enabled or disabled after reset is applied which means software does not have to configure the slave" "0: slave is enabled,1: slave is disabled Software should ensure that"
newline
bitfld.long 0x00 5. "I2C_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master" "0: disable,1: enable"
newline
bitfld.long 0x00 4. "I2C_10BITADDR_MASTER,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x00 3. "I2C_10BITADDR_SLAVE,When acting as a slave this bit controls whether the controller responds to 7- or 10-bit addresses" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x00 1.--2. "I2C_SPEED,These bits control at which speed the controller operates" "?,1: standard mode (100 kbit/s),2: fast mode (400 kbit/s),3: high speed mode"
newline
bitfld.long 0x00 0. "I2C_MASTER_MODE,This bit controls whether the controller master is enabled" "0: master disabled,1: master enabled Software should ensure that"
group.long 0x10++0x03
line.long 0x00 "I2C3_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register"
bitfld.long 0x00 10. "I2C_RESTART,This bit controls whether a RESTART is issued before the byte is sent or received" "0: If IC_RESTART_EN is 1 a RESTART is issued only,1: If IC_RESTART_EN is 1 a RESTART is issued.."
newline
bitfld.long 0x00 9. "I2C_STOP,This bit controls whether a STOP is issued after the byte is sent or received" "0: STOP is not issued after this byte regardless..,1: STOP is issued after this byte regardless of"
newline
bitfld.long 0x00 8. "I2C_CMD,This bit controls whether a read or a write is performed" "0: Write When,1: "
newline
hexmask.long.byte 0x00 0.--7. 1. "I2C_DAT,This register contains the data to be transmitted or received on the I2C bus"
group.long 0x88++0x03
line.long 0x00 "I2C3_DMA_CR_REG,DMA Control Register"
bitfld.long 0x00 1. "TDMAE,Transmit DMA Enable" "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x00 0. "RDMAE,Receive DMA Enable" "0: Receive DMA disabled,1: Receive DMA enabled"
group.long 0x90++0x03
line.long 0x00 "I2C3_DMA_RDLR_REG,I2C Receive Data Level Register"
bitfld.long 0x00 0.--4. "DMARDL,Receive Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8C++0x03
line.long 0x00 "I2C3_DMA_TDLR_REG,DMA Transmit Data Level Register"
bitfld.long 0x00 0.--4. "DMATDL,Transmit Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C++0x03
line.long 0x00 "I2C3_ENABLE_REG,I2C Enable Register"
bitfld.long 0x00 2. "I2C_TX_CMD_BLOCK,In Master mode" "0,1"
newline
bitfld.long 0x00 1. "I2C_ABORT,The software can abort the I2C transfer in master mode by setting this bit" "0,1"
newline
bitfld.long 0x00 0. "I2C_EN,Controls whether the controller is enabled" "0: Disables the controller (TX and RX FIFOs are,1: Enables the controller Software can disable the"
group.long 0x9C++0x03
line.long 0x00 "I2C3_ENABLE_STATUS_REG,I2C Enable Status Register"
rbitfld.long 0x00 2. "SLV_RX_DATA_LOST,Slave Received Data Lost" "0: Slave RX Data is not lost,1: Slave RX Data is lost"
newline
rbitfld.long 0x00 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive)" "0: Slave is disabled when it is idle,1: Slave is disabled when it is active"
newline
rbitfld.long 0x00 0. "IC_EN,ic_en Status" "0: I2C disabled,1: I2C enabled"
group.long 0x1C++0x03
line.long 0x00 "I2C3_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x20++0x03
line.long 0x00 "I2C3_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x0C++0x03
line.long 0x00 "I2C3_HS_MADDR_REG,I2C High Speed Master Mode Code Address Register"
bitfld.long 0x00 0.--2. "I2C_IC_HS_MAR,This bit field holds the value of the I2C HS mode master code" "0,1,2,3,4,5,6,7"
group.long 0x24++0x03
line.long 0x00 "I2C3_HS_SCL_HCNT_REG,High Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_HS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x28++0x03
line.long 0x00 "I2C3_HS_SCL_LCNT_REG,High Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_HS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0xA0++0x03
line.long 0x00 "I2C3_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size"
hexmask.long.byte 0x00 0.--7. 1. "I2C_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.long 0xA4++0x03
line.long 0x00 "I2C3_IC_HS_SPKLEN_REG,I2C HS spike suppression limit Size"
hexmask.long.byte 0x00 0.--7. 1. "I2C_HS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.long 0x30++0x03
line.long 0x00 "I2C3_INTR_MASK_REG,I2C Interrupt Mask Register"
rbitfld.long 0x00 14. "M_SCL_STUCK_AT_LOW,M_SCL_STUCK_AT_LOW Register field Reserved bits" "0,1"
newline
bitfld.long 0x00 13. "M_MASTER_ON_HOLD,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 12. "M_RESTART_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 11. "M_GEN_CALL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 10. "M_START_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 9. "M_STOP_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 8. "M_ACTIVITY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 7. "M_RX_DONE,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 6. "M_TX_ABRT,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 5. "M_RD_REQ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 4. "M_TX_EMPTY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 3. "M_TX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 2. "M_RX_FULL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 1. "M_RX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.long 0x00 0. "M_RX_UNDER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
group.long 0x2C++0x03
line.long 0x00 "I2C3_INTR_STAT_REG,I2C Interrupt Status Register"
rbitfld.long 0x00 14. "R_SCL_STUCK_AT_LOW," "0,1"
newline
rbitfld.long 0x00 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty" "0,1"
newline
rbitfld.long 0x00 12. "R_RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed" "0,1"
newline
rbitfld.long 0x00 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
newline
rbitfld.long 0x00 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 9. "R_STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 8. "R_ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
newline
rbitfld.long 0x00 7. "R_RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.long 0x00 6. "R_TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
newline
rbitfld.long 0x00 5. "R_RD_REQ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
newline
rbitfld.long 0x00 4. "R_TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
newline
rbitfld.long 0x00 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
newline
rbitfld.long 0x00 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
newline
rbitfld.long 0x00 1. "R_RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
newline
rbitfld.long 0x00 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.long 0x34++0x03
line.long 0x00 "I2C3_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register"
rbitfld.long 0x00 14. "SCL_STUCK_AT_LOW,CL_STUCK_AT_LOW Register field Reserved bits" "0,1"
newline
rbitfld.long 0x00 13. "MASTER_ON_HOLD,ndicates whether master is holding the bus and TX FIFO is empty" "0,1"
newline
rbitfld.long 0x00 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed" "0,1"
newline
rbitfld.long 0x00 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
newline
rbitfld.long 0x00 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.long 0x00 8. "ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
newline
rbitfld.long 0x00 7. "RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.long 0x00 6. "TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
newline
rbitfld.long 0x00 5. "RD_REQ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
newline
rbitfld.long 0x00 4. "TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
newline
rbitfld.long 0x00 3. "TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
newline
rbitfld.long 0x00 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
newline
rbitfld.long 0x00 1. "RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
newline
rbitfld.long 0x00 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.long 0x78++0x03
line.long 0x00 "I2C3_RXFLR_REG,I2C Receive FIFO Level Register"
rbitfld.long 0x00 0.--5. "RXFLR,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "I2C3_RX_TL_REG,I2C Receive FIFO Threshold Register"
bitfld.long 0x00 0.--4. "RX_TL,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "I2C3_SAR_REG,I2C Slave Address Register"
hexmask.long.word 0x00 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave"
group.long 0x7C++0x03
line.long 0x00 "I2C3_SDA_HOLD_REG,I2C SDA Hold Time Length Register"
hexmask.long.byte 0x00 16.--23. 1. "I2C_SDA_RX_HOLD,Sets the required SDA hold time in units of ic_clk period when receiver"
newline
hexmask.long.word 0x00 0.--15. 1. "I2C_SDA_TX_HOLD,Sets the required SDA hold time in units of ic_clk period when transmitter"
group.long 0x94++0x03
line.long 0x00 "I2C3_SDA_SETUP_REG,I2C SDA Setup Register"
hexmask.long.byte 0x00 0.--7. 1. "SDA_SETUP,SDA Setup"
group.long 0x14++0x03
line.long 0x00 "I2C3_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x18++0x03
line.long 0x00 "I2C3_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.long 0x70++0x03
line.long 0x00 "I2C3_STATUS_REG,I2C Status Register"
rbitfld.long 0x00 10. "LV_HOLD_RX_FIFO_FULL,This bit indicates the BUS Hold in Slave mode due to Rx FIFO is Full and an additional byte has been received" "0: Slave is not holding the bus or Bus hold is not,1: Slave holds the bus due to Rx FIFO is full"
newline
rbitfld.long 0x00 9. "SLV_HOLD_TX_FIFO_EMPTY,This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty" "0: Slave is not holding the bus or Bus hold is not,1: Slave holds the bus due to Tx FIFO is empty"
newline
rbitfld.long 0x00 8. "MST_HOLD_RX_FIFO_FULL,This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received" "0: Master is not holding the bus or Bus hold is..,1: Master holds the bus due to Rx FIFO is full"
newline
rbitfld.long 0x00 7. "MST_HOLD_TX_FIFO_EMPTY,the DW_apb_i2c master stalls the write transfer when Tx FIFO is empty and the the last byte does not have the Stop bit set" "0: Master is not holding the bus or Bus hold is..,1: Master holds the bus due to Tx FIFO is empty"
newline
rbitfld.long 0x00 6. "SLV_ACTIVITY,Slave FSM Activity Status" "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave.."
newline
rbitfld.long 0x00 5. "MST_ACTIVITY,Master FSM Activity Status" "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
newline
rbitfld.long 0x00 4. "RFF,Receive FIFO Completely Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.long 0x00 3. "RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
rbitfld.long 0x00 2. "TFE,Transmit FIFO Completely Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
rbitfld.long 0x00 1. "TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
newline
rbitfld.long 0x00 0. "I2C_ACTIVITY,I2C Activity Status" "0,1"
group.long 0x04++0x03
line.long 0x00 "I2C3_TAR_REG,I2C Target Address Register"
bitfld.long 0x00 11. "SPECIAL,On read This bit indicates whether software performs a General Call or START BYTE command" "0: Disables programming of GENERAL_CALL or,1: Enables programming of GENERAL_CALL or"
newline
bitfld.long 0x00 10. "GC_OR_START,On read If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a General Call or START byte command is to be performed by the controller" "0: GENERAL_CALL byte transmission Writes to this,1: START byte transmission"
newline
hexmask.long.word 0x00 0.--9. 1. "IC_TAR,This is the target address for any master transaction"
group.long 0x74++0x03
line.long 0x00 "I2C3_TXFLR_REG,I2C Transmit FIFO Level Register"
rbitfld.long 0x00 0.--5. "TXFLR,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "I2C3_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register"
rbitfld.long 0x00 16. "ABRT_USER_ABRT,Master-Transmitter : This is a master-mode-only bit" "0,1"
newline
rbitfld.long 0x00 15. "ABRT_SLVRD_INTX,Slave-Transmitter : When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register" "0: Slave trying to transmit to remote master in,1: Slave trying to transmit to remote master in"
newline
rbitfld.long 0x00 14. "ABRT_SLV_ARBLOST,Slave-Transmitter : Slave lost the bus while transmitting data to a remote master" "0: Slave lost arbitration to remote master,1: Slave lost arbitration to remote master"
newline
rbitfld.long 0x00 13. "ABRT_SLVFLUSH_TXFIFO,Slave-Transmitter : Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO" "0: Slave flushes existing data in TX-FIFO upon,1: Slave flushes existing data in TX-FIFO upon"
newline
rbitfld.long 0x00 12. "ARB_LOST,Master-Transmitter or Slave-Transmitter : Master has lost arbitration or if I2C_TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitration" "0: Master or Slave-Transmitter lost arbitration,1: Master or Slave-Transmitter lost arbitration"
newline
rbitfld.long 0x00 11. "ABRT_MASTER_DIS,Master-Transmitter or Master-Receiver : User tries to initiate a Master operation with the Master mode disabled" "0: User initiating master operation when MASTER,1: User intitating master operation when MASTER"
newline
rbitfld.long 0x00 10. "ABRT_10B_RD_NORSTRT,Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode" "0: Master not trying to read in 10Bit addressing,1: Master trying to read in 10Bit addressing mode"
newline
rbitfld.long 0x00 9. "ABRT_SBYTE_NORSTRT,Master : To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1) the SPECIAL bit must be cleared (I2C_TAR[11]) or the GC_OR_START bit must be cleared (I2C_TAR[10])" "0: User trying to send START byte when RESTART,1: User trying to send START byte when RESTART"
newline
rbitfld.long 0x00 8. "ABRT_HS_NORSTRT,Master-Transmitter or Master-Receiver : The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode" "0: User trying to switch Master to HS mode when,1: User trying to switch Master to HS mode when"
newline
rbitfld.long 0x00 7. "ABRT_SBYTE_ACKDET,Master : Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)" "0: ACK detected for START byte- scenario not..,1: ACK detected for START byte"
newline
rbitfld.long 0x00 6. "ABRT_HS_ACKDET,Master : Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior)" "0: HS Master code ACKed in HS Mode- scenario not,1: HS Master code ACKed in HS Mode"
newline
rbitfld.long 0x00 5. "ABRT_GCALL_READ,Master-Transmitter : The controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)" "0: GCALL is followed by read from bus-scenario not,1: GCALL is followed by read from bus"
newline
rbitfld.long 0x00 4. "ABRT_GCALL_NOACK,Master-Transmitter : the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call" "0: GCALL not ACKed by any slave-scenario not..,1: GCALL not ACKed by any slave"
newline
rbitfld.long 0x00 3. "ABRT_TXDATA_NOACK,Master-Transmitter : This is a master-mode only bit" "0: Transmitted data non-ACKed by addressed,1: Transmitted data not ACKed by addressed slave"
newline
rbitfld.long 0x00 2. "ABRT_10ADDR2_NOACK,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave" "0: This abort is not generated,1: Byte 2 of 10Bit Address not ACKed by any slave"
newline
rbitfld.long 0x00 1. "ABRT_10ADDR1_NOACK,Master-Transmitter or Master-Receiver : Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave" "0: This abort is not generated,1: Byte 1 of 10Bit Address not ACKed by any slave"
newline
rbitfld.long 0x00 0. "ABRT_7B_ADDR_NOACK,Master-Transmitter or Master-Receiver : Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave" "0: This abort is not generated,1: This abort is generated because of NOACK for"
group.long 0x3C++0x03
line.long 0x00 "I2C3_TX_TL_REG,I2C Transmit FIFO Threshold Register"
bitfld.long 0x00 0.--4. "TX_TL,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "I3C"
base ad:0x50020C00
group.long 0xD4++0x03
line.long 0x00 "I3C_BUS_FREE_AVAIL_TIMING_REG,Bus Free Timing Register"
hexmask.long.word 0x00 0.--15. 1. "BUS_FREE_TIME,This register field is used only in Master mode of operation I3C Bus Free Count Value"
group.long 0x0C++0x03
line.long 0x00 "I3C_COMMAND_QUEUE_PORT_REG,COMMAND_QUEUE_PORT"
hexmask.long 0x00 0.--31. 1. "COMMAND,32 bit command"
group.long 0x50++0x03
line.long 0x00 "I3C_DATA_BUFFER_STAT_LEVEL_REG,Data Buffer Status Level Register"
hexmask.long.byte 0x00 16.--23. 1. "RX_BUF_BLR,Receive Buffer Level Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "TX_BUF_EMPTY_LOC,Transmit Buffer Empty Level Value"
group.long 0x20++0x03
line.long 0x00 "I3C_DATA_BUFFER_THLD_CTRL_REG,Data Buffer Threshold Control Register"
bitfld.long 0x00 24.--26. "RX_START_THLD,Receive Start Threshold Value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "TX_START_THLD,Transfer Start Threshold Value" "0: 1,1: 4,2: 8,3: 16,4: 32,5: 64,?..."
newline
bitfld.long 0x00 8.--10. "RX_BUF_THLD,Receive Buffer Threshold Value" "0: 1,1: 4,2: 8,3: 16,4: 32,5: 64,?..."
newline
bitfld.long 0x00 0.--2. "TX_EMPTY_BUF_THLD,Transmit Buffer Threshold Value" "0: 1,1: 4,2: 8,3: 16,4: 32,5: 64,?..."
group.long 0x04++0x03
line.long 0x00 "I3C_DEVICE_ADDR_REG,Device Address Register"
bitfld.long 0x00 31. "DYNAMIC_ADDR_VALID,Dynamic Address Valid This bit is used to control whether the DYNAMIC_ADDR is valid or not" "0,1"
newline
hexmask.long.byte 0x00 16.--22. 1. "DYNAMIC_ADDR,Device Dynamic Address"
group.long 0x5C++0x03
line.long 0x00 "I3C_DEVICE_ADDR_TABLE_PTR_REG,Pointer for Device Address Table Registers"
hexmask.long.word 0x00 16.--31. 1. "DEV_ADDR_TABLE_DEPTH,Depth of Device Address Table"
newline
hexmask.long.word 0x00 0.--15. 1. "P_DEV_ADDR_TABLE_START_ADDR,Start Address of Device Address Table"
group.long 0xB0++0x03
line.long 0x00 "I3C_DEVICE_CTRL_EXTENDED_REG,Device Control Extended Register"
bitfld.long 0x00 0.--1. "DEV_OPERATION_MODE,This bit is used to select the Device Operation Mode before the controller is enabled" "0: Master,1: Slave,2: Reserved,3: Reserved This"
group.long 0x00++0x03
line.long 0x00 "I3C_DEVICE_CTRL_REG,Device Control Register"
bitfld.long 0x00 31. "ENABLE,Controls whether or not DWC_mipi_i3c is enabled" "0: Disables the DWC_mipi_i3c controller,1: Enables the DWC_mipi_i3c controller"
newline
bitfld.long 0x00 30. "RESUME,DWC_mipi_i3c Resume" "0,1"
newline
bitfld.long 0x00 29. "ABORT,DWC_mipi_i3c Abort" "0,1"
newline
bitfld.long 0x00 28. "DMA_ENABLE_I3C,DMA Handshake Interface Enable" "0: The DMA handshake control has no significance,1: Enables the DMA handshake control to interact"
newline
bitfld.long 0x00 8. "HOT_JOIN_CTRL,Hot-Join Ack/Nack Control This bit is used in master mode of operation" "0: ACK the Hot-join request,1: NACK and send broadcast CCC to disable Hot-join"
newline
bitfld.long 0x00 7. "I2C_SLAVE_PRESENT,I2C Slave Present This bit is used in master mode of operation" "0,1"
newline
bitfld.long 0x00 0. "IBA_INCLUDE,I3C Broadcast Address include" "0,1"
group.long 0x280++0x03
line.long 0x00 "I3C_DEV_ADDR_TABLE_LOC1_REG,Device Address Table of Device1"
bitfld.long 0x00 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not" "0,1"
newline
bitfld.long 0x00 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address"
group.long 0x284++0x03
line.long 0x00 "I3C_DEV_ADDR_TABLE_LOC2_REG,Device Address Table of Device2"
bitfld.long 0x00 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not" "0,1"
newline
bitfld.long 0x00 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address"
group.long 0x288++0x03
line.long 0x00 "I3C_DEV_ADDR_TABLE_LOC3_REG,Device Address Table of Device3"
bitfld.long 0x00 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not" "0,1"
newline
bitfld.long 0x00 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address"
group.long 0x28C++0x03
line.long 0x00 "I3C_DEV_ADDR_TABLE_LOC4_REG,Device Address Table of Device4"
bitfld.long 0x00 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not" "0,1"
newline
bitfld.long 0x00 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address"
group.long 0x290++0x03
line.long 0x00 "I3C_DEV_ADDR_TABLE_LOC5_REG,Device Address Table of Device5"
bitfld.long 0x00 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not" "0,1"
newline
bitfld.long 0x00 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address"
group.long 0x294++0x03
line.long 0x00 "I3C_DEV_ADDR_TABLE_LOC6_REG,Device Address Table of Device6"
bitfld.long 0x00 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not" "0,1"
newline
bitfld.long 0x00 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address"
group.long 0x298++0x03
line.long 0x00 "I3C_DEV_ADDR_TABLE_LOC7_REG,Device Address Table of Device7"
bitfld.long 0x00 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not" "0,1"
newline
bitfld.long 0x00 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address"
group.long 0x29C++0x03
line.long 0x00 "I3C_DEV_ADDR_TABLE_LOC8_REG,Device Address Table of Device8"
bitfld.long 0x00 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not" "0,1"
newline
bitfld.long 0x00 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device" "0,1,2,3"
newline
hexmask.long.byte 0x00 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address"
group.long 0x200++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE1_LOC1_REG,Device Characteristic Table Location-1 of Device1"
hexmask.long 0x00 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
group.long 0x204++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE1_LOC2_REG,Device Characteristic Table Location-2 of Device1"
hexmask.long.word 0x00 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
group.long 0x208++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE1_LOC3_REG,Device Characteristic Table Location-3 of Device1"
hexmask.long.byte 0x00 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "DCR,Device Characteristic Value"
group.long 0x20C++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE1_LOC4_REG,Device Characteristic Table Location-4 of Device1"
hexmask.long.byte 0x00 0.--7. 1. "DEV_DYNAMIC_ADDR_LOC4,Device Dynamic Address assigned"
group.long 0x210++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE2_LOC1_REG,Device Characteristic Table Location-1 of Device2"
hexmask.long 0x00 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
group.long 0x214++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE2_LOC2_REG,Device Characteristic Table Location-2 of Device2"
hexmask.long.word 0x00 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
group.long 0x218++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE2_LOC3_REG,Device Characteristic Table Location-3 of Device2"
hexmask.long.byte 0x00 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "DCR,Device Characteristic Value"
group.long 0x21C++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE2_LOC4_REG,Device Characteristic Table Location-4 of Device2"
hexmask.long.byte 0x00 0.--7. 1. "DEV_DYNAMIC_ADDR_LOC4,Device Dynamic Address assigned"
group.long 0x220++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE3_LOC1_REG,Device Characteristic Table Location-1 of Device3"
hexmask.long 0x00 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
group.long 0x224++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE3_LOC2_REG,Device Characteristic Table Location-2 of Device3"
hexmask.long.word 0x00 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
group.long 0x228++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE3_LOC3_REG,Device Characteristic Table Location-3 of Device3"
hexmask.long.byte 0x00 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "DCR,Device Characteristic Value"
group.long 0x22C++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE3_LOC4_REG,Device Characteristic Table Location-4 of Device3"
hexmask.long.byte 0x00 0.--7. 1. "DEV_DYNAMIC_ADDR_LOC4,Device Dynamic Address assigned"
group.long 0x230++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE4_LOC1_REG,Device Characteristic Table Location-1 of Device4"
hexmask.long 0x00 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
group.long 0x234++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE4_LOC2_REG,Device Characteristic Table Location-2 of Device4"
hexmask.long.word 0x00 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
group.long 0x238++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE4_LOC3_REG,Device Characteristic Table Location-3 of Device4"
hexmask.long.byte 0x00 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "DCR,Device Characteristic Value"
group.long 0x23C++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE4_LOC4_REG,Device Characteristic Table Location-4 of Device4"
hexmask.long.byte 0x00 0.--7. 1. "DEV_DYNAMIC_ADDR_LOC4,Device Dynamic Address assigned"
group.long 0x240++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE5_LOC1_REG,Device Characteristic Table Location-1 of Device5"
hexmask.long 0x00 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
group.long 0x244++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE5_LOC2_REG,Device Characteristic Table Location-2 of Device5"
hexmask.long.word 0x00 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
group.long 0x248++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE5_LOC3_REG,Device Characteristic Table Location-3 of Device5"
hexmask.long.byte 0x00 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "DCR,Device Characteristic Value"
group.long 0x24C++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE5_LOC4_REG,Device Characteristic Table Location-4 of Device5"
hexmask.long.byte 0x00 0.--7. 1. "DEV_DYNAMIC_ADDR_LOC4,Device Dynamic Address assigned"
group.long 0x250++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE6_LOC1_REG,Device Characteristic Table Location-1 of Device6"
hexmask.long 0x00 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
group.long 0x254++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE6_LOC2_REG,Device Characteristic Table Location-2 of Device6"
hexmask.long.word 0x00 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
group.long 0x258++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE6_LOC3_REG,Device Characteristic Table Location-3 of Device6"
hexmask.long.byte 0x00 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "DCR,Device Characteristic Value"
group.long 0x25C++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE6_LOC4_REG,Device Characteristic Table Location-4 of Device6"
hexmask.long.byte 0x00 0.--7. 1. "DEV_DYNAMIC_ADDR_LOC4,Device Dynamic Address assigned"
group.long 0x260++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE7_LOC1_REG,Device Characteristic Table Location-1 of Device7"
hexmask.long 0x00 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
group.long 0x264++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE7_LOC2_REG,Device Characteristic Table Location-2 of Device7"
hexmask.long.word 0x00 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
group.long 0x268++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE7_LOC3_REG,Device Characteristic Table Location-3 of Device7"
hexmask.long.byte 0x00 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "DCR,Device Characteristic Value"
group.long 0x26C++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE7_LOC4_REG,Device Characteristic Table Location-4 of Device7"
hexmask.long.byte 0x00 0.--7. 1. "DEV_DYNAMIC_ADDR_LOC4,Device Dynamic Address assigned"
group.long 0x270++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE8_LOC1_REG,Device Characteristic Table Location-1 of Device8"
hexmask.long 0x00 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
group.long 0x274++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE8_LOC2_REG,Device Characteristic Table Location-2 of Device8"
hexmask.long.word 0x00 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
group.long 0x278++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE8_LOC3_REG,Device Characteristic Table Location-3 of Device8"
hexmask.long.byte 0x00 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "DCR,Device Characteristic Value"
group.long 0x27C++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE8_LOC4_REG,Device Characteristic Table Location-4 of Device8"
hexmask.long.byte 0x00 0.--7. 1. "DEV_DYNAMIC_ADDR_LOC4,Device Dynamic Address assigned"
group.long 0x60++0x03
line.long 0x00 "I3C_DEV_CHAR_TABLE_POINTER_REG,Pointer for Device Characteristics Table"
bitfld.long 0x00 19.--21. "PRESENT_DEV_CHAR_TABLE_INDX,Current index of Device Characteristics Table" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 12.--18. 1. "DEV_CHAR_TABLE_DEPTH,Depth of Device Characteristics Table"
newline
hexmask.long.word 0x00 0.--11. 1. "P_DEV_CHAR_TABLE_START_ADDR,Start Address of Device Characteristics Table"
group.long 0x08++0x03
line.long 0x00 "I3C_HW_CAPABILITY_REG,Hardware Capability register"
rbitfld.long 0x00 19. "SLV_IBI_CAP,Reflects the IC_SLV_IBI Configurable Parameter" "0,1"
newline
rbitfld.long 0x00 18. "SLV_HJ_CAP,Reflects the IC_SLV_HJ Configurable Parameter" "0,1"
newline
rbitfld.long 0x00 17. "DMA_EN,Reflects the IC_HAS_DMA Configurable Parameter" "0,1"
newline
rbitfld.long 0x00 11.--16. "HDR_TX_CLOCK_PERIOD,Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 5.--10. "CLOCK_PERIOD,Reflects the IC_CLK_PERIOD Configurable Parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 4. "HDR_TS_EN,Reflects the IC_SPEED_HDR_TS Configurable Parameter" "0: HDR-TS not supported,1: HDR-TS supported"
newline
rbitfld.long 0x00 3. "HDR_DDR_EN,Reflects the IC_SPEED_HDR_DDR Configurable Parameter" "0: HDR-DDR not supported,1: HDR-DDR supported"
newline
rbitfld.long 0x00 0.--2. "DEVICE_ROLE_CONFIG,Reflects the IC_DEVICE_ROLE Configurable Parameter" "?,1: Master Only,2: Programmable Master-Slave,3: Secondary Master,4: Slave Only,?..."
group.long 0x24++0x03
line.long 0x00 "I3C_IBI_QUEUE_CTRL_REG,IBI Queue Control Register"
bitfld.long 0x00 3. "NOTIFY_SIR_REJECTED,Notify Rejected Slave Interrupt Request Control" "0: Suppress passing the IBI Status to the IBI FIFO,1: Writes IBI Status to the IBI FIFO (hence"
newline
bitfld.long 0x00 0. "NOTIFY_HJ_REJECTED,Notify Rejected Hot-Join Control" "0: Suppress passing the IBI Status to the IBI FIFO,1: Writes IBI Status to the IBI FIFO (hence"
group.long 0x18++0x03
line.long 0x00 "I3C_IBI_QUEUE_STATUS_DATA_REG,In-Band Interrupt Queue Status and Data Register"
rbitfld.long 0x00 28.--31. "IBI_STS,IBI Received Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "IBI_ID,IBI Identifier"
newline
hexmask.long.byte 0x00 0.--7. 1. "DATA_LENGTH,In-Band Interrupt data length"
group.long 0x30++0x03
line.long 0x00 "I3C_IBI_SIR_REQ_REJECT_REG,IBI SIR Request Rejection Control Register"
abitfld.long 0x00 0.--31. "SIR_REQ_REJECT,In-band Slave Interrupt Request Reject" "0x00000000=0: ACK the SIR Request,0x00000001=1: NACK and send directed auto.."
group.long 0x48++0x03
line.long 0x00 "I3C_INTR_FORCE_REG,Interrupt Force Enable Register"
bitfld.long 0x00 9. "TRANSFER_ERR_FORCE_EN,Transfer Error Force Enable" "0,1"
newline
bitfld.long 0x00 5. "TRANSFER_ABORT_FORCE_EN,Transfer Abort Force Enable" "0,1"
newline
bitfld.long 0x00 4. "RESP_READY_FORCE_EN,Response Queue Ready Force Enable" "0,1"
newline
bitfld.long 0x00 3. "CMD_QUEUE_READY_FORCE_EN,Command Queue Ready Force Enable" "0,1"
newline
bitfld.long 0x00 2. "IBI_THLD_FORCE_EN,IBI Buffer Threshold Force Enable" "0,1"
newline
bitfld.long 0x00 1. "RX_THLD_FORCE_EN,Receive Buffer Threshold Force Enable" "0,1"
newline
bitfld.long 0x00 0. "TX_THLD_FORCE_EN,Transmit Buffer Threshold Force Enable" "0,1"
group.long 0x44++0x03
line.long 0x00 "I3C_INTR_SIGNAL_EN_REG,Interrupt Signal Enable Register"
bitfld.long 0x00 9. "TRANSFER_ERR_SIGNAL_EN,Transfer Error Signal Enable" "0,1"
newline
bitfld.long 0x00 5. "TRANSFER_ABORT_SIGNAL_EN,Transfer Abort Signal Enable" "0,1"
newline
bitfld.long 0x00 4. "RESP_READY_SIGNAL_EN,Response Queue Ready Signal Enable" "0,1"
newline
bitfld.long 0x00 3. "CMD_QUEUE_READY_SIGNAL_EN,Command Queue Ready Signal Enable" "0,1"
newline
bitfld.long 0x00 2. "IBI_THLD_SIGNAL_EN,IBI Buffer Threshold Signal Enable" "0,1"
newline
bitfld.long 0x00 1. "RX_THLD_SIGNAL_EN,Receive Buffer Threshold Signal Enable" "0,1"
newline
bitfld.long 0x00 0. "TX_THLD_SIGNAL_EN,Transmit Buffer Threshold Signal Enable" "0,1"
group.long 0x40++0x03
line.long 0x00 "I3C_INTR_STATUS_EN_REG,Interrupt Status Enable Register"
bitfld.long 0x00 9. "TRANSFER_ERR_STS_EN,Transfer Error Status Enable" "0,1"
newline
bitfld.long 0x00 5. "TRANSFER_ABORT_STS_EN,Transfer Abort Status Enable" "0,1"
newline
bitfld.long 0x00 4. "RESP_READY_STS_EN,Response Queue Ready Status Enable" "0,1"
newline
bitfld.long 0x00 3. "CMD_QUEUE_READY_STS_EN,Command Queue Ready Status Enable" "0,1"
newline
bitfld.long 0x00 2. "IBI_THLD_STS_EN,IBI Buffer Threshold Status Enable" "0,1"
newline
bitfld.long 0x00 1. "RX_THLD_STS_EN,Receive Buffer Threshold Status Enable" "0,1"
newline
bitfld.long 0x00 0. "TX_THLD_STS_EN,Transmit Buffer Threshold Status Enable" "0,1"
group.long 0x3C++0x03
line.long 0x00 "I3C_INTR_STATUS_REG,Interrupt Status Register"
bitfld.long 0x00 9. "TRANSFER_ERR_STS,Transfer Error Status" "0,1"
newline
bitfld.long 0x00 5. "TRANSFER_ABORT_STS,Transfer Abort Status" "0,1"
newline
rbitfld.long 0x00 4. "RESP_READY_STS,Response Queue Ready Status" "0,1"
newline
rbitfld.long 0x00 3. "CMD_QUEUE_READY_STS,Command Queue Ready" "0,1"
newline
rbitfld.long 0x00 2. "IBI_THLD_STS,IBI Buffer Threshold Status" "0,1"
newline
rbitfld.long 0x00 1. "RX_THLD_STS,Receive Buffer Threshold Status" "0,1"
newline
rbitfld.long 0x00 0. "TX_THLD_STS,Transmit Buffer Threshold Status" "0,1"
group.long 0x54++0x03
line.long 0x00 "I3C_PRESENT_STATE_REG,Present State Register"
rbitfld.long 0x00 28. "MASTER_IDLE,This field reflects whether the Master Controller is in Idle state or not" "0,1"
newline
rbitfld.long 0x00 24.--27. "CMD_TID,This field reflects the Transaction-ID of the current executing command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--21. "CM_TFR_ST_STS,Current Master Transfer State Status" "0: IDLE (Controller is Idle state waiting for,1: START Generation State,2: RESTART Generation State,3: STOP Generation State,4: START Hold Generation for the Slave Initiated,5: Broadcast Write Address Header(7'h7E W),6: Broadcast Read Address Header(7'h7E R),7: Dynamic Address Assignment State,8: Slave Address Generation State,?,?,11: CCC Byte Generation State,12: HDR Command Generation State,13: Write Data Transfer State,14: Read Data Transfer State,15: In-Band Interrupt(SIR) Read Data State,16: In-Band Interrupt Auto-Disable State,17: HDR-DDR CRC Data Generation/Receive State,18: Clock Extension State,19: Halt State,?..."
newline
rbitfld.long 0x00 8.--13. "CM_TFR_STS,Transfer Type Status" "0: IDLE (Controller is in Idle state waiting for,1: Broadcast CCC Write Transfer,2: Directed CCC Write Transfer,3: Directed CCC Read Transfer,4: ENTDAA Address Assignment Transfer,5: SETDASA Address Assignment Transfer,6: Private I3C SDR Write Transfer,7: Private I3C SDR Read Transfer,8: Private I2C SDR Write Transfer,9: Private I2C SDR Read Transfer,10: Private HDR Ternary Symbol(TS) Write Transfer,11: Private HDR Ternary Symbol(TS) Read Transfer,12: Private HDR Double-Data Rate(DDR) Write..,13: Private HDR Double-Data Rate(DDR) Read..,14: Servicing In-Band Interrupt Transfer,15: Halt state (Controller is in Halt State..,?..."
newline
rbitfld.long 0x00 2. "CURRENT_MASTER,This Bit is used to check whether the Master is Current Master or not" "0: Master is not Current Master,1: Master is Current Master"
newline
rbitfld.long 0x00 1. "SDA_LINE_SIGNAL_LEVEL,This bit is used to check the SDA line level to recover from errors and for debugging" "0,1"
newline
rbitfld.long 0x00 0. "SCL_LINE_SIGNAL_LEVEL,This bit is used to check the SCL line level to recover from errors and for debugging" "0,1"
group.long 0xE8++0x03
line.long 0x00 "I3C_QUEUE_SIZE_CAPABILITY_REG,DWC_mipi_i3c Queue Size Capability Register"
rbitfld.long 0x00 16.--19. "IBI_BUF_SIZE,IBI Queue Size This field reflects the configured IBI Queue size (in DWORDS) in Encoded Values" "0: 2 DWORDS,1: 4 DWORDS,2: 8 DWORDS,3: 16 DWORDS,?..."
newline
rbitfld.long 0x00 12.--15. "RESP_BUF_SIZE,Response Queue Size This field reflects the configured Response Queue size (in DWORDS) in Encoded Values" "0: 2 DWORDS,1: 4 DWORDS,2: 8 DWORDS,3: 16 DWORDS,?..."
newline
rbitfld.long 0x00 8.--11. "CMD_BUF_SIZE,Command Queue Size This field reflects the configured Command Queue size (in DWORDS) in Encoded Values" "0: 2 DWORDS,1: 4 DWORDS,2: 8 DWORDS,3: 16 DWORDS,?..."
newline
rbitfld.long 0x00 4.--7. "RX_BUF_SIZE,Receive Data Buffer Size This field reflects the configured Receive Buffer size (in DWORDS) in Encoded Values" "0: 2 DWORDS,1: 4 DWORDS,2: 8 DWORDS,3: 16 DWORDS,4: 32 DWORDS,5: 64 DWORDS,?..."
newline
rbitfld.long 0x00 0.--3. "TX_BUF_SIZE,Transmit Data Buffer Size This field reflects the configured Transmit Buffer size (in DWORDS) in Encoded Values" "0: 2 DWORDS,1: 4 DWORDS,2: 8 DWORDS,3: 16 DWORDS,4: 32 DWORDS,5: 64 DWORDS,?..."
group.long 0x4C++0x03
line.long 0x00 "I3C_QUEUE_STATUS_LEVEL_REG,Queue Status Level Register"
rbitfld.long 0x00 24.--28. "IBI_STS_CNT,IBI Buffer Status Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 16.--23. 1. "IBI_BUF_BLR,IBI Buffer Level Value"
newline
hexmask.long.byte 0x00 8.--15. 1. "RESP_BUF_BLR,Response Buffer Level Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "CMD_QUEUE_EMPTY_LOC,Command Queue Empty Locations"
group.long 0x1C++0x03
line.long 0x00 "I3C_QUEUE_THLD_CTRL_REG,Queue Threshold Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IBI_STATUS_THLD,In-Band Interrupt Status Threshold Value"
newline
hexmask.long.byte 0x00 8.--15. 1. "RESP_BUF_THLD,Response Buffer Threshold Value"
newline
hexmask.long.byte 0x00 0.--7. 1. "CMD_EMPTY_BUF_THLD,Command Buffer Empty Threshold Value"
group.long 0x34++0x03
line.long 0x00 "I3C_RESET_CTRL_REG,Reset Control Register"
bitfld.long 0x00 5. "IBI_QUEUE_RST,IBI Queue Software Reset" "0,1"
newline
bitfld.long 0x00 4. "RX_FIFO_RST,Receive Buffer Software Reset" "0,1"
newline
bitfld.long 0x00 3. "TX_FIFO_RST,Transmit Buffer Software Reset" "0,1"
newline
bitfld.long 0x00 2. "RESP_QUEUE_RST,Response Queue Software Reset" "0,1"
newline
bitfld.long 0x00 1. "CMD_QUEUE_RST,Command Queue Software Reset" "0,1"
newline
bitfld.long 0x00 0. "SOFT_RST,Core Software Reset" "0,1"
group.long 0x10++0x03
line.long 0x00 "I3C_RESPONSE_QUEUE_PORT_REG,RESPONSE_QUEUE_PORT"
hexmask.long 0x00 0.--31. 1. "RESPONSE,32 bit Response"
group.long 0x14++0x03
line.long 0x00 "I3C_RX_TX_DATA_PORT_REG,Receive and Transmit Data Port Register"
hexmask.long 0x00 0.--31. 1. "RX_TX_DATA_PORT,Receive and Transmit Data Port"
group.long 0xC8++0x03
line.long 0x00 "I3C_SCL_EXT_LCNT_TIMING_REG,SCL Extended Low Count Timing Register"
hexmask.long.byte 0x00 24.--31. 1. "I3C_EXT_LCNT_4,I3C Extended Low Count Register 4 SDR4 uses this register field for data transfer"
newline
hexmask.long.byte 0x00 16.--23. 1. "I3C_EXT_LCNT_3,I3C Extended Low Count Register 3 SDR3 uses this register field for data transfer"
newline
hexmask.long.byte 0x00 8.--15. 1. "I3C_EXT_LCNT_2,I3C Extended Low Count Register 2 SDR2 uses this register field for data transfer"
newline
hexmask.long.byte 0x00 0.--7. 1. "I3C_EXT_LCNT_1,I3C Extended Low Count Register 1 SDR1 uses this register field for data transfer"
group.long 0xCC++0x03
line.long 0x00 "I3C_SCL_EXT_TERMN_LCNT_TIME_REG,SCL Termination Bit Low count Timing Register"
bitfld.long 0x00 0.--3. "I3C_EXT_TERMN_LCNT,I3C Read Termination Bit Low count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0++0x03
line.long 0x00 "I3C_SCL_I2C_FMP_TIMING_REG,SCL I2C Fast Mode Plus Timing Register"
hexmask.long.byte 0x00 16.--23. 1. "I2C_FMP_HCNT,I2C Fast Mode Plus High Count The SCL open-drain high count timing for I2C fast mode transfers"
newline
hexmask.long.word 0x00 0.--15. 1. "I2C_FMP_LCNT,I2C Fast Mode Plus Low Count The SCL open-drain low count timing for I2C fast mode transfers"
group.long 0xBC++0x03
line.long 0x00 "I3C_SCL_I2C_FM_TIMING_REG,SCL I2C Fast Mode Timing Register"
hexmask.long.word 0x00 16.--31. 1. "I2C_FM_HCNT,I2C Fast Mode High Count The SCL open-drain high count timing for I2C fast mode transfers"
newline
hexmask.long.word 0x00 0.--15. 1. "I2C_FM_LCNT,I2C Fast Mode Low Count The SCL open-drain low count timing for I2C fast mode transfers"
group.long 0xB4++0x03
line.long 0x00 "I3C_SCL_I3C_OD_TIMING_REG,SCL I3C Open Drain Timing Register"
hexmask.long.byte 0x00 16.--23. 1. "I3C_OD_HCNT,I3C Open Drain High Count"
newline
hexmask.long.byte 0x00 0.--7. 1. "I3C_OD_LCNT,I3C Open Drain Low Count"
group.long 0xB8++0x03
line.long 0x00 "I3C_SCL_I3C_PP_TIMING_REG,SCL I3C Push Pull Timing Register"
hexmask.long.byte 0x00 16.--23. 1. "I3C_PP_HCNT,I3C Push Pull High Count"
newline
hexmask.long.byte 0x00 0.--7. 1. "I3C_PP_LCNT,I3C Push Pull Low Count"
group.long 0xD0++0x03
line.long 0x00 "I3C_SDA_HOLD_DLY_TIMING_REG,SDA Hold Delay Timing Register"
bitfld.long 0x00 16.--18. "SDA_TX_HOLD,This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with respect to the SCL edge in FM FM+ SDR and DDR speed mode of operations" "0,1,2,3,4,5,6,7"
group.long 0x38++0x03
line.long 0x00 "I3C_SLV_EVENT_STATUS_REG,Slave Event Status Register"
bitfld.long 0x00 7. "MWL_UPDATED,MWL Updated Status" "0,1"
newline
bitfld.long 0x00 6. "MRL_UPDATED,MRL Updated Status" "0,1"
newline
rbitfld.long 0x00 4.--5. "ACTIVITY_STATE,Activity State Status" "0,1,2,3"
group.long 0x6C++0x03
line.long 0x00 "I3C_VENDOR_SPECIFIC_REG_PTR_REG,Pointer for Vendor specific Registers"
hexmask.long.word 0x00 0.--15. 1. "P_VENDOR_REG_START_ADDR,Start Address of Vendor specific registers"
group.long 0xE0++0x03
line.long 0x00 "I3C_VER_ID_REG,DWC_mipi_i3c Version ID Register"
hexmask.long 0x00 0.--31. 1. "I3C_VER_ID,Current release type This field indicates the Synopsys DesignWare Cores DWC_mipi_i3c current release type that is read by an application"
group.long 0xE4++0x03
line.long 0x00 "I3C_VER_TYPE_REG,DWC_mipi_i3c Version Type Register"
hexmask.long 0x00 0.--31. 1. "I3C_VER_TYPE,Current release type This field indicates the Synopsys DesignWare Cores DWC_mipi_i3c current release type that is read by an application"
tree.end
tree "LCDC"
base ad:0x30030000
group.long 0x1C++0x03
line.long 0x00 "LCDC_BACKPORCHXY_REG,Back Porch X and Y"
hexmask.long.word 0x00 16.--31. 1. "BPORCH_X,Back porch X (lines)"
newline
hexmask.long.word 0x00 0.--15. 1. "BPORCH_Y,Back porch Y (pixel clocks)"
group.long 0x08++0x03
line.long 0x00 "LCDC_BGCOLOR_REG,Background Color"
hexmask.long.byte 0x00 24.--31. 1. "BG_RED,Red color used as background"
newline
hexmask.long.byte 0x00 16.--23. 1. "BG_GREEN,Green color used as background"
newline
hexmask.long.byte 0x00 8.--15. 1. "BG_BLUE,Blue color used as background"
newline
hexmask.long.byte 0x00 0.--7. 1. "BG_ALPHA,Alpha color used as background"
group.long 0x18++0x03
line.long 0x00 "LCDC_BLANKINGXY_REG,Blanking X and Y"
hexmask.long.word 0x00 16.--31. 1. "BLANKING_X,Blanking period X (VSYNC lines)"
newline
hexmask.long.word 0x00 0.--15. 1. "BLANKING_Y,Blanking period Y (HSYNC pulse length)"
group.long 0x1A8++0x03
line.long 0x00 "LCDC_CLKCTRL_CG_REG,Controls the CLock Gaters and the routing of format and pixel clock"
bitfld.long 0x00 2. "LCDC_SWAP_PIX_FORMAT_CLK," "0,1"
newline
bitfld.long 0x00 1. "LCDC_INV_CLK_POLARITY," "0,1"
newline
bitfld.long 0x00 0. "LCDC_CLK_DIV_EN," "0,1"
group.long 0x04++0x03
line.long 0x00 "LCDC_CLKCTRL_REG,Clock Divider"
bitfld.long 0x00 27.--31. "SEC_CLK_DIV,Secondary clock divider that generates the format pipeline clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--13. "DMA_HOLD,Hold time before DMA activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "CLK_DIV,Clock divider that generates the pixel pipeline clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x100++0x03
line.long 0x00 "LCDC_COLMOD,Color mode status register"
rbitfld.long 0x00 31. "BP_DBIB,Indicates that back pressure support for the DBI Type B interface is enabled" "0,1"
newline
hexmask.long.tbyte 0x00 0.--16. 1. "COLMODES,16 bit: Indicates that the LUT8 color format is enabled 15 bit: Indicates that the RGBA5551 16-bit color format is enabled 14 bit: Indicates that the RGBA8888 32-bit color format is enabled 13 bit: Indicates that the RGB332 8-bit color format.."
group.long 0xF0++0x03
line.long 0x00 "LCDC_CONF_REG,Supported config"
hexmask.long.word 0x00 0.--15. 1. "CONF,"
group.long 0x184++0x03
line.long 0x00 "LCDC_CRC_REG,CRC check"
hexmask.long 0x00 0.--31. 1. "CRC,CRC check"
group.long 0x28++0x03
line.long 0x00 "LCDC_DBIB_CFG_REG,MIPI Config Register"
bitfld.long 0x00 31. "DBIB_INTERFACE_EN,When set to 1 the DBI Type-B interface is activated" "0,1"
newline
bitfld.long 0x00 30. "DBIB_CSX_CFG_EN,When set to 1 the value of the CSX signal of the DBI Type-B interface can be configured from the DBIB_CFG[29] register bit" "0,1"
newline
bitfld.long 0x00 29. "DBIB_CSX_CFG,Sets the value of DBIB_CSX signal: CSX is set to one if DBIB_CFG[29] has the value of one CSX is set to zero if DBIB_CFG[29] has the value of zero" "0,1"
newline
bitfld.long 0x00 28. "DBIB_TE_DISABLE,When set to 1 the DBIB_TE signal is disabled" "0,1"
newline
bitfld.long 0x00 27. "SPI_DC_AS_SPI_SD1,When set to 1 enables the usage of SPI_DC wire as SPI_SD1" "0,1"
newline
bitfld.long 0x00 26. "DBIB_FORCE_IDLE,When set to 1 force DBI Type-B interface to idle state" "0,1"
newline
bitfld.long 0x00 25. "DBIB_RESX_OUT_EN,Drives DBIB_RESX output signal of DBI Type-B interface" "0,1"
newline
bitfld.long 0x00 24. "SUB_PIXEL_REVERSE,Reverse sub pixel order" "0,1"
newline
bitfld.long 0x00 23. "SPI3_EN,When set to 1 SPI 3-wire interface is enabled" "0,1"
newline
bitfld.long 0x00 22. "SPI4_EN,When set to 1 SPI 4-wire interface is enabled" "0,1"
newline
bitfld.long 0x00 21. "DBIB_BACK_PRESSURE_EN,When set to 1 Enables back-pressure for DBI Type-B interface" "0,1"
newline
bitfld.long 0x00 20. "SPI_CLK_PHASE,Sets SPI Clock Phase" "0,1"
newline
bitfld.long 0x00 19. "SPI_CLK_POLARITY,Sets SPI Clock Polarity" "0,1"
newline
bitfld.long 0x00 18. "SPID_JDI," "0,1"
newline
bitfld.long 0x00 17. "CMD_DATA_AS_HEADER,When set to 1 command data are used as header of each line" "0,1"
newline
bitfld.long 0x00 16. "BIT_ORDER_ADDR_INVERT,When set to 1 inverts the bit-order of the horizontal line address (used along with DBIB_CFG[17] register bit)" "0,1"
newline
bitfld.long 0x00 15. "SPI_2BYTE_ADDR,When set to 1 two-byte address is sent with each horizontal line (SPI)" "0,1"
newline
bitfld.long 0x00 14. "PIX_CLK_AT_DBIB_CLK,When set to 1 expose pixel generation clock on the DBIB_CLK" "0,1"
newline
bitfld.long 0x00 13. "EXT_CTRL_EN,When set to 1 enables the external control" "0,1"
newline
bitfld.long 0x00 12. "HORIZONTAL_BLANK_EN,When set to 1 enables the horizontal blanking" "0,1"
newline
bitfld.long 0x00 11. "DUAL_SPI_SUBPIXEL_EXTRACT_EN,When set to 1 Enables DualSPI sub-pixel transaction" "0,1"
newline
bitfld.long 0x00 10. "QUAD_SPI_EN,When set to 1 Enables QuadSPI" "0,1"
newline
bitfld.long 0x00 9. "DUAL_SPI_EN,When set to 1 Enables DualSPI" "0,1"
newline
bitfld.long 0x00 6.--8. "DBIB_INTERFACE_WIDTH,Set DBI Type-B interface width (8 9 or 16 bits) and the serial interface" "0: 8-bit interface,1: 9-bit interface,2: 16-bit interface,3: SPI,4: Dual SPI,5: Quad SPI,?..."
newline
bitfld.long 0x00 3.--5. "DBIB_DATA_ORDER,Set the data order of the 8-bit data word" "0: option 0,1: option 1,2: option 2,3: option 3,4: option 4,5: Reserved,6: Reserved,7: Reserved"
newline
bitfld.long 0x00 0.--2. "DBIB_COLOR_FMT,Defines the output format and depends of the type of the output interface" "0: Reserved,1: RGB111,2: RGB332,3: RGB444,4: Reserved,5: RGB565,6: RGB666,7: RGB888"
group.long 0xE8++0x03
line.long 0x00 "LCDC_DBIB_CMD_REG,MIPI DBIB Command Register"
bitfld.long 0x00 31. "PART_UPDATE,When set to 0 indicates that the command data are the Base address for partial update" "0,1"
newline
bitfld.long 0x00 30. "DBIB_CMD_SEND,Send command to the DBI interface" "0,1"
newline
bitfld.long 0x00 28.--29. "CMD_WIDTH,Determine the command width" "0: 1 Byte,1: 2 Bytes,2: 3 Bytes,3: Reserved"
newline
bitfld.long 0x00 27. "DBIB_CMD_STORE,This bit has meaning only when LCDC_DBIB_CFG_REG[LCDC_DBIB_SPI_JDI] = 1" "0,1"
newline
bitfld.long 0x00 26. "RD_MODE_EN,When sets to 1 read mode is enabled" "0,1"
newline
bitfld.long 0x00 25. "FMTCTRL_EXPOSE_SETTING,When sets to 1 FMTCTRL[15:8] is exposed on DBIB_CT pins and FMTCTRL[31] on DBIB_GE else FMTCTRL[15:8] is exposed on DBIB_CT pins and FMTCTRL[30] on DBIB_GE" "0,1"
newline
bitfld.long 0x00 24. "ST_INT_CMD_TYPE,When sets to 1 store internally a command type which is transmitted at the beggining of each scanline" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "DBIB_CMD_VAL,Data to send to the DBI interface"
group.long 0xEC++0x03
line.long 0x00 "LCDC_DBIB_RDAT,Data read by DBI Type-B/SPI interface"
abitfld.long 0x00 0.--31. "DBIB_RDAT,On Write: 31-30 bits: Specify the number of read cycles" "0x00000000=0: 8 cycles,0x00000001=1: 16 cycles,0x00000002=2: 24 cycles,0x00000003=3: Used along with"
group.long 0x1A4++0x03
line.long 0x00 "LCDC_FMTCTRL_2_REG,DBI and JDI format control"
hexmask.long 0x00 0.--31. 1. "FMTCTRL,Bits Description When DBI-Type B Interface is selected: Bits Description 31-16 bits: Reserved 15-0 bits: Specify the blanking period length for the X dimension When JDI-Parallel Interface is selected: Bits Description 31-20 bits: Reserved 19-10.."
group.long 0x1A0++0x03
line.long 0x00 "LCDC_FMTCTRL_REG,DBI and JDI format control"
abitfld.long 0x00 0.--31. "FMTCTRL,When DBI-Type B Interface is selected: Bits Description 31 bit : Candidate for DBIB_GE associated with [15:8] bits (DSI interface specific) 30 bit : Candidate for DBIB_GE associated with [7:0] bits (DSI interface specific) 29-21 bits: Reserved.." "0x00000000=0: 1 cycles,0x00000001=1: 2 cycles,0x00000002=2: 3 cycles,0x00000030=48: 31 cycles,0x00000031=49: 32 cycles 15-8 bits"
group.long 0x14++0x03
line.long 0x00 "LCDC_FRONTPORCHXY_REG,Front Porch X and Y"
hexmask.long.word 0x00 16.--31. 1. "FPORCH_X,Front porch X (lines)"
newline
hexmask.long.word 0x00 0.--15. 1. "FPORCH_Y,Front porch Y (pixel clocks)"
group.long 0x2C++0x03
line.long 0x00 "LCDC_GPIO_REG,General Purpose IO (8-bits)"
bitfld.long 0x00 16. "DPI_CM_ASSERT,Assert DPI-2 Color Mode signal" "0,1"
newline
bitfld.long 0x00 15. "DPI_SD_ASSERT,Assert DPI-2 Shutdown signal" "0,1"
newline
bitfld.long 0x00 13.--14. "SCAL_ADVANCE,scalar advance" "0,1,2,3"
newline
hexmask.long.byte 0x00 6.--12. 1. "LCDC_OTHER,TBD"
newline
bitfld.long 0x00 5. "GPIO_SPI_SI_ON_SD_PAD,Enable to have the SPI SI on the SPI SD pad" "0,1"
newline
bitfld.long 0x00 3.--4. "GPIO_OUTPUT_MODE,Select the mode that should be mapped on the GPIO pins" "0: JDI,1: DPI,2: DBI,3: SPI"
newline
bitfld.long 0x00 2. "GPIO_OUTPUT_EN,Enable the GPIO pins for LCDC control" "0,1"
newline
bitfld.long 0x00 1. "TE_INV,Applies an inversion on the TE (tearing effect) signal" "0: the inversion is not applied on the TE signal,1: the inversion is applied on TE signal"
newline
bitfld.long 0x00 0. "CLK_DIV_2DIV3,Divide clock by 2/3 clock-gating" "0,1"
group.long 0xF4++0x03
line.long 0x00 "LCDC_IDREG_REG,Identification Register"
hexmask.long 0x00 0.--31. 1. "NEMADC_ID,Identification register"
group.long 0xF8++0x03
line.long 0x00 "LCDC_INTERRUPT_REG,Interrupt Register"
bitfld.long 0x00 31. "IRQ_TRIGGER_SEL,IRQ trigger control" "0: Level triggering,1: Edge triggering In the case of the level"
newline
bitfld.long 0x00 30. "IRQ_OUT," "0,1"
newline
bitfld.long 0x00 4. "FE_IRQ_EN," "0,1"
newline
bitfld.long 0x00 3. "TE_IRQ_EN," "0,1"
newline
bitfld.long 0x00 2. "MMU_ERROR_IRQ_EN," "0,1"
newline
bitfld.long 0x00 1. "HSYNC_IRQ_EN,HSYNC interrupt enabled" "0,1"
newline
bitfld.long 0x00 0. "VSYNC_IRQ_EN,VSYNC or TE interrupt enabled" "0,1"
group.long 0x3C++0x03
line.long 0x00 "LCDC_LAYER0_BASEADDR_REG,Layer0 Base Addr"
hexmask.long 0x00 0.--31. 1. "L0_BASE_ADDR,Base Address of the frame buffer"
group.long 0x30++0x03
line.long 0x00 "LCDC_LAYER0_MODE_REG,Layer0 Mode"
bitfld.long 0x00 31. "L0_EN,Enable layer" "0: disable,1: enable"
newline
bitfld.long 0x00 30. "L0_FORCE_ALPHA,When set to 1 force alpha with global alpha" "0,1"
newline
bitfld.long 0x00 29. "L0_DIS_BIL_FILTERING,When set to 0 bilinear filtering is enabled" "0,1"
newline
bitfld.long 0x00 28. "L0_PREMUL_IMG_ALPHA,When set to 1 premultiply image alpha is enabled" "0,1"
newline
bitfld.long 0x00 27. "L0_ASSERT_HCLK_DMA,When set to 1 HLOCK signal on AHB DMAs is asserted" "0,1"
newline
bitfld.long 0x00 26. "L0_GAMMA_LUT_EN,When set to 1 Gamma Look Up Table is enabled" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "L0_ALPHA,Alpha layer global value (0x00-0xFF range)"
newline
bitfld.long 0x00 12.--15. "L0_DST_BLEND,Destinary Blending Function" "0: BLEND ZERO,1: BLEND ONE,2: BLEND ALPHA SRC,3: BLEND ALPHA GBL,4: BLEND ALPHA SRCGBL,5: BLEND INV SRC,6: BLEND INV GBL,7: BLEND INV SRCGBL,?,?,10: BLEND ALPHA DST,?,?,13: BLEND INV DST,?..."
newline
bitfld.long 0x00 8.--11. "L0_SRC_BLEND,Source Blending Function" "0: BLEND ZERO,1: BLEND ONE,2: BLEND ALPHA SRC,3: BLEND ALPHA GBL,4: BLEND ALPHA SRCGBL,5: BLEND INV SRC,6: BLEND INV GBL,7: BLEND INV SRCGBL,?,?,10: BLEND ALPHA DST,?,?,13: BLEND INV DST,?..."
newline
bitfld.long 0x00 0.--4. "L0_COLOR_MODE,Color Mode" "?,1: 16-bit RGBX5551 color format,2: 32-bit RGBX8888 color format,?,4: 8-bit RGB332 color format,5: 16-bit RGB565 color format,6: 32-bit XRGB8888,7: L8 Grayscale/Palette format,8: L1 Grayscale/Palette format,9: L4 Grayscale/Palette format,?,?,?,13: ABGR8888,14: BGRA8888,?..."
group.long 0x44++0x03
line.long 0x00 "LCDC_LAYER0_RESXY_REG,Layer0 Res XY"
hexmask.long.word 0x00 16.--31. 1. "L0_RES_X,Resolution X (Resolution of layer in pixels)"
newline
hexmask.long.word 0x00 0.--15. 1. "L0_RES_Y,Resolution Y (Resolution of layer in pixels)"
group.long 0x38++0x03
line.long 0x00 "LCDC_LAYER0_SIZEXY_REG,Layer0 Size XY"
hexmask.long.word 0x00 16.--31. 1. "L0_SIZE_X,Size X (Size of layer in pixels)"
newline
hexmask.long.word 0x00 0.--15. 1. "L0_SIZE_Y,Size Y (Size of layer in pixels)"
group.long 0x34++0x03
line.long 0x00 "LCDC_LAYER0_STARTXY_REG,Layer0 Start XY"
hexmask.long.word 0x00 16.--31. 1. "L0_START_X,Start X (offset pixels)"
newline
hexmask.long.word 0x00 0.--15. 1. "L0_START_Y,Start Y (offset pixels)"
group.long 0x40++0x03
line.long 0x00 "LCDC_LAYER0_STRIDE_REG,Layer0 Stride"
bitfld.long 0x00 19.--20. "L0_FIFO_THR,Layer dma fifo threshold burst start" "0: half fifo (default),1: 2 burst size,2: 4 burst size,3: 8 burst size"
newline
bitfld.long 0x00 16.--18. "L0_BURST_LEN,Layer burst length" "0: 16-beats (default),1: 2-beats,2: 4-beats,3: 8-beats,4: 16-beats,?..."
newline
hexmask.long.word 0x00 0.--15. 1. "L0_STRIDE,Layer Stride (distance from line to line in bytes)"
group.long 0x5C++0x03
line.long 0x00 "LCDC_LAYER1_BASEADDR_REG,Layer1 Base Addr"
hexmask.long 0x00 0.--31. 1. "L1_BASE_ADDR,Base Address of the frame buffer"
group.long 0x50++0x03
line.long 0x00 "LCDC_LAYER1_MODE_REG,Layer1 Mode"
bitfld.long 0x00 31. "L1_EN,Enable layer" "0: disable,1: enable"
newline
bitfld.long 0x00 30. "L1_FORCE_ALPHA,When set to 1 force alpha with global alpha" "0,1"
newline
bitfld.long 0x00 29. "L1_DIS_BIL_FILTERING,When set to 0 bilinear filtering is enabled" "0,1"
newline
bitfld.long 0x00 28. "L1_PREMUL_IMG_ALPHA,When set to 1 premultiply image alpha is enabled" "0,1"
newline
bitfld.long 0x00 27. "L1_ASSERT_HCLK_DMA,When set to 1 HLOCK signal on AHB DMAs is asserted" "0,1"
newline
bitfld.long 0x00 26. "L1_GAMMA_LUT_EN,When set to 1 Gamma Look Up Table is enabled" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "L1_ALPHA,Alpha layer global value (0x00-0xFF range)"
newline
bitfld.long 0x00 12.--15. "L1_DST_BLEND,Destinary Blending Function" "0: BLEND ZERO,1: BLEND ONE,2: BLEND ALPHA SRC,3: BLEND ALPHA GBL,4: BLEND ALPHA SRCGBL,5: BLEND INV SRC,6: BLEND INV GBL,7: BLEND INV SRCGBL,?,?,10: BLEND ALPHA DST,?,?,13: BLEND INV DST,?..."
newline
bitfld.long 0x00 8.--11. "L1_SRC_BLEND,Source Blending Function" "0: BLEND ZERO,1: BLEND ONE,2: BLEND ALPHA SRC,3: BLEND ALPHA GBL,4: BLEND ALPHA SRCGBL,5: BLEND INV SRC,6: BLEND INV GBL,7: BLEND INV SRCGBL,?,?,10: BLEND ALPHA DST,?,?,13: BLEND INV DST,?..."
newline
bitfld.long 0x00 0.--4. "L1_COLOR_MODE,Color Mode" "?,1: 16-bit RGBX5551 color format,2: 32-bit RGBX8888 color format,?,4: 8-bit RGB332 color format,5: 16-bit RGB565 color format,6: 32-bit XRGB8888,7: L8 Grayscale/Palette format,8: L1 Grayscale/Palette format,9: L4 Grayscale/Palette format,?,?,?,13: ABGR8888,14: BGRA8888,?..."
group.long 0x64++0x03
line.long 0x00 "LCDC_LAYER1_RESXY_REG,Layer1 Res XY"
hexmask.long.word 0x00 16.--31. 1. "L1_RES_X,Resolution X (Resolution of layer in pixels)"
newline
hexmask.long.word 0x00 0.--15. 1. "L1_RES_Y,Resolution Y (Resolution of layer in pixels)"
group.long 0x58++0x03
line.long 0x00 "LCDC_LAYER1_SIZEXY_REG,Layer1 Size XY"
hexmask.long.word 0x00 16.--31. 1. "L1_SIZE_X,Size X (Size of layer in pixels)"
newline
hexmask.long.word 0x00 0.--15. 1. "L1_SIZE_Y,Size Y (Size of layer in pixels)"
group.long 0x54++0x03
line.long 0x00 "LCDC_LAYER1_STARTXY_REG,Layer0 Start XY"
hexmask.long.word 0x00 16.--31. 1. "L1_START_X,Start X (offset pixels)"
newline
hexmask.long.word 0x00 0.--15. 1. "L1_START_Y,Start Y (offset pixels)"
group.long 0x60++0x03
line.long 0x00 "LCDC_LAYER1_STRIDE_REG,Layer1 Stride"
bitfld.long 0x00 19.--20. "L1_FIFO_THR,Layer dma fifo threshold burst start" "0: half fifo (default),1: 2 burst size,2: 4 burst size,3: 8 burst size"
newline
bitfld.long 0x00 16.--18. "L1_BURST_LEN,Layer burst length" "0: 16-beats (default),1: 2-beats,2: 4-beats,3: 8-beats,4: 16-beats,?..."
newline
hexmask.long.word 0x00 0.--15. 1. "L1_STRIDE,Layer Stride (distance from line to line in bytes)"
group.long 0x00++0x03
line.long 0x00 "LCDC_MODE_REG,Display Mode"
bitfld.long 0x00 31. "MODE_EN,Mode register" "0: disable,1: enable"
newline
bitfld.long 0x00 28. "VSYNC_POL,VSYNC polarity" "0: positive,1: negative"
newline
bitfld.long 0x00 27. "HSYNC_POL,HSYNC polarity" "0: positive,1: negative"
newline
bitfld.long 0x00 26. "DE_POL,DE polarity" "0: positive,1: negative"
newline
bitfld.long 0x00 24.--25. "DITH_MODE," "?,1: Dithering 18-bits mode,2: Dithering 16-bits mode,3: Dithering 15-bits mode"
newline
bitfld.long 0x00 23. "VSYNC_SCPL,Set VSYNC for a single cycle per line" "0: disable,1: enable"
newline
bitfld.long 0x00 22. "PIXCLKOUT_POL,Pixel clock out polarity" "0: positive,1: negative"
newline
bitfld.long 0x00 20. "GLOBAL_GAMMA_EN,When set to 1 global gamma correction is enabled" "0,1"
newline
bitfld.long 0x00 19. "FORCE_BLANK,Forces output to blank" "0: disable,1: enable"
newline
bitfld.long 0x00 17. "SFRAME_UPD,Single frame update" "0: disable,1: enable"
newline
bitfld.long 0x00 12.--14. "DPI2_CONFIG,Defines MIPI DPI-2 Configuration" "0: RGB888 24-bits,1: RGB666 18-bits Configuration 1,2: RGB666 18-bits Configuration 2,3: RGB565 16-bits Configuration 1,4: RGB565 16-bits Configuration 2,5: RGB565 16-bits Configuration 3,6: Reserved,7: Reserved"
newline
bitfld.long 0x00 11. "PIXCLKOUT_SEL,Selects the pixel out clock for the display" "0: based on the pixel pipeline clock,1: based on the format pipeline clock See also the"
newline
bitfld.long 0x00 5.--8. "OUT_MODE,Selection of the output mode" "0: Parallel RGB,?,?,?,?,?,?,?,8: JDI MIP All the other values are,?..."
newline
bitfld.long 0x00 4. "DBIB_OFF,When set to 0 DBI Type-B interface is enabled" "0,1"
newline
bitfld.long 0x00 3. "FORM_OFF,Formating off" "0: disabled,1: enabled"
newline
bitfld.long 0x00 1. "DSCAN,Double horizontal scan" "0: disabled,1: enabled"
newline
bitfld.long 0x00 0. "TMODE,Test mode" "0: disabled,1: enabled"
group.long 0x7FC++0x03
line.long 0x00 "LCDC_PALETTE_255,Global palette/gamma correction"
hexmask.long.byte 0x00 16.--23. 1. "PALLETE_R,Gamma ramp red bits"
newline
hexmask.long.byte 0x00 8.--15. 1. "PALLETE_G,Gamma ramp green bits"
newline
hexmask.long.byte 0x00 0.--7. 1. "PALLETE_B,Gamma ramp blue bits"
group.long 0x400++0x03
line.long 0x00 "LCDC_PALETTE_BASE,Global palette/gamma correction"
hexmask.long.byte 0x00 16.--23. 1. "PALLETE_R,Gamma ramp red bits"
newline
hexmask.long.byte 0x00 8.--15. 1. "PALLETE_G,Gamma ramp green bits"
newline
hexmask.long.byte 0x00 0.--7. 1. "PALLETE_B,Gamma ramp blue bits"
group.long 0x0C++0x03
line.long 0x00 "LCDC_RESXY_REG,Resolution X Y"
hexmask.long.word 0x00 16.--31. 1. "RES_X,Resolution X in pixels"
newline
hexmask.long.word 0x00 0.--15. 1. "RES_Y,Resolution Y in pixels"
group.long 0x24++0x03
line.long 0x00 "LCDC_STARTXY_REG,Specifies the start position of the very first frame"
hexmask.long.word 0x00 16.--31. 1. "START_X,Specify framess X dimension"
newline
hexmask.long.word 0x00 0.--15. 1. "START_Y,Specify framess Y dimension"
group.long 0xFC++0x03
line.long 0x00 "LCDC_STATUS_REG,Status Register"
rbitfld.long 0x00 15. "DBIB_CMD_FIFO_FULL,Indicates if the command FIFO is full" "0,1"
newline
rbitfld.long 0x00 14. "DBI_SPI_CS,Indicates DBI/SPI CS status" "0,1"
newline
rbitfld.long 0x00 13. "FRAME_END,Frame end (active high)" "0,1"
newline
rbitfld.long 0x00 12. "DBIB_OUT_TRANS_PENDING,Pending output transaction in DBI Type-B interface" "0,1"
newline
rbitfld.long 0x00 11. "DBIB_CMD_PENDING,Transferring of command in progress" "0: idle,1: in progress"
newline
rbitfld.long 0x00 10. "DBIB_DATA_PENDING,Pending RGB data in DBI Type-B interface" "0,1"
newline
rbitfld.long 0x00 8. "DBIB_TE,The DBIB tearing effect signal" "0,1"
newline
rbitfld.long 0x00 7. "STICKY_UNDERFLOW,Sticky underflow(clear with write in the LCDC_INTERRUPT_REG)" "0: There is no underflow,1: Underflow has been detected.Remains high until"
newline
rbitfld.long 0x00 6. "UNDERFLOW,Underflow on the current transfer" "0: There is no underflow,1: Underflow has been detected"
newline
rbitfld.long 0x00 5. "LAST_ROW,Last row (Last row is currently displayed)" "0,1"
newline
rbitfld.long 0x00 4. "STAT_CSYNC,CSYNC signal level" "0,1"
newline
rbitfld.long 0x00 3. "STAT_VSYNC,VSYNC signal level" "0,1"
newline
rbitfld.long 0x00 2. "STAT_HSYNC,HSYNC signal level" "0,1"
newline
rbitfld.long 0x00 1. "FRAMEGEN_BUSY,The frame generator is busy (active high)" "0,1"
newline
rbitfld.long 0x00 0. "STAT_ACTIVE,Active (When not in vertical blanking)" "0,1"
tree.end
tree "MEMCTRL"
base ad:0x50050000
group.long 0x78++0x03
line.long 0x00 "BUSY_RESET_REG,BSR Reset Register"
bitfld.long 0x00 30.--31. "BUSY_SDADC,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 28.--29. "BUSY_GPADC,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "BUSY_SRC2,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 24.--25. "BUSY_SRC,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "BUSY_PDM,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 20.--21. "BUSY_PCM,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "BUSY_I3C,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 16.--17. "BUSY_I2C3,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "BUSY_I2C2,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 12.--13. "BUSY_I2C,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "BUSY_SPI3,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 8.--9. "BUSY_SPI2,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "BUSY_SPI,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 4.--5. "BUSY_UART3,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "BUSY_UART2,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 0.--1. "BUSY_UART,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
group.long 0x7C++0x03
line.long 0x00 "BUSY_RESET_REG2,BSR2 Reset Register"
bitfld.long 0x00 10.--11. "BUSY_TIMER6,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 8.--9. "BUSY_TIMER5,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "BUSY_TIMER4,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 4.--5. "BUSY_TIMER3,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "BUSY_TIMER2,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
bitfld.long 0x00 0.--1. "BUSY_TIMER,Clear the BUSY bitfield by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register" "0,1,2,3"
group.long 0x70++0x03
line.long 0x00 "BUSY_SET_REG,BSR Set Register"
bitfld.long 0x00 30.--31. "BUSY_SDADC,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 28.--29. "BUSY_GPADC,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "BUSY_SRC2,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 24.--25. "BUSY_SRC,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "BUSY_PDM,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 20.--21. "BUSY_PCM,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "BUSY_I3C,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 16.--17. "BUSY_I2C3,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "BUSY_I2C2,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 12.--13. "BUSY_I2C,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "BUSY_SPI3,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 8.--9. "BUSY_SPI2,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "BUSY_SPI,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 4.--5. "BUSY_UART3,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "BUSY_UART2,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "BUSY_UART,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
group.long 0x74++0x03
line.long 0x00 "BUSY_SET_REG2,BSR2 Set Register"
bitfld.long 0x00 10.--11. "BUSY_TIMER6,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 8.--9. "BUSY_TIMER5,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "BUSY_TIMER4,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 4.--5. "BUSY_TIMER3,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "BUSY_TIMER2,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
bitfld.long 0x00 0.--1. "BUSY_TIMER,Writing a non-zero value to this field sets the corresponding BUSY bit but only if it was not claimed (BUSY=0)" "0,1,2,3"
group.long 0x80++0x03
line.long 0x00 "BUSY_STAT_REG,BSR Status Register"
rbitfld.long 0x00 30.--31. "BUSY_SDADC,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 28.--29. "BUSY_GPADC,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 26.--27. "BUSY_SRC2,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 24.--25. "BUSY_SRC,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 22.--23. "BUSY_PDM,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 20.--21. "BUSY_PCM,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 18.--19. "BUSY_I3C,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 16.--17. "BUSY_I2C3,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 14.--15. "BUSY_I2C2,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 12.--13. "BUSY_I2C,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 10.--11. "BUSY_SPI3,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 8.--9. "BUSY_SPI2,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 6.--7. "BUSY_SPI,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 4.--5. "BUSY_UART3,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 2.--3. "BUSY_UART2,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 0.--1. "BUSY_UART,A non-zero value indicates the resource is busy" "0,1,2,3"
group.long 0x84++0x03
line.long 0x00 "BUSY_STAT_REG2,BSR2 Status Register"
rbitfld.long 0x00 10.--11. "BUSY_TIMER6,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 8.--9. "BUSY_TIMER5,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 6.--7. "BUSY_TIMER4,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 4.--5. "BUSY_TIMER3,A non-zero value indicates the resource is busy" "0,1,2,3"
newline
rbitfld.long 0x00 2.--3. "BUSY_TIMER2,A non-zero value indicates the resource is busy" "0,1,2,3"
rbitfld.long 0x00 0.--1. "BUSY_TIMER,A non-zero value indicates the resource is busy" "0,1,2,3"
group.long 0x30++0x03
line.long 0x00 "CMAC_STATUS_REG,Memory Arbiter Status Register"
bitfld.long 0x00 13. "CMI_CLEAR_READY,Writing a '1' clears CMI_NOT_READY bit" "0,1"
rbitfld.long 0x00 12. "CMI_NOT_READY," "0,1"
newline
rbitfld.long 0x00 8.--11. "AHB_RFMON_WR_BUFF_CNT,The maximum number of arbiter clock cycles that an CPUC AHB access has been buffered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "AHB_SYS2CMAC_WR_BUFF_CNT,The maximum number of arbiter clock cycles that an CPUS_AHB access has been buffered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "AHB_RFMON_CLR_WR_BUFF,Writing a '1' clears AHB_CPUC_WR_BUFF_CNT" "0,1"
bitfld.long 0x00 2. "AHB_SYS2CMAC_CLR_WR_BUFF,Writing a '1' clears AHB_CPUS_WR_BUFF_CNT" "0,1"
newline
rbitfld.long 0x00 1. "AHB_RFMON_WRITE_BUFF," "0,1"
rbitfld.long 0x00 0. "AHB_SYS2CMAC_WRITE_BUFF," "0,1"
group.long 0x20++0x03
line.long 0x00 "CMI_CODE_BASE_REG,CMAC code Base Address Register"
abitfld.long 0x00 10.--19. "CMI_CODE_BASE_ADDR,Base address for CMAC code with steps of 1 kB" "0x001=1: 1 kB base address,0x010=16: 16 kB base address,0x100=256: 256 kB base address"
group.long 0x24++0x03
line.long 0x00 "CMI_DATA_BASE_REG,CMAC data Base Address Register"
abitfld.long 0x00 2.--19. "CMI_DATA_BASE_ADDR,Base address for CMAC data with steps of 4 bytes" "0x00001=1: 4 byte base address,0x00010=16: 64 byte base address,0x00100=256: 1 kB base address,0x01000=4096: 16 kB base address,0x10000=65536: 256 kB base address"
group.long 0x2C++0x03
line.long 0x00 "CMI_END_REG,CMAC end Address Register"
abitfld.long 0x00 10.--19. "CMI_END_ADDR,End address for CMAC code and data accesses with steps of 1 kB" "0x000=0: accesses up to 1kB are allowed,0x001=1: accesses up to 2kB are allowed,0x01F=31: accesses up to 32kB are allowed,0x1FF=511: accesses up to 512kB are allowed"
group.long 0x28++0x03
line.long 0x00 "CMI_SHARED_BASE_REG,CMAC shared data Base Address Register"
abitfld.long 0x00 10.--19. "CMI_SHARED_BASE_ADDR,Base address for CMAC shared data with steps of 1 kB" "0x001=1: 1 kB base address,0x010=16: 16 kB base address,0x100=256: 256 kB base address"
group.long 0x04++0x03
line.long 0x00 "MEM_PRIO_ARB1_4_REG,Priority Control Register for arbiter 1 2 3 and 4"
bitfld.long 0x00 28.--29. "ARB4_AHB_DMA_PRIO,Priority for the DMA AHB interface of arbiter 4" "0: low priority (default),1: mid priority 1x,?..."
bitfld.long 0x00 26.--27. "ARB4_AHB_CPUS_PRIO,Priority for the CPUS AHB interface of arbiter 4" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
newline
bitfld.long 0x00 20.--21. "ARB3_AHB_DMA_PRIO,Priority for the DMA AHB interface of arbiter 3" "0: low priority (default),1: mid priority 1x,?..."
bitfld.long 0x00 18.--19. "ARB3_AHB_CPUS_PRIO,Priority for the CPUS AHB interface of arbiter 3" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
newline
bitfld.long 0x00 16.--17. "ARB3_AHB_CPUC_PRIO,Priority for the CPUC AHB interface of arbiter 3" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
bitfld.long 0x00 14.--15. "ARB2_SNC_PRIO,Priority for the SNC interface of arbiter 2" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
newline
bitfld.long 0x00 12.--13. "ARB2_AHB_DMA_PRIO,Priority for the DMA AHB interface of arbiter 2" "0: low priority (default),1: mid priority 1x,?..."
bitfld.long 0x00 10.--11. "ARB2_AHB_CPUS_PRIO,Priority for the CPUS AHB interface of arbiter 2" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
newline
bitfld.long 0x00 8.--9. "ARB2_AHB_CPUC_PRIO,Priority for the CPUC AHB interface of arbiter 2" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
bitfld.long 0x00 6.--7. "ARB1_SNC_PRIO,Priority for the SNC interface of arbiter 1" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
newline
bitfld.long 0x00 4.--5. "ARB1_AHB_DMA_PRIO,Priority for the DMA AHB interface of arbiter 1" "0: low priority (default),1: mid priority 1x,?..."
bitfld.long 0x00 2.--3. "ARB1_AHB_CPUS_PRIO,Priority for the CPUS AHB interface of arbiter 1" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
newline
bitfld.long 0x00 0.--1. "ARB1_AHB_CPUC_PRIO,Priority for the CPUC AHB interface of arbiter 1" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
group.long 0x08++0x03
line.long 0x00 "MEM_PRIO_ARB5_8_REG,Priority Control Register for arbiter 5 6 7 and 8"
bitfld.long 0x00 30.--31. "ARB8_SNC_PRIO,Priority for the SNC interface of arbiter 8" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
bitfld.long 0x00 28.--29. "ARB8_AHB_DMA_PRIO,Priority for the DMA AHB interface of arbiter 8" "0: low priority (default),1: mid priority 1x,?..."
newline
bitfld.long 0x00 26.--27. "ARB8_AHB_CPUS_PRIO,Priority for the CPUS AHB interface of arbiter 8" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
bitfld.long 0x00 20.--21. "ARB7_AHB_DMA_PRIO,Priority for the DMA AHB interface of arbiter 7" "0: low priority (default),1: mid priority 1x,?..."
newline
bitfld.long 0x00 18.--19. "ARB7_AHB_CPUS_PRIO,Priority for the CPUS AHB interface of arbiter 7" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
bitfld.long 0x00 12.--13. "ARB6_AHB_DMA_PRIO,Priority for the DMA AHB interface of arbiter 6" "0: low priority (default),1: mid priority 1x,?..."
newline
bitfld.long 0x00 10.--11. "ARB6_AHB_CPUS_PRIO,Priority for the CPUS AHB interface of arbiter 6" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
bitfld.long 0x00 4.--5. "ARB5_AHB_DMA_PRIO,Priority for the DMA AHB interface of arbiter 5" "0: low priority (default),1: mid priority 1x,?..."
newline
bitfld.long 0x00 2.--3. "ARB5_AHB_CPUS_PRIO,Priority for the CPUS AHB interface of arbiter 5" "0: low priority (default),1: mid priority,2: high priority,3: top priority"
group.long 0x10++0x03
line.long 0x00 "MEM_STALL_REG,Maximum Stall cycles Control Register"
bitfld.long 0x00 12.--15. "SNC_MAX_STALL,Maximum allowed number of stall cycles for the SNC interface" "0: don't use not feasible and can block other,1: max 1 stall cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15: max 15 stall cycles"
bitfld.long 0x00 8.--11. "AHB_DMA_MAX_STALL,Maximum allowed number of stall cycles for the DMA AHB interface" "0: don't use not feasible and can block other,1: max 1 stall cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15: max 15 stall cycles"
newline
bitfld.long 0x00 4.--7. "AHB_CPUS_MAX_STALL,Maximum allowed number of stall cycles for the CPUS AHB interface" "0: don't use not feasible and can block other,1: max 1 stall cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15: max 15 stall cycles"
bitfld.long 0x00 0.--3. "AHB_CPUC_MAX_STALL,Maximum allowed number of stall cycles for the CPUC AHB interface" "0: don't use not feasible and can block other,1: max 1 stall cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15: max 15 stall cycles"
group.long 0x18++0x03
line.long 0x00 "MEM_STATUS2_REG,RAM cells Status Register"
bitfld.long 0x00 13. "RAM13_OFF_BUT_ACCESS,Reading a '1' indicates RAM13 was off but still access was performed" "0,1"
bitfld.long 0x00 12. "RAM12_OFF_BUT_ACCESS,Reading a '1' indicates RAM12 was off but still access was performed" "0,1"
newline
bitfld.long 0x00 11. "RAM11_OFF_BUT_ACCESS,Reading a '1' indicates RAM11 was off but still access was performed" "0,1"
bitfld.long 0x00 10. "RAM10_OFF_BUT_ACCESS,Reading a '1' indicates RAM10 was off but still access was performed" "0,1"
newline
bitfld.long 0x00 9. "RAM9_OFF_BUT_ACCESS,Reading a '1' indicates RAM9 was off but still access was performed" "0,1"
bitfld.long 0x00 8. "RAM8_OFF_BUT_ACCESS,Reading a '1' indicates RAM8 was off but still access was performed" "0,1"
newline
bitfld.long 0x00 7. "RAM7_OFF_BUT_ACCESS,Reading a '1' indicates RAM7 was off but still access was performed" "0,1"
bitfld.long 0x00 6. "RAM6_OFF_BUT_ACCESS,Reading a '1' indicates RAM6 was off but still access was performed" "0,1"
newline
bitfld.long 0x00 5. "RAM5_OFF_BUT_ACCESS,Reading a '1' indicates RAM5 was off but still access was performed" "0,1"
bitfld.long 0x00 4. "RAM4_OFF_BUT_ACCESS,Reading a '1' indicates RAM4 was off but still access was performed" "0,1"
newline
bitfld.long 0x00 3. "RAM3_OFF_BUT_ACCESS,Reading a '1' indicates RAM3 was off but still access was performed" "0,1"
bitfld.long 0x00 2. "RAM2_OFF_BUT_ACCESS,Reading a '1' indicates RAM2 was off but still access was performed" "0,1"
newline
bitfld.long 0x00 1. "RAM1_OFF_BUT_ACCESS,Reading a '1' indicates RAM1 was off but still access was performed" "0,1"
bitfld.long 0x00 0. "RAM0_OFF_BUT_ACCESS,Reading a '1' indicates RAM0 was off but still access was performed" "0,1"
group.long 0x14++0x03
line.long 0x00 "MEM_STATUS_REG,Memory Arbiter Status Register"
rbitfld.long 0x00 20.--23. "AHB_SNC_WR_BUFF_CNT,The maximum number of arbiter clock cycles that an SNC AHB access has been buffered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 16.--19. "AHB_DMA_WR_BUFF_CNT,The maximum number of arbiter clock cycles that an DMA AHB access has been buffered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 12.--15. "AHB_CPUC_WR_BUFF_CNT,The maximum number of arbiter clock cycles that an CPUC AHB access has been buffered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 8.--11. "AHB_CPUS_WR_BUFF_CNT,The maximum number of arbiter clock cycles that an CPUS_AHB access has been buffered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "AHB_SNC_CLR_WR_BUFF,Writing a '1' clears AHB_SNC_WR_BUFF_CNT" "0,1"
bitfld.long 0x00 6. "AHB_DMA_CLR_WR_BUFF,Writing a '1' clears AHB_DMA_WR_BUFF_CNT" "0,1"
newline
bitfld.long 0x00 5. "AHB_CPUC_CLR_WR_BUFF,Writing a '1' clears AHB_CPUC_WR_BUFF_CNT" "0,1"
bitfld.long 0x00 4. "AHB_CPUS_CLR_WR_BUFF,Writing a '1' clears AHB_CPUS_WR_BUFF_CNT" "0,1"
newline
rbitfld.long 0x00 3. "AHB_SNC_WRITE_BUFF," "0,1"
rbitfld.long 0x00 2. "AHB_DMA_WRITE_BUFF," "0,1"
newline
rbitfld.long 0x00 1. "AHB_CPUC_WRITE_BUFF," "0,1"
rbitfld.long 0x00 0. "AHB_CPUS_WRITE_BUFF," "0,1"
tree.end
tree "OQSPIF"
base ad:0x36000000
group.long 0x34++0x03
line.long 0x00 "OQSPIF_BURSTBRK_REG,Read break sequence in Auto mode"
bitfld.long 0x00 23. "OSPIC_BRK_EN,Controls the application of a special command (read burst break sequence) that is used in order to force the device to abandon the continuous read mode" "0: The special command is not applied,1: the previous command that has been applied in"
newline
bitfld.long 0x00 22. "OSPIC_SEC_HF_DS,Disable output during the transmission of the second half (OSPIC_BRK_WRD[3:0])" "0: The controller drives the OSPI bus during the,1: The controller leaves the OSPI bus in Hi-Z"
newline
bitfld.long 0x00 20.--21. "OSPIC_BRK_TX_MD,The mode of the OSPI Bus during the transmission of the burst break sequence" "0: Single,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 16.--19. "OSPIC_BRK_SZ,The size of Burst Break Sequence" "0: One byte (Send OSPIC_BRK_WRD[15:8]),1: Two bytes (Send OSPIC_BRK_WRD[15:0]) 2-15,?..."
newline
hexmask.long.word 0x00 0.--15. 1. "OSPIC_BRK_WRD,This is the value of a special command (read burst break sequence) that is applied by the controller to the external memory device in order to force the memory device to abandon the continuous read mode"
group.long 0x0C++0x03
line.long 0x00 "OQSPIF_BURSTCMDA_REG,The way of reading in Auto mode (command register A)"
bitfld.long 0x00 30.--31. "OSPIC_DMY_TX_MD,It describes the mode of the SPI bus during the Dummy bytes phase" "0: Single SPI,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 28.--29. "OSPIC_EXT_TX_MD,It describes the mode of the SPI bus during the Extra Byte phase" "0: Single SPI,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 26.--27. "OSPIC_ADR_TX_MD,It describes the mode of the SPI bus during the address phase" "0: Single SPI,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 24.--25. "OSPIC_INST_TX_MD,It describes the mode of the SPI bus during the instruction phase" "0: Single SPI,1: Dual,2: Quad,3: Octal"
newline
hexmask.long.byte 0x00 16.--23. 1. "OSPIC_EXT_BYTE,The value of an extra byte which will be transferred after address (only if OSPIC_EXT_BYTE_EN= 1)"
newline
hexmask.long.byte 0x00 8.--15. 1. "OSPIC_INST_WB,Instruction Value for Wrapping Burst"
newline
hexmask.long.byte 0x00 0.--7. 1. "OSPIC_INST,Instruction Value for Incremental Burst or Single read access"
group.long 0x10++0x03
line.long 0x00 "OQSPIF_BURSTCMDB_REG,The way of reading in Auto mode (command register B)"
bitfld.long 0x00 16.--18. "OSPIC_CS_HIGH_MIN,Between the transmissions of two different instructions to the flash memory the SPI bus stays in idle state (OSPI_CS high) for at least this number of OSPI_SCK clock cycles" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--15. "OSPIC_WRAP_SIZE,It describes the selected data size of a wrapping burst (OSPIC_WRAP_MD)" "0: byte access (8-bits),1: half word access (16 bits),2: word access (32-bits),3: Reserved"
newline
bitfld.long 0x00 12.--13. "OSPIC_WRAP_LEN,It describes the selected length of a wrapping burst (OSPIC_WRAP_MD)" "0: 4 beat wrapping burst,1: 8 beat wrapping burst,2: 16 beat wrapping burst,3: Reserved"
newline
bitfld.long 0x00 11. "OSPIC_WRAP_MD,Wrap mode" "0: The OSPIC_INST is the selected instruction at,1: The OSPIC_INST_WB is the selected instruction.."
newline
bitfld.long 0x00 10. "OSPIC_INST_MD,Instruction mode" "0: Transmit instruction at any burst access,1: Transmit instruction only in the first access"
newline
bitfld.long 0x00 9. "OSPIC_DMY_EN,Dummy bytes enable" "0: Don't send the dummy bytes,1: Send the dummy bytes"
newline
bitfld.long 0x00 4.--8. "OSPIC_DMY_NUM,Number of dummy bytes (minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 3. "OSPIC_EXT_HF_DS,Extra half disable output" "0: if OSPIC_EXT_BYTE_EN=1 is transmitted the,1: if OSPIC_EXT_BYTE_EN=1 the output is disabled"
newline
bitfld.long 0x00 2. "OSPIC_EXT_BYTE_EN,Extra byte enable" "0: Don't send the OSPIC_EXT_BYTE,1: Send the OSPIC_EXT_BYTE"
newline
bitfld.long 0x00 0.--1. "OSPIC_DAT_RX_MD,It describes the mode of the SPI bus during the data phase" "0: Single SPI,1: Dual,2: Quad,3: Octal"
group.long 0x3C++0x03
line.long 0x00 "OQSPIF_CHCKERASE_REG,Check erase progress in Auto mode"
hexmask.long 0x00 0.--31. 1. "OSPIC_CHCKERASE,Writing any value to this register during erasing forces the controller to read the flash memory status register"
group.long 0x00++0x03
line.long 0x00 "OQSPIF_CTRLBUS_REG,SPI Bus control register for the Manual mode"
bitfld.long 0x00 5. "OSPIC_DIS_CS,Write 1 to disable the chip select (active low) when the controller is in Manual mode" "0,1"
newline
bitfld.long 0x00 4. "OSPIC_EN_CS,Write 1 to enable the chip select (active low) when the controller is in Manual mode" "0,1"
newline
bitfld.long 0x00 3. "OSPIC_SET_OCTAL,Write 1 to set the bus mode in Octal mode when the controller is in Manual mode" "0,1"
newline
bitfld.long 0x00 2. "OSPIC_SET_QUAD,Write 1 to set the bus mode in Quad mode when the controller is in Manual mode" "0,1"
newline
bitfld.long 0x00 1. "OSPIC_SET_DUAL,Write 1 to set the bus mode in Dual mode when the controller is in Manual mode" "0,1"
newline
bitfld.long 0x00 0. "OSPIC_SET_SINGLE,Write 1 to set the bus mode in Single SPI mode when the controller is in Manual mode" "0,1"
group.long 0x04++0x03
line.long 0x00 "OQSPIF_CTRLMODE_REG,Mode Control register"
bitfld.long 0x00 28.--31. "OSPIC_IO_UH_DAT,The value of OSPI_IO4-7 pads if OSPI_IO_UH_OEN is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 27. "OSPIC_IO_UH_OEN,Forces the output enable for the upper half of the OSPI bus (OSPI_IO4-7)" "0: The OSPI_IO4-7 pad direction is decided by the,1: The OSPI_IO4-7 pad are outputs"
newline
bitfld.long 0x00 18. "OSPIC_INC_LIM_EN,This bit has meaning only for the read in auto mode and only when the read access in the AHB bus is an incremental bust of unspecified length" "0: The length of the burst is considered as,1: The length of the burst is considered as equal"
newline
bitfld.long 0x00 17. "OSPIC_RD_ERR_EN,Controls the generation of AHB bus error response when a read is performed in the address space where the flash device is mapped and the Auto mode is not enabled" "0: The controller ignores the access,1: The controller responds with an AHB error.."
newline
bitfld.long 0x00 16. "OSPIC_MAN_DIRCHG_MD,Selection of the direction change method in manual mode" "0: the bus direction goes to input after each..,1: the bus direction goes to input only after a"
newline
bitfld.long 0x00 15. "OSPIC_DMY_MD,Defines the clock cycle where the bus will turn in Hi-z during the transmission of dummy bytes" "0: the bus will become Hi-Z on the last clock,1: the bus will become Hi-Z on the last two clocks"
newline
bitfld.long 0x00 14. "OSPIC_CMD_X2_EN,Defines the number of bytes that consist the instruction code in the command sequences that produced by the OSPIC during Auto mode" "0: The instruction code is one byte only,1: The instruction code is two bytes"
newline
bitfld.long 0x00 13. "OSPIC_USE_32BA,Controls the length of the address that the external memory device uses" "0: The external memory device uses 24 bits address,1: The external memory device uses 32 bits address"
newline
bitfld.long 0x00 12. "OSPIC_BUF_LIM_EN,This bit has meaning only for the read in auto mode" "0: The access in the flash device is not..,1: The access in the flash device is terminated"
newline
bitfld.long 0x00 9.--11. "OSPIC_PCLK_MD,Read pipe clock delay relative to the falling edge of OSPI_SCK" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "OSPIC_RPIPE_EN,Controls the use of the data read pipe" "0: The read pipe is disabled the sampling clock is,1: The read pipe is enabled"
newline
bitfld.long 0x00 7. "OSPIC_RXD_NEG,Defines the clock edge that is used for the capturing of the received data when the read pipe is not active (OSPIC_RPIPE_EN = 0)" "0: Sampling of the received data with the positive,1: Sampling of the received data with the negative"
newline
bitfld.long 0x00 6. "OSPIC_HRDY_MD,This configuration bit is useful when the frequency of the OSPI clock is much lower than the clock of the AMBA bus in order to not locks the AMBA bus for a long time" "0: Adds wait states via hready signal when an,1: The controller don't adds wait states via the"
newline
bitfld.long 0x00 5. "OSPIC_IO3_DAT,The value of OSPI_IO3 pad if OSPI_IO3_OEN is 1" "0,1"
newline
bitfld.long 0x00 4. "OSPIC_IO2_DAT,The value of OSPI_IO2 pad if OSPI_IO2_OEN is 1" "0,1"
newline
bitfld.long 0x00 3. "OSPIC_IO3_OEN,Forces the output enable of the OSPI_IO3" "0: The OSPI_IO3 pad direction is decided by the,1: The OSPI_IO3 pad is output"
newline
bitfld.long 0x00 2. "OSPIC_IO2_OEN,Forces the output enable of the OSPI_IO2" "0: The OSPI_IO2 pad direction is decided by the,1: The OSPI_IO2 pad is output"
newline
bitfld.long 0x00 1. "OSPIC_CLK_MD,Mode of the generated OSPI_SCK clock" "0: Use Mode 0 for the OSPI_CLK,1: Use Mode 3 for the OSPI_CLK"
newline
bitfld.long 0x00 0. "OSPIC_AUTO_MD,Mode of operation" "0: The Manual Mode is selected,1: The Auto Mode is selected"
group.long 0x100++0x03
line.long 0x00 "OQSPIF_CTR_CTRL_REG,Control register for the decryption engine of the OSPIC"
bitfld.long 0x00 0. "OSPIC_CTR_EN,Controls the AES-CTR decryption feature of the OSPIC which enables the decryption (on-the-fly) of the data that are retrieved from the flash memory device" "0: The AES-CTR decryption is disabled,1: The controller will decrypt the content of the"
group.long 0x108++0x03
line.long 0x00 "OQSPIF_CTR_EADDR_REG,End address of the encrypted content in the OSPI flash"
hexmask.long.tbyte 0x00 10.--31. 1. "OSPIC_CTR_EADDR,Defines the bits [31:10] of the end address in the flash memory where an encrypted image is placed"
group.long 0x114++0x03
line.long 0x00 "OQSPIF_CTR_KEY_0_3_REG,Key bytes 0 to 3 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_KEY_0_3,Defines the key that is used by the AES-CTR algorithm when the on-the-fly decryption is enabled ( OSPIC_CTR_CTRL_REG[OSPIC_CTR_EN] = 1 )"
group.long 0x120++0x03
line.long 0x00 "OQSPIF_CTR_KEY_12_15_REG,Key bytes 12 to 15 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_KEY_12_15,See the description in the OSPIC_CTR_KEY_0_3"
group.long 0x124++0x03
line.long 0x00 "OQSPIF_CTR_KEY_16_19_REG,Key bytes 16 to 19 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_KEY_16_19,See the description in the OSPIC_CTR_KEY_0_3"
group.long 0x128++0x03
line.long 0x00 "OQSPIF_CTR_KEY_20_23_REG,Key bytes 20 to 23 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_KEY_20_23,See the description in the OSPIC_CTR_KEY_0_3"
group.long 0x12C++0x03
line.long 0x00 "OQSPIF_CTR_KEY_24_27_REG,Key bytes 24 to 27 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_KEY_24_27,See the description in the OSPIC_CTR_KEY_0_3"
group.long 0x130++0x03
line.long 0x00 "OQSPIF_CTR_KEY_28_31_REG,Key bytes 28 to 31 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_KEY_28_31,See the description in the OSPIC_CTR_KEY_0_3"
group.long 0x118++0x03
line.long 0x00 "OQSPIF_CTR_KEY_4_7_REG,Key bytes 4 to 7 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_KEY_4_7,See the description in the OSPIC_CTR_KEY_0_3"
group.long 0x11C++0x03
line.long 0x00 "OQSPIF_CTR_KEY_8_11_REG,Key bytes 8 to 11 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_KEY_8_11,See the description in the OSPIC_CTR_KEY_0_3"
group.long 0x10C++0x03
line.long 0x00 "OQSPIF_CTR_NONCE_0_3_REG,Nonce bytes 0 to 3 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_NONCE_0_3,Defines the 8 bytes of the nonce value (N0 - N7) that is used by the AES-CTR algorithm in order to be constructed the counter block (CTRB)"
group.long 0x110++0x03
line.long 0x00 "OQSPIF_CTR_NONCE_4_7_REG,Nonce bytes 4 to 7 for the AES-CTR algorithm"
hexmask.long 0x00 0.--31. 1. "OSPIC_CTR_NONCE_4_7,See the description in the OSPIC_NONCE_0_3"
group.long 0x104++0x03
line.long 0x00 "OQSPIF_CTR_SADDR_REG,Start address of the encrypted content in the OSPI flash"
hexmask.long.tbyte 0x00 10.--31. 1. "OSPIC_CTR_SADDR,Defines the bits [31:10] of the start address in the flash memory where an encrypted image is placed"
group.long 0x20++0x03
line.long 0x00 "OQSPIF_DUMMYDATA_REG,Send dummy clocks to SPI Bus for the Manual mode"
hexmask.long 0x00 0.--31. 1. "OSPIC_DUMMYDATA,Writing to this register generates a number of clock pulses to the SPI bus"
group.long 0x28++0x03
line.long 0x00 "OQSPIF_ERASECMDA_REG,The way of erasing in Auto mode (command register A)"
hexmask.long.byte 0x00 24.--31. 1. "OSPIC_RES_INST,The code value of the erase resume instruction"
newline
hexmask.long.byte 0x00 16.--23. 1. "OSPIC_SUS_INST,The code value of the erase suspend instruction"
newline
hexmask.long.byte 0x00 8.--15. 1. "OSPIC_WEN_INST,The code value of the write enable instruction"
newline
hexmask.long.byte 0x00 0.--7. 1. "OSPIC_ERS_INST,The code value of the erase instruction"
group.long 0x2C++0x03
line.long 0x00 "OQSPIF_ERASECMDB_REG,The way of erasing in Auto mode (command register B)"
hexmask.long.byte 0x00 24.--31. 1. "OSPIC_RESSUS_DLY,Defines a timer that counts the minimum allowed delay between an erase suspend command and the previous erase resume command (or the initial erase command)"
newline
bitfld.long 0x00 16.--19. "OSPIC_ERSRES_HLD,The controller must stay without flash memory reading requests for this number of AMBA hclk clock cycles before to perform the command of erase or erase resume" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--14. "OSPIC_ERS_CS_HI,After the execution of instructions: write enable erase erase suspend and erase resume the OSPI_CS remains high for at least this number of OSPI bus clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--9. "OSPIC_EAD_TX_MD,The mode of the OSPI Bus during the address phase of the erase instruction" "0: Single,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 6.--7. "OSPIC_RES_TX_MD,The mode of the OSPI Bus during the transmission of the resume instruction" "0: Single,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 4.--5. "OSPIC_SUS_TX_MD,The mode of the OSPI Bus during the transmission of the suspend instruction" "0: Single,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 2.--3. "OSPIC_WEN_TX_MD,The mode of the OSPI Bus during the transmission of the write enable instruction" "0: Single,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 0.--1. "OSPIC_ERS_TX_MD,The mode of the OSPI Bus during the instruction phase of the erase instruction" "0: Single,1: Dual,2: Quad,3: Octal"
group.long 0x30++0x03
line.long 0x00 "OQSPIF_ERASECMDC_REG,The way of erasing in Auto mode (command register C)"
bitfld.long 0x00 0.--5. "OSPIC_SUSSTS_DLY,Defines a timer that counts the minimum allowed delay between an erase suspend command and the next read status command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x24++0x03
line.long 0x00 "OQSPIF_ERASECTRL_REG,OSPI Erase control register"
bitfld.long 0x00 28. "OSPIC_ERS_RES_DIS,This configuration bit has meaning when an erase has been suspended" "0: A suspended erase will be resumed based on the,1: The erase will not be resumed even after the"
newline
rbitfld.long 0x00 25.--27. "OSPIC_ERS_STATE,It shows the progress of sector/block erasing (read only)" "0: No Erase,1: Pending erase request,2: Erase procedure is running,3: Suspended Erase procedure,4: Finishing the Erase procedure 0x5..0x7:..,?..."
newline
bitfld.long 0x00 24. "OSPIC_ERASE_EN,During Manual mode (OSPIC_AUTO_MD = 0)" "0,1"
newline
hexmask.long.tbyte 0x00 4.--23. 1. "OSPIC_ERS_ADDR,Defines the address of the block/sector that is requested to be erased"
group.long 0x40++0x03
line.long 0x00 "OQSPIF_GP_REG,OSPI General Purpose control register"
bitfld.long 0x00 3.--4. "OSPIC_PADS_SLEW,QSPI pads slew rate control" "0: Rise=1.7 V/ns Fall=1.9 V/ns (weak),1: Rise=2.0 V/ns Fall=2.3 V/ns,2: Rise=2.3 V/ns Fall=2.6 V/ns,3: Rise=2.4 V/ns Fall=2.7 V/ns (strong) Conditions"
newline
bitfld.long 0x00 1.--2. "OSPIC_PADS_DRV,QSPI pads drive current" "0: 4 mA,1: 8 mA,2: 12 mA,3: 16 mA"
group.long 0x1C++0x03
line.long 0x00 "OQSPIF_READDATA_REG,Read data from SPI Bus for the Manual mode"
hexmask.long 0x00 0.--31. 1. "OSPIC_READDATA,A read access at this register generates a data transfer from the external memory device to the OSPIC controller"
group.long 0x08++0x03
line.long 0x00 "OQSPIF_RECVDATA_REG,Received data for the Manual mode"
hexmask.long 0x00 0.--31. 1. "OSPIC_RECVDATA,This register contains the received data when the OSPIC_READDATA_REG register is used in Manual mode in order to be retrieved data from the external memory device and OSPIC_HRDY_MD=1 && OSPIC_BUSY=0"
group.long 0x38++0x03
line.long 0x00 "OQSPIF_STATUSCMD_REG,The way of reading the status of external device in Auto mode"
bitfld.long 0x00 30. "OSPIC_RSTAT_DMY_ZERO,Defines the value of that is transferred on the OSPI bus during the phase of the dummy bytes" "0: The controller keeps the data in the bus,1: Forces the dummy bytes to get the zero value"
newline
bitfld.long 0x00 28.--29. "OSPIC_RSTAT_DMY_TX_MD,It describes the mode of the OSPI bus during the dummy bytes phase" "0: Single SPI,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 24.--27. "OSPIC_RSTAT_DMY_NUM,Number of dummy bytes (minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 23. "OSPIC_RSTAT_DMY_EN,Enables the transmission of dummy bytes immediately after the instruction code of the read status command" "0: Don't send the dummy bytes,1: Send the dummy bytes"
newline
bitfld.long 0x00 22. "OSPIC_STSDLY_SEL,Defines the timer which is used to count the delay that it has to wait before to read the FLASH Status Register after an erase or an erase resume command" "0: The delay is controlled by the OSPIC_RESSTS_DLY,1: The delay is controlled by the OSPIC_RESSUS_DLY"
newline
bitfld.long 0x00 16.--21. "OSPIC_RESSTS_DLY,Defines a timer that counts the minimum required delay between the reading of the status register and of the previous erase or erase resume instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15. "OSPIC_BUSY_VAL,Defines the value of the Busy bit which means that the flash is busy" "0: The flash is busy when the Busy bit is equal..,1: The flash is busy when the Busy bit is equal.."
newline
bitfld.long 0x00 12.--14. "OSPIC_BUSY_POS,It describes who from the bits of status represents the Busy bit (7 - 0)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--11. "OSPIC_RSTAT_RX_MD,The mode of the OSPI Bus during the receive status phase of the read status instruction" "0: Single,1: Dual,2: Quad,3: Octal"
newline
bitfld.long 0x00 8.--9. "OSPIC_RSTAT_TX_MD,The mode of the OSPI Bus during the instruction phase of the read status instruction" "0: Single,1: Dual,2: Quad,3: Octal"
newline
hexmask.long.byte 0x00 0.--7. 1. "OSPIC_RSTAT_INST,The code value of the read status instruction"
group.long 0x14++0x03
line.long 0x00 "OQSPIF_STATUS_REG,The status register of the OSPI controller"
rbitfld.long 0x00 0. "OSPIC_BUSY,The status of the SPI Bus" "0: The SPI Bus is idle,1: The SPI Bus is active"
group.long 0x18++0x03
line.long 0x00 "OQSPIF_WRITEDATA_REG,Write data to SPI Bus for the Manual mode"
hexmask.long 0x00 0.--31. 1. "OSPIC_WRITEDATA,Writing to this register is generating a data transfer from the controller to the external memory device"
tree.end
autoindent.off
newline
Reference in New Issue View Git Blame Copy Permalink