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Gen4_R-Car_Trace32/2_Trunk/perda14680.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: DA14680 On-Chip Peripherals
; @Props: Released
; @Author: PIW
; @Changelog: 2022-02-11 PIW
; @Manufacturer: Dialog Semiconductor
; @Doc: SVD generated based on: DA14680.svd
; @Core: Cortex-M0
; @Chip: DA14680
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perda14680.per 14332 2022-02-17 10:51:37Z kwisniewski $
config 16. 8.
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "NVIC (Cortex M0 NVIC registers)"
base ad:0xE000E100
group.long 0x00++0x03
line.long 0x00 "ISER,Interrupt set-enable register"
bitfld.long 0x00 31. "Rsvd__irq__n,Rsvd__irq__n (Reserved)" "0,1"
bitfld.long 0x00 30. "XTAL16RDY_IRQn,XTAL16RDY_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 29. "DCDC_IRQn,DCDC_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 28. "TRNG_IRQn,TRNG_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 27. "RF_DIAG_IRQn,RF_DIAG_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 26. "DMA_IRQn,DMA_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 25. "VBUS_IRQn,VBUS_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 24. "SRC_OUT_IRQn,SRC_OUT_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 23. "SRC_IN_IRQn,SRC_IN_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 22. "PCM_IRQn,PCM_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 21. "USB_IRQn,USB_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 20. "QUADEC_IRQn,QUADEC_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 19. "SWTIM1_IRQn,SWTIM1_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 18. "SWTIM0_IRQn,SWTIM0_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 17. "WKUP_GPIO_IRQn,WKUP_GPIO_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 16. "IRGEN_IRQn,IRGEN_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 15. "KEYBRD_IRQn,KEYBRD_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 14. "ADC_IRQn,ADC_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 13. "SPI2_IRQn,SPI2_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 12. "SPI_IRQn,SPI_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 11. "I2C2_IRQn,I2C2_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 10. "I2C_IRQn,I2C_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 9. "UART2_IRQn,UART2_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 8. "UART_IRQn,UART_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 7. "MRM_IRQn,MRM_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 6. "CRYPTO_IRQn,CRYPTO_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 5. "COEX_IRQn,COEX_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 4. "RFCAL_IRQn,RFCAL_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 3. "FTDF_GEN_IRQn,FTDF_GEN_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 2. "FTDF_WAKEUP_IRQn,FTDF_WAKEUP_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 1. "BLE_GEN_IRQn,BLE_GEN_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 0. "BLE_WAKEUP_LP_IRQn,BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit)" "0,1"
group.long 0x80++0x03
line.long 0x00 "ICER,Interrupt clear-enable register"
bitfld.long 0x00 31. "Rsvd__irq__n,Rsvd__irq__n (Reserved)" "0,1"
bitfld.long 0x00 30. "XTAL16RDY_IRQn,XTAL16RDY_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 29. "DCDC_IRQn,DCDC_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 28. "TRNG_IRQn,TRNG_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 27. "RF_DIAG_IRQn,RF_DIAG_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 26. "DMA_IRQn,DMA_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 25. "VBUS_IRQn,VBUS_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 24. "SRC_OUT_IRQn,SRC_OUT_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 23. "SRC_IN_IRQn,SRC_IN_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 22. "PCM_IRQn,PCM_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 21. "USB_IRQn,USB_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 20. "QUADEC_IRQn,QUADEC_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 19. "SWTIM1_IRQn,SWTIM1_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 18. "SWTIM0_IRQn,SWTIM0_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 17. "WKUP_GPIO_IRQn,WKUP_GPIO_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 16. "IRGEN_IRQn,IRGEN_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 15. "KEYBRD_IRQn,KEYBRD_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 14. "ADC_IRQn,ADC_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 13. "SPI2_IRQn,SPI2_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 12. "SPI_IRQn,SPI_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 11. "I2C2_IRQn,I2C2_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 10. "I2C_IRQn,I2C_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 9. "UART2_IRQn,UART2_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 8. "UART_IRQn,UART_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 7. "MRM_IRQn,MRM_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 6. "CRYPTO_IRQn,CRYPTO_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 5. "COEX_IRQn,COEX_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 4. "RFCAL_IRQn,RFCAL_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 3. "FTDF_GEN_IRQn,FTDF_GEN_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 2. "FTDF_WAKEUP_IRQn,FTDF_WAKEUP_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 1. "BLE_GEN_IRQn,BLE_GEN_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 0. "BLE_WAKEUP_LP_IRQn,BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit)" "0,1"
group.long 0x100++0x03
line.long 0x00 "ISPR,Interrupt set-pending register"
bitfld.long 0x00 31. "Rsvd__irq__n,Rsvd__irq__n (Reserved)" "0,1"
bitfld.long 0x00 30. "XTAL16RDY_IRQn,XTAL16RDY_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 29. "DCDC_IRQn,DCDC_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 28. "TRNG_IRQn,TRNG_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 27. "RF_DIAG_IRQn,RF_DIAG_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 26. "DMA_IRQn,DMA_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 25. "VBUS_IRQn,VBUS_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 24. "SRC_OUT_IRQn,SRC_OUT_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 23. "SRC_IN_IRQn,SRC_IN_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 22. "PCM_IRQn,PCM_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 21. "USB_IRQn,USB_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 20. "QUADEC_IRQn,QUADEC_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 19. "SWTIM1_IRQn,SWTIM1_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 18. "SWTIM0_IRQn,SWTIM0_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 17. "WKUP_GPIO_IRQn,WKUP_GPIO_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 16. "IRGEN_IRQn,IRGEN_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 15. "KEYBRD_IRQn,KEYBRD_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 14. "ADC_IRQn,ADC_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 13. "SPI2_IRQn,SPI2_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 12. "SPI_IRQn,SPI_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 11. "I2C2_IRQn,I2C2_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 10. "I2C_IRQn,I2C_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 9. "UART2_IRQn,UART2_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 8. "UART_IRQn,UART_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 7. "MRM_IRQn,MRM_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 6. "CRYPTO_IRQn,CRYPTO_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 5. "COEX_IRQn,COEX_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 4. "RFCAL_IRQn,RFCAL_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 3. "FTDF_GEN_IRQn,FTDF_GEN_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 2. "FTDF_WAKEUP_IRQn,FTDF_WAKEUP_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 1. "BLE_GEN_IRQn,BLE_GEN_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 0. "BLE_WAKEUP_LP_IRQn,BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit)" "0,1"
group.long 0x180++0x03
line.long 0x00 "ICPR,Interrupt clear-pending register"
bitfld.long 0x00 31. "Rsvd__irq__n,Rsvd__irq__n (Reserved)" "0,1"
bitfld.long 0x00 30. "XTAL16RDY_IRQn,XTAL16RDY_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 29. "DCDC_IRQn,DCDC_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 28. "TRNG_IRQn,TRNG_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 27. "RF_DIAG_IRQn,RF_DIAG_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 26. "DMA_IRQn,DMA_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 25. "VBUS_IRQn,VBUS_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 24. "SRC_OUT_IRQn,SRC_OUT_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 23. "SRC_IN_IRQn,SRC_IN_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 22. "PCM_IRQn,PCM_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 21. "USB_IRQn,USB_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 20. "QUADEC_IRQn,QUADEC_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 19. "SWTIM1_IRQn,SWTIM1_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 18. "SWTIM0_IRQn,SWTIM0_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 17. "WKUP_GPIO_IRQn,WKUP_GPIO_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 16. "IRGEN_IRQn,IRGEN_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 15. "KEYBRD_IRQn,KEYBRD_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 14. "ADC_IRQn,ADC_IRQn (Interrupt clear-pending bit)" "0,1"
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bitfld.long 0x00 13. "SPI2_IRQn,SPI2_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 12. "SPI_IRQn,SPI_IRQn (Interrupt clear-pending bit)" "0,1"
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bitfld.long 0x00 11. "I2C2_IRQn,I2C2_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 10. "I2C_IRQn,I2C_IRQn (Interrupt clear-pending bit)" "0,1"
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bitfld.long 0x00 9. "UART2_IRQn,UART2_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 8. "UART_IRQn,UART_IRQn (Interrupt clear-pending bit)" "0,1"
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bitfld.long 0x00 7. "MRM_IRQn,MRM_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 6. "CRYPTO_IRQn,CRYPTO_IRQn (Interrupt clear-pending bit)" "0,1"
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bitfld.long 0x00 5. "COEX_IRQn,COEX_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 4. "RFCAL_IRQn,RFCAL_IRQn (Interrupt clear-pending bit)" "0,1"
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bitfld.long 0x00 3. "FTDF_GEN_IRQn,FTDF_GEN_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 2. "FTDF_WAKEUP_IRQn,FTDF_WAKEUP_IRQn (Interrupt clear-pending bit)" "0,1"
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bitfld.long 0x00 1. "BLE_GEN_IRQn,BLE_GEN_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 0. "BLE_WAKEUP_LP_IRQn,BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit)" "0,1"
group.long 0x300++0x03
line.long 0x00 "IPR0,Interrupt priority register 0"
hexmask.long.byte 0x00 24.--31. 1. "FTDF_GEN_IRQn_prio,FTDF_GEN_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "FTDF_WAKEUP_IRQn_prio,FTDF_WAKEUP_IRQn[7:0] bits (Interrupt priority)"
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hexmask.long.byte 0x00 8.--15. 1. "BLE_GEN_IRQn_prio,BLE_GEN_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "BLE_WAKEUP_LP_IRQn_prio,BLE_WAKEUP_LP_IRQn[7:0] bits (Interrupt priority)"
group.long 0x304++0x03
line.long 0x00 "IPR1,Interrupt priority register 1"
hexmask.long.byte 0x00 24.--31. 1. "MRM_IRQn_prio,MRM_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "CRYPTO_IRQn_prio,CRYPTO_IRQn[7:0] bits (Interrupt priority)"
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hexmask.long.byte 0x00 8.--15. 1. "COEX_IRQn_prio,COEX_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "RFCAL_IRQn_prio,RFCAL_IRQn[7:0] bits (Interrupt priority)"
group.long 0x308++0x03
line.long 0x00 "IPR2,Interrupt priority register 2"
hexmask.long.byte 0x00 24.--31. 1. "I2C2_IRQn_prio,I2C2_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "I2C_IRQn_prio,I2C_IRQn[7:0] bits (Interrupt priority)"
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hexmask.long.byte 0x00 8.--15. 1. "UART2_IRQn_prio,UART2_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "UART_IRQn_prio,UART_IRQn[7:0] bits (Interrupt priority)"
group.long 0x30C++0x03
line.long 0x00 "IPR3,Interrupt priority register 3"
hexmask.long.byte 0x00 24.--31. 1. "KEYBRD_IRQn_prio,KEYBRD_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "ADC_IRQn_prio,ADC_IRQn[7:0] bits (Interrupt priority)"
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hexmask.long.byte 0x00 8.--15. 1. "SPI2_IRQn_prio,SPI2_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "SPI_IRQn_prio,SPI_IRQn[7:0] bits (Interrupt priority)"
group.long 0x310++0x03
line.long 0x00 "IPR4,Interrupt priority register 4"
hexmask.long.byte 0x00 24.--31. 1. "SWTIM1_IRQn_prio,SWTIM1_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "SWTIM0_IRQn_prio,SWTIM0_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "WKUP_GPIO_IRQn_prio,WKUP_GPIO_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "IRGEN_IRQn_prio,IRGEN_IRQn[7:0] bits (Interrupt priority)"
group.long 0x314++0x03
line.long 0x00 "IPR5,Interrupt priority register 5"
hexmask.long.byte 0x00 24.--31. 1. "SRC_IN_IRQn_prio,SRC_IN_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "PCM_IRQn_prio,PCM_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "USB_IRQn_prio,USB_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "QUADEC_IRQn_prio,QUADEC_IRQn[7:0] bits (Interrupt priority)"
group.long 0x318++0x03
line.long 0x00 "IPR6,Interrupt priority register 6"
hexmask.long.byte 0x00 24.--31. 1. "RF_DIAG_IRQn_prio,RF_DIAG_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "DMA_IRQn_prio,DMA_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "VBUS_IRQn_prio,VBUS_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "SRC_OUT_IRQn_prio,SRC_OUT_IRQn[7:0] bits (Interrupt priority)"
group.long 0x31C++0x03
line.long 0x00 "IPR7,Interrupt priority register 7"
hexmask.long.byte 0x00 24.--31. 1. "RESERVED31_IRQn_DONT_USE,RESERVED31_IRQn[7:0] bits (Reserved)"
hexmask.long.byte 0x00 16.--23. 1. "XTAL16RDY_IRQn_prio,XTAL16RDY_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "DCDC_IRQn_prio,DCDC_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "TRNG_IRQn_prio,TRNG_IRQn[7:0] bits (Interrupt priority)"
tree.end
tree "PERIPHERAL_REGISTERS (AES_HASH registers)"
tree "AES_HASH"
base ad:0x40020000
group.long 0x18++0x03
line.long 0x00 "CRYPTO_CLRIRQ_REG,Crypto Clear interrupt request"
bitfld.long 0x00 0. "CRYPTO_CLRIRQ,Write 1 to clear a pending interrupt request" "0,1"
group.long 0x00++0x03
line.long 0x00 "CRYPTO_CTRL_REG,Crypto Control register"
bitfld.long 0x00 17. "CRYPTO_AES_KEXP,It forces (active high) the execution of the key expansion process with the starting of the AES encryption/decryption process" "0,1"
bitfld.long 0x00 16. "CRYPTO_MORE_IN," "0,1"
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bitfld.long 0x00 10.--15. "CRYPTO_HASH_OUT_LEN,The number of bytes minus one of the hash result which will be saved at the memory by the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 9. "CRYPTO_HASH_SEL,Selects the type of the algorithm" "0: The encryption algorithm (AES),1: A hash algorithm"
newline
bitfld.long 0x00 8. "CRYPTO_IRQ_EN,Interrupt Request Enable" "0: The interrupt generation ability is disabled,1: The interrupt generation ability is enabled"
bitfld.long 0x00 7. "CRYPTO_ENCDEC,Encryption/Decryption" "0: Decryption,1: Encryption"
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bitfld.long 0x00 5.--6. "CRYPTO_AES_KEY_SZ,The size of AES Key" "0,1,2,3"
bitfld.long 0x00 4. "CRYPTO_OUT_MD,Output Mode" "0: Write back to memory all the resulting data,1: Write back to memory only the final block of.."
newline
bitfld.long 0x00 2.--3. "CRYPTO_ALG_MD,It defines the mode of operation of the AES algorithm when the controller is configured for an encryption/decryption processing (CRYPTO_HASH_SEL = 0)" "0: HASH algorithms that are based on 32 bits,1: HASH algorithms that are based on 64 bits,2: Reserved,3: Reserved See also the CRYPTO_ALG field"
bitfld.long 0x00 0.--1. "CRYPTO_ALG,Algorithm selection" "0: SHA-384,1: SHA-512,2: SHA-512/224,3: SHA-512/256"
group.long 0x10++0x03
line.long 0x00 "CRYPTO_DEST_ADDR_REG,Crypto DMA destination memory"
hexmask.long 0x00 0.--31. 1. "CRYPTO_DEST_ADDR,Destination address at where the result of the processing is stored"
group.long 0x08++0x03
line.long 0x00 "CRYPTO_FETCH_ADDR_REG,Crypto DMA fetch register"
hexmask.long 0x00 0.--31. 1. "CRYPTO_FETCH_ADDR,The memory address from where will be retrieved the data that will be processed"
group.long 0x100++0x03
line.long 0x00 "CRYPTO_KEYS_START,Crypto First position of the AES keys storage memory"
hexmask.long 0x00 0.--31. 1. "CRYPTO_KEY_X,CRYPTO_KEY_(0-63) This is the AES keys storage memory"
group.long 0x0C++0x03
line.long 0x00 "CRYPTO_LEN_REG,Crypto Length of the input block in bytes"
hexmask.long.tbyte 0x00 0.--23. 1. "CRYPTO_LEN,It contains the number of bytes of input data"
group.long 0x1C++0x03
line.long 0x00 "CRYPTO_MREG0_REG,Crypto Mode depended register 0"
hexmask.long 0x00 0.--31. 1. "CRYPTO_MREG0,It contains information that are depended by the mode of operation when is used the AES algorithm: CBC - IV[31:0] CTR - CTRBLK[31:0]"
group.long 0x20++0x03
line.long 0x00 "CRYPTO_MREG1_REG,Crypto Mode depended register 1"
hexmask.long 0x00 0.--31. 1. "CRYPTO_MREG1,It contains information that are depended by the mode of operation when is used the AES algorithm: CBC - IV[63:32] CTR - CTRBLK[63:32] At any other mode the contents of this register has no meaning"
group.long 0x24++0x03
line.long 0x00 "CRYPTO_MREG2_REG,Crypto Mode depended register 2"
hexmask.long 0x00 0.--31. 1. "CRYPTO_MREG2,It contains information that are depended by the mode of operation when is used the AES algorithm: CBC - IV[95:64] CTR - CTRBLK[95:64] At any other mode the contents of this register has no meaning"
group.long 0x28++0x03
line.long 0x00 "CRYPTO_MREG3_REG,Crypto Mode depended register 3"
hexmask.long 0x00 0.--31. 1. "CRYPTO_MREG3,It contains information that are depended by the mode of operation when is used the AES algorithm: CBC - IV[127:96] CTR - CTRBLK[127:96] At any other mode the contents of this register has no meaning"
group.long 0x04++0x03
line.long 0x00 "CRYPTO_START_REG,Crypto Start calculation"
bitfld.long 0x00 0. "CRYPTO_START,Write 1 to initiate the processing of the input data" "0,1"
group.long 0x14++0x03
line.long 0x00 "CRYPTO_STATUS_REG,Crypto Status register"
rbitfld.long 0x00 2. "CRYPTO_IRQ_ST,The status of the interrupt request line of the CRYPTO block" "0: There is no active interrupt request,1: An interrupt request is pending"
rbitfld.long 0x00 1. "CRYPTO_WAIT_FOR_IN,Indicates the situation where the engine waits for more input data" "0: The crypto is not waiting for more input data,1: The crypto waits for more input data"
newline
rbitfld.long 0x00 0. "CRYPTO_INACTIVE," "0,1"
tree.end
tree "ANAMISC"
base ad:0x50001B00
group.word 0x08++0x01
line.word 0x00 "CHARGER_CTRL1_REG,Charger control register 1"
bitfld.word 0x00 14. "DIE_TEMP_DISABLE," "0,1"
bitfld.word 0x00 12.--13. "DIE_TEMP_SET,Die temperature protection level" "0: 0oC (do not use for test only),1: 50oC (do not use for test only),2: 80oC (default),3: 100oC"
newline
bitfld.word 0x00 8.--11. "CHARGE_CUR,Constant Current levels (typical values)" "0: 5 mA,1: 10 mA,2: 30 mA,3: 45 mA,4: 60 mA,5: 90 mA,6: 120 mA,7: 150 mA,8: 180 mA,9: 210 mA,10: 270 mA,11: 300 mA,12: 350 mA,13: 400 mA,?..."
bitfld.word 0x00 7. "NTC_LOW_DISABLE," "0,1"
newline
bitfld.word 0x00 6. "NTC_DISABLE," "0,1"
bitfld.word 0x00 5. "CHARGE_ON," "0,1"
newline
bitfld.word 0x00 0.--4. "CHARGE_LEVEL,Constant Voltage Levels" "0: 3.00V (reset),1: 3.40V (e.g. 2xNiMH),2: 3.50V,3: 3.60V (e.g,4: 3.74V,5: 3.86V,6: 4.00V,7: 4.05V,8: 4.10V,9: 4.15V,10: 4.20V (e.g. Li-Co,11: 4.25V,12: 4.30V,13: 4.35V,14: 4.40V,15: 4.50V,16: 4.60V,17: 4.90V e.g,18: 5.00V,?..."
group.word 0x0A++0x01
line.word 0x00 "CHARGER_CTRL2_REG,Charger control register 2"
bitfld.word 0x00 13.--15. "CHARGER_TEST,Signals are mapped on SPDIF pin" "0: normal mode (no test selected),1: Vptat (temperature sensor) [1.4V max],2: Vbat_sense after divider [1.2V],3: Current loop output [0 to vsupply],4: Voltage loop output [0 to vsupply],5: Imeas or Iref/10,6: Icharge reduced by 26.6,7: reserved"
bitfld.word 0x00 8.--12. "CURRENT_OFFSET_TRIM,do not change for test purpose only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 4.--7. "CHARGER_VFLOAT_ADJ,Independent adjustment for the charge level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CURRENT_GAIN_TRIM,do not change for test purpose only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x0C++0x01
line.word 0x00 "CHARGER_STATUS_REG,Charger status and trimming register"
rbitfld.word 0x00 6. "CHARGER_TMODE_PROT," "0,1"
rbitfld.word 0x00 5. "CHARGER_BATTEMP_HIGH," "0,1"
newline
rbitfld.word 0x00 4. "CHARGER_BATTEMP_OK," "0,1"
rbitfld.word 0x00 3. "CHARGER_BATTEMP_LOW," "0,1"
newline
rbitfld.word 0x00 2. "END_OF_CHARGE," "0,1"
rbitfld.word 0x00 1. "CHARGER_CV_MODE," "0,1"
newline
rbitfld.word 0x00 0. "CHARGER_CC_MODE," "0,1"
group.word 0x62++0x01
line.word 0x00 "CLK_REF_CNT_REG,Count value for oscillator calibration"
hexmask.word 0x00 0.--15. 1. "REF_CNT_VAL,Indicates the calibration time with a decrement counter to 1"
group.word 0x60++0x01
line.word 0x00 "CLK_REF_SEL_REG,Select clock for oscillator calibration"
bitfld.word 0x00 2. "REF_CAL_START,Writing a '1' starts a calibration" "0,1"
bitfld.word 0x00 0.--1. "REF_CLK_SEL,Select clock input for calibration" "0: RC32K oscillator,1: RC16M oscillator,2: XTAL32K oscillator,3: RCX oscillator"
group.word 0x66++0x01
line.word 0x00 "CLK_REF_VAL_H_REG,DIVN reference cycles upper 16 bits"
hexmask.word 0x00 0.--15. 1. "XTAL_CNT_VAL,Returns the upper 16 bits of DIVN clock cycles counted during the calibration time defined with REF_CNT_VAL"
group.word 0x64++0x01
line.word 0x00 "CLK_REF_VAL_L_REG,DIVN reference cycles lower 16 bits"
hexmask.word 0x00 0.--15. 1. "XTAL_CNT_VAL,Returns the lower 16 bits of DIVN clock cycles counted during the calibration time defined with REF_CNT_VAL"
group.word 0x46++0x01
line.word 0x00 "SOC_ADD2CH_REG,Fuel Gauge manually add extra charge to SOC_CHARGE_CNTRx_REG"
hexmask.word 0x00 0.--15. 1. "SOC_ADD2CH,Extra charge to be added to the SOC_CHARGE_CNTRx_REG per sample period (9-bit + sign + 6 fractional bits"
group.word 0x50++0x01
line.word 0x00 "SOC_CHARGE_AVG_REG,Fuel Gauge Average charge counter"
hexmask.word 0x00 0.--15. 1. "CHARGE_AVG,Average of 'charge' current (9-bit + sign and 6 fractional bits"
group.word 0x48++0x01
line.word 0x00 "SOC_CHARGE_CNTR1_REG,Fuel Gauge Charge counter bits 15-0"
hexmask.word 0x00 0.--15. 1. "CHARGE_CNT1,Sum of the charge-values per sampling period (bits15:0) The absolute full-scale charge value is 6-bits At full scale charge current it takes 2^26 sampling periods until overflow of the charge_cnt register after a reset_charge event"
group.word 0x4A++0x01
line.word 0x00 "SOC_CHARGE_CNTR2_REG,Fuel Gauge Charge counter bits 31-16"
hexmask.word 0x00 0.--15. 1. "CHARGE_CNT2,Sum of the charge-values per sampling period (bits23:16)"
group.word 0x4C++0x01
line.word 0x00 "SOC_CHARGE_CNTR3_REG,Fuel Gauge Charge counter bits 39-32"
hexmask.word.byte 0x00 0.--7. 1. "CHARGE_CNT3,Sum of the charge-values per sampling period (bits39:24)"
group.word 0x40++0x01
line.word 0x00 "SOC_CTRL1_REG,Fuel Gauge Control register 1"
bitfld.word 0x00 14.--15. "SOC_CINT,Integrator capacitor scaler" "0: Cint = 1 pF,1: Cint = 2 pF,2: Cint = 4 pF,3: Cint = 8 pF (=default)"
bitfld.word 0x00 12.--13. "SOC_BIAS,Current DAC scaler" "0: Ibias = 2 uA,1: Ibias = 1 uA (=default),2: Ibias = 0.5 uA,3: Ibias = 0.25 uA"
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bitfld.word 0x00 9.--11. "SOC_CLK,SOC Sample frequency" "0: automatic mode (tbd),1: fs = 18 kHz,2: fs = 36 kHz,3: fs = 72 kHz,4: fs = 144 kHz (=default),5: fs = 288 kHz,6: fs = 576 kHz,7: fs = 1152 kHz"
bitfld.word 0x00 8. "SOC_LPF," "0,1"
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bitfld.word 0x00 6.--7. "SOC_IDAC,Scales the current DAC (Ibias: default=1uA)" "0: Idac=0.25*Ibias,1: Idac=0.5*Ibias,2: Idac=Ibias (=default),3: Idac=2*Ibias"
bitfld.word 0x00 5. "SOC_SIGN,Defines the sign of the charge converter input and output to perform a chopper function to eliminate offset voltage (see also SOC_CHOP and 'sign' on output pin)" "0: non-inverted inputs and outputs,1: inverted inputs and outputs"
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bitfld.word 0x00 4. "SOC_GPIO,Reserved (not yet implemented): switches the SOC-inputs to the GPIO pins" "0,1"
bitfld.word 0x00 3. "SOC_MUTE," "0,1"
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bitfld.word 0x00 2. "SOC_RESET_AVG," "0,1"
bitfld.word 0x00 1. "SOC_RESET_CHARGE," "0,1"
newline
bitfld.word 0x00 0. "SOC_ENABLE," "0,1"
group.word 0x42++0x01
line.word 0x00 "SOC_CTRL2_REG,Fuel Gauge Control register 2"
bitfld.word 0x00 15. "SOC_DYNAVG,if HIGH then 'weight' of Moving Average is forced to 1 if the converter detects significant input change (if dcharge > 4*delta_c or high_limit or low_limit)" "0,1"
bitfld.word 0x00 12.--14. "SOC_MAW,Moving Average Weight factor charge_avg(n) = (weight*charge_avg(n-1) + charge(n) ) / (weight+1) where:weight = 2^(soc_maw)" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 11. "SOC_CMIREG_ENABLE,SOC_CMIREG enable" "0,1"
bitfld.word 0x00 8.--10. "SOC_CHOP,Chopping control" "0: 'external' chopping control with..,1: chop each 2^1*scycle fs-periods,2: chop each 2^2*scycle fs-periods,?,?,?,?,7: chop each 2^7*scycle fs-periods"
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bitfld.word 0x00 6.--7. "SOC_ICM,adds a common-mode current to Idac to increase the common-mode input-level of the integrator" "0: Icm=0,1: Icm=1*Ibias (=default),2: Icm=2*Ibias,3: Icm=4*Ibias"
bitfld.word 0x00 5. "SOC_DCYCLE,Cycle the current divider segments of Idac" "0: no cycling,1: cycle each scycle fs-periods"
newline
bitfld.word 0x00 2.--4. "SOC_SCYCLE,Cycle current segments (8 segments) of Idac" "0: no cycling,1: cycle each fs-period,2: cycle each 2 fs-periods,?,?,?,?,7: cycle each 7 fs-periods"
bitfld.word 0x00 0.--1. "SOC_RVI,Voltage-to-current resistor scaler" "0: Rvi = 25 k,1: Rvi = 50 k,2: Rvi = 100 k (= default),3: Rvi = 200 k"
group.word 0x44++0x01
line.word 0x00 "SOC_CTRL3_REG,Fuel Gauge Control register 3"
bitfld.word 0x00 4.--5. "SOC_VCMI,Common Input Voltage target of regulator (see SOC_CMIREG_ENABLE)" "0: 50 mV,1: 100 mV,2: 150 mV,3: 200 mV"
bitfld.word 0x00 3. "SOC_DYNHYS,Reserved" "0,1"
newline
bitfld.word 0x00 2. "SOC_DYNTARG,Reserved" "0: Vint_target = 0V,1: Vint_target tracks the 2 MSB's of the charge"
bitfld.word 0x00 0.--1. "SOC_VSAT,Trigger level of the high-limit and low-limit comparators" "0: low_limit = -50mV high_limit = +50mV,1: low_limit = -100mV high_limit = +100mV..,2: low_limit = -200mV high_limit = +200mV,3: low_limit = -400mV high_limit = +400mV"
group.word 0x54++0x01
line.word 0x00 "SOC_EXT_IN_REG,Fuel Gauge input test register"
bitfld.word 0x00 15. "SOC_EXT_IDAC_EN," "0,1"
bitfld.word 0x00 14. "SOC_EXT_SCYCLE_EN," "0,1"
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bitfld.word 0x00 11.--13. "SOC_NR_SCYCLE,Number of the scycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 10. "SOC_RDAC_DIS," "0,1"
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bitfld.word 0x00 9. "SOC_IDAC_SIGN," "0,1"
hexmask.word 0x00 0.--8. 1. "SOC_IDAC_VAL,Controls the current for the DAC"
group.word 0x56++0x01
line.word 0x00 "SOC_EXT_OUT_REG,Fuel Gauge output test register"
rbitfld.word 0x00 8. "SOC_CTRL_EVENT,Controller event" "0,1"
rbitfld.word 0x00 4.--7. "SOC_STATE,Controller state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.word 0x00 3. "SOC_RISING_COMP,Rising comparator output" "0,1"
rbitfld.word 0x00 2. "SOC_POS_COMP,Positive comparator output" "0,1"
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rbitfld.word 0x00 1. "SOC_LOWLIM_COMP,Low_limit comparator output" "0,1"
rbitfld.word 0x00 0. "SOC_HIGH_LIM,High_limit comparator output" "0,1"
group.word 0x52++0x01
line.word 0x00 "SOC_STATUS_REG,Fuel Gauge Status register"
rbitfld.word 0x00 1. "SOC_INT_LOCKED," "0,1"
rbitfld.word 0x00 0. "SOC_INT_OVERLOAD," "0,1"
tree.end
tree "APU"
base ad:0x50004000
group.long 0x1C++0x03
line.long 0x00 "APU_MUX_REG,APU mux register"
bitfld.long 0x00 6. "PDM1_MUX_IN,PDM1 input mux" "0: SRC1_MUX_IN,1: PDM input"
bitfld.long 0x00 3.--5. "PCM1_MUX_IN,PCM1 input mux" "0: off,1: SRC1 output,2: PCM output registers,?..."
newline
bitfld.long 0x00 0.--2. "SRC1_MUX_IN,SRC1 input mux" "0: off,1: PCM output,2: SRC1 input,?..."
group.long 0x34++0x03
line.long 0x00 "COEF0A_SET1_REG,SRC coefficient 10 set 1"
hexmask.long.word 0x00 0.--15. 1. "SRC_COEF10,coefficient 10"
group.long 0x20++0x03
line.long 0x00 "COEF10_SET1_REG,SRC coefficient 1 0 set 1"
hexmask.long.word 0x00 16.--31. 1. "SRC_COEF1,coefficient 1"
hexmask.long.word 0x00 0.--15. 1. "SRC_COEF0,coefficient 0"
group.long 0x24++0x03
line.long 0x00 "COEF32_SET1_REG,SRC coefficient 3 2 set 1"
hexmask.long.word 0x00 16.--31. 1. "SRC_COEF3,coefficient 3"
hexmask.long.word 0x00 0.--15. 1. "SRC_COEF2,coefficient 2"
group.long 0x28++0x03
line.long 0x00 "COEF54_SET1_REG,SRC coefficient 5 4 set 1"
hexmask.long.word 0x00 16.--31. 1. "SRC_COEF5,coefficient 5"
hexmask.long.word 0x00 0.--15. 1. "SRC_COEF4,coefficient 4"
group.long 0x2C++0x03
line.long 0x00 "COEF76_SET1_REG,SRC coefficient 7 6 set 1"
hexmask.long.word 0x00 16.--31. 1. "SRC_COEF7,coefficient 7"
hexmask.long.word 0x00 0.--15. 1. "SRC_COEF6,coefficient 6"
group.long 0x30++0x03
line.long 0x00 "COEF98_SET1_REG,SRC coefficient 9 8 set 1"
hexmask.long.word 0x00 16.--31. 1. "SRC_COEF9,coefficient 9"
hexmask.long.word 0x00 0.--15. 1. "SRC_COEF8,coefficient 8"
group.long 0x100++0x03
line.long 0x00 "PCM1_CTRL_REG,PCM1 Control register"
hexmask.long.word 0x00 20.--31. 1. "PCM_FSC_DIV,PCM Framesync divider Values 7-0xFFF"
bitfld.long 0x00 16. "PCM_FSC_EDGE," "0,1"
newline
bitfld.long 0x00 11.--15. "PCM_CH_DEL,Channel delay in multiples of 8 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "PCM_CLK_BIT," "0,1"
newline
bitfld.long 0x00 9. "PCM_FSCINV," "0,1"
bitfld.long 0x00 8. "PCM_CLKINV," "0,1"
newline
bitfld.long 0x00 7. "PCM_PPOD," "0,1"
bitfld.long 0x00 6. "PCM_FSCDEL," "0,1"
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bitfld.long 0x00 2.--5. "PCM_FSCLEN," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "PCM_MASTER," "0,1"
newline
bitfld.long 0x00 0. "PCM_EN," "0,1"
group.long 0x104++0x03
line.long 0x00 "PCM1_IN1_REG,PCM1 data in 1"
hexmask.long 0x00 0.--31. 1. "PCM_IN,PCM1_IN1 bits 31-0"
group.long 0x108++0x03
line.long 0x00 "PCM1_IN2_REG,PCM1 data in 2"
hexmask.long 0x00 0.--31. 1. "PCM_IN,PCM1_IN2 bits 31-0"
group.long 0x10C++0x03
line.long 0x00 "PCM1_OUT1_REG,PCM1 data out 1"
hexmask.long 0x00 0.--31. 1. "PCM_OUT,PCM1_OUT1 bits 31-0"
group.long 0x110++0x03
line.long 0x00 "PCM1_OUT2_REG,PCM1 data out 2"
hexmask.long 0x00 0.--31. 1. "PCM_OUT,PCM1_OUT2 bits 31-0"
group.long 0x00++0x03
line.long 0x00 "SRC1_CTRL_REG,SRC1 control register"
bitfld.long 0x00 28.--29. "SRC_PDM_MODE,PDM Output mode selection on PDM_DO1" "0: No output,1: Right channel (falling edge of PDM_CLK),2: Left channel (rising edge of PDM_CLK),3: Left and Right channel"
bitfld.long 0x00 25. "SRC_OUT_FLOWCLR,Writing a 1 clears the SRC1_OUT Overflow/underflow bits 23-22" "0,1"
newline
bitfld.long 0x00 24. "SRC_IN_FLOWCLR,Writing a 1 clears the SRC1_IN Overflow/underflow bits 21-20" "0,1"
rbitfld.long 0x00 23. "SRC_OUT_UNFLOW," "0,1"
newline
rbitfld.long 0x00 22. "SRC_OUT_OVFLOW," "0,1"
rbitfld.long 0x00 21. "SRC_IN_UNFLOW," "0,1"
newline
rbitfld.long 0x00 20. "SRC_IN_OVFLOW," "0,1"
rbitfld.long 0x00 18. "SRC_OUT_OK,SRC1_OUT Status" "0: acquisition in progress,1: acquisition ready (In manual mode this bit is"
newline
bitfld.long 0x00 16.--17. "SRC_OUT_US,SRC1_OUT UpSampling IIR filters setting" "0: for sample rates up-to 48kHz,1: for sample rates of 96kHz,2: reserved,3: for sample rates of 192kHz"
bitfld.long 0x00 14. "SRC_OUT_CAL_BYPASS,SRC1_OUT1 upsampiling filter bypass" "0: Do not bypass,1: Bypass filter"
newline
bitfld.long 0x00 13. "SRC_OUT_AMODE,SRC1_OUT1 Automatic Conversion mode" "0: Manual mode,1: Automatic mode"
bitfld.long 0x00 7. "SRC_DITHER_DISABLE,Dithering feature" "0: Enable,1: Disable"
newline
rbitfld.long 0x00 6. "SRC_IN_OK,SRC1_IN status" "0: Acquisition in progress,1: Acquisition ready"
bitfld.long 0x00 4.--5. "SRC_IN_DS,SRC1_IN UpSampling IIR filters setting" "0: for sample rates up-to 48kHz,1: for sample rates of 96kHz,2: reserved,3: for sample rates of 192kHz"
newline
bitfld.long 0x00 2. "SRC_IN_CAL_BYPASS,SRC1_IN upsampeling filter bypass" "0: Do not bypass,1: Bypass filter"
bitfld.long 0x00 1. "SRC_IN_AMODE,SRC1_IN Automatic conversion mode" "0: Manual mode,1: Automatic mode"
newline
bitfld.long 0x00 0. "SRC_EN,SRC1_IN and SRC1_OUT enable" "0: disabled,1: enabled"
group.long 0x0C++0x03
line.long 0x00 "SRC1_IN1_REG,SRC1 data in 1"
hexmask.long.tbyte 0x00 8.--31. 1. "SRC_IN,SRC1_IN1"
group.long 0x10++0x03
line.long 0x00 "SRC1_IN2_REG,SRC1 data in 2"
hexmask.long.tbyte 0x00 8.--31. 1. "SRC_IN,SRC1_IN2"
group.long 0x04++0x03
line.long 0x00 "SRC1_IN_FS_REG,SRC1 Sample input rate"
hexmask.long.tbyte 0x00 0.--23. 1. "SRC_IN_FS,SRC_IN Sample rate SRC_IN_FS = 8192*Sample_rate/100 Sample_rate upper limit is 192 kHz"
group.long 0x14++0x03
line.long 0x00 "SRC1_OUT1_REG,SRC1 data out 1"
hexmask.long.tbyte 0x00 8.--31. 1. "SRC_OUT,SRC1_OUT1"
group.long 0x18++0x03
line.long 0x00 "SRC1_OUT2_REG,SRC1 data out 2"
hexmask.long.tbyte 0x00 8.--31. 1. "SRC_OUT,SRC1_OUT2"
group.long 0x08++0x03
line.long 0x00 "SRC1_OUT_FS_REG,SRC1 Sample output rate"
hexmask.long.tbyte 0x00 0.--23. 1. "SRC_OUT_FS,SRC_OUT Sample rate SRC_OUT_FS = 8192*Sample_rate/100 Sample_rate upper limit is 192 kHz"
tree.end
tree "BLE"
base ad:0x40000000
group.long 0xA4++0x03
line.long 0x00 "BLE_ACTSCANSTAT_REG,Active scan register"
hexmask.long.word 0x00 16.--24. 1. "BACKOFF,Active scan mode back-off counter initialization value"
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hexmask.long.word 0x00 0.--8. 1. "UPPERLIMIT,Active scan mode upper limit counter value"
group.long 0x90++0x03
line.long 0x00 "BLE_ADVCHMAP_REG,Advertising Channel Map"
bitfld.long 0x00 0.--2. "ADVCHMAP,Advertising Channel Map defined as per the advertising connection settings" "0: Do not use data channel i+37,1: Use data channel i+37,?..."
group.long 0xA0++0x03
line.long 0x00 "BLE_ADVTIM_REG,Advertising Packet Interval"
hexmask.long.word 0x00 0.--13. 1. "ADVINT,Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent"
group.long 0xC0++0x03
line.long 0x00 "BLE_AESCNTL_REG,Start AES register"
bitfld.long 0x00 1. "AES_MODE," "0,1"
newline
bitfld.long 0x00 0. "AES_START,Writing a 1 starts AES-128 ciphering/deciphering process" "0,1"
group.long 0xD0++0x03
line.long 0x00 "BLE_AESKEY127_96_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. "AESKEY127_96,AES encryption 128-bit key"
group.long 0xC4++0x03
line.long 0x00 "BLE_AESKEY31_0_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. "AESKEY31_0,AES encryption 128-bit key"
group.long 0xC8++0x03
line.long 0x00 "BLE_AESKEY63_32_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. "AESKEY63_32,AES encryption 128-bit key"
group.long 0xCC++0x03
line.long 0x00 "BLE_AESKEY95_64_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. "AESKEY95_64,AES encryption 128-bit key"
group.long 0xD4++0x03
line.long 0x00 "BLE_AESPTR_REG,Pointer to the block to encrypt/decrypt"
hexmask.long.word 0x00 0.--15. 1. "AESPTR,Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored"
group.long 0x44++0x03
line.long 0x00 "BLE_BASETIMECNTCORR_REG,Base Time Counter"
hexmask.long 0x00 0.--26. 1. "BASETIMECNTCORR,Base Time Counter correction value"
group.long 0x1C++0x03
line.long 0x00 "BLE_BASETIMECNT_REG,Base time reference counter"
hexmask.long 0x00 0.--26. 1. "BASETIMECNT,Value of the 625us base time reference counter"
group.long 0x24++0x03
line.long 0x00 "BLE_BDADDRL_REG,BLE device address LSB register"
hexmask.long 0x00 0.--31. 1. "BDADDRL,Bluetooth Low Energy Device Address"
group.long 0x28++0x03
line.long 0x00 "BLE_BDADDRU_REG,BLE device address MSB register"
bitfld.long 0x00 16. "PRIV_NPUB,Bluetooth Low Energy Device Address privacy indicator" "0: Public Bluetooth Device Address,1: Private Bluetooth Device Address"
newline
hexmask.long.word 0x00 0.--15. 1. "BDADDRU,Bluetooth Low Energy Device Address"
group.long 0x108++0x03
line.long 0x00 "BLE_BLEMPRIO0_REG,Coexistence interface Priority 0 Register"
bitfld.long 0x00 28.--31. "BLEM7,Set Priority value for Passive Scanning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 24.--27. "BLEM6,Set Priority value for Non-Connectable Advertising" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "BLEM5,Set Priority value for Connectable Advertising BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "BLEM4,Set Priority value for Active Scanning BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "BLEM3,Set Priority value for Initiating (Scanning) BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "BLEM2,Set Priority value for Data Channel transmission BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "BLEM1,Set Priority value for LLCP BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "BLEM0,Set Priority value for Initiating (Connection Request Response) BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10C++0x03
line.long 0x00 "BLE_BLEMPRIO1_REG,Coexistence interface Priority 1 Register"
bitfld.long 0x00 28.--31. "BLEMDEFAULT,Set default priority value for other BLE message than those defined above" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x110++0x03
line.long 0x00 "BLE_BLEPRIOSCHARB_REG,Priority Scheduling Arbiter Control Register"
bitfld.long 0x00 15. "BLEPRIOMODE,Determine BLE Priority Scheduling Arbitration Mode" "0: BLE Decision instant not used,1: BLE Decision instant used"
newline
hexmask.long.byte 0x00 0.--7. 1. "BLEMARGIN,Determine the decision instant margin for Priority Scheduling Arbitration"
group.long 0x200++0x03
line.long 0x00 "BLE_CNTL2_REG,BLE Control Register 2"
bitfld.long 0x00 21. "BLE_RSSI_SEL," "0,1"
newline
bitfld.long 0x00 20. "WAKEUPLPSTAT,The status of the BLE_WAKEUP_LP_IRQ" "0,1"
newline
bitfld.long 0x00 19. "SW_RPL_SPI,Keep to 0" "0,1"
newline
bitfld.long 0x00 9.--14. "BLE_CLK_SEL,BLE Clock Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8. "RADIO_PWRDN_ALLOW,This active high signal indicates when it is allowed for the BLE core (embedded in the Radio sub-System power domain) to be powered down" "0,1"
newline
bitfld.long 0x00 7. "MON_LP_CLK,The SW can only write a 0 to this bit" "0,1"
newline
bitfld.long 0x00 6. "BLE_CLK_STAT," "0,1"
newline
bitfld.long 0x00 2. "EMACCERRMSK,Exchange Memory Access Error Mask: When cleared to 0 the EM_ACC_ERR will not cause an BLE_ERROR_IRQ interrupt" "0,1"
newline
bitfld.long 0x00 1. "EMACCERRACK,Exchange Memory Access Error Acknowledge" "0,1"
newline
bitfld.long 0x00 0. "EMACCERRSTAT,Exchange Memory Access Error Status: The bit is read-only and can be cleared only by writing a 1 at EMACCERRACK bitfield" "0,1"
group.long 0x100++0x03
line.long 0x00 "BLE_COEXIFCNTL0_REG,Coexistence interface Control 0 Register"
bitfld.long 0x00 20.--21. "WLCRXPRIOMODE,Defines Bluetooth Low Energy packet ble_rx mode behavior" "0: Rx indication excluding Rx Power up delay,1: Rx indication including Rx Power up delay,2: Rx High priority indicator,3: n/a"
newline
bitfld.long 0x00 16.--17. "WLCTXPRIOMODE,Defines Bluetooth Low Energy packet ble_tx mode behavior" "0: Tx indication excluding Tx Power up delay,1: Tx indication including Tx Power up delay,2: Tx High priority indicator,3: n/a"
newline
bitfld.long 0x00 6.--7. "WLANTXMSK,Determines how wlan_tx impact BLE Tx and Rx" "0: wlan_tx has no impact (default mode),1: wlan_tx can stop BLE Tx no impact on BLE Rx,2: wlan_tx can stop BLE Rx no impact on BLE Tx,3: wlan_tx can stop both BLE Tx and BLE Rx"
newline
bitfld.long 0x00 4.--5. "WLANRXMSK,Determines how wlan_rx impact BLE Tx and Rx" "0: wlan_rx has no impact,1: wlan_rx can stop BLE Tx no impact on BLE Rx,2: wlan_rx can stop BLE Rx no impact on BLE Tx,3: wlan_rx can stop both BLE Tx and BLE Rx"
newline
bitfld.long 0x00 1. "SYNCGEN_EN,Determines whether ble_sync is generated or not" "0: ble_sync pulse not generated,1: ble_sync pulse generated"
newline
bitfld.long 0x00 0. "COEX_EN,Enable / Disable control of the MWS/WLAN Coexistence control" "0: Coexistence interface disabled,1: Coexistence interface enabled"
group.long 0x104++0x03
line.long 0x00 "BLE_COEXIFCNTL1_REG,Coexistence interface Control 1 Register"
bitfld.long 0x00 24.--28. "WLCPRXTHR,Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines the threshold for Rx priority setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "WLCPTXTHR,Applies on ble_tx if WLCTXPRIOMODE equals 10 Determines the threshold for priority setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 8.--14. 1. "WLCPDURATION,Applies on ble_tx if WLCTXPRIOMODE equals 10 Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines how many s the priority information must be maintained Note that if WLCPDURATION = 0x00 then Tx/Rx priority levels are maintained till.."
newline
hexmask.long.byte 0x00 0.--6. 1. "WLCPDELAY,Applies on ble_tx if WLCTXPRIOMODE equals 10"
group.long 0x2C++0x03
line.long 0x00 "BLE_CURRENTRXDESCPTR_REG,Rx Descriptor Pointer for the Receive Buffer Chained List"
hexmask.long.word 0x00 16.--31. 1. "ETPTR,Exchange Table Pointer that determines the starting point of the Exchange Table"
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hexmask.long.word 0x00 0.--14. 1. "CURRENTRXDESCPTR,Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List"
group.long 0x58++0x03
line.long 0x00 "BLE_DEBUGADDMAX_REG,Upper limit for the memory zone"
hexmask.long.word 0x00 16.--31. 1. "REG_ADDMAX,Upper limit for the Register zone indicated by the reg_inzone flag"
newline
hexmask.long.word 0x00 0.--15. 1. "EM_ADDMAX,Upper limit for the Exchange Memory zone indicated by the em_inzone flag"
group.long 0x5C++0x03
line.long 0x00 "BLE_DEBUGADDMIN_REG,Lower limit for the memory zone"
hexmask.long.word 0x00 16.--31. 1. "REG_ADDMIN,Lower limit for the Register zone indicated by the reg_inzone flag"
newline
hexmask.long.word 0x00 0.--15. 1. "EM_ADDMIN,Lower limit for the Exchange Memory zone indicated by the em_inzone flag"
group.long 0x30++0x03
line.long 0x00 "BLE_DEEPSLCNTL_REG,Deep-Sleep control register"
bitfld.long 0x00 31. "EXTWKUPDSB,External Wake-Up disable" "0: RW-BLE Core can be woken by external wake-up,1: RW-BLE Core cannot be woken up by external.."
newline
rbitfld.long 0x00 15. "DEEP_SLEEP_STAT,Indicator of current Deep Sleep clock mux status" "0: RW-BLE Core is not yet in Deep Sleep Mode,1: RW-BLE Core is in Deep Sleep Mode (only"
newline
bitfld.long 0x00 4. "SOFT_WAKEUP_REQ,Wake Up Request from RW-BLE Software" "0,1"
newline
bitfld.long 0x00 3. "DEEP_SLEEP_CORR_EN,625us base time reference integer and fractional part correction" "0,1"
newline
bitfld.long 0x00 2. "DEEP_SLEEP_ON," "0,1"
newline
bitfld.long 0x00 0.--1. "DEEP_SLEEP_IRQ_EN,Always set to 3 when DEEP_SLEEP_ON is set to 1" "0,1,2,3"
group.long 0x38++0x03
line.long 0x00 "BLE_DEEPSLSTAT_REG,Duration of the last deep sleep phase register"
hexmask.long 0x00 0.--31. 1. "DEEPSLDUR,Actual duration of the last deep sleep phase measured in low_power_clk clock cycle"
group.long 0x34++0x03
line.long 0x00 "BLE_DEEPSLWKUP_REG,Time (measured in Low Power clock cycles) in Deep Sleep Mode before waking-up the device"
hexmask.long 0x00 0.--31. 1. "DEEPSLTIME,Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device"
group.long 0x20C++0x03
line.long 0x00 "BLE_DIAGCNTL2_REG,Debug use only"
bitfld.long 0x00 31. "DIAG7_EN," "0,1"
newline
bitfld.long 0x00 24.--29. "DIAG7,Only relevant when DIAG7_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 23. "DIAG6_EN," "0,1"
newline
bitfld.long 0x00 16.--21. "DIAG6,Only relevant when DIAG6_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15. "DIAG5_EN," "0,1"
newline
bitfld.long 0x00 8.--13. "DIAG5,Only relevant when DIAG5_EN= 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 7. "DIAG4_EN," "0,1"
newline
bitfld.long 0x00 0.--5. "DIAG4,Only relevant when DIAG4_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x210++0x03
line.long 0x00 "BLE_DIAGCNTL3_REG,Debug use only"
bitfld.long 0x00 31. "DIAG7_INV,If set then the specific diagnostic bit will be inverted" "0,1"
newline
bitfld.long 0x00 28.--30. "DIAG7_BIT,Selects which bit from the DIAG7 word will be forwarded to bit 7 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 27. "DIAG6_INV,If set then the specific diagnostic bit will be inverted" "0,1"
newline
bitfld.long 0x00 24.--26. "DIAG6_BIT,Selects which bit from the DIAG6 word will be forwarded to bit 6 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 23. "DIAG5_INV,If set then the specific diagnostic bit will be inverted" "0,1"
newline
bitfld.long 0x00 20.--22. "DIAG5_BIT,Selects which bit from the DIAG5 word will be forwarded to bit 5 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19. "DIAG4_INV,If set then the specific diagnostic bit will be inverted" "0,1"
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bitfld.long 0x00 16.--18. "DIAG4_BIT,Selects which bit from the DIAG4 word will be forwarded to bit 4 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "DIAG3_INV,If set then the specific diagnostic bit will be inverted" "0,1"
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bitfld.long 0x00 12.--14. "DIAG3_BIT,Selects which bit from the DIAG3 word will be forwarded to bit 3 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 11. "DIAG2_INV,If set then the specific diagnostic bit will be inverted" "0,1"
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bitfld.long 0x00 8.--10. "DIAG2_BIT,Selects which bit from the DIAG2 word will be forwarded to bit 2 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 7. "DIAG1_INV,If set then the specific diagnostic bit will be inverted" "0,1"
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bitfld.long 0x00 4.--6. "DIAG1_BIT,Selects which bit from the DIAG1 word will be forwarded to bit 1 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3. "DIAG0_INV,If set then the specific diagnostic bit will be inverted" "0,1"
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bitfld.long 0x00 0.--2. "DIAG0_BIT,Selects which bit from the DIAG0 word will be forwarded to bit 0 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
group.long 0x50++0x03
line.long 0x00 "BLE_DIAGCNTL_REG,Diagnostics Register"
bitfld.long 0x00 31. "DIAG3_EN," "0,1"
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bitfld.long 0x00 24.--29. "DIAG3,Only relevant when DIAG3_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 23. "DIAG2_EN," "0,1"
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bitfld.long 0x00 16.--21. "DIAG2,Only relevant when DIAG2_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "DIAG1_EN," "0,1"
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bitfld.long 0x00 8.--13. "DIAG1,Only relevant when DIAG1_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "DIAG0_EN," "0,1"
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bitfld.long 0x00 0.--5. "DIAG0,Only relevant when DIAG0_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x03
line.long 0x00 "BLE_DIAGSTAT_REG,Debug use only"
hexmask.long.byte 0x00 24.--31. 1. "DIAG3STAT,Directly connected to ble_dbg3[7:0] output"
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hexmask.long.byte 0x00 16.--23. 1. "DIAG2STAT,Directly connected to ble_dbg2[7:0] output"
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hexmask.long.byte 0x00 8.--15. 1. "DIAG1STAT,Directly connected to ble_dbg1[7:0] output"
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hexmask.long.byte 0x00 0.--7. 1. "DIAG0STAT,Directly connected to ble_dbg0[7:0] output"
group.long 0x208++0x03
line.long 0x00 "BLE_EM_BASE_REG,Exchange Memory Base Register"
hexmask.long.byte 0x00 10.--16. 1. "BLE_EM_BASE_16_10,The physical address on the system memory map of the base of the Exchange Memory"
group.long 0x3C++0x03
line.long 0x00 "BLE_ENBPRESET_REG,Time in low power oscillator cycles register"
hexmask.long.word 0x00 21.--31. 1. "TWEXT,Minimum and recommended value is TWIRQ_RESET + 1"
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hexmask.long.word 0x00 10.--20. 1. "TWIRQ_SET,Minimum value is TWIRQ_RESET + 1"
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hexmask.long.word 0x00 0.--9. 1. "TWIRQ_RESET,Recommended value is 1"
group.long 0x60++0x03
line.long 0x00 "BLE_ERRORTYPESTAT_REG,Error Type Status registers"
bitfld.long 0x00 17. "CONCEVTIRQ_ERROR,Indicates whether two consecutive and concurrent ble_event_irq have been generated and not acknowledged in time by the RW-BLE Software" "0: No error,1: Error occurred"
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rbitfld.long 0x00 16. "RXDATA_PTR_ERROR,Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure" "0: No error,1: Error occurred"
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rbitfld.long 0x00 15. "TXDATA_PTR_ERROR,Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning / Initiating events or during Master / Slave connections with non-null packet length: this is a major programming failure" "0: No error,1: Error occurred"
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rbitfld.long 0x00 14. "RXDESC_EMPTY_ERROR,Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure" "0: No error,1: Error occurred"
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rbitfld.long 0x00 13. "TXDESC_EMPTY_ERROR,Indicates whether Tx Descriptor pointer value programmed in Control Structure is null during Advertising / Scanning / Initiating events: this is a major programming failure" "0: No error,1: Error occurred"
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rbitfld.long 0x00 12. "CSFORMAT_ERROR,Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure" "0: No error,1: Error occurred"
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rbitfld.long 0x00 11. "LLCHMAP_ERROR,Indicates Link Layer Channel Map error happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process" "0: No error,1: Error occurred"
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rbitfld.long 0x00 10. "ADV_UNDERRUN,Indicates Advertising Interval Under run occurs if time between two consecutive Advertising packet (in Advertising mode) is lower than the expected value" "0: No error,1: Error occurred"
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rbitfld.long 0x00 9. "IFS_UNDERRUN,Indicates Inter Frame Space Under run occurs if IFS time is not enough to update and read Control Structure/Descriptors and/or White List parsing is not finished and/or Decryption time is too long to be finished on time" "0: No error,1: Error occurred"
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rbitfld.long 0x00 8. "WHITELIST_ERROR,Indicates White List Timeout error occurs if White List parsing is not finished on time" "0: No error,1: Error occurred"
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rbitfld.long 0x00 7. "EVT_CNTL_APFM_ERROR,Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed and when the first event is not completely finished while second pre-fetch instant is reached" "0: No error,1: Error occured"
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rbitfld.long 0x00 6. "EVT_SCHDL_APFM_ERROR,Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed and when the first event is not completely finished while second pre-fetch instant is reached" "0: No error,1: Error occured"
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rbitfld.long 0x00 5. "EVT_SCHDL_ENTRY_ERROR,Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset)" "0: No error,1: Error occurred"
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bitfld.long 0x00 4. "EVT_SCHDL_EMACC_ERROR,Indicates Event Scheduler Exchange Memory access error happens when Exchange Memory accesses are not served in time and blocks the Exchange Table entry" "0: No error,1: Error occurred"
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rbitfld.long 0x00 3. "RADIO_EMACC_ERROR,Indicates Radio Controller Exchange Memory access error happens when Exchange Memory accesses are not served in time and data are corrupted" "0: No error,1: Error occurred"
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rbitfld.long 0x00 2. "PKTCNTL_EMACC_ERROR,Indicates Packet Controller Exchange Memory access error happens when Exchange Memory accesses are not served in time and Tx/Rx data are corrupted" "0: No error,1: Error occurred"
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rbitfld.long 0x00 1. "RXCRYPT_ERROR,Indicates real time decryption error happens when AES-CCM decryption is too slow compared to Packet Controller requests" "0: No error,1: Error occurred"
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rbitfld.long 0x00 0. "TXCRYPT_ERROR,Indicates Real Time encryption error happens when AES-CCM encryption is too slow compared to Packet Controller requests" "0: No error,1: Error occurred"
group.long 0x40++0x03
line.long 0x00 "BLE_FINECNTCORR_REG,Phase correction value register"
hexmask.long.word 0x00 0.--9. 1. "FINECNTCORR,Phase correction value for the 625us reference counter (i.e. Fine Counter) in us"
group.long 0x20++0x03
line.long 0x00 "BLE_FINETIMECNT_REG,Fine time reference counter"
hexmask.long.word 0x00 0.--9. 1. "FINECNT,Value of the current s fine time reference counter"
group.long 0xF8++0x03
line.long 0x00 "BLE_FINETIMTGT_REG,Fine Timer Target value"
hexmask.long 0x00 0.--26. 1. "FINETARGET,Fine Timer Target value on which a ble_finetgtim_irq must be generated"
group.long 0xF4++0x03
line.long 0x00 "BLE_GROSSTIMTGT_REG,Gross Timer Target value"
hexmask.long.tbyte 0x00 0.--22. 1. "GROSSTARGET,Gross Timer Target value on which a ble_grosstgtim_irq must be generated"
group.long 0x18++0x03
line.long 0x00 "BLE_INTACK_REG,Interrupt acknowledge register"
bitfld.long 0x00 9. "SWINTACK,SW triggered interrupt acknowledgement bit Software writing 1 acknowledges the SW triggered interrupt" "0,1"
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bitfld.long 0x00 8. "EVENTAPFAINTACK,End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit Software writing 1 acknowledges the End of event / Anticipated Pre-Fetch Abort interrupt" "0,1"
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bitfld.long 0x00 7. "FINETGTIMINTACK,Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Fine Timer interrupt" "0,1"
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bitfld.long 0x00 6. "GROSSTGTIMINTACK,Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Gross Timer interrupt" "0,1"
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bitfld.long 0x00 5. "ERRORINTACK,Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt" "0,1"
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bitfld.long 0x00 4. "CRYPTINTACK,Encryption engine interrupt acknowledgement bit Software writing 1 acknowledges the Encryption engine interrupt" "0,1"
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bitfld.long 0x00 3. "EVENTINTACK,End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt" "0,1"
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bitfld.long 0x00 2. "SLPINTACK,End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt" "0,1"
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bitfld.long 0x00 1. "RXINTACK,Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt" "0,1"
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bitfld.long 0x00 0. "CSCNTINTACK,625us base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt" "0,1"
group.long 0x0C++0x03
line.long 0x00 "BLE_INTCNTL_REG,Interrupt controller register"
bitfld.long 0x00 15. "CSCNTDEVMSK,CSCNT interrupt mask during event" "0: CSCNT Interrupt not generated during events,1: CSCNT Interrupt generated during events"
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bitfld.long 0x00 9. "SWINTMSK,SW triggered interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 8. "EVENTAPFAINTMSK,End of event / anticipated pre-fetch abort interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 7. "FINETGTIMINTMSK,Fine Target Timer Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 6. "GROSSTGTIMINTMSK,Gross Target Timer Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 5. "ERRORINTMSK,Error Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 4. "CRYPTINTMSK,Encryption engine Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 3. "EVENTINTMSK,End of event Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 2. "SLPINTMSK,Sleep Mode Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 1. "RXINTMSK,Rx Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
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bitfld.long 0x00 0. "CSCNTINTMSK,625us Base Time Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
group.long 0x14++0x03
line.long 0x00 "BLE_INTRAWSTAT_REG,Interrupt raw status register"
rbitfld.long 0x00 9. "SWINTRAWSTAT,SW triggered interrupt raw status" "0: No SW triggered interrupt,1: A SW triggered interrupt is pending"
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rbitfld.long 0x00 8. "EVENTAPFAINTRAWSTAT,End of event / Anticipated Pre-Fetch Abort interrupt raw status" "0: No End of Event interrupt,1: An End of Event interrupt is pending"
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rbitfld.long 0x00 7. "FINETGTIMINTRAWSTAT,Fine Target Timer Error interrupt raw status" "0: No Fine Target Timer interrupt,1: A Fine Target Timer interrupt is pending"
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rbitfld.long 0x00 6. "GROSSTGTIMINTRAWSTAT,Gross Target Timer interrupt raw status" "0: No Gross Target Timer interrupt,1: A Gross Target Timer interrupt is pending"
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rbitfld.long 0x00 5. "ERRORINTRAWSTAT,Error interrupt raw status" "0: No Error interrupt,1: An Error interrupt is pending"
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rbitfld.long 0x00 4. "CRYPTINTRAWSTAT,Encryption engine interrupt raw status" "0: No Encryption / Decryption interrupt,1: An Encryption / Decryption interrupt is pending"
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rbitfld.long 0x00 3. "EVENTINTRAWSTAT,End of Event interrupt raw status" "0: No End of Advertising / Scanning / Connection,1: An End of Advertising / Scanning / Connection"
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rbitfld.long 0x00 2. "SLPINTRAWSTAT,Sleep interrupt raw status" "0: No End of Sleep Mode interrupt,1: An End of Sleep Mode interrupt is pending"
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rbitfld.long 0x00 1. "RXINTRAWSTAT,Packet Reception interrupt raw status" "0: No Rx interrupt,1: An Rx interrupt is pending"
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rbitfld.long 0x00 0. "CSCNTINTRAWSTAT,625us base time reference interrupt raw status" "0: No 625us Base Time interrupt,1: A 625us Base Time interrupt is pending"
group.long 0x10++0x03
line.long 0x00 "BLE_INTSTAT_REG,Interrupt status register"
rbitfld.long 0x00 9. "SWINTSTAT,SW triggered interrupt status" "0: No SW triggered interrupt,1: A SW triggered interrupt is pending"
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rbitfld.long 0x00 8. "EVENTAPFAINTSTAT,End of event / Anticipated Pre-Fetch Abort interrupt status" "0: No End of Event interrupt,1: An End of Event interrupt is pending"
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rbitfld.long 0x00 7. "FINETGTIMINTSTAT,Masked Fine Target Timer Error interrupt status" "0: No Fine Target Timer interrupt,1: A Fine Target Timer interrupt is pending"
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rbitfld.long 0x00 6. "GROSSTGTIMINTSTAT,Masked Gross Target Timer interrupt status" "0: No Gross Target Timer interrupt,1: A Gross Target Timer interrupt is pending"
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rbitfld.long 0x00 5. "ERRORINTSTAT,Masked Error interrupt status" "0: No Error interrupt,1: An Error interrupt is pending"
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rbitfld.long 0x00 4. "CRYPTINTSTAT,Masked Encryption engine interrupt status" "0: No Encryption / Decryption interrupt,1: An Encryption / Decryption interrupt is pending"
newline
rbitfld.long 0x00 3. "EVENTINTSTAT,Masked End of Event interrupt status" "0: No End of Advertising / Scanning / Connection,1: An End of Advertising / Scanning / Connection"
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rbitfld.long 0x00 2. "SLPINTSTAT,Masked Sleep interrupt status" "0: No End of Sleep Mode interrupt,1: An End of Sleep Mode interrupt is pending"
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rbitfld.long 0x00 1. "RXINTSTAT,Masked Packet Reception interrupt status" "0: No Rx interrupt,1: An Rx interrupt is pending"
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rbitfld.long 0x00 0. "CSCNTINTSTAT,Masked 625us base time reference interrupt status" "0: No 625us Base Time interrupt,1: A 625us Base Time interrupt is pending"
group.long 0x70++0x03
line.long 0x00 "BLE_RADIOCNTL0_REG,Radio interface control register"
group.long 0x74++0x03
line.long 0x00 "BLE_RADIOCNTL1_REG,Radio interface control register"
bitfld.long 0x00 16.--20. "XRFSEL,Extended radio selection field Must be set to 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x78++0x03
line.long 0x00 "BLE_RADIOCNTL2_REG,Radio interface control register"
group.long 0x7C++0x03
line.long 0x00 "BLE_RADIOCNTL3_REG,Radio interface control register"
group.long 0x80++0x03
line.long 0x00 "BLE_RADIOPWRUPDN_REG,RX/TX power up/down phase register"
hexmask.long.byte 0x00 24.--30. 1. "RTRIP_DELAY,Defines round trip delay value"
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hexmask.long.byte 0x00 16.--23. 1. "RXPWRUP,This register holds the length in s of the RX power up phase for the current radio device"
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bitfld.long 0x00 8.--11. "TXPWRDN,This register extends the length in s of the TX power down phase for the current radio device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "TXPWRUP,This register holds the length in s of the TX power up phase for the current radio device"
group.long 0xE0++0x03
line.long 0x00 "BLE_RFTESTCNTL_REG,RF Testing Register"
bitfld.long 0x00 31. "INFINITERX,Applicable in RF Test Mode only" "0: Normal mode of operation,1: Infinite Rx window"
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bitfld.long 0x00 27. "RXPKTCNTEN,Applicable in RF Test Mode only" "0: Rx packet count disabled,1: Rx packet count enabled and reported in"
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bitfld.long 0x00 15. "INFINITETX,Applicable in RF Test Mode only" "0: Normal mode of operation,1: Infinite Tx packet / Normal start of a packet"
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bitfld.long 0x00 14. "TXLENGTHSRC,Applicable only in Tx/Rx RF Test mode" "0: Normal mode of operation,1: Uses RFTESTCNTL-TXLENGTH packet length (can"
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bitfld.long 0x00 13. "PRBSTYPE,Applicable only in Tx/Rx RF Test mode" "0: Tx Packet Payload are PRBS9 type,1: Tx Packet Payload are PRBS15 type"
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bitfld.long 0x00 12. "TXPLDSRC,Applicable only in Tx/Rx RF Test mode" "0: Tx Packet Payload source is the Control..,1: Tx Packet Payload are PRBS generator"
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bitfld.long 0x00 11. "TXPKTCNTEN,Applicable in RF Test Mode only" "0: Tx packet count disabled,1: Tx packet count enabled and reported in"
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hexmask.long.word 0x00 0.--8. 1. "TXLENGTH,Applicable only for Tx/Rx RF Test mode and valid when RFTESTCNTL-TXLENGTHSRC = 1 Tx packet length in number of byte"
group.long 0xE8++0x03
line.long 0x00 "BLE_RFTESTRXSTAT_REG,RF Testing Register"
hexmask.long 0x00 0.--31. 1. "RXPKTCNT,Reports number of correctly received packet during Test Modes (no sync error no CRC error)"
group.long 0xE4++0x03
line.long 0x00 "BLE_RFTESTTXSTAT_REG,RF Testing Register"
hexmask.long 0x00 0.--31. 1. "TXPKTCNT,Reports number of transmitted packet during Test Modes"
group.long 0x00++0x03
line.long 0x00 "BLE_RWBLECNTL_REG,BLE Control register"
bitfld.long 0x00 31. "MASTER_SOFT_RST,Reset the complete BLE Core except registers and timing generator when written with a 1" "0,1"
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bitfld.long 0x00 30. "MASTER_TGSOFT_RST,Reset the timing generator when written with a 1" "0,1"
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bitfld.long 0x00 29. "REG_SOFT_RST,Reset the complete register block when written with a 1" "0,1"
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bitfld.long 0x00 28. "SWINT_REQ,Forces the generation of ble_sw_irq when written with a 1 and proper masking is set" "0,1"
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bitfld.long 0x00 26. "RFTEST_ABORT,Abort the current RF Testing defined as per CS-FORMAT when written with a 1" "0,1"
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bitfld.long 0x00 25. "ADVERT_ABORT,Abort the current Advertising event when written with a 1" "0,1"
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bitfld.long 0x00 24. "SCAN_ABORT,Abort the current scan window when written with a 1" "0,1"
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bitfld.long 0x00 22. "MD_DSB," "0,1"
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bitfld.long 0x00 21. "SN_DSB," "0,1"
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bitfld.long 0x00 20. "NESN_DSB," "0,1"
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bitfld.long 0x00 19. "CRYPT_DSB," "0,1"
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bitfld.long 0x00 18. "WHIT_DSB," "0,1"
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bitfld.long 0x00 17. "CRC_DSB," "0,1"
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bitfld.long 0x00 16. "HOP_REMAP_DSB," "0,1"
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bitfld.long 0x00 12.--13. "CORR_MODE,Defines correlation mode" "0: Correlates onto Access Address,1: Correlates onto half preamble and Access..,2: Correlates onto full preamble and Access..,3: n/a"
newline
bitfld.long 0x00 9. "ADVERTFILT_EN,Advertising Channels Error Filtering Enable control" "0: RW-BLE Core reports all errors to RW-BLE..,1: RW-BLE Core reports only correctly received"
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bitfld.long 0x00 8. "RWBLE_EN," "0,1"
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bitfld.long 0x00 4.--7. "RXWINSZDEF,Default Rx Window size in us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--2. "SYNCERR,Indicates the maximum number of errors allowed to recognize the synchronization word" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "BLE_RWBLECONF_REG,Configuration register"
rbitfld.long 0x00 24.--29. "ADD_WIDTH,Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 16.--22. 1. "RFIF,Radio Interface ID"
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rbitfld.long 0x00 8.--13. "CLK_SEL,Operating Frequency (in MHz)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "DECIPHER," "0,1"
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rbitfld.long 0x00 5. "DMMODE," "0,1"
newline
rbitfld.long 0x00 4. "INTMODE," "0,1"
newline
rbitfld.long 0x00 3. "COEX," "0,1"
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rbitfld.long 0x00 2. "USEDBG," "0,1"
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rbitfld.long 0x00 1. "USECRYPT," "0,1"
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rbitfld.long 0x00 0. "BUSWIDTH,Processor bus width" "0,1"
group.long 0xDC++0x03
line.long 0x00 "BLE_RXMICVAL_REG,AES / CCM plain MIC value"
hexmask.long 0x00 0.--31. 1. "RXMICVAL,AES-CCM plain MIC value"
group.long 0xFC++0x03
line.long 0x00 "BLE_SAMPLECLK_REG,Samples the Base Time Counter"
bitfld.long 0x00 0. "SAMP,Writing a 1 samples the Base Time Counter value in BASETIMECNT register" "0,1"
group.long 0x64++0x03
line.long 0x00 "BLE_SWPROFILING_REG,Software Profiling register"
hexmask.long 0x00 0.--31. 1. "SWPROFVAL,Software Profiling register: used by RW-BLE Software for profiling purpose: this value is copied on Diagnostic port"
group.long 0xF0++0x03
line.long 0x00 "BLE_TIMGENCNTL_REG,Timing Generator Register"
bitfld.long 0x00 31. "APFM_EN,Controls the Anticipated pre-Fetch Abort mechanism" "0: Disabled,1: Enabled"
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hexmask.long.word 0x00 16.--25. 1. "PREFETCHABORT_TIME,Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort"
newline
hexmask.long.word 0x00 0.--8. 1. "PREFETCH_TIME,Defines Exchange Table pre-fetch instant in us"
group.long 0xD8++0x03
line.long 0x00 "BLE_TXMICVAL_REG,AES / CCM plain MIC value"
hexmask.long 0x00 0.--31. 1. "TXMICVAL,AES-CCM plain MIC value"
group.long 0x04++0x03
line.long 0x00 "BLE_VERSION_REG,Version register"
hexmask.long.byte 0x00 24.--31. 1. "TYP,BLE Core Type"
newline
hexmask.long.byte 0x00 16.--23. 1. "REL,BLE Core version Major release number"
newline
hexmask.long.byte 0x00 8.--15. 1. "UPG,BLE Core upgrade Upgrade number"
newline
hexmask.long.byte 0x00 0.--7. 1. "BUILD,BLE Core Build Build number"
group.long 0xB8++0x03
line.long 0x00 "BLE_WLNBDEV_REG,Devices in white list"
hexmask.long.byte 0x00 8.--15. 1. "NBPRIVDEV,Number of private devices in the white list"
newline
hexmask.long.byte 0x00 0.--7. 1. "NBPUBDEV,Number of public devices in the white list"
group.long 0xB4++0x03
line.long 0x00 "BLE_WLPRIVADDPTR_REG,Start address of private devices list"
hexmask.long.word 0x00 0.--15. 1. "WLPRIVADDPTR,Start address pointer of the private devices white list"
group.long 0xB0++0x03
line.long 0x00 "BLE_WLPUBADDPTR_REG,Start address of public devices list"
hexmask.long.word 0x00 0.--15. 1. "WLPUBADDPTR,Start address pointer of the public devices white list"
tree.end
tree "CACHE"
base ad:0x400C3000
group.long 0x08++0x03
line.long 0x00 "CACHE_ASSOCCFG_REG,Cache associativity configuration register"
bitfld.long 0x00 0.--1. "CACHE_ASSOC,Cache associativity" "0: 1-way (direct mapped),1: 2-way,2: 4-way,3: reserved"
group.long 0x00++0x03
line.long 0x00 "CACHE_CTRL1_REG,Cache control register 1"
bitfld.long 0x00 1. "CACHE_RES1,Reserved" "0,1"
bitfld.long 0x00 0. "CACHE_FLUSH,Writing a '1' into this bit flushes the contents of the tag memories which invalidates the content of the cache memory" "0,1"
group.long 0x20++0x03
line.long 0x00 "CACHE_CTRL2_REG,Cache control register 2"
bitfld.long 0x00 12. "ENABLE_ALSO_QSPIFLASH_CACHED,Enable also the QSPI FLASH cacheability when remapped to OTP (cached)" "0,1"
bitfld.long 0x00 11. "ENABLE_ALSO_OTP_CACHED,Enable also the OTP cacheability when remapped to QSPI FLASH (cached)" "0,1"
newline
bitfld.long 0x00 10. "CACHE_CGEN," "0,1"
bitfld.long 0x00 9. "CACHE_WEN," "0,1"
newline
abitfld.long 0x00 0.--8. "CACHE_LEN,Length of QSPI FLASH cacheable memory" "0x001=1: The OTP memory is completely cacheable..,0x002=2: The max"
group.long 0x04++0x03
line.long 0x00 "CACHE_LNSIZECFG_REG,Cache line size configuration register"
bitfld.long 0x00 0.--1. "CACHE_LINE,Cache line size" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: reserved"
group.long 0x30++0x03
line.long 0x00 "CACHE_MRM_CTRL_REG,Cache MRM (Miss Rate Monitor) CONTROL register"
bitfld.long 0x00 3. "MRM_IRQ_THRES_STATUS," "0,1"
bitfld.long 0x00 2. "MRM_IRQ_TINT_STATUS," "0,1"
newline
bitfld.long 0x00 1. "MRM_IRQ_MASK," "0,1"
bitfld.long 0x00 0. "MRM_START," "0,1"
group.long 0x28++0x03
line.long 0x00 "CACHE_MRM_HITS_REG,Cache MRM (Miss Rate Monitor) HITS register"
hexmask.long.tbyte 0x00 0.--18. 1. "MRM_HITS,Contains the amount of cache hits"
group.long 0x2C++0x03
line.long 0x00 "CACHE_MRM_MISSES_REG,Cache MRM (Miss Rate Monitor) MISSES register"
hexmask.long.tbyte 0x00 0.--17. 1. "MRM_MISSES,Contains the amount of cache misses"
group.long 0x38++0x03
line.long 0x00 "CACHE_MRM_THRES_REG,Cache MRM (Miss Rate Monitor) THRESHOLD register"
hexmask.long.tbyte 0x00 0.--17. 1. "MRM_THRES,Defines the threshold to trigger the interrupt generation"
group.long 0x34++0x03
line.long 0x00 "CACHE_MRM_TINT_REG,Cache MRM (Miss Rate Monitor) TIME INTERVAL register"
hexmask.long.tbyte 0x00 0.--17. 1. "MRM_TINT,Defines the time interval for the monitoring in 16 MHz clock cycles"
group.long 0x50++0x03
line.long 0x00 "SWD_RESET_REG,SWD HW reset control register"
bitfld.long 0x00 0. "SWD_HW_RESET_REQ," "0,1"
tree.end
tree "CHIP_VERSION"
base ad:0x50003200
group.byte 0x00++0x00
line.byte 0x00 "CHIP_ID1_REG,Chip identification register 1"
hexmask.byte 0x00 0.--7. 1. "CHIP_ID1,First character of device type 680 in ASCII"
group.byte 0x01++0x00
line.byte 0x00 "CHIP_ID2_REG,Chip identification register 2"
hexmask.byte 0x00 0.--7. 1. "CHIP_ID2,Second character of device type 680 in ASCII"
group.byte 0x02++0x00
line.byte 0x00 "CHIP_ID3_REG,Chip identification register 3"
hexmask.byte 0x00 0.--7. 1. "CHIP_ID3,Third character of device type 680 in ASCII"
group.byte 0x04++0x00
line.byte 0x00 "CHIP_REVISION_REG,Chip revision register"
abitfld.byte 0x00 0.--7. "REVISION_ID,Chip version corresponds with type number in ASCII" "0x41=65: 'A',0x42=66: 'B'"
group.byte 0x03++0x00
line.byte 0x00 "CHIP_SWC_REG,Software compatibility register"
rbitfld.byte 0x00 0.--3. "CHIP_SWC,SoftWare Compatibility code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "COEX"
base ad:0x50002F00
group.word 0x08++0x01
line.word 0x00 "COEX_BLE_PTI_REG,COEX BLE PTI Control Register"
bitfld.word 0x00 0.--2. "COEX_BLE_PTI,This value specifies the PTI value that characterizes the next BLE transaction that will be initiated on the following ble_active positive edge" "0,1,2,3,4,5,6,7"
group.word 0x00++0x01
line.word 0x00 "COEX_CTRL_REG,COEX Control Register"
bitfld.word 0x00 15. "IGNORE_BLE,If set to 1 then all BLE requests are ignored by masking the internal ble_active signal" "0,1"
bitfld.word 0x00 14. "IGNORE_FTDF,If set to 1 then all FTDF requests are ignored by masking the internal ftdf_active signal" "0,1"
newline
bitfld.word 0x00 13. "IGNORE_EXT,If set to 1 then all EXT requests are ignored by masking the internal ext_act signal ( ext_act is the logical OR of ext_act0 and ext_act1 )" "0,1"
bitfld.word 0x00 11.--12. "SEL_BLE_RADIO_BUSY,Select the logic driving the BLE core input ble.radio_busy" "0: (decision==BLE) AND rfcu.radio_busy,1: Hold to 0,2: (decision==FTDF) OR (decision==EXT) OR,3: (decision==FTDF) OR (decision==EXT)"
newline
bitfld.word 0x00 10. "SEL_BLE_WLAN_TX_RX,If set to 1 then the COEX block will drive the WLAN_TX and WLAN_RX inputs of the BLE core" "0,1"
bitfld.word 0x00 8. "SEL_FTDF_PTI,It controls the source of the FTDF PTI value that the COEX Arbiter will use" "0,1"
newline
bitfld.word 0x00 7. "SEL_FTDF_CCA,If set to 1 and the COEX decision is different than FTDF then the CCA_STAT signal going to FTDF (generated from the radio) will be forced to 1 otherwise the FTDF.CCA_STAT will be driven with the signal generated from the radio" "0,1"
bitfld.word 0x00 5.--6. "SEL_COEX_DIAG,The COEX block can provide internal diagnostic signals by overwriting the BLE diagnostic bus which is forwarded to GPIO multiplexing" "0: P2[2],1: Overwrite the BLE Diagnostic bits 2 down to,2: Overwrite the BLE Diagnostic bits 5 down to,3: Reserved"
newline
bitfld.word 0x00 4. "SMART_ACT_IMPL,Controls the behavior of the SMART_ACT (and SMART_PRI as a consequence)" "0,1"
bitfld.word 0x00 0. "PRGING_ARBITER,If set to 1 then the current BLE transaction will complete normally and after that no further decision will be taken by the arbiter" "0,1"
group.word 0x0C++0x01
line.word 0x00 "COEX_DIAG_REG,COEX Diagnostic Monitor Register"
hexmask.word 0x00 0.--15. 1. "COEX_DIAG_MON,provides the current value of the diagnostic bus forwarded to the GPIO multiplexing (named PPA)"
group.word 0x0A++0x01
line.word 0x00 "COEX_FTDF_PTI_REG,COEX FTDF PTI Control Register"
bitfld.word 0x00 0.--2. "COEX_FTDF_PTI,This value specifies the PTI value that characterizes the next FTDF transaction that will be initiated on the following ftdf_active positive edge" "0,1,2,3,4,5,6,7"
group.word 0x04++0x01
line.word 0x00 "COEX_INT_MASK_REG,COEX Interrupt Mask Register"
bitfld.word 0x00 15. "COEX_IRQ_ON_DECISION_SW,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_DECISION_SW] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
bitfld.word 0x00 14. "COEX_IRQ_ON_START_MID,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_START_MID] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
newline
bitfld.word 0x00 13. "COEX_IRQ_ON_CLOSING_BRK,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_CLOSING_BRK] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
bitfld.word 0x00 12. "COEX_IRQ_ON_RADIO_BUSY_F,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_RADIO_BUSY_F] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
newline
bitfld.word 0x00 11. "COEX_IRQ_ON_RADIO_BUSY_R,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_RADIO_BUSY_R] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
bitfld.word 0x00 10. "COEX_IRQ_ON_BLE_ACTIVE_F,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_BLE_ACTIVE_F] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
newline
bitfld.word 0x00 9. "COEX_IRQ_ON_BLE_ACTIVE_R,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_BLE_ACTIVE_R] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
bitfld.word 0x00 8. "COEX_IRQ_ON_FTDF_ACTIVE_F,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_FTDF_ACTIVE_F] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
newline
bitfld.word 0x00 7. "COEX_IRQ_ON_FTDF_ACTIVE_R,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_FTDF_ACTIVE_R] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
bitfld.word 0x00 6. "COEX_IRQ_ON_EXT_ACT_F,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_EXT_ACT_F] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
newline
bitfld.word 0x00 5. "COEX_IRQ_ON_EXT_ACT_R,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_EXT_ACT_R] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
bitfld.word 0x00 4. "COEX_IRQ_ON_SMART_PRI_F,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_PRI_F] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
newline
bitfld.word 0x00 3. "COEX_IRQ_ON_SMART_PRI_R,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_PRI_R] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
bitfld.word 0x00 2. "COEX_IRQ_ON_SMART_ACT_F,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_ACT_F] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
newline
bitfld.word 0x00 1. "COEX_IRQ_ON_SMART_ACT_R,If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_ACT_R] will cause COEX_IRQ_STAT to be set also to 1" "0,1"
bitfld.word 0x00 0. "COEX_IRQ_MASK,If set to 1 then sent an COEX_IRQ event to CPU as long as COEX_INT_STAT_REG[COEX_IRQ_STAT] is 1" "0,1"
group.word 0x06++0x01
line.word 0x00 "COEX_INT_STAT_REG,COEX Interrupt Status Register"
rbitfld.word 0x00 15. "COEX_IRQ_ON_DECISION_SW,IRQ event when the decision switches to a new MAC" "0,1"
rbitfld.word 0x00 14. "COEX_IRQ_ON_START_MID,IRQ event when the decision switches to a MAC while the TX_EN or RX_EN of this MAC are high" "0,1"
newline
rbitfld.word 0x00 13. "COEX_IRQ_ON_CLOSING_BRK,IRQ if while entering into closing sub-state the TX_EN or RX_EN are active" "0,1"
rbitfld.word 0x00 12. "COEX_IRQ_ON_RADIO_BUSY_F,IRQ event on falling edge of RADIO_BUSY" "0,1"
newline
rbitfld.word 0x00 11. "COEX_IRQ_ON_RADIO_BUSY_R,IRQ event on rising edge of RADIO_BUSY" "0,1"
rbitfld.word 0x00 10. "COEX_IRQ_ON_BLE_ACTIVE_F,IRQ event on falling edge of BLE_ACTIVE internal signal" "0,1"
newline
rbitfld.word 0x00 9. "COEX_IRQ_ON_BLE_ACTIVE_R,IRQ event on rising edge of BLE_ACTIVE internal signal" "0,1"
rbitfld.word 0x00 8. "COEX_IRQ_ON_FTDF_ACTIVE_F,IRQ event on falling edge of FTDF_ACTIVE internal signal" "0,1"
newline
rbitfld.word 0x00 7. "COEX_IRQ_ON_FTDF_ACTIVE_R,IRQ event on rising edge of FTDF_ACTIVE internal signal" "0,1"
rbitfld.word 0x00 6. "COEX_IRQ_ON_EXT_ACT_F,RQ event on falling edge of EXT_ACT" "0,1"
newline
rbitfld.word 0x00 5. "COEX_IRQ_ON_EXT_ACT_R,IRQ event on rising edge of EXT_ACT" "0,1"
rbitfld.word 0x00 4. "COEX_IRQ_ON_SMART_PRI_F,IRQ event on falling edge of SMART_PRI" "0,1"
newline
rbitfld.word 0x00 3. "COEX_IRQ_ON_SMART_PRI_R,IRQ event on rising edge of SMART_PRI" "0,1"
rbitfld.word 0x00 2. "COEX_IRQ_ON_SMART_ACT_F,IRQ event on falling edge of SMART_ACT" "0,1"
newline
rbitfld.word 0x00 1. "COEX_IRQ_ON_SMART_ACT_R,IRQ event on rising edge of SMART_ACT" "0,1"
rbitfld.word 0x00 0. "COEX_IRQ_STAT,For each COEX_IRQ_ON_* bitfield of COEX_INT_STAT_REG the corresponding mask is applied and afterwards all the intermediate results are combined with a logical OR in order to produce the COEX_IRQ_STAT bitfield" "0,1"
group.word 0x24++0x01
line.word 0x00 "COEX_PRI10_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x26++0x01
line.word 0x00 "COEX_PRI11_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x28++0x01
line.word 0x00 "COEX_PRI12_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x2A++0x01
line.word 0x00 "COEX_PRI13_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x2C++0x01
line.word 0x00 "COEX_PRI14_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x2E++0x01
line.word 0x00 "COEX_PRI15_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x30++0x01
line.word 0x00 "COEX_PRI16_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x32++0x01
line.word 0x00 "COEX_PRI17_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x12++0x01
line.word 0x00 "COEX_PRI1_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Specifies the MAC that has been assigned with the specific priority level" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,The priority level specified by this register will be applied to the packets coming from the MAC specified by the COEX_PRI_MAC bitfield and characterized with the PTI value specified by the COEX_PRI_PTI bitfield" "0,1,2,3,4,5,6,7"
group.word 0x14++0x01
line.word 0x00 "COEX_PRI2_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x16++0x01
line.word 0x00 "COEX_PRI3_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x18++0x01
line.word 0x00 "COEX_PRI4_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x1A++0x01
line.word 0x00 "COEX_PRI5_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x1C++0x01
line.word 0x00 "COEX_PRI6_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x1E++0x01
line.word 0x00 "COEX_PRI7_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x20++0x01
line.word 0x00 "COEX_PRI8_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x22++0x01
line.word 0x00 "COEX_PRI9_REG,COEX Priority Register"
bitfld.word 0x00 3.--4. "COEX_PRI_MAC,Refer to COEX_PRI1_REG" "0,1,2,3"
bitfld.word 0x00 0.--2. "COEX_PRI_PTI,Refer to COEX_PRI1_REG" "0,1,2,3,4,5,6,7"
group.word 0x02++0x01
line.word 0x00 "COEX_STAT_REG,COEX Status Register"
rbitfld.word 0x00 15. "IGNORE_BLE_STAT,This signal is constantly 1 on FTDF-only chips" "0,1"
rbitfld.word 0x00 14. "IGNORE_FTDF_STAT,This signal is constantly 1 on BLE-only chips" "0,1"
newline
rbitfld.word 0x00 13. "IGNORE_EXT_STAT,If set to 1 then all EXT requests are ignored by masking immediately the request signal from the external MAC" "0,1"
rbitfld.word 0x00 12. "COEX_RADIO_BUSY,Current state of RADIO_BUSY signal generated from RFCU which is the logical OR among all Radio DCFs" "0,1"
newline
rbitfld.word 0x00 11. "EXT_ACT1,Current state of the pin" "0,1"
rbitfld.word 0x00 10. "EXT_ACT0,Current state of the pin" "0,1"
newline
rbitfld.word 0x00 9. "SMART_PRI,Current state of the pin" "0,1"
rbitfld.word 0x00 8. "SMART_ACT,Current state of the pin" "0,1"
newline
rbitfld.word 0x00 7. "COEX_DECISION_CLOSING,Provides the value of the CLOSING substate" "0,1"
rbitfld.word 0x00 5.--6. "COEX_DECISION,Decision values" "0: Decision is NONE,1: Decision is BLE,2: Decision is FTDF,3: Decision is EXT"
newline
rbitfld.word 0x00 0.--4. "COEX_DECISION_PTR,Provides the number x of the COEX_PRIx_REG that win the last arbitration cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "CRG_PER"
base ad:0x50001C00
group.word 0x04++0x01
line.word 0x00 "CLK_PER_REG,Peripheral divider register"
bitfld.word 0x00 11. "ADC_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.word 0x00 10. "KBSCAN_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
newline
bitfld.word 0x00 9. "I2C_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.word 0x00 8. "SPI_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
newline
bitfld.word 0x00 5. "KBSCAN_ENABLE,Enables the clock" "0,1"
bitfld.word 0x00 4. "IR_CLK_ENABLE,Enables the clock" "0,1"
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bitfld.word 0x00 3. "QUAD_ENABLE,Enables the clock" "0,1"
bitfld.word 0x00 2. "I2C_ENABLE,Enables the clock" "0,1"
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bitfld.word 0x00 1. "SPI_ENABLE,Enables the clock" "0,1"
bitfld.word 0x00 0. "UART_ENABLE,Enables the clock" "0,1"
group.word 0x40++0x01
line.word 0x00 "PCM_DIV_REG,PCM divider and enables"
bitfld.word 0x00 13. "PCM_SRC_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
bitfld.word 0x00 12. "CLK_PCM_EN,Enable for the internally generated PCM clock The PCM_DIV must be set before or together with CLK_PCM_EN" "0,1"
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hexmask.word 0x00 0.--11. 1. "PCM_DIV,PCM clock divider"
group.word 0x42++0x01
line.word 0x00 "PCM_FDIV_REG,PCM fractional division register"
hexmask.word 0x00 0.--15. 1. "PCM_FDIV,These bits define the fractional division part of the PCM clock"
group.word 0x44++0x01
line.word 0x00 "PDM_DIV_REG,PDM divider and enables"
bitfld.word 0x00 9. "PDM_MASTER_MODE,Master mode selection" "0: slave mode,1: master mode"
bitfld.word 0x00 8. "CLK_PDM_EN,Enable for the internally generated PDM clock The PDM_DIV must be set before or together with CLK_PDM_EN" "0,1"
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hexmask.word.byte 0x00 0.--7. 1. "PDM_DIV,PDM clock divider"
group.word 0x46++0x01
line.word 0x00 "SRC_DIV_REG,SRC divider and enables"
bitfld.word 0x00 8. "CLK_SRC_EN,Enable for the internally generated SRC clock The SRC_DIV must be set before or together with CLK_SRC_EN" "0,1"
hexmask.word.byte 0x00 0.--7. 1. "SRC_DIV,SRC clock divider"
group.word 0x4A++0x01
line.word 0x00 "USBPAD_REG,USB pads control register"
bitfld.word 0x00 2. "USBPHY_FORCE_SW2_ON," "0,1"
bitfld.word 0x00 1. "USBPHY_FORCE_SW1_OFF," "0,1"
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bitfld.word 0x00 0. "USBPAD_EN," "0,1"
tree.end
tree "CRG_TOP"
base ad:0x50000000
group.word 0x2A++0x01
line.word 0x00 "ANA_STATUS_REG,status bit of analog (power management) circuits"
rbitfld.word 0x00 15. "COMP_1V8_PA_HIGH,VDD1V8P > 1.7V" "0,1"
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rbitfld.word 0x00 14. "COMP_1V8_FLASH_HIGH,VDD1V8 > 1.7V" "0,1"
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rbitfld.word 0x00 13. "COMP_V33_HIGH,V33 > 1.7V" "0,1"
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rbitfld.word 0x00 12. "COMP_VBUS_LOW,VBUS > 3.4V" "0,1"
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rbitfld.word 0x00 11. "COMP_VBUS_HIGH,VBUS > 4V" "0,1"
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rbitfld.word 0x00 10. "LDO_1V8_FLASH_OK,ldo_vdd1v8 = ok" "0,1"
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rbitfld.word 0x00 9. "LDO_1V8_PA_OK,ldo_vdd1v8P = ok" "0,1"
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rbitfld.word 0x00 8. "LDO_CORE_OK,ldo_core = ok" "0,1"
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rbitfld.word 0x00 7. "COMP_VDD_HIGH,VDD > 1.13V" "0,1"
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rbitfld.word 0x00 6. "BANDGAP_OK,bandgap = ok" "0,1"
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rbitfld.word 0x00 5. "LDO_SUPPLY_USB_OK,ldo_supply_usb = ok" "0,1"
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rbitfld.word 0x00 4. "LDO_SUPPLY_VBAT_OK,ldo_supply_vbat =ok" "0,1"
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rbitfld.word 0x00 3. "NEWBAT,new battery has been detected" "0,1"
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rbitfld.word 0x00 2. "VBUS_AVAILABLE,vbus is available (vbus > vbat)" "0,1"
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rbitfld.word 0x00 1. "COMP_VBAT_OK,vbat > 1.7V" "0,1"
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rbitfld.word 0x00 0. "LDO_RADIO_OK,ldo_radio = ok" "0,1"
group.word 0x28++0x01
line.word 0x00 "BANDGAP_REG,bandgap trimming"
bitfld.word 0x00 14. "BYPASS_COLD_BOOT_DISABLE,0x1 -> Switch to LDO_SUPPLY_USB on vbus_available & vbus_high & wokenup (SET to 0x1 after boot) 0x0 -> Switch to LDO_SUPPLY_USB on vbus_available" "0,1"
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bitfld.word 0x00 10.--13. "LDO_SLEEP_TRIM,0x4 --> 1120 mV 0x5 --> 1089 mV 0x6 --> 1058 mV 0x7 --> 1030 mV 0x0 --> 1037 mV 0x1 --> 1005 mV 0x2 --> 978 mV 0x3 --> 946 mV 0x8 --> 952 mV 0x9 --> 918 mV 0xA --> 889 mV 0xB --> 861 mV 0xC --> 862 mV 0xD --> 828 mV 0xE --> 798 mV 0xF -->.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 5.--9. "BGR_ITRIM,Current trimming for bias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x00 0.--4. "BGR_TRIM,Trim register for bandgap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x36++0x01
line.word 0x00 "BOD_CTRL2_REG,Brown Out Detection control register"
bitfld.word 0x00 5. "BOD_VBAT_EN,VBAT BOD Enable" "0,1"
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bitfld.word 0x00 4. "BOD_1V8_FLASH_EN,1V8 Flash BOD Enable" "0,1"
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bitfld.word 0x00 3. "BOD_1V8_PA_EN,1V8 PA BOD Enable" "0,1"
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bitfld.word 0x00 2. "BOD_V33_EN,V33 BOD Enable" "0,1"
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bitfld.word 0x00 1. "BOD_VDD_EN,VDD BOD Enable" "0,1"
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bitfld.word 0x00 0. "BOD_RESET_EN,Generate a chip reset on BOD event" "0,1"
group.word 0x34++0x01
line.word 0x00 "BOD_CTRL_REG,Brown Out Detection control register"
bitfld.word 0x00 8.--10. "BOD_VDD_LVL,VDD BOD Level" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 6.--7. "BOD_V33_TRIM,V33 BOD Trimming bits" "0,1,2,3"
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bitfld.word 0x00 4.--5. "BOD_1V8_PA_TRIM,1V8 PA BOD Trimming bits" "0,1,2,3"
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bitfld.word 0x00 2.--3. "BOD_1V8_FLASH_TRIM,1V8 Flash BOD Trimming bits" "0,1,2,3"
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bitfld.word 0x00 0.--1. "BOD_VDD_TRIM,VDD BOD Trimming bits" "0,1,2,3"
group.word 0x38++0x01
line.word 0x00 "BOD_STATUS_REG,Brown Out Detection status register"
bitfld.word 0x00 4. "BOD_VBAT_LOW,Indicates VBAT > VBAT_Trigger" "0,1"
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bitfld.word 0x00 3. "BOD_V33_LOW,Indicates V33 > V33_Trigger" "0,1"
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bitfld.word 0x00 2. "BOD_1V8_FLASH_LOW,Indicates V18_Flash > V18_Flash_Trigger" "0,1"
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bitfld.word 0x00 1. "BOD_1V8_PA_LOW,Indicates V18_PA > V18_PA_Trigger" "0,1"
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bitfld.word 0x00 0. "BOD_VDD_LOW,Indicates VDD > VDD_Trigger" "0,1"
group.word 0x22++0x01
line.word 0x00 "CLK_16M_REG,16 MHz RC and xtal oscillator register"
bitfld.word 0x00 15. "RC16M_STARTUP_DISABLE,Gates the RC16M enable from the startup block" "0,1"
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bitfld.word 0x00 14. "XTAL16_HPASS_FLT_EN,enables high pass filter" "0,1"
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bitfld.word 0x00 13. "XTAL16_SPIKE_FLT_BYPASS,bypasses spikefilter" "0,1"
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bitfld.word 0x00 10.--12. "XTAL16_AMP_TRIM,sets xtal amplitude 0 is minimum 101 is maximum" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 9. "XTAL16_EXT_CLK_ENABLE,Uses the signal on the xtal-p pin as the clock the xtal-n pin can float" "0,1"
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bitfld.word 0x00 8. "XTAL16_MAX_CURRENT,Uses the maximum current for testing purpose only" "0,1"
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bitfld.word 0x00 5.--7. "XTAL16_CUR_SET,start-up current for the 16MHz XTAL oscillator" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 1.--4. "RC16M_TRIM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0. "RC16M_ENABLE,Enables the 16MHz RC oscillator" "0,1"
group.word 0x20++0x01
line.word 0x00 "CLK_32K_REG,32 kHz oscillator register"
bitfld.word 0x00 12. "XTAL32K_DISABLE_AMPREG,Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator" "0,1"
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bitfld.word 0x00 8.--11. "RC32K_TRIM," "?,?,?,?,?,?,?,7: default,?,?,?,?,?,?,?,15: highest frequency"
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bitfld.word 0x00 7. "RC32K_ENABLE,Enables the 32kHz RC oscillator" "0,1"
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bitfld.word 0x00 3.--6. "XTAL32K_CUR,Bias current for the 32kHz XTAL oscillator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 1.--2. "XTAL32K_RBIAS,Setting for the bias resistor" "0,1,2,3"
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bitfld.word 0x00 0. "XTAL32K_ENABLE,Enables the 32kHz XTAL oscillator" "0,1"
group.word 0x00++0x01
line.word 0x00 "CLK_AMBA_REG,HCLK PCLK divider and clock gates"
bitfld.word 0x00 12. "QSPI_ENABLE,Clock enable for QSPI controller" "0,1"
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bitfld.word 0x00 10.--11. "QSPI_DIV,QSPI divider" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8"
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bitfld.word 0x00 9. "OTP_ENABLE,Clock enable for OTP controller" "0,1"
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bitfld.word 0x00 8. "TRNG_CLK_ENABLE,Clock enable for TRNG block" "0,1"
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bitfld.word 0x00 7. "ECC_CLK_ENABLE,Clock enable for ECC block" "0,1"
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bitfld.word 0x00 6. "AES_CLK_ENABLE,Clock enable for AES crypto block" "0,1"
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bitfld.word 0x00 4.--5. "PCLK_DIV,APB interface clock Cascaded with HCLK" "0: divide hclk by 1,1: divide hclk by 2,2: divide hclk by 4,3: divide hclk by 8"
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bitfld.word 0x00 0.--2. "HCLK_DIV,AHB interface and microprocessor clock" "0: divide hclk by 1,1: divide hclk by 2,2: divide hclk by 4,3: divide hclk by 8 1xx = divide hclk by 16,?..."
group.word 0x0A++0x01
line.word 0x00 "CLK_CTRL_REG,Clock control register"
rbitfld.word 0x00 15. "RUNNING_AT_PLL96M,Indicates that the PLL96MHz clock is used as clock and may not be switched off" "0,1"
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rbitfld.word 0x00 14. "RUNNING_AT_XTAL16M,Indicates that the XTAL16M clock is used as clock and may not be switched off" "0,1"
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rbitfld.word 0x00 13. "RUNNING_AT_RC16M,Indicates that the RC16M clock is used as clock" "0,1"
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rbitfld.word 0x00 12. "RUNNING_AT_32K,Indicates that either the RC32k or XTAL32k is being used as clock" "0,1"
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bitfld.word 0x00 8.--9. "CLK32K_SOURCE,Sets the clock source of the LowerPower clock '00': 32 Khz RC Oscillator '01': RCX Oscillator '10': XTAL32kHz when using an external crystal i.c.w" "0,1,2,3"
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bitfld.word 0x00 7. "DIVN_SYNC_LEVEL,Level of the RF divider to sync with in case XTAL32_MODE is set" "0,1"
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bitfld.word 0x00 6. "DIVN_XTAL32M_MODE,Enables the DIVN divide-by-2 in case of a 32 MHz crystal (See also XTAL32M_MODE) to keep the DIVN clock at 16 MHz" "0,1"
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bitfld.word 0x00 5. "PLL_DIV2,Divides the PLL clock by 2 before being used" "0,1"
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bitfld.word 0x00 4. "USB_CLK_SRC,Selects the USB source clock" "0: PLL clock,1: HCLK"
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bitfld.word 0x00 3. "XTAL32M_MODE,Enables dividers in the XTAL for both the RF and the BB PLL" "0,1"
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bitfld.word 0x00 2. "XTAL16M_DISABLE,Setting this bit instantaneously disables the 16 MHz crystal oscillator" "0,1"
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bitfld.word 0x00 0.--1. "SYS_CLK_SEL,Selects the clock source" "0: XTAL16M (check the XTAL16_TRIM_READY bit!!),1: RC16M,2: The Low Power clock is used,3: The PLL96Mhz is used"
group.word 0x02++0x01
line.word 0x00 "CLK_FREQ_TRIM_REG,Xtal frequency trimming register"
bitfld.word 0x00 8.--10. "COARSE_ADJ,Xtal frequency course trimming register" "0: lowest frequency,?,?,?,?,?,?,7: highest frequencyIncrement or decrement the"
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hexmask.word.byte 0x00 0.--7. 1. "FINE_ADJ,Xtal frequency fine trimming register.0x00 = lowest frequency"
group.word 0x08++0x01
line.word 0x00 "CLK_RADIO_REG,Radio PLL control register"
bitfld.word 0x00 11. "FTDF_MAC_ENABLE,Enable the FTDF MAC core clocks" "0,1"
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bitfld.word 0x00 8.--9. "FTDF_MAC_DIV,Division factor for FTCF MAC clock relative to the DIVN clock" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8 It should always be"
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bitfld.word 0x00 7. "BLE_ENABLE,Enable the BLE core clocks" "0,1"
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bitfld.word 0x00 6. "BLE_LP_RESET,Reset for the BLE LP timer" "0,1"
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bitfld.word 0x00 4.--5. "BLE_DIV,Division factor for BLE core blocks having as reference the DIVN clock" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8 The programmed"
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bitfld.word 0x00 3. "RFCU_ENABLE,Enable the RF control Unit clock" "0,1"
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bitfld.word 0x00 0.--1. "RFCU_DIV,Division factor for RF Control Unit" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8 The programmed"
group.word 0x24++0x01
line.word 0x00 "CLK_RCX20K_REG,RCX-oscillator control register"
bitfld.word 0x00 11. "RCX20K_ENABLE,Enable the RCX oscillator" "0,1"
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bitfld.word 0x00 10. "RCX20K_LOWF,Extra low frequency" "0,1"
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bitfld.word 0x00 8.--9. "RCX20K_BIAS,Bias control" "0,1,2,3"
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bitfld.word 0x00 4.--7. "RCX20K_NTC,Temperature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. "RCX20K_TRIM," "?,?,?,?,?,?,?,7: default,?,?,?,?,?,?,?,15: highest frequency"
group.word 0x0C++0x01
line.word 0x00 "CLK_TMR_REG,Clock control for the timers"
bitfld.word 0x00 14. "P06_TMR1_PWM_MODE,Maps Timer1_pwm onto P0_6 when DEBUGGER_EN = '0'" "0,1"
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bitfld.word 0x00 13. "WAKEUPCT_ENABLE,Enables the clock" "0,1"
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bitfld.word 0x00 12. "BREATH_ENABLE,Enables the clock" "0,1"
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bitfld.word 0x00 11. "TMR2_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
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bitfld.word 0x00 10. "TMR2_ENABLE,Enable timer clock" "0,1"
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bitfld.word 0x00 8.--9. "TMR2_DIV,Division factor for Timer" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8"
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bitfld.word 0x00 7. "TMR1_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
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bitfld.word 0x00 6. "TMR1_ENABLE,Enable timer clock" "0,1"
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bitfld.word 0x00 4.--5. "TMR1_DIV,Division factor for Timer" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8"
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bitfld.word 0x00 3. "TMR0_CLK_SEL,Selects the clock source" "0: DIVN clock,1: DIV1 clock"
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bitfld.word 0x00 2. "TMR0_ENABLE,Enable timer clock" "0,1"
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bitfld.word 0x00 0.--1. "TMR0_DIV,Division factor for Timer" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8"
group.word 0x3A++0x01
line.word 0x00 "LDO_CTRL1_REG,LDO control register"
bitfld.word 0x00 14. "LDO_RADIO_ENABLE,Enables (1) or disables (0) LDO_RADIO (V14) For fast XTAL startup this bit may be kept to '1' during deep sleep" "0,1"
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bitfld.word 0x00 11.--13. "LDO_RADIO_SETVDD,Sets the output voltage of LDO_RADIO" "0: 1.30 V,1: 1.35 V,2: 1.40 V,3: 1.45 V 1XX =,?..."
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bitfld.word 0x00 8.--10. "LDO_CORE_SETVDD,Sets the output voltage of LDO_CORE" "0: 1.20 V,1: 1.15 V,2: 1.10 V,3: 1.05 V 1XX =,?..."
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bitfld.word 0x00 6.--7. "LDO_SUPPLY_USB_LEVEL,Sets the output voltage of LDO_SUPPLY_USB" "0: 2.40 V,1: 3.30 V,2: 3.45 V,3: 3.60 V"
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bitfld.word 0x00 4.--5. "LDO_SUPPLY_VBAT_LEVEL,Sets the output voltage of LDO_SUPPLY_VBAT" "0: 2.40 V,1: 3.30 V,2: 3.45 V,3: 3.60 V"
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bitfld.word 0x00 2.--3. "LDO_VBAT_RET_LEVEL,Sets the output voltage of LDO_VBAT_RET" "0: 2.40 V,1: 3.30 V,2: 3.45 V,3: 3.60 V"
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bitfld.word 0x00 0.--1. "LDO_CORE_CURLIM,Sets the current limit of LDO_CORE" "0: Current,1: 8 mA,2: 60 mA,3: 80 mA"
group.word 0x3C++0x01
line.word 0x00 "LDO_CTRL2_REG,LDO control register"
bitfld.word 0x00 6. "LDO_1V8_PA_RET_DISABLE,Disables (1) or enables (0) LDO_1V8_PA_RET" "0,1"
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bitfld.word 0x00 5. "LDO_1V8_FLASH_RET_DISABLE,Disables (1) or enables (0) LDO_1V8_FLASH_RET" "0,1"
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bitfld.word 0x00 4. "LDO_VBAT_RET_DISABLE,Disables (1) or enables (0) LDO_VBAT_RET" "0,1"
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bitfld.word 0x00 3. "LDO_1V8_PA_ON,Enables (1) or disables (0) LDO_1V8_PA" "0,1"
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bitfld.word 0x00 2. "LDO_1V8_FLASH_ON,Enables (1) or disables (0) LDO_1V8_FLASH" "0,1"
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bitfld.word 0x00 1. "LDO_3V3_ON,Enables (1) or disables (0) LDO_SUPPLY_VBAT and LDO_SUPPLY_USB" "0,1"
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bitfld.word 0x00 0. "LDO_1V2_ON,Enables (1) or disables (0) LDO_CORE" "0,1"
group.word 0x10++0x01
line.word 0x00 "PMU_CTRL_REG,Power Management Unit control register"
bitfld.word 0x00 15. "RETAIN_ECCRAM,Selects the retainability of the ECC RAM during deep sleep" "0,1"
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bitfld.word 0x00 14. "RETAIN_CACHE,Selects the retainability of the cache block during deep sleep" "0,1"
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bitfld.word 0x00 13. "ENABLE_CLKLESS,Selects the clockless sleep mode" "0,1"
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bitfld.word 0x00 8.--12. "RETAIN_RAM,Select the retainability of the 5 system memory RAM macros during deep sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x00 6.--7. "OTP_COPY_DIV,Sets the HCLK division during OTP mirroring" "0,1,2,3"
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bitfld.word 0x00 5. "RESET_ON_WAKEUP,Perform a Hardware Reset after waking up" "0,1"
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bitfld.word 0x00 3. "FTDF_SLEEP,Put the FTDF in powerdown" "0,1"
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bitfld.word 0x00 2. "BLE_SLEEP,Put the BLE in powerdown" "0,1"
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bitfld.word 0x00 1. "RADIO_SLEEP,Put the digital part of the radio in powerdown" "0,1"
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bitfld.word 0x00 0. "PERIPH_SLEEP,Put all peripherals (I2C UART SPI ADC) in powerdown" "0,1"
group.word 0x3E++0x01
line.word 0x00 "SLEEP_TIMER_REG,Timer for regulated sleep"
hexmask.word 0x00 0.--15. 1. "SLEEP_TIMER,Defines the amount of ticks of the sleep clock between enabling the bandgap for re-charging the retention LDOs"
group.word 0x12++0x01
line.word 0x00 "SYS_CTRL_REG,System Control register"
bitfld.word 0x00 15. "SW_RESET,Writing a '1' to this bit will generate a SW_RESET" "0,1"
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bitfld.word 0x00 14. "REMAP_INTVECT," "0,1"
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bitfld.word 0x00 13. "OTP_COPY,Enables OTP to SysRAM copy action after waking up PD_SYS" "0,1"
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bitfld.word 0x00 12. "QSPI_INIT,Enables QSPI initialization after wakeup" "0,1"
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bitfld.word 0x00 11. "DEV_PHASE,Sets the development phase mode used in combination with OTP_COPY No copy action to SysRAM is done when the system wakes up" "0,1"
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bitfld.word 0x00 10. "CACHERAM_MUX,Controls accessiblity of Cache RAM" "0: the cache controller is bypassed the cacheRAM..,1: the cache controller is enabled the cacheRAM is"
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bitfld.word 0x00 9. "TIMEOUT_DISABLE,Disables timeout in Power statemachine" "0,1"
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bitfld.word 0x00 8. "DRA_OFF,Disables the DRA mode and released the ARM reset" "0,1"
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bitfld.word 0x00 7. "DEBUGGER_ENABLE,Enable the debugger" "0,1"
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bitfld.word 0x00 6. "OTPC_RESET_REQ,Reset request for the OTP controller" "0,1"
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bitfld.word 0x00 5. "PAD_LATCH_EN,Latches the control signals of the pads for state retention in powerdown mode" "0: Control signals are retained,1: Latch is transparant pad can be recontrolled"
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bitfld.word 0x00 3.--4. "REMAP_RAMS,Defines the sequence of the 3 first DataRAMs in the memory space" "0: DataRAM1 DataRAM2 DataRAM3,1: DataRAM2 DataRAM1 DataRAM3,2: DataRAM3 DataRAM1 DataRAM2,3: DataRAM3 DataRAM2 DataRAM1"
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bitfld.word 0x00 0.--2. "REMAP_ADR0,Controls which memory is located at address 0x0000 for execution" "0: ROM,1: DWord (64 bits) access is not supported by the,2: DMA access is not supported by the Cache Data,3: RAMS (for the exact configuration see..,4: FLASH un-cached (for verification only),5: OTP un-cached (for verification only),6: Cache Data RAM (CACHERAM_MUX=0 for testing,?..."
group.word 0x14++0x01
line.word 0x00 "SYS_STAT_REG,System status register"
rbitfld.word 0x00 11. "FTDF_IS_UP,Indicates that PD_DBG is functional" "0,1"
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rbitfld.word 0x00 10. "FTDF_IS_DOWN,Indicates that PD_DBG is in power down" "0,1"
newline
rbitfld.word 0x00 9. "BLE_IS_UP,Indicates that PD_DBG is functional" "0,1"
newline
rbitfld.word 0x00 8. "BLE_IS_DOWN,Indicates that PD_DBG is in power down" "0,1"
newline
rbitfld.word 0x00 6. "XTAL16_TRIM_READY,Indicates that XTAL trimming mechanism is ready i.e" "0,1"
newline
rbitfld.word 0x00 5. "DBG_IS_ACTIVE,Indicates that a debugger is attached" "0,1"
newline
rbitfld.word 0x00 3. "PER_IS_UP,Indicates that PD_PER is functional" "0,1"
newline
rbitfld.word 0x00 2. "PER_IS_DOWN,Indicates that PD_PER is in power down" "0,1"
newline
rbitfld.word 0x00 1. "RAD_IS_UP,Indicates that PD_RAD is functional" "0,1"
newline
rbitfld.word 0x00 0. "RAD_IS_DOWN,Indicates that PD_RAD is in power down" "0,1"
group.word 0x32++0x01
line.word 0x00 "VBUS_IRQ_CLEAR_REG,Clear pending IRQ register"
hexmask.word 0x00 0.--15. 1. "VBUS_IRQ_CLEAR,Writing any value to this register will reset the VBUS_IRQ line"
group.word 0x30++0x01
line.word 0x00 "VBUS_IRQ_MASK_REG,IRQ masking"
bitfld.word 0x00 1. "VBUS_IRQ_EN_RISE,Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to ramp above threshold" "0,1"
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bitfld.word 0x00 0. "VBUS_IRQ_EN_FALL,Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to fall below threshold" "0,1"
group.word 0x50++0x01
line.word 0x00 "XTALRDY_CTRL_REG,Control register for XTALRDY IRQ"
hexmask.word.byte 0x00 0.--7. 1. "XTALRDY_CNT,Number of LP cycles between the crystal is enabled and the XTALRDY_IRQ is fired"
tree.end
tree "DCDC"
base ad:0x50000080
group.word 0x02++0x01
line.word 0x00 "DCDC_CTRL_0_REG,DCDC First Control Register"
bitfld.word 0x00 14. "DCDC_FAST_STARTUP,Set current limit to maximum during initial startup" "0,1"
bitfld.word 0x00 13. "DCDC_BROWNOUT_LV_MODE,Switches to low voltage settings when battery voltage drops below 2.5 V" "0,1"
newline
bitfld.word 0x00 11.--12. "DCDC_IDLE_CLK_DIV,Idle Clock Divider" "0: 2,1: 4,2: 8,3: 16"
hexmask.word.byte 0x00 3.--10. 1. "DCDC_PRIORITY,Charge priority register (4x 2 bit ID) Charge sequence is [1:0] > [3:2] > [5:4] > [7:6] ID[V14] = 00 ID[V18] = 01 ID[VDD] = 10 ID[V18P] = 11"
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bitfld.word 0x00 2. "DCDC_FW_ENABLE,Freewheel switch enable" "0,1"
bitfld.word 0x00 0.--1. "DCDC_MODE,DCDC converter mode" "0: Disabled,1: Active,2: Sleep mode,3: Disabled"
group.word 0x04++0x01
line.word 0x00 "DCDC_CTRL_1_REG,DCDC Second Control Register"
bitfld.word 0x00 11.--15. "DCDC_STARTUP_DELAY,Delay between turning bias on and converter becoming active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 5.--10. "DCDC_GLOBAL_MAX_IDLE_TIME,Global maximum idle time The current limit of any output that is idle for this long will be downramped faster than normal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x00 0.--4. "DCDC_TIMEOUT,P and N switch timeout if switch is closed longer than this a timeout is generated and the FSM is forced to the next state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x06++0x01
line.word 0x00 "DCDC_CTRL_2_REG,DCDC Third Control Register"
bitfld.word 0x00 12.--15. "DCDC_TIMEOUT_IRQ_TRIG,Number of timeout events before timeout interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 8.--11. "DCDC_TIMEOUT_IRQ_RES,Number of successive non-timed out charge events required to clear timeout event counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 6.--7. "DCDC_TUNE,Trim current sensing circuitry" "0: +0 percent,1: +4 percent,2: +8 percent,3: +12 percent"
bitfld.word 0x00 3.--5. "DCDC_LSSUP_TRIM,Trim low side supply voltage V = 2 V + 100 mV * N" "0,1,2,3,4,5,6,7"
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bitfld.word 0x00 0.--2. "DCDC_HSGND_TRIM,Trim high side ground V = VBAT - (2.2 V + 200 mV * N)" "0,1,2,3,4,5,6,7"
group.word 0x36++0x01
line.word 0x00 "DCDC_IRQ_CLEAR_REG,DCDC Interrupt Clear Register"
bitfld.word 0x00 4. "DCDC_BROWN_OUT_IRQ_CLEAR,Clear brown out interrupt" "0,1"
bitfld.word 0x00 3. "DCDC_V18P_TIMEOUT_IRQ_CLEAR,Clear V18P timeout interrupt" "0,1"
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bitfld.word 0x00 2. "DCDC_VDD_TIMEOUT_IRQ_CLEAR,Clear VDD timeout interrupt" "0,1"
bitfld.word 0x00 1. "DCDC_V18_TIMEOUT_IRQ_CLEAR,Clear V18 timeout interrupt" "0,1"
newline
bitfld.word 0x00 0. "DCDC_V14_TIMEOUT_IRQ_CLEAR,Clear V14 timeout interrupt" "0,1"
group.word 0x38++0x01
line.word 0x00 "DCDC_IRQ_MASK_REG,DCDC Interrupt Clear Register"
bitfld.word 0x00 4. "DCDC_BROWN_OUT_IRQ_MASK,Mask brown out interrupt" "0,1"
bitfld.word 0x00 3. "DCDC_V18P_TIMEOUT_IRQ_MASK,Mask V18P timeout interrupt" "0,1"
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bitfld.word 0x00 2. "DCDC_VDD_TIMEOUT_IRQ_MASK,Mask VDD timeout interrupt" "0,1"
bitfld.word 0x00 1. "DCDC_V18_TIMEOUT_IRQ_MASK,Mask V18 timeout interrupt" "0,1"
newline
bitfld.word 0x00 0. "DCDC_V14_TIMEOUT_IRQ_MASK,Mask V14 timeout interrupt" "0,1"
group.word 0x34++0x01
line.word 0x00 "DCDC_IRQ_STATUS_REG,DCDC Interrupt Status Register"
rbitfld.word 0x00 4. "DCDC_BROWN_OUT_IRQ_STATUS,Brown out detector triggered (battery voltage below 2.5 V)" "0,1"
rbitfld.word 0x00 3. "DCDC_V18P_TIMEOUT_IRQ_STATUS,Timeout occured on V18P output" "0,1"
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rbitfld.word 0x00 2. "DCDC_VDD_TIMEOUT_IRQ_STATUS,Timeout occured on VDD output" "0,1"
rbitfld.word 0x00 1. "DCDC_V18_TIMEOUT_IRQ_STATUS,Timeout occured on V18 output" "0,1"
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rbitfld.word 0x00 0. "DCDC_V14_TIMEOUT_IRQ_STATUS,Timeout occured on V14 output" "0,1"
group.word 0x18++0x01
line.word 0x00 "DCDC_RET_0_REG,DCDC First Retention Mode Register"
bitfld.word 0x00 13.--15. "DCDC_V18P_RET_CYCLES,Charge cycles for V18P output in sleep mode Cycles = 1 + 2 * N" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 8.--12. "DCDC_V18P_CUR_LIM_RET,V18P output sleep mode current limit I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x00 5.--7. "DCDC_VDD_RET_CYCLES,Charge cycles for VDD output in sleep mode Cycles = 1 + 2 * N" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--4. "DCDC_VDD_CUR_LIM_RET,VDD output sleep mode current limit I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1A++0x01
line.word 0x00 "DCDC_RET_1_REG,DCDC Second Retention Mode Register"
bitfld.word 0x00 13.--15. "DCDC_V18_RET_CYCLES,Charge cycles for V18 output in sleep mode Cycles = 1 + 2 * N" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 8.--12. "DCDC_V18_CUR_LIM_RET,V18 output sleep mode current limit I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 5.--7. "DCDC_V14_RET_CYCLES,Charge cycles for V14 output in sleep mode Cycles = 1 + 2 * N" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--4. "DCDC_V14_CUR_LIM_RET,V14 output sleep mode current limit I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x22++0x01
line.word 0x00 "DCDC_STATUS_0_REG,DCDC First Status Register"
rbitfld.word 0x00 9.--11. "DCDC_CHARGE_REG_3,Charge register position 3" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 6.--8. "DCDC_CHARGE_REG_2,Charge register position 2" "0,1,2,3,4,5,6,7"
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rbitfld.word 0x00 3.--5. "DCDC_CHARGE_REG_1,Charge register position 1" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--2. "DCDC_CHARGE_REG_0,Charge register position 0" "0,1,2,3,4,5,6,7"
group.word 0x24++0x01
line.word 0x00 "DCDC_STATUS_1_REG,DCDC Second Status Register"
rbitfld.word 0x00 11. "DCDC_V18P_AVAILABLE,Indicates whether V18P is available Requires that converter is enabled output is enabled and V_OK and V_NOK have both occured" "0,1"
rbitfld.word 0x00 10. "DCDC_VDD_AVAILABLE,Indicates whether VDD is available Requires that converter is enabled output is enabled and V_OK and V_NOK have both occured" "0,1"
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rbitfld.word 0x00 9. "DCDC_V18_AVAILABLE,Indicates whether V18 is available Requires that converter is enabled output is enabled and V_OK and V_NOK have both occured" "0,1"
rbitfld.word 0x00 8. "DCDC_V14_AVAILABLE,Indicates whether V14 is available Requires that converter is enabled output is enabled and V_OK and V_NOK have both occured" "0,1"
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rbitfld.word 0x00 7. "DCDC_V18P_OK,OK output of V18P comparator" "0,1"
rbitfld.word 0x00 6. "DCDC_VDD_OK,OK output of VDD comparator" "0,1"
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rbitfld.word 0x00 5. "DCDC_V18_OK,OK output of V18 comparator" "0,1"
rbitfld.word 0x00 4. "DCDC_V14_OK,OK output of V14 comparator" "0,1"
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rbitfld.word 0x00 3. "DCDC_V18P_NOK,NOK output of V18P comparator" "0,1"
rbitfld.word 0x00 2. "DCDC_VDD_NOK,NOK output of VDD comparator" "0,1"
newline
rbitfld.word 0x00 1. "DCDC_V18_NOK,NOK output of V18 comparator" "0,1"
rbitfld.word 0x00 0. "DCDC_V14_NOK,NOK output of V14 comparator" "0,1"
group.word 0x26++0x01
line.word 0x00 "DCDC_STATUS_2_REG,DCDC Third Status Register"
rbitfld.word 0x00 11. "DCDC_V18P_SW_STATE,DCDC state machine V18P output" "0,1"
rbitfld.word 0x00 10. "DCDC_VDD_SW_STATE,DCDC state machine VDD output" "0,1"
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rbitfld.word 0x00 9. "DCDC_V18_SW_STATE,DCDC state machine V18 output" "0,1"
rbitfld.word 0x00 8. "DCDC_V14_SW_STATE,DCDC state machine V14 output" "0,1"
newline
rbitfld.word 0x00 7. "DCDC_NSW_STATE,DCDC state machine NSW output" "0,1"
rbitfld.word 0x00 6. "DCDC_PSW_STATE,DCDC state machine PSW output" "0,1"
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rbitfld.word 0x00 5. "DCDC_P_COMP_P,DCDC P side dynamic comparator P output" "0,1"
rbitfld.word 0x00 4. "DCDC_P_COMP_N,DCDC P side dynamic comparator N output" "0,1"
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rbitfld.word 0x00 3. "DCDC_N_COMP_P,DCDC N side dynamic comparator P output" "0,1"
rbitfld.word 0x00 2. "DCDC_N_COMP_N,DCDC N side dynamic comparator N output" "0,1"
newline
rbitfld.word 0x00 1. "DCDC_P_COMP,DCDC P side continuous time comparator output" "0,1"
rbitfld.word 0x00 0. "DCDC_N_COMP,DCDC N side continuous time comparator output" "0,1"
group.word 0x28++0x01
line.word 0x00 "DCDC_STATUS_3_REG,DCDC Fourth Status Register"
rbitfld.word 0x00 10. "DCDC_LV_MODE,Indicates if the converter is in low battery voltage mode" "0,1"
rbitfld.word 0x00 5.--9. "DCDC_I_LIM_V18P,Actual V18P current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.word 0x00 0.--4. "DCDC_I_LIM_VDD,Actual VDD current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2A++0x01
line.word 0x00 "DCDC_STATUS_4_REG,DCDC Fifth Status Register"
rbitfld.word 0x00 5.--9. "DCDC_I_LIM_V18,Actual V18 current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.word 0x00 0.--4. "DCDC_I_LIM_V14,Actual V14 current limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1E++0x01
line.word 0x00 "DCDC_TEST_0_REG,DCDC Test Register"
bitfld.word 0x00 15. "DCDC_FORCE_COMP_CLK,Disables automatic comparator clock clock lines values based on DCDC_COMP_CLK" "0,1"
bitfld.word 0x00 14. "DCDC_FORCE_CURRENT,Force output current setting" "0,1"
newline
bitfld.word 0x00 11.--13. "DCDC_OUTPUT_MONITOR,Output monitor switch (connect to ADC)" "0: None,1: V14,2: V18,3: VDD,4: VPA,5: None,6: None,7: None"
bitfld.word 0x00 8.--10. "DCDC_ANA_TEST,Analog test bus" "0: None,1: High side ground,2: Low side supply,3: 1.2 V buffer output,4: None,5: None,6: None,7: None"
newline
bitfld.word 0x00 7. "DCDC_FORCE_IDLE,Force idle mode" "0,1"
bitfld.word 0x00 6. "DCDC_FORCE_V18P,Force V18P switch on" "0,1"
newline
bitfld.word 0x00 5. "DCDC_FORCE_VDD,Force VDD switch on" "0,1"
bitfld.word 0x00 4. "DCDC_FORCE_V18,Force V18 switch on" "0,1"
newline
bitfld.word 0x00 3. "DCDC_FORCE_V14,Force V14 switch on" "0,1"
bitfld.word 0x00 2. "DCDC_FORCE_FW,Force FW switch on" "0,1"
newline
bitfld.word 0x00 1. "DCDC_FORCE_NSW,Force N switch on" "0,1"
bitfld.word 0x00 0. "DCDC_FORCE_PSW,Force P switch on" "0,1"
group.word 0x20++0x01
line.word 0x00 "DCDC_TEST_1_REG,DCDC Test Register"
bitfld.word 0x00 9.--12. "DCDC_COMP_CLK,Forced clock values for [COMP_VPA COMP_VDD COMP_V18 COMP_V14] (requires DCDC_FORCE_COMP_CLK = 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 4.--8. "DCDC_TEST_CURRENT,Current limit setting when current limit is forced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--3. "DCDC_TEST_REG,Determines which register appears on the testbus" "0: DCDC_NONE,1: DCDC_STATUS_0,2: DCDC_STATUS_1,3: DCDC_STATUS_2,4: DCDC_STATUS_3,5: DCDC_STATUS_4,6: DCDC_TRIM_0,7: DCDC_TRIM_1,8: DCDC_TRIM_2,9: DCDC_TRIM_3 0xA-0xF = DCDC_NONE,?..."
group.word 0x2C++0x01
line.word 0x00 "DCDC_TRIM_0_REG,DCDC V14 Comparator Trim Register"
rbitfld.word 0x00 6.--11. "DCDC_V14_TRIM_P,P comparator trim value when V14 is active Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +47 mV,32: +16 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -15 mV"
rbitfld.word 0x00 0.--5. "DCDC_V14_TRIM_N,N comparator trim value when V14 is active Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +13 mV,32: -22 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -56 mV"
group.word 0x2E++0x01
line.word 0x00 "DCDC_TRIM_1_REG,DCDC V18 Comparator Trim Register"
rbitfld.word 0x00 6.--11. "DCDC_V18_TRIM_P,P comparator trim value when V18 is active Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +47 mV,32: +16 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -15 mV"
rbitfld.word 0x00 0.--5. "DCDC_V18_TRIM_N,N comparator trim value when V18 is active Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +13 mV,32: -22 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -56 mV"
group.word 0x30++0x01
line.word 0x00 "DCDC_TRIM_2_REG,DCDC VDD Comparator Trim Register"
rbitfld.word 0x00 6.--11. "DCDC_VDD_TRIM_P,P comparator trim value when VDD is active Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +47 mV,32: +16 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -15 mV"
rbitfld.word 0x00 0.--5. "DCDC_VDD_TRIM_N,N comparator trim value when VDD is active Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +13 mV,32: -22 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -56 mV"
group.word 0x32++0x01
line.word 0x00 "DCDC_TRIM_3_REG,DCDC VPA Comparator Trim Register"
rbitfld.word 0x00 6.--11. "DCDC_V18P_TRIM_P,P comparator trim value when V18P is active Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +47 mV,32: +16 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -15 mV"
rbitfld.word 0x00 0.--5. "DCDC_V18P_TRIM_N,N comparator trim value when V18P is active Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +13 mV,32: -22 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -56 mV"
group.word 0x1C++0x01
line.word 0x00 "DCDC_TRIM_REG,DCDC Comparator Trim Register"
bitfld.word 0x00 13. "DCDC_P_COMP_MAN_TRIM,Trim mode for P side comparator" "0: Automatic,1: Manual"
bitfld.word 0x00 7.--12. "DCDC_P_COMP_TRIM,Manual trim value for P side comparator Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +47 mV,32: +16 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -15 mV"
newline
bitfld.word 0x00 6. "DCDC_N_COMP_MAN_TRIM,Trim mode for N side comparator" "0: Automatic,1: Manual"
bitfld.word 0x00 0.--5. "DCDC_N_COMP_TRIM,Manual trim value for N side comparator Signed magnitude representation" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: +13 mV,32: -22 mV,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: -56 mV"
group.word 0x08++0x01
line.word 0x00 "DCDC_V14_0_REG,DCDC V14 First Control Register"
bitfld.word 0x00 15. "DCDC_V14_FAST_RAMPING,V14 output fast current ramping (improves response time at the cost of more ripple)" "0,1"
bitfld.word 0x00 10.--14. "DCDC_V14_VOLTAGE,V14 output voltage V = 1.2 V + 25 mV * N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 5.--9. "DCDC_V14_CUR_LIM_MAX_HV,V14 output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--4. "DCDC_V14_CUR_LIM_MIN,V14 output minimum current limit I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x0A++0x01
line.word 0x00 "DCDC_V14_1_REG,DCDC V14 Second Control Register"
bitfld.word 0x00 15. "DCDC_V14_ENABLE_HV,V14 output enable (high battery voltage mode)" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "DCDC_V14_ENABLE_LV,V14 output enable (low battery voltage mode)" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 10.--13. "DCDC_V14_CUR_LIM_MAX_LV,V14 output maximum current limit low battery voltage mode) I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 5.--9. "DCDC_V14_IDLE_HYST,V14 output idle time hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--4. "DCDC_V14_IDLE_MIN,V14 output minimum idle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x14++0x01
line.word 0x00 "DCDC_V18P_0_REG,DCDC VPA First Control Register"
bitfld.word 0x00 15. "DCDC_V18P_FAST_RAMPING,V18P output fast current ramping (improves response time at the cost of more ripple)" "0,1"
bitfld.word 0x00 10.--14. "DCDC_V18P_VOLTAGE,V18P output voltage V = 1.2 V + 25 mV * N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 5.--9. "DCDC_V18P_CUR_LIM_MAX_HV,V18P output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--4. "DCDC_V18P_CUR_LIM_MIN,V18P output minimum current limit I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x16++0x01
line.word 0x00 "DCDC_V18P_1_REG,DCDC VPA Second Control Register"
bitfld.word 0x00 15. "DCDC_V18P_ENABLE_HV,V18P output enable (high battery voltage mode)" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "DCDC_V18P_ENABLE_LV,V18P output enable (low battery voltage mode)" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 10.--13. "DCDC_V18P_CUR_LIM_MAX_LV,V18P output maximum current limit low battery voltage mode) I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 5.--9. "DCDC_V18P_IDLE_HYST,V18P output idle time hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--4. "DCDC_V18P_IDLE_MIN,V18P output minimum idle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x0C++0x01
line.word 0x00 "DCDC_V18_0_REG,DCDC V18 First Control Register"
bitfld.word 0x00 15. "DCDC_V18_FAST_RAMPING,V18 output fast current ramping (improves response time at the cost of more ripple)" "0,1"
bitfld.word 0x00 10.--14. "DCDC_V18_VOLTAGE,V18 output voltage V = 1.2 V + 25 mV * N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 5.--9. "DCDC_V18_CUR_LIM_MAX_HV,V18 output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--4. "DCDC_V18_CUR_LIM_MIN,V18 output minimum current limit I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x0E++0x01
line.word 0x00 "DCDC_V18_1_REG,DCDC V18 Second Control Register"
bitfld.word 0x00 15. "DCDC_V18_ENABLE_HV,V18 output enable (high battery voltage mode)" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "DCDC_V18_ENABLE_LV,V18 output enable (low battery voltage mode)" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 10.--13. "DCDC_V18_CUR_LIM_MAX_LV,V18 output maximum current limit low battery voltage mode) I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 5.--9. "DCDC_V18_IDLE_HYST,V18 output idle time hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--4. "DCDC_V18_IDLE_MIN,V18 output minimum idle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x10++0x01
line.word 0x00 "DCDC_VDD_0_REG,DCDC VDD First Control Register"
bitfld.word 0x00 15. "DCDC_VDD_FAST_RAMPING,VDD output fast current ramping (improves response time at the cost of more ripple)" "0,1"
bitfld.word 0x00 10.--14. "DCDC_VDD_VOLTAGE,VDD output voltage V = 0.8 V + 25 mV * N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 5.--9. "DCDC_VDD_CUR_LIM_MAX_HV,VDD output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--4. "DCDC_VDD_CUR_LIM_MIN,VDD output minimum current limit I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x12++0x01
line.word 0x00 "DCDC_VDD_1_REG,DCDC VDD Second Control Register"
bitfld.word 0x00 15. "DCDC_VDD_ENABLE_HV,VDD output enable (high battery voltage mode)" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "DCDC_VDD_ENABLE_LV,VDD output enable (low battery voltage mode)" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 10.--13. "DCDC_VDD_CUR_LIM_MAX_LV,VDD output maximum current limit low battery voltage mode) I = 30 mA * (1 + N)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 5.--9. "DCDC_VDD_IDLE_HYST,VDD output idle time hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--4. "DCDC_VDD_IDLE_MIN,VDD output minimum idle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "DMA"
base ad:0x50003500
group.word 0x02++0x01
line.word 0x00 "DMA0_A_STARTH_REG,Start address High A of DMA channel 0"
hexmask.word 0x00 0.--15. 1. "DMA0_A_STARTH,Source start address upper 16 bits"
group.word 0x00++0x01
line.word 0x00 "DMA0_A_STARTL_REG,Start address Low A of DMA channel 0"
hexmask.word 0x00 0.--15. 1. "DMA0_A_STARTL,Source start address lower 16 bits"
group.word 0x06++0x01
line.word 0x00 "DMA0_B_STARTH_REG,Start address High B of DMA channel 0"
hexmask.word 0x00 0.--15. 1. "DMA0_B_STARTH,Destination start address upper 16 bits"
group.word 0x04++0x01
line.word 0x00 "DMA0_B_STARTL_REG,Start address Low B of DMA channel 0"
hexmask.word 0x00 0.--15. 1. "DMA0_B_STARTL,Destination start address lower 16 bits"
group.word 0x0C++0x01
line.word 0x00 "DMA0_CTRL_REG,Control register for the DMA channel 0"
bitfld.word 0x00 12. "DMA_INIT," "0,1"
bitfld.word 0x00 11. "DMA_IDLE," "0,1"
newline
bitfld.word 0x00 8.--10. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
bitfld.word 0x00 7. "CIRCULAR," "0,1"
newline
bitfld.word 0x00 6. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
bitfld.word 0x00 5. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.word 0x00 4. "DREQ_MODE," "0,1"
bitfld.word 0x00 3. "IRQ_ENABLE," "0,1"
newline
bitfld.word 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
bitfld.word 0x00 0. "DMA_ON," "0,1"
group.word 0x0E++0x01
line.word 0x00 "DMA0_IDX_REG,Index value of DMA channel 0"
hexmask.word 0x00 0.--15. 1. "DMA0_IDX,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer"
group.word 0x08++0x01
line.word 0x00 "DMA0_INT_REG,DMA receive interrupt register channel 0"
hexmask.word 0x00 0.--15. 1. "DMA0_INT,Number of transfers until an interrupt is generated"
group.word 0x0A++0x01
line.word 0x00 "DMA0_LEN_REG,DMA receive length register channel 0"
hexmask.word 0x00 0.--15. 1. "DMA0_LEN,DMA channel's transfer length"
group.word 0x12++0x01
line.word 0x00 "DMA1_A_STARTH_REG,Start address High A of DMA channel 1"
hexmask.word 0x00 0.--15. 1. "DMA1_A_STARTH,Source start address upper 16 bits"
group.word 0x10++0x01
line.word 0x00 "DMA1_A_STARTL_REG,Start address Low A of DMA channel 1"
hexmask.word 0x00 0.--15. 1. "DMA1_A_STARTL,Source start address lower 16 bits"
group.word 0x16++0x01
line.word 0x00 "DMA1_B_STARTH_REG,Start address High B of DMA channel 1"
hexmask.word 0x00 0.--15. 1. "DMA1_B_STARTH,Destination start address upper 16 bits"
group.word 0x14++0x01
line.word 0x00 "DMA1_B_STARTL_REG,Start address Low B of DMA channel 1"
hexmask.word 0x00 0.--15. 1. "DMA1_B_STARTL,Destination start address lower 16 bits"
group.word 0x1C++0x01
line.word 0x00 "DMA1_CTRL_REG,Control register for the DMA channel 1"
bitfld.word 0x00 12. "DMA_INIT," "0,1"
bitfld.word 0x00 11. "DMA_IDLE," "0,1"
newline
bitfld.word 0x00 8.--10. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
bitfld.word 0x00 7. "CIRCULAR," "0,1"
newline
bitfld.word 0x00 6. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
bitfld.word 0x00 5. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.word 0x00 4. "DREQ_MODE," "0,1"
bitfld.word 0x00 3. "IRQ_ENABLE," "0,1"
newline
bitfld.word 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
bitfld.word 0x00 0. "DMA_ON," "0,1"
group.word 0x1E++0x01
line.word 0x00 "DMA1_IDX_REG,Index value of DMA channel 1"
hexmask.word 0x00 0.--15. 1. "DMA1_IDX,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer"
group.word 0x18++0x01
line.word 0x00 "DMA1_INT_REG,DMA receive interrupt register channel 1"
hexmask.word 0x00 0.--15. 1. "DMA1_INT,Number of transfers until an interrupt is generated"
group.word 0x1A++0x01
line.word 0x00 "DMA1_LEN_REG,DMA receive length register channel 1"
hexmask.word 0x00 0.--15. 1. "DMA1_LEN,DMA channel's transfer length"
group.word 0x22++0x01
line.word 0x00 "DMA2_A_STARTH_REG,Start address High A of DMA channel 2"
hexmask.word 0x00 0.--15. 1. "DMA2_A_STARTH,Source start address upper 16 bits"
group.word 0x20++0x01
line.word 0x00 "DMA2_A_STARTL_REG,Start address Low A of DMA channel 2"
hexmask.word 0x00 0.--15. 1. "DMA2_A_STARTL,Source start address lower 16 bits"
group.word 0x26++0x01
line.word 0x00 "DMA2_B_STARTH_REG,Start address High B of DMA channel 2"
hexmask.word 0x00 0.--15. 1. "DMA2_B_STARTH,Destination start address upper 16 bits"
group.word 0x24++0x01
line.word 0x00 "DMA2_B_STARTL_REG,Start address Low B of DMA channel 2"
hexmask.word 0x00 0.--15. 1. "DMA2_B_STARTL,Destination start address lower 16 bits"
group.word 0x2C++0x01
line.word 0x00 "DMA2_CTRL_REG,Control register for the DMA channel 2"
bitfld.word 0x00 12. "DMA_INIT," "0,1"
bitfld.word 0x00 11. "DMA_IDLE," "0,1"
newline
bitfld.word 0x00 8.--10. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
bitfld.word 0x00 7. "CIRCULAR," "0,1"
newline
bitfld.word 0x00 6. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
bitfld.word 0x00 5. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.word 0x00 4. "DREQ_MODE," "0,1"
bitfld.word 0x00 3. "IRQ_ENABLE," "0,1"
newline
bitfld.word 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
bitfld.word 0x00 0. "DMA_ON," "0,1"
group.word 0x2E++0x01
line.word 0x00 "DMA2_IDX_REG,Index value of DMA channel 2"
hexmask.word 0x00 0.--15. 1. "DMA2_IDX,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer"
group.word 0x28++0x01
line.word 0x00 "DMA2_INT_REG,DMA receive interrupt register channel 2"
hexmask.word 0x00 0.--15. 1. "DMA2_INT,Number of transfers until an interrupt is generated"
group.word 0x2A++0x01
line.word 0x00 "DMA2_LEN_REG,DMA receive length register channel 2"
hexmask.word 0x00 0.--15. 1. "DMA2_LEN,DMA channel's transfer length"
group.word 0x32++0x01
line.word 0x00 "DMA3_A_STARTH_REG,Start address High A of DMA channel 3"
hexmask.word 0x00 0.--15. 1. "DMA3_A_STARTH,Source start address upper 16 bits"
group.word 0x30++0x01
line.word 0x00 "DMA3_A_STARTL_REG,Start address Low A of DMA channel 3"
hexmask.word 0x00 0.--15. 1. "DMA3_A_STARTL,Source start address lower 16 bits"
group.word 0x36++0x01
line.word 0x00 "DMA3_B_STARTH_REG,Start address High B of DMA channel 3"
hexmask.word 0x00 0.--15. 1. "DMA3_B_STARTH,Destination start address upper 16 bits"
group.word 0x34++0x01
line.word 0x00 "DMA3_B_STARTL_REG,Start address Low B of DMA channel 3"
hexmask.word 0x00 0.--15. 1. "DMA3_B_STARTL,Destination start address lower 16 bits"
group.word 0x3C++0x01
line.word 0x00 "DMA3_CTRL_REG,Control register for the DMA channel 3"
bitfld.word 0x00 12. "DMA_INIT," "0,1"
bitfld.word 0x00 11. "DMA_IDLE," "0,1"
newline
bitfld.word 0x00 8.--10. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
bitfld.word 0x00 7. "CIRCULAR," "0,1"
newline
bitfld.word 0x00 6. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
bitfld.word 0x00 5. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.word 0x00 4. "DREQ_MODE," "0,1"
bitfld.word 0x00 3. "IRQ_ENABLE," "0,1"
newline
bitfld.word 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
bitfld.word 0x00 0. "DMA_ON," "0,1"
group.word 0x3E++0x01
line.word 0x00 "DMA3_IDX_REG,Index value of DMA channel 3"
hexmask.word 0x00 0.--15. 1. "DMA3_IDX,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer"
group.word 0x38++0x01
line.word 0x00 "DMA3_INT_REG,DMA receive interrupt register channel 3"
hexmask.word 0x00 0.--15. 1. "DMA3_INT,Number of transfers until an interrupt is generated"
group.word 0x3A++0x01
line.word 0x00 "DMA3_LEN_REG,DMA receive length register channel 3"
hexmask.word 0x00 0.--15. 1. "DMA3_LEN,DMA channel's transfer length"
group.word 0x42++0x01
line.word 0x00 "DMA4_A_STARTH_REG,Start address High A of DMA channel 4"
hexmask.word 0x00 0.--15. 1. "DMA4_A_STARTH,Source start address upper 16 bits"
group.word 0x40++0x01
line.word 0x00 "DMA4_A_STARTL_REG,Start address Low A of DMA channel 4"
hexmask.word 0x00 0.--15. 1. "DMA4_A_STARTL,Source start address lower 16 bits"
group.word 0x46++0x01
line.word 0x00 "DMA4_B_STARTH_REG,Start address High B of DMA channel 4"
hexmask.word 0x00 0.--15. 1. "DMA4_B_STARTH,Destination start address upper 16 bits"
group.word 0x44++0x01
line.word 0x00 "DMA4_B_STARTL_REG,Start address Low B of DMA channel 4"
hexmask.word 0x00 0.--15. 1. "DMA4_B_STARTL,Destination start address lower 16 bits"
group.word 0x4C++0x01
line.word 0x00 "DMA4_CTRL_REG,Control register for the DMA channel 4"
bitfld.word 0x00 12. "DMA_INIT," "0,1"
bitfld.word 0x00 11. "DMA_IDLE," "0,1"
newline
bitfld.word 0x00 8.--10. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
bitfld.word 0x00 7. "CIRCULAR," "0,1"
newline
bitfld.word 0x00 6. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
bitfld.word 0x00 5. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.word 0x00 4. "DREQ_MODE," "0,1"
bitfld.word 0x00 3. "IRQ_ENABLE," "0,1"
newline
bitfld.word 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
bitfld.word 0x00 0. "DMA_ON," "0,1"
group.word 0x4E++0x01
line.word 0x00 "DMA4_IDX_REG,Index value of DMA channel 4"
hexmask.word 0x00 0.--15. 1. "DMA4_IDX,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer"
group.word 0x48++0x01
line.word 0x00 "DMA4_INT_REG,DMA receive interrupt register channel 4"
hexmask.word 0x00 0.--15. 1. "DMA4_INT,Number of transfers until an interrupt is generated"
group.word 0x4A++0x01
line.word 0x00 "DMA4_LEN_REG,DMA receive length register channel 4"
hexmask.word 0x00 0.--15. 1. "DMA4_LEN,DMA channel's transfer length"
group.word 0x52++0x01
line.word 0x00 "DMA5_A_STARTH_REG,Start address High A of DMA channel 5"
hexmask.word 0x00 0.--15. 1. "DMA5_A_STARTH,Source start address upper 16 bits"
group.word 0x50++0x01
line.word 0x00 "DMA5_A_STARTL_REG,Start address Low A of DMA channel 5"
hexmask.word 0x00 0.--15. 1. "DMA5_A_STARTL,Source start address lower 16 bits"
group.word 0x56++0x01
line.word 0x00 "DMA5_B_STARTH_REG,Start address High B of DMA channel 5"
hexmask.word 0x00 0.--15. 1. "DMA5_B_STARTH,Destination start address upper 16 bits"
group.word 0x54++0x01
line.word 0x00 "DMA5_B_STARTL_REG,Start address Low B of DMA channel 5"
hexmask.word 0x00 0.--15. 1. "DMA5_B_STARTL,Destination start address lower 16 bits"
group.word 0x5C++0x01
line.word 0x00 "DMA5_CTRL_REG,Control register for the DMA channel 5"
bitfld.word 0x00 12. "DMA_INIT," "0,1"
bitfld.word 0x00 11. "DMA_IDLE," "0,1"
newline
bitfld.word 0x00 8.--10. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
bitfld.word 0x00 7. "CIRCULAR," "0,1"
newline
bitfld.word 0x00 6. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
bitfld.word 0x00 5. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.word 0x00 4. "DREQ_MODE," "0,1"
bitfld.word 0x00 3. "IRQ_ENABLE," "0,1"
newline
bitfld.word 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
bitfld.word 0x00 0. "DMA_ON," "0,1"
group.word 0x5E++0x01
line.word 0x00 "DMA5_IDX_REG,Index value of DMA channel 5"
hexmask.word 0x00 0.--15. 1. "DMA5_IDX,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer"
group.word 0x58++0x01
line.word 0x00 "DMA5_INT_REG,DMA receive interrupt register channel 5"
hexmask.word 0x00 0.--15. 1. "DMA5_INT,Number of transfers until an interrupt is generated"
group.word 0x5A++0x01
line.word 0x00 "DMA5_LEN_REG,DMA receive length register channel 5"
hexmask.word 0x00 0.--15. 1. "DMA5_LEN,DMA channel's transfer length"
group.word 0x62++0x01
line.word 0x00 "DMA6_A_STARTH_REG,Start address High A of DMA channel 6"
hexmask.word 0x00 0.--15. 1. "DMA6_A_STARTH,Source start address upper 16 bits"
group.word 0x60++0x01
line.word 0x00 "DMA6_A_STARTL_REG,Start address Low A of DMA channel 6"
hexmask.word 0x00 0.--15. 1. "DMA6_A_STARTL,Source start address lower 16 bits"
group.word 0x66++0x01
line.word 0x00 "DMA6_B_STARTH_REG,Start address High B of DMA channel 6"
hexmask.word 0x00 0.--15. 1. "DMA6_B_STARTH,Destination start address upper 16 bits"
group.word 0x64++0x01
line.word 0x00 "DMA6_B_STARTL_REG,Start address Low B of DMA channel 6"
hexmask.word 0x00 0.--15. 1. "DMA6_B_STARTL,Destination start address lower 16 bits"
group.word 0x6C++0x01
line.word 0x00 "DMA6_CTRL_REG,Control register for the DMA channel 6"
bitfld.word 0x00 12. "DMA_INIT," "0,1"
bitfld.word 0x00 11. "DMA_IDLE," "0,1"
newline
bitfld.word 0x00 8.--10. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
bitfld.word 0x00 7. "CIRCULAR," "0,1"
newline
bitfld.word 0x00 6. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
bitfld.word 0x00 5. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.word 0x00 4. "DREQ_MODE," "0,1"
bitfld.word 0x00 3. "IRQ_ENABLE," "0,1"
newline
bitfld.word 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
bitfld.word 0x00 0. "DMA_ON," "0,1"
group.word 0x6E++0x01
line.word 0x00 "DMA6_IDX_REG,Index value of DMA channel 6"
hexmask.word 0x00 0.--15. 1. "DMA6_IDX,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer"
group.word 0x68++0x01
line.word 0x00 "DMA6_INT_REG,DMA receive interrupt register channel 6"
hexmask.word 0x00 0.--15. 1. "DMA6_INT,Number of transfers until an interrupt is generated"
group.word 0x6A++0x01
line.word 0x00 "DMA6_LEN_REG,DMA receive length register channel 6"
hexmask.word 0x00 0.--15. 1. "DMA6_LEN,DMA channel's transfer length"
group.word 0x72++0x01
line.word 0x00 "DMA7_A_STARTH_REG,Start address High A of DMA channel 7"
hexmask.word 0x00 0.--15. 1. "DMA7_A_STARTH,Source start address upper 16 bits"
group.word 0x70++0x01
line.word 0x00 "DMA7_A_STARTL_REG,Start address Low A of DMA channel 7"
hexmask.word 0x00 0.--15. 1. "DMA7_A_STARTL,Source start address lower 16 bits"
group.word 0x76++0x01
line.word 0x00 "DMA7_B_STARTH_REG,Start address High B of DMA channel 7"
hexmask.word 0x00 0.--15. 1. "DMA7_B_STARTH,Destination start address upper 16 bits"
group.word 0x74++0x01
line.word 0x00 "DMA7_B_STARTL_REG,Start address Low B of DMA channel 7"
hexmask.word 0x00 0.--15. 1. "DMA7_B_STARTL,Destination start address lower 16 bits"
group.word 0x7C++0x01
line.word 0x00 "DMA7_CTRL_REG,Control register for the DMA channel 7"
bitfld.word 0x00 12. "DMA_INIT," "0,1"
bitfld.word 0x00 11. "DMA_IDLE," "0,1"
newline
bitfld.word 0x00 8.--10. "DMA_PRIO,The priority level determines which DMA channel will be granted access for transferring data in case more than one channels are active and request the bus at the same time" "0: lowest priority,?,?,?,?,?,?,7: highest priority If different channels with"
bitfld.word 0x00 7. "CIRCULAR," "0,1"
newline
bitfld.word 0x00 6. "AINC,Enable increment of source address" "0: do not increment (source address stays the same,1: increment according to the value of BW.."
bitfld.word 0x00 5. "BINC,Enable increment of destination address" "0: do not increment (destination address stays the,1: increment according to the value of BW.."
newline
bitfld.word 0x00 4. "DREQ_MODE," "0,1"
bitfld.word 0x00 3. "IRQ_ENABLE," "0,1"
newline
bitfld.word 0x00 1.--2. "BW,Bus transfer width" "0: 1 Byte (suggested for peripherals like UART and,1: 2 Bytes (suggested for peripherals like I2C and,2: 4 Bytes (suggested for Memory-to-Memory..,3: Reserved"
bitfld.word 0x00 0. "DMA_ON," "0,1"
group.word 0x7E++0x01
line.word 0x00 "DMA7_IDX_REG,Index value of DMA channel 7"
hexmask.word 0x00 0.--15. 1. "DMA7_IDX,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer"
group.word 0x78++0x01
line.word 0x00 "DMA7_INT_REG,DMA receive interrupt register channel 7"
hexmask.word 0x00 0.--15. 1. "DMA7_INT,Number of transfers until an interrupt is generated"
group.word 0x7A++0x01
line.word 0x00 "DMA7_LEN_REG,DMA receive length register channel 7"
hexmask.word 0x00 0.--15. 1. "DMA7_LEN,DMA channel's transfer length"
group.word 0x84++0x01
line.word 0x00 "DMA_CLEAR_INT_REG,DMA clear interrupt register"
bitfld.word 0x00 7. "DMA_RST_IRQ_CH7,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 7 writing a 0 will have no effect" "0,1"
bitfld.word 0x00 6. "DMA_RST_IRQ_CH6,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 6 writing a 0 will have no effect" "0,1"
newline
bitfld.word 0x00 5. "DMA_RST_IRQ_CH5,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 5 writing a 0 will have no effect" "0,1"
bitfld.word 0x00 4. "DMA_RST_IRQ_CH4,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 4 writing a 0 will have no effect" "0,1"
newline
bitfld.word 0x00 3. "DMA_RST_IRQ_CH3,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 3 writing a 0 will have no effect" "0,1"
bitfld.word 0x00 2. "DMA_RST_IRQ_CH2,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 2 writing a 0 will have no effect" "0,1"
newline
bitfld.word 0x00 1. "DMA_RST_IRQ_CH1,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 1 writing a 0 will have no effect" "0,1"
bitfld.word 0x00 0. "DMA_RST_IRQ_CH0,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 0 writing a 0 will have no effect" "0,1"
group.word 0x82++0x01
line.word 0x00 "DMA_INT_STATUS_REG,DMA interrupt status register"
rbitfld.word 0x00 7. "DMA_IRQ_CH7," "0,1"
rbitfld.word 0x00 6. "DMA_IRQ_CH6," "0,1"
newline
rbitfld.word 0x00 5. "DMA_IRQ_CH5," "0,1"
rbitfld.word 0x00 4. "DMA_IRQ_CH4," "0,1"
newline
rbitfld.word 0x00 3. "DMA_IRQ_CH3," "0,1"
rbitfld.word 0x00 2. "DMA_IRQ_CH2," "0,1"
newline
rbitfld.word 0x00 1. "DMA_IRQ_CH1," "0,1"
rbitfld.word 0x00 0. "DMA_IRQ_CH0," "0,1"
group.word 0x80++0x01
line.word 0x00 "DMA_REQ_MUX_REG,DMA channel assignments"
bitfld.word 0x00 12.--15. "DMA67_SEL,Select which combination of peripherals are mapped on the DMA channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 8.--11. "DMA45_SEL,Select which combination of peripherals are mapped on the DMA channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 4.--7. "DMA23_SEL,Select which combination of peripherals are mapped on the DMA channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "DMA01_SEL,Select which combination of peripherals are mapped on the DMA channels" "0: SPI_rx / SPI_tx,1: SPI2_rx / SPI2_tx,2: UART_rx / UART_tx,3: UART2_rx / UART2_tx,4: I2C_rx / I2C_tx,5: I2C2_rx / I2C2_tx,6: USB_rx / USB_tx,7: Reserved,8: PCM_rx / PCM_tx,9: SRC_rx / SRC_tx (for all the supported,10: FTDF_rx / FTDF_tx,11: Reserved,12: ADC /,13: Reserved,14: Reserved,15: Reserved"
tree.end
tree "ECC"
base ad:0x50006000
group.long 0x04++0x03
line.long 0x00 "ECC_COMMAND_REG,Command register"
bitfld.long 0x00 31. "ECC_CalcR2,This bit indicates if the IP has to calculate R mod N for the next operation" "0,1"
bitfld.long 0x00 30. "ECC_SignB,Sign of parameter B in equation y2=x3+Ax+B '0': B is positive '1': B is negative" "0,1"
newline
bitfld.long 0x00 29. "ECC_SignA,Sign of parameter A in equation y2=x3+Ax+B '0': A is positive '1': A is negative" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "ECC_SizeOfOperands,This field defines the size (= number of 64-bit double words) of the operands for the current operation"
newline
bitfld.long 0x00 7. "ECC_Field,'0': Field is F(p) '1': Field is F(2m)" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "ECC_TypeOperation,Primitive Arithmetic Operations F(p) & F(2m) [6:4] = 0x0 [3:0] = 0x0 -> Reserved 0x1 -> Modular Addition 0x2 -> Modular Subtraction 0x3 -> Modular Multiplication (Odd N) 0x4 -> Modular Reduction (Odd N) 0x5 -> Modular Division (Odd N).."
group.long 0x00++0x03
line.long 0x00 "ECC_CONFIG_REG,Configuration register"
bitfld.long 0x00 16.--20. "ECC_OpPtrC,When executing primitive arithmetic operations this pointer defines the location where the result will be stored in Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "ECC_OpPtrB,When executing primitive arithmetic operations this Pointer defines where operand B is located in memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "ECC_OpPtrA,When executing primitive arithmetic operations this Pointer defines where operand A is located in memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "ECC_CONTROL_REG,Control register"
bitfld.long 0x00 0. "ECC_Start,The Start signal is activated when all data and key inputs have been loaded in the external crypto memory and are available for processing" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ECC_STATUS_REG,Status register"
rbitfld.long 0x00 16. "ECC_Busy,This Status Signal indicates that the core is processing data" "0,1"
rbitfld.long 0x00 12. "ECC_PrimalityTestResult,After the Miller-Rabin Primality test this flag is: - set to 0 when the random number under test is probably prime - cleared to 1 when the random number under test is composite" "0,1"
newline
rbitfld.long 0x00 11. "ECC_NotInvertible,This flag is set to 1 when executing a modular inversion (PK_CommandReg[3:0] = 0x6 or 0x9) if the operand is not invertible" "0,1"
rbitfld.long 0x00 10. "ECC_Param_AB_NotValid,Status signal set to 1 when parameters A and B are not valid i.e 4A+ 27B = 0" "0,1"
newline
rbitfld.long 0x00 9. "ECC_Signature_NotValid,This flag indicates if the signature can be accepted or must be rejected" "0,1"
rbitfld.long 0x00 7. "ECC_Param_n_NotValid,Status signal set to 1 when Parameter n is not valid" "0,1"
newline
rbitfld.long 0x00 6. "ECC_Couple_NotValid,Status signal set to 1 when couple x y is not valid (i.e. not smaller than the prime)" "0,1"
rbitfld.long 0x00 5. "ECC_Point_Px_AtInfinity,Status signal set to 1 when Point Px is at the infinity" "0,1"
newline
rbitfld.long 0x00 4. "ECC_Point_Px_NotOnCurve,Status signal set to 1 when Point Px is not on the defined EC" "0,1"
rbitfld.long 0x00 0.--3. "ECC_Fail_Address,Address of the last Point detected as Not On Curve Not Valid or at the infinity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "ECC_VERSION_REG,Version register"
hexmask.long.byte 0x00 8.--15. 1. "ECC_HVN,Version of IP to be read via CPU interface"
hexmask.long.byte 0x00 0.--7. 1. "ECC_SVN,Version of Crypto code to be read via CPU interface.Note that this should be read before ECC is used since it corrupts its contents"
tree.end
tree "FTDF"
base ad:0x40080000
group.long 0x10010++0x03
line.long 0x00 "FTDF_BUILDTIME_0_REG,Build time"
hexmask.long 0x00 0.--31. 1. "BUILDTIME,Build time of device"
group.long 0x10014++0x03
line.long 0x00 "FTDF_BUILDTIME_1_REG,Build time"
hexmask.long 0x00 0.--31. 1. "BUILDTIME,Build time of device"
group.long 0x10018++0x03
line.long 0x00 "FTDF_BUILDTIME_2_REG,Build time"
hexmask.long 0x00 0.--31. 1. "BUILDTIME,Build time of device"
group.long 0x1001C++0x03
line.long 0x00 "FTDF_BUILDTIME_3_REG,Build time"
hexmask.long 0x00 0.--31. 1. "BUILDTIME,Build time of device"
group.long 0x10390++0x03
line.long 0x00 "FTDF_DEBUGCONTROL_REG,Debug control register"
bitfld.long 0x00 8. "DBG_RX_INPUT,If set the Rx debug interface will be selected as input for the Rx pipeline" "0,1"
group.long 0x10058++0x03
line.long 0x00 "FTDF_EVENTCURRVAL_REG,Value of event generator"
hexmask.long 0x00 0.--31. 1. "EVENTCURRVAL,Value of captured Event generator"
group.long 0x10250++0x03
line.long 0x00 "FTDF_FTDF_CE_REG,Selection register events"
rbitfld.long 0x00 0.--5. "FTDF_CE,Composite serveice request from ftdf macro (see FR0400 in v40.100.2.41.pdf) Bit" "0: unused Bit,1: rx interrupts Bit,2: unused Bit,3: miscelaneous interrupts Bit,4: tx interrupts Bit,5: Reserved,?..."
group.long 0x10254++0x03
line.long 0x00 "FTDF_FTDF_CM_REG,Mask selection register events"
bitfld.long 0x00 0.--5. "FTDF_CM,mask bits for ftf_ce" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10020++0x03
line.long 0x00 "FTDF_GLOB_CONTROL_0_REG,Global control register"
bitfld.long 0x00 18. "MACTSCHENABLED,If set TSCH mode is enabled" "0,1"
bitfld.long 0x00 17. "MACLEENABLED,If set Low Energy mode is enabled" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "MACSIMPLEADDRESS,Simple address of the PAN coordinator"
bitfld.long 0x00 3. "TX_DMA_REQ,Source of the TX_DMA_REQ output of this block" "0,1"
newline
bitfld.long 0x00 2. "RX_DMA_REQ,Source of the RX_DMA_REQ output of this block" "0,1"
bitfld.long 0x00 1. "ISPANCOORDINATOR,Enable/disable receiver check on address fields (0=enabled 1=disabled)" "0,1"
group.long 0x10024++0x03
line.long 0x00 "FTDF_GLOB_CONTROL_1_REG,Global control register"
hexmask.long.word 0x00 16.--31. 1. "MACSHORTADDRESS,The values 0xFFFF and 0xFFFE indicate that no IEEE Short Address is available"
hexmask.long.word 0x00 0.--15. 1. "MACPANID,The values 0xFFFF indicates that the device is not associated"
group.long 0x10028++0x03
line.long 0x00 "FTDF_GLOB_CONTROL_2_REG,Global control register"
hexmask.long 0x00 0.--31. 1. "AEXTENDEDADDRESS_L,Unique device address lower 32 bit"
group.long 0x1002C++0x03
line.long 0x00 "FTDF_GLOB_CONTROL_3_REG,Global control register"
hexmask.long 0x00 0.--31. 1. "AEXTENDEDADDRESS_H,Unique device address higher 16 bit"
group.long 0x10360++0x03
line.long 0x00 "FTDF_LMACRESET_REG,Lmax reset register"
bitfld.long 0x00 16. "LMACGLOBRESET_COUNT,If set the LMAC performance and traffic counters will be reset" "0,1"
bitfld.long 0x00 10. "LMACRESET_TIMCTRL,LmacReset_count: A '1' Resets LMAC timing control block (for debug and MLME-reset)" "0,1"
newline
bitfld.long 0x00 9. "LMACRESET_COUNT,LmacReset_count: A '1' Resets LMAC mac counters (for debug and MLME-reset)" "0,1"
bitfld.long 0x00 7. "LMACRESET_SEC,LmacReset_sec: A '1' Resets LMAC security (for debug and MLME-reset) #LmacReset_wutim@on_off_regmap #LmacReset_wutim: A '1' Resets LMAC wake-up timer (for debug and MLME-reset)" "0,1"
newline
bitfld.long 0x00 6. "LMACRESET_TSTIM,LmacReset_tstim: A '1' Resets LMAC timestamp timer (for debug and MLME-reset)" "0,1"
bitfld.long 0x00 4. "LMACRESET_OREG,LmacReset_oreg: A '1' Resets LMAC on_off regmap (for debug and MLME-reset) #LmacReset_areg@on_off_regmap #LmacReset_areg: A '1' Resets LMAC always_on regmap (for debug and MLME-reset)" "0,1"
newline
bitfld.long 0x00 3. "LMACRESET_AHB,LmacReset_ahb: A '1' Resets LMAC ahb interface (for debug and MLME-reset)" "0,1"
bitfld.long 0x00 2. "LMACRESET_TX,LmacReset_tx: A '1' Resets LMAC tx pipeline (for debug and MLME-reset)" "0,1"
newline
bitfld.long 0x00 1. "LMACRESET_RX,LmacReset_rx: A '1' Resets LMAC rx pipeline (for debug and MLME-reset)" "0,1"
bitfld.long 0x00 0. "LMACRESET_CONTROL,LmacReset_control: A '1' Resets LMAC Controller (for debug and MLME-reset)" "0,1"
group.long 0x10030++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_0_REG,Lmac control register"
bitfld.long 0x00 31. "KEEP_PHY_EN,When the transmit or receive action is ready (LmacReady4Sleep will is set) the phy_en signal is cleared unless the control register keep_phy_en is set" "0,1"
bitfld.long 0x00 27.--30. "PTI,Info to arbiter if phy_en is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 25. "RXALWAYSON,If set the receiver shall be always on if RxEnable is set" "0,1"
hexmask.long.tbyte 0x00 1.--24. 1. "RXONDURATION,Time the Rx must be on"
group.long 0x1010C++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_10_REG,Lmac control register"
bitfld.long 0x00 28.--31. "MACRZZEROVAL,If the current RZtime is less or Equal to macRZzeroVal an RZtime with value zero is inserted in the wakeup frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "MACCSLMARGINRZ,The UMAC can set the margin for the expected frame by control register macCSLmarginRZ (in 10 sym)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 0.--7. 1. "MACWURZCORRECTION,This register shall be used if the Wake-up frame to be transmitted is larger than 15 octets"
group.long 0x1006C++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_11_REG,Lmac control register"
bitfld.long 0x00 16. "MACDISCARXOFFTORZ,This switching off and on of the PHY Rx can be disabled whith the control register macDisCaRxOfftoRZ" "0: Disabled,1: Enabled"
hexmask.long.word 0x00 0.--15. 1. "MACRXTOTALCYCLETIME,In order to make it easier to calculate if it is efficient to disable and enable the PHY Rx until the RZ time is reached a control register indicates the time needed to disable and enable the PHY Rx: macRxTotalCycleTime (resolution.."
group.long 0x10040++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_1_REG,Lmac control register"
bitfld.long 0x00 15. "PHYRXATTR_HSI,HighSide injection" "0,1"
bitfld.long 0x00 12.--14. "PHYRXATTR_RF_GPIO_PINS,Slot-basis signals mapped on GPIO via PPA" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--11. "PHYRXATTR_CALCAP,CalCap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "PHYRXATTR_CN,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "PHYRXATTR_DEM_PTI,DEM packet information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10044++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_2_REG,Lmac control register"
hexmask.long.tbyte 0x00 8.--31. 1. "EDSCANDURATION,Length of ED scan"
bitfld.long 0x00 0. "EDSCANENABLE,if set Energy Detect scan will be done" "0,1"
group.long 0x10048++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_3_REG,Lmac control register"
hexmask.long.byte 0x00 16.--23. 1. "CCAIDLEWAIT,Time to wait after CCA returned &quot medium idle&quot before starting TX-ON (in us)"
hexmask.long.word 0x00 0.--15. 1. "MACMAXFRAMETOTALWAITTIME,Max time to wait for a requested Data Frame or an announced broadcast frame"
group.long 0x10060++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_4_REG,Lmac control register"
bitfld.long 0x00 31. "PHYACKATTR_HSI,HighSide injection" "0,1"
bitfld.long 0x00 28.--30. "PHYACKATTR_RF_GPIO_PINS,Slot-basis signals mapped on GPIO via PPA" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--27. "PHYACKATTR_CALCAP,CalCap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "PHYACKATTR_CN,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PHYACKATTR_DEM_PTI,DEM packet information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "RXPIPEPROPDELAY,The control register RxPipePropDelay indicates the propagation delay in ~s of the Rx pipeline between the last symbol being captured at the DPHY interface and the &quot data valid&quot indication to the LMAC controller"
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hexmask.long.byte 0x00 0.--7. 1. "PHYSLEEPWAIT,Time between negate and assert PHY_EN When the signal phy_en is deasserted it will not be asserted within the time phySleepWait"
group.long 0x10064++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_5_REG,Lmac control register"
bitfld.long 0x00 31. "PHYCSMACAATTR_HSI,HighSide injection" "0,1"
bitfld.long 0x00 28.--30. "PHYCSMACAATTR_RF_GPIO_PINS,Slot-basis signals mapped on GPIO via PPA" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--27. "PHYCSMACAATTR_CALCAP,CalCap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "PHYCSMACAATTR_CN,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PHYCSMACAATTR_DEM_PTI,DEM packet information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CCASTATWAIT,The output CCASTAT is valid after 8 symbols + phyRxStartup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "ACK_RESPONSE_DELAY,In order to have some flexibility the control register Ack_Response_Delay indicates the Acknowledge response time in ~s"
group.long 0x10068++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_6_REG,Lmac control register"
hexmask.long.byte 0x00 16.--23. 1. "WUIFSPERIOD,The WakeUp IFS period is programmable by WUifsPeriod (in symbols)"
hexmask.long.byte 0x00 8.--15. 1. "SIFSPERIOD,The SIFS period is programmable by SifsPeriod (in symbols)"
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hexmask.long.byte 0x00 0.--7. 1. "LIFSPERIOD,The LIFS period is programmable by LifsPeriod (in symbols)"
group.long 0x10100++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_7_REG,Lmac control register"
hexmask.long.word 0x00 16.--31. 1. "MACCSLSAMPLEPERIOD,When performing a idle listening the receiver is enabled for at least macCSLsamplePeriod (in symbols)"
hexmask.long.word 0x00 0.--15. 1. "MACWUPERIOD,Wake-up duration in symbols"
group.long 0x10104++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_8_REG,Lmac control register"
hexmask.long 0x00 0.--31. 1. "MACCSLSTARTSAMPLETIME,The control register macCSLstartSampleTime indicates the TimeStamp generator time (in symbols) when to start listening (called &quot idle listening&quot )"
group.long 0x10108++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_9_REG,Lmac control register"
hexmask.long.word 0x00 16.--31. 1. "MACCSLFRAMEPENDINGWAITT,If a non Wake-up frame with Frame Pending bit = '1' is received the receiver is enabled for at least an extra period of macCSLFramePendingWaitT (in symbols) after the end of the received frame"
hexmask.long.word 0x00 0.--15. 1. "MACCSLDATAPERIOD,After the wake-up sequence a frame is expected the receiver will be enabled for at least a period of macCSLdataPeriod (in symbols)"
group.long 0x10070++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_DELTA_REG,Lmac delta control register"
bitfld.long 0x00 6. "WAKEUPTIMERENABLESTATUS_D,Delta which indicates that WakeupTimerEnableStatus has changed" "0,1"
bitfld.long 0x00 5. "GETGENERATORVAL_E,Event which indicates the getGeneratorVal request is completed" "0,1"
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bitfld.long 0x00 4. "SYMBOLTIME2THR_E,Event that symboltime counter matched SymbolTime2Thr" "0,1"
bitfld.long 0x00 3. "SYMBOLTIMETHR_E,Event that symboltime counter matched SymbolTimeThr" "0,1"
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bitfld.long 0x00 2. "SYNCTIMESTAMP_E,The SyncTimeStamp_e event is set when the TimeStampgenerator is loaded with SyncTimeStampVal" "0,1"
bitfld.long 0x00 1. "LMACREADY4SLEEP_D,Delta bit for register &quot LmacReady4sleep&quot" "0,1"
group.long 0x10080++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_MASK_REG,Lmac mask control register"
bitfld.long 0x00 6. "WAKEUPTIMERENABLESTATUS_M,Mask for WakeupTimerEnableStatus_d" "0,1"
bitfld.long 0x00 5. "GETGENERATORVAL_M,Mask for getGeneratorVal_e" "0,1"
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bitfld.long 0x00 4. "SYMBOLTIME2THR_M,Mask for SymbolTime2Thr_e" "0,1"
bitfld.long 0x00 3. "SYMBOLTIMETHR_M,Mask for SymbolTimeThr_e" "0,1"
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bitfld.long 0x00 2. "SYNCTIMESTAMP_M,Mask bit for event register SyncTimeStamp_e" "0,1"
bitfld.long 0x00 1. "LMACREADY4SLEEP_M,Mask bit for delta bit &quot LmacReady4sleep_d&quot" "0,1"
group.long 0x10050++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_OS_REG,Lmac control register"
bitfld.long 0x00 2. "SINGLECCA,If set a single CCA will be performed" "0,1"
bitfld.long 0x00 1. "RXENABLE,If set receiving data may be done" "0,1"
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bitfld.long 0x00 0. "GETGENERATORVAL,If set the current values of WU gen and TS gen will be captured" "0,1"
group.long 0x10054++0x03
line.long 0x00 "FTDF_LMAC_CONTROL_STATUS_REG,Lmac status register"
hexmask.long.byte 0x00 8.--15. 1. "EDSCANVALUE,Result of ED scan"
rbitfld.long 0x00 6. "WAKEUPTIMERENABLESTATUS,Status of WakeupTimerEnable after being clocked by LP_CLK (showing it's effective value)" "0,1"
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rbitfld.long 0x00 2. "CCASTAT,Value single CCA when CCAstat_e is set" "0,1"
rbitfld.long 0x00 1. "LMACREADY4SLEEP,Indicates that the LMAC is ready to go to sleep" "0,1"
group.long 0x10090++0x03
line.long 0x00 "FTDF_LMAC_EVENT_REG,Lmac event regsiter"
bitfld.long 0x00 2. "RXTIMEREXPIRED_E,Set if one of the timers enabling the RX-ON mode expires without having received any valid frame" "0,1"
bitfld.long 0x00 1. "CCASTAT_E,If set the single CCA is ready" "0,1"
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bitfld.long 0x00 0. "EDSCANREADY_E,The event EdScanReady_e is set to notify that the ED scan is ready" "0,1"
group.long 0x100A0++0x03
line.long 0x00 "FTDF_LMAC_MANUAL_1_REG,Lmax manual PHY register"
bitfld.long 0x00 31. "LMAC_MANUAL_PHY_ATTR_HSI,HighSide injection" "0,1"
bitfld.long 0x00 28.--30. "LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS,Slot-basis signals mapped on GPIO via PPA" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--27. "LMAC_MANUAL_PHY_ATTR_CALCAP,CalCap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "LMAC_MANUAL_PHY_ATTR_CN,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "LMAC_MANUAL_PHY_ATTR_DEM_PTI,DEM packet information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LMAC_MANUAL_PTI,lmac_manual_pti controls the PTI interface signal when lmac_manual_mode is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "LMAC_MANUAL_TX_FRM_NR,lmac_manual_tx_frm_nr controls the entry in the tx buffer to be transmitted" "0,1,2,3"
bitfld.long 0x00 5. "LMAC_MANUAL_ED_REQUEST,lmac_manual_ed_request controls the ED_REQUEST interface signal when lmac_manual_mode is set" "0,1"
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bitfld.long 0x00 4. "LMAC_MANUAL_RX_PIPE_EN,lmac_manual_rx_pipe_en controls the rx_enable signal towards the rx pipeline when lmac_manual_mode is set" "0,1"
bitfld.long 0x00 3. "LMAC_MANUAL_RX_EN,lmac_manual_rx_en controls the RX_EN interface signal when lmac_manual_mode is set" "0,1"
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bitfld.long 0x00 2. "LMAC_MANUAL_TX_EN,lmac_manual_tx_en controls the TX_EN interface signal when lmac_manual_mode is set" "0,1"
bitfld.long 0x00 1. "LMAC_MANUAL_PHY_EN,lmac_manual_phy_en controls the PHY_EN interface signal when lmac_manual_mode is set" "0,1"
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bitfld.long 0x00 0. "LMAC_MANUAL_MODE,If the control register lmac_manual_mode is set the LMAC controller control signals should be controlled by the lmac_manual_control registers" "0,1"
group.long 0x100A4++0x03
line.long 0x00 "FTDF_LMAC_MANUAL_OS_REG,One shot register triggers transmission in manual mode"
bitfld.long 0x00 0. "LMAC_MANUAL_TX_START,One shot register which triggers the transmission of a frame from the tx buffer in lmac_manual_mode" "0,1"
group.long 0x100A8++0x03
line.long 0x00 "FTDF_LMAC_MANUAL_STATUS_REG,Lmac status register in manual mode"
hexmask.long.byte 0x00 8.--15. 1. "LMAC_MANUAL_ED_STAT,lmac_manual_ed_stat shows the status of the ED_STAT interface signal"
rbitfld.long 0x00 0. "LMAC_MANUAL_CCA_STAT,lmac_manual_cca_stat shows the status of the CCA_STAT" "0,1"
group.long 0x10094++0x03
line.long 0x00 "FTDF_LMAC_MASK_REG,Lmac mask register"
bitfld.long 0x00 2. "RXTIMEREXPIRED_M,Mask bit for event &quot RxTimerExpired_e&quot" "0,1"
bitfld.long 0x00 1. "CCASTAT_M,Mask bit for event &quot CCAstat_e&quot" "0,1"
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bitfld.long 0x00 0. "EDSCANREADY_M,Mask bit for event &quot EdScanReady_e&quot" "0,1"
group.long 0x10038++0x03
line.long 0x00 "FTDF_MACACKWAITDURATION_REG,Maximum time to wait for a ACK"
hexmask.long.byte 0x00 0.--7. 1. "MACACKWAITDURATION,Max time to wait for a (normal) ACK"
group.long 0x1003C++0x03
line.long 0x00 "FTDF_MACENHACKWAITDURATION_REG,Maximum time to wait for an enhanced ACK frame"
hexmask.long.word 0x00 0.--15. 1. "MACENHACKWAITDURATION,The maximum time (in s) to wait for an enhanced acknowledgement frame"
group.long 0x10340++0x03
line.long 0x00 "FTDF_MACFCSERRORCOUNT_REG,Lmac FCS error register"
hexmask.long 0x00 0.--31. 1. "MACFCSERRORCOUNT,The number of received frames that were discarded due to an incorrect FCS"
group.long 0x10318++0x03
line.long 0x00 "FTDF_MACRXADDRFAILFRMCNT_REG,Discarded frames register"
hexmask.long 0x00 0.--31. 1. "MACRXADDRFAILFRMCNT,Frames discarded due to incorrect address or PAN Id"
group.long 0x10314++0x03
line.long 0x00 "FTDF_MACRXSTDACKFRMOKCNT_REG,Received acknowledgment frames"
hexmask.long 0x00 0.--31. 1. "MACRXSTDACKFRMOKCNT,Standard Acknowledgment frames received"
group.long 0x1031C++0x03
line.long 0x00 "FTDF_MACRXUNSUPFRMCNT_REG,Unsupported frames register"
hexmask.long 0x00 0.--31. 1. "MACRXUNSUPFRMCNT,Frames which do pass the checks but are not supported"
group.long 0x10078++0x03
line.long 0x00 "FTDF_MACTSTXACKDELAYVAL_REG,Time left until next ACK is sent (us)"
hexmask.long.word 0x00 0.--15. 1. "MACTSTXACKDELAYVAL,The time in us left until the ack frame is sent by the lmac"
group.long 0x10310++0x03
line.long 0x00 "FTDF_MACTXSTDACKFRMCNT_REG,Transmitted acknowledgment frames"
hexmask.long 0x00 0.--31. 1. "MACTXSTDACKFRMCNT,Standard Acknowledgment frames transmitted"
group.long 0x10180++0x03
line.long 0x00 "FTDF_PHY_PARAMETERS_0_REG,Lmac PHY parameter register"
bitfld.long 0x00 28.--30. "RXBITPOS_7,See rxBitPos_0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "RXBITPOS_6,See rxBitPos_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. "RXBITPOS_5,See rxBitPos_0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "RXBITPOS_4,See rxBitPos_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. "RXBITPOS_3,See rxBitPos_0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "RXBITPOS_2,See rxBitPos_0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "RXBITPOS_1,See rxBitPos_0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "RXBITPOS_0,Control rxBitPos(8)(3) controls the position that a bit should have at the DPHY interface" "0,1,2,3,4,5,6,7"
group.long 0x10184++0x03
line.long 0x00 "FTDF_PHY_PARAMETERS_1_REG,Lmac PHY parameter register"
bitfld.long 0x00 28.--30. "TXBITPOS_7,See txBitPos_0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "TXBITPOS_6,See txBitPos_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. "TXBITPOS_5,See txBitPos_0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "TXBITPOS_4,See txBitPos_0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "TXBITPOS_3,See txBitPos_0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "TXBITPOS_2,See txBitPos_0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "TXBITPOS_1,See txBitPos_0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "TXBITPOS_0,Control txBitPos(8)(3) controls the position that a bit should have at the DPHY interface" "0,1,2,3,4,5,6,7"
group.long 0x10188++0x03
line.long 0x00 "FTDF_PHY_PARAMETERS_2_REG,Lmac PHY parameter register"
hexmask.long.byte 0x00 24.--31. 1. "PHYTRXWAIT,Phy wait time between TX_EN/RX_EN"
hexmask.long.byte 0x00 16.--23. 1. "PHYTXFINISH,Phy wait time before deasserting TX_EN"
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hexmask.long.byte 0x00 8.--15. 1. "PHYTXLATENCY,Phy delay between DPHY i/f and air"
hexmask.long.byte 0x00 0.--7. 1. "PHYTXSTARTUP,Phy wait time before transmission"
group.long 0x1018C++0x03
line.long 0x00 "FTDF_PHY_PARAMETERS_3_REG,Lmac PHY parameter register"
hexmask.long.byte 0x00 16.--23. 1. "PHYENABLE,Asserting the DPHY interface signals TX_EN or RX_EN does not take place within the time phyEnable after asserting the signal phy_en"
hexmask.long.byte 0x00 8.--15. 1. "PHYRXLATENCY,Phy delay between air and DPHY i/f"
newline
hexmask.long.byte 0x00 0.--7. 1. "PHYRXSTARTUP,Phy wait time before receiving"
group.long 0x10000++0x03
line.long 0x00 "FTDF_REL_NAME_0_REG,Name of the release"
hexmask.long 0x00 0.--31. 1. "REL_NAME,Name of the release"
group.long 0x10004++0x03
line.long 0x00 "FTDF_REL_NAME_1_REG,Name of the release"
hexmask.long 0x00 0.--31. 1. "REL_NAME,Name of the release"
group.long 0x10008++0x03
line.long 0x00 "FTDF_REL_NAME_2_REG,Name of the release"
hexmask.long 0x00 0.--31. 1. "REL_NAME,Name of the release"
group.long 0x1000C++0x03
line.long 0x00 "FTDF_REL_NAME_3_REG,Name of the release"
hexmask.long 0x00 0.--31. 1. "REL_NAME,Name of the release"
group.long 0x10200++0x03
line.long 0x00 "FTDF_RX_CONTROL_0_REG,Receive control register"
bitfld.long 0x00 27. "DISRXACKRECEIVEDCA,If set the LMAC controller shall ignore all consequent actions upon a set AR bit in the transmitted frame" "0,1"
bitfld.long 0x00 26. "MACIMPLICITBROADCAST,If set Frame Version 2 frames without Daddr or DPANId shall be accepted" "0,1"
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bitfld.long 0x00 25. "MACPASSWAKEUP,If set WakeUp frames will not be reported but will be put into the Rx buffer" "0,1"
bitfld.long 0x00 24. "MACALWAYSPASSWAKEUP,If the control register macAlwaysPassWakeUp is set received Wake- up frames for this device are put into the Rx packet buffer without notifying the LMAC Controller" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "MACALWAYSPASSFRMTYPE,The control registers macAlwaysPassFrmType[7:0] shall control if this Frame Type shall be dropped"
bitfld.long 0x00 15. "MACALWAYSPASSTOPANCOORDINATOR,When the control register macAlwaysPassToPanCoordinator is set the frame is not dropped due to a span_coord_error" "0,1"
newline
bitfld.long 0x00 14. "MACALWAYSPASSBEACONWRONGPANID,If the control register macAlwaysPassBeaconWrongPANId is set the frame is not dropped in case of a mismatch in PAN-ID irrespective of the setting of RxBeaconOnly" "0,1"
bitfld.long 0x00 13. "MACALWAYSPASSWRONGDADDR,If set a packet with a wrong DAddr is not dropped" "0,1"
newline
bitfld.long 0x00 12. "MACALWAYSPASSWRONGDPANID,If register macAlwaysPassWrongDPANId is set packet with a wrong Destiantion PanID will not be dropped" "0,1"
bitfld.long 0x00 11. "MACALWAYSPASSRESFRAMEVERSION,If set a packet with a reserved FrameVersion shall not be dropped" "0,1"
newline
bitfld.long 0x00 10. "DISDATAREQUESTCA,When the control register DisDataRequestCa is set the notification of the received Data Request is disabled" "0,1"
bitfld.long 0x00 9. "MACALWAYSPASSCRCERROR,If set a FCS error will not drop the frame" "0,1"
newline
bitfld.long 0x00 8. "DISRXACKREQUESTCA,When the control register DisRxAckRequestca is set all consequent actions for a received Acknowledge Request bit are disabled" "0,1"
bitfld.long 0x00 7. "DISRXFRMPENDINGCA,Whan the control register DisRxFrmPendingCa is set the notification of the received FP bit to the LMAC Controller is disabled" "0,1"
newline
bitfld.long 0x00 3.--6. "RX_READ_BUF_PTR,Indication where new data will be read All four bits shall be used when using these pointer values (0d - 15d)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "RXCOORDREALIGNONLY,If set only Coordinator Realignment frames are accepted" "0,1"
newline
bitfld.long 0x00 1. "RXBEACONONLY,If set only Beacons frames are accepted" "0,1"
bitfld.long 0x00 0. "DBGRXTRANSPARENTMODE,If set Rx pipe is fully set in transparent mode (for debug purpose)" "0,1"
group.long 0x10204++0x03
line.long 0x00 "FTDF_RX_EVENT_REG,Receive event register"
bitfld.long 0x00 3. "RXBYTE_E,Indicates the first byte of a new packet is received" "0,1"
bitfld.long 0x00 2. "RX_BUF_AVAIL_E,Indicates that a new packet is received" "0,1"
newline
bitfld.long 0x00 1. "RX_OVERFLOW_E,Indicates that the Rx packet buffer has an overflowl" "0,1"
bitfld.long 0x00 0. "RXSOF_E,Set when RX_SOF has been detected" "0,1"
group.long 0x8000++0x03
line.long 0x00 "FTDF_RX_FIFO_0_0_REG,Address receive fifo 0"
hexmask.long 0x00 0.--31. 1. "RX_FIFO,Receive fifo ram contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x8080++0x03
line.long 0x00 "FTDF_RX_FIFO_1_0_REG,Address transmit fifo 1"
hexmask.long 0x00 0.--31. 1. "RX_FIFO,Receive fifo ram contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x8100++0x03
line.long 0x00 "FTDF_RX_FIFO_2_0_REG,Address transmit fifo 2"
hexmask.long 0x00 0.--31. 1. "RX_FIFO,Receive fifo ram contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x8180++0x03
line.long 0x00 "FTDF_RX_FIFO_3_0_REG,Address transmit fifo 3"
hexmask.long 0x00 0.--31. 1. "RX_FIFO,Receive fifo ram contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x8200++0x03
line.long 0x00 "FTDF_RX_FIFO_4_0_REG,Address transmit fifo 4"
hexmask.long 0x00 0.--31. 1. "RX_FIFO,Receive fifo ram contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x8280++0x03
line.long 0x00 "FTDF_RX_FIFO_5_0_REG,Address transmit fifo 5"
hexmask.long 0x00 0.--31. 1. "RX_FIFO,Receive fifo ram contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x8300++0x03
line.long 0x00 "FTDF_RX_FIFO_6_0_REG,Address transmit fifo 6"
hexmask.long 0x00 0.--31. 1. "RX_FIFO,Receive fifo ram contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x8380++0x03
line.long 0x00 "FTDF_RX_FIFO_7_0_REG,Address transmit fifo 7"
hexmask.long 0x00 0.--31. 1. "RX_FIFO,Receive fifo ram contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x10208++0x03
line.long 0x00 "FTDF_RX_MASK_REG,Receive event mask register"
bitfld.long 0x00 3. "RXBYTE_M,Mask bit for event &quot rxbyte_e&quot" "0,1"
bitfld.long 0x00 2. "RX_BUF_AVAIL_M,Mask bit for event &quot rx_buf_avail_e&quot" "0,1"
newline
bitfld.long 0x00 1. "RX_OVERFLOW_M,Mask bit for event &quot rx_overflow_e&quot" "0,1"
bitfld.long 0x00 0. "RXSOF_M,Mask bit for event &quot RxSof_e&quot" "0,1"
group.long 0x280++0x03
line.long 0x00 "FTDF_RX_META_0_0_REG,Receive metadata register 0"
hexmask.long 0x00 0.--31. 1. "RX_TIMESTAMP,Timestamp taken when frame was received"
group.long 0x290++0x03
line.long 0x00 "FTDF_RX_META_0_1_REG,Receive metadata register 1"
hexmask.long 0x00 0.--31. 1. "RX_TIMESTAMP,Timestamp taken when frame was received"
group.long 0x2A0++0x03
line.long 0x00 "FTDF_RX_META_0_2_REG,Receive metadata register 2"
hexmask.long 0x00 0.--31. 1. "RX_TIMESTAMP,Timestamp taken when frame was received"
group.long 0x2B0++0x03
line.long 0x00 "FTDF_RX_META_0_3_REG,Receive metadata register 3"
hexmask.long 0x00 0.--31. 1. "RX_TIMESTAMP,Timestamp taken when frame was received"
group.long 0x2C0++0x03
line.long 0x00 "FTDF_RX_META_0_4_REG,Receive metadata register 4"
hexmask.long 0x00 0.--31. 1. "RX_TIMESTAMP,Timestamp taken when frame was received"
group.long 0x2D0++0x03
line.long 0x00 "FTDF_RX_META_0_5_REG,Receive metadata register 5"
hexmask.long 0x00 0.--31. 1. "RX_TIMESTAMP,Timestamp taken when frame was received"
group.long 0x2E0++0x03
line.long 0x00 "FTDF_RX_META_0_6_REG,Receive metadata register 6"
hexmask.long 0x00 0.--31. 1. "RX_TIMESTAMP,Timestamp taken when frame was received"
group.long 0x2F0++0x03
line.long 0x00 "FTDF_RX_META_0_7_REG,Receive metadata register 7"
hexmask.long 0x00 0.--31. 1. "RX_TIMESTAMP,Timestamp taken when frame was received"
group.long 0x284++0x03
line.long 0x00 "FTDF_RX_META_1_0_REG,Receive metadata register 0"
hexmask.long.byte 0x00 8.--15. 1. "QUALITY_INDICATOR,Link Quality Indication # software_scratch@retention_ram # TX ram not used by hardware can be used by software as scratch ram with retention"
rbitfld.long 0x00 7. "ISPANID_COORD_ERROR,Received frame not for PAN coordinator applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 6. "SPANID_ERROR,PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 5. "DADDR_ERROR,D Address error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 4. "DPANID_ERROR,D PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 3. "RES_FRM_VERSION_ERROR,Not supported frame version error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 2. "RES_FRM_TYPE_ERROR,Not supported frame type error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 0. "CRC16_ERROR,CRC error applicable for transparent mode only" "0,1"
group.long 0x294++0x03
line.long 0x00 "FTDF_RX_META_1_1_REG,Receive metadata register 1"
hexmask.long.byte 0x00 8.--15. 1. "QUALITY_INDICATOR,Link Quality Indication # software_scratch@retention_ram # TX ram not used by hardware can be used by software as scratch ram with retention"
rbitfld.long 0x00 7. "ISPANID_COORD_ERROR,Received frame not for PAN coordinator applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 6. "SPANID_ERROR,PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 5. "DADDR_ERROR,D Address error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 4. "DPANID_ERROR,D PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 3. "RES_FRM_VERSION_ERROR,Not supported frame version error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 2. "RES_FRM_TYPE_ERROR,Not supported frame type error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 0. "CRC16_ERROR,CRC error applicable for transparent mode only" "0,1"
group.long 0x2A4++0x03
line.long 0x00 "FTDF_RX_META_1_2_REG,Receive metadata register 2"
hexmask.long.byte 0x00 8.--15. 1. "QUALITY_INDICATOR,Link Quality Indication # software_scratch@retention_ram # TX ram not used by hardware can be used by software as scratch ram with retention"
rbitfld.long 0x00 7. "ISPANID_COORD_ERROR,Received frame not for PAN coordinator applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 6. "SPANID_ERROR,PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 5. "DADDR_ERROR,D Address error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 4. "DPANID_ERROR,D PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 3. "RES_FRM_VERSION_ERROR,Not supported frame version error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 2. "RES_FRM_TYPE_ERROR,Not supported frame type error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 0. "CRC16_ERROR,CRC error applicable for transparent mode only" "0,1"
group.long 0x2B4++0x03
line.long 0x00 "FTDF_RX_META_1_3_REG,Receive metadata register 3"
hexmask.long.byte 0x00 8.--15. 1. "QUALITY_INDICATOR,Link Quality Indication # software_scratch@retention_ram # TX ram not used by hardware can be used by software as scratch ram with retention"
rbitfld.long 0x00 7. "ISPANID_COORD_ERROR,Received frame not for PAN coordinator applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 6. "SPANID_ERROR,PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 5. "DADDR_ERROR,D Address error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 4. "DPANID_ERROR,D PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 3. "RES_FRM_VERSION_ERROR,Not supported frame version error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 2. "RES_FRM_TYPE_ERROR,Not supported frame type error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 0. "CRC16_ERROR,CRC error applicable for transparent mode only" "0,1"
group.long 0x2C4++0x03
line.long 0x00 "FTDF_RX_META_1_4_REG,Receive metadata register 4"
hexmask.long.byte 0x00 8.--15. 1. "QUALITY_INDICATOR,Link Quality Indication # software_scratch@retention_ram # TX ram not used by hardware can be used by software as scratch ram with retention"
rbitfld.long 0x00 7. "ISPANID_COORD_ERROR,Received frame not for PAN coordinator applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 6. "SPANID_ERROR,PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 5. "DADDR_ERROR,D Address error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 4. "DPANID_ERROR,D PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 3. "RES_FRM_VERSION_ERROR,Not supported frame version error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 2. "RES_FRM_TYPE_ERROR,Not supported frame type error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 0. "CRC16_ERROR,CRC error applicable for transparent mode only" "0,1"
group.long 0x2D4++0x03
line.long 0x00 "FTDF_RX_META_1_5_REG,Receive metadata register 5"
hexmask.long.byte 0x00 8.--15. 1. "QUALITY_INDICATOR,Link Quality Indication # software_scratch@retention_ram # TX ram not used by hardware can be used by software as scratch ram with retention"
rbitfld.long 0x00 7. "ISPANID_COORD_ERROR,Received frame not for PAN coordinator applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 6. "SPANID_ERROR,PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 5. "DADDR_ERROR,D Address error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 4. "DPANID_ERROR,D PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 3. "RES_FRM_VERSION_ERROR,Not supported frame version error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 2. "RES_FRM_TYPE_ERROR,Not supported frame type error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 0. "CRC16_ERROR,CRC error applicable for transparent mode only" "0,1"
group.long 0x2E4++0x03
line.long 0x00 "FTDF_RX_META_1_6_REG,Receive metadata register 6"
hexmask.long.byte 0x00 8.--15. 1. "QUALITY_INDICATOR,Link Quality Indication # software_scratch@retention_ram # TX ram not used by hardware can be used by software as scratch ram with retention"
rbitfld.long 0x00 7. "ISPANID_COORD_ERROR,Received frame not for PAN coordinator applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 6. "SPANID_ERROR,PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 5. "DADDR_ERROR,D Address error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 4. "DPANID_ERROR,D PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 3. "RES_FRM_VERSION_ERROR,Not supported frame version error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 2. "RES_FRM_TYPE_ERROR,Not supported frame type error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 0. "CRC16_ERROR,CRC error applicable for transparent mode only" "0,1"
group.long 0x2F4++0x03
line.long 0x00 "FTDF_RX_META_1_7_REG,Receive metadata register 7"
hexmask.long.byte 0x00 8.--15. 1. "QUALITY_INDICATOR,Link Quality Indication # software_scratch@retention_ram # TX ram not used by hardware can be used by software as scratch ram with retention"
rbitfld.long 0x00 7. "ISPANID_COORD_ERROR,Received frame not for PAN coordinator applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 6. "SPANID_ERROR,PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 5. "DADDR_ERROR,D Address error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 4. "DPANID_ERROR,D PAN ID error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 3. "RES_FRM_VERSION_ERROR,Not supported frame version error applicable when frame is not discarded" "0,1"
newline
rbitfld.long 0x00 2. "RES_FRM_TYPE_ERROR,Not supported frame type error applicable when frame is not discarded" "0,1"
rbitfld.long 0x00 0. "CRC16_ERROR,CRC error applicable for transparent mode only" "0,1"
group.long 0x10220++0x03
line.long 0x00 "FTDF_RX_STATUS_DELTA_REG,Receive status delta register"
bitfld.long 0x00 0. "RX_BUFF_IS_FULL_D,Delta bit of status &quot rx_buff_is_full&quot" "0,1"
group.long 0x10224++0x03
line.long 0x00 "FTDF_RX_STATUS_MASK_REG,Receive status delta mask register"
bitfld.long 0x00 0. "RX_BUFF_IS_FULL_M,Mask bit of status &quot rx_buff_is_full&quot" "0,1"
group.long 0x1020C++0x03
line.long 0x00 "FTDF_RX_STATUS_REG,Receive status register"
rbitfld.long 0x00 1.--4. "RX_WRITE_BUF_PTR,Indication where new data will be written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0. "RX_BUFF_IS_FULL,Indicates that the Rx packet buffer is full" "0,1"
group.long 0x10118++0x03
line.long 0x00 "FTDF_SECKEY_0_REG,Seckey register"
hexmask.long 0x00 0.--31. 1. "SECKEY_0,Registers secKey[0..3] contain the key to be used"
group.long 0x1011C++0x03
line.long 0x00 "FTDF_SECKEY_1_REG,Seckey register"
hexmask.long 0x00 0.--31. 1. "SECKEY_1,See register &quot secKey_0&quot"
group.long 0x10120++0x03
line.long 0x00 "FTDF_SECKEY_2_REG,SecKey register"
hexmask.long 0x00 0.--31. 1. "SECKEY_2,See register &quot secKey_0&quot"
group.long 0x10124++0x03
line.long 0x00 "FTDF_SECKEY_3_REG,Seckey register"
hexmask.long 0x00 0.--31. 1. "SECKEY_3,See register &quot secKey_0&quot"
group.long 0x10128++0x03
line.long 0x00 "FTDF_SECNONCE_0_REG,Nonce register used for encryption/decryption"
hexmask.long 0x00 0.--31. 1. "SECNONCE_0,Register secNonce[0..3] contains the Nonce to be used for encryption/decryption"
group.long 0x1012C++0x03
line.long 0x00 "FTDF_SECNONCE_1_REG,Nonce register used for encryption/decryption"
hexmask.long 0x00 0.--31. 1. "SECNONCE_1,See register &quot Nonce_0&quot"
group.long 0x10130++0x03
line.long 0x00 "FTDF_SECNONCE_2_REG,Nonce register used for encryption/decryption"
hexmask.long 0x00 0.--31. 1. "SECNONCE_2,See register &quot Nonce_0&quot"
group.long 0x10134++0x03
line.long 0x00 "FTDF_SECNONCE_3_REG,Nonce register used for encryption/decryption"
hexmask.long.byte 0x00 0.--7. 1. "SECNONCE_3,See register &quot Nonce_0&quot"
group.long 0x10110++0x03
line.long 0x00 "FTDF_SECURITY_0_REG,Security register"
bitfld.long 0x00 31. "SECENCDECN,The control register secEncDecn indicates whether to encrypt ('1') or decrypt ('0') the data" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "SECMLENGTH,The length of the m_data is indicated by control register secMlength"
newline
hexmask.long.byte 0x00 16.--22. 1. "SECALENGTH,The length of the a_data is indicated by control register secAlength"
bitfld.long 0x00 8.--11. "SECENTRY,The UMAC shall indicate by control registers secEntry and secTxRxn which entry to use and if it's from the Tx or Rx buffer ('1' resp. '0')" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SECTXRXN,See register &quot secEntry&quot" "0,1"
group.long 0x10114++0x03
line.long 0x00 "FTDF_SECURITY_1_REG,Security register"
hexmask.long.byte 0x00 8.--15. 1. "SECENCRFLAGS,Register secEncrFlags contain the encryption flags field"
hexmask.long.byte 0x00 0.--7. 1. "SECAUTHFLAGS,Register secAuthFlags contains the authentication flags fields"
group.long 0x10154++0x03
line.long 0x00 "FTDF_SECURITY_EVENTMASK_REG,security event mask register"
bitfld.long 0x00 0. "SECREADY_M,Mask bit for event &quot secReady_e&quot" "0,1"
group.long 0x10150++0x03
line.long 0x00 "FTDF_SECURITY_EVENT_REG,security event register"
bitfld.long 0x00 0. "SECREADY_E,The Event bit secReady_e is set when the authentication process is ready (i.e. secBusy is cleared)" "0,1"
group.long 0x10138++0x03
line.long 0x00 "FTDF_SECURITY_OS_REG,One shot register to start encryption/decryption"
bitfld.long 0x00 1. "SECSTART,One_shot register to start the encryption decryption and authentication support task" "0,1"
bitfld.long 0x00 0. "SECABORT,See register &quot Nonce_0&quot" "0,1"
group.long 0x10140++0x03
line.long 0x00 "FTDF_SECURITY_STATUS_REG,Security status register"
rbitfld.long 0x00 1. "SECAUTHFAIL,In case of decryption the status bit secAuthFail will be set when the authentication has failed" "0,1"
rbitfld.long 0x00 0. "SECBUSY,Register &quot secBusy&quot indicates if the encryption/decryption process is still running" "0,1"
group.long 0x10384++0x03
line.long 0x00 "FTDF_SYMBOLTIME2THR_REG,Symboltime threshold register 2"
hexmask.long 0x00 0.--31. 1. "SYMBOLTIME2THR,Symboltime 2 Threshold to generate a general interrupt"
group.long 0x10210++0x03
line.long 0x00 "FTDF_SYMBOLTIMESNAPSHOTVAL_REG,Value timestamp generator"
hexmask.long 0x00 0.--31. 1. "SYMBOLTIMESNAPSHOTVAL,The Status register SymbolTimeSnapshotVal indicates the actual value of the TimeStamp generator"
group.long 0x10380++0x03
line.long 0x00 "FTDF_SYMBOLTIMETHR_REG,Symboltime threshold register 1"
hexmask.long 0x00 0.--31. 1. "SYMBOLTIMETHR,Symboltime Threshold to generate a general interrupt"
group.long 0x10320++0x03
line.long 0x00 "FTDF_SYNCTIMESTAMPPHASEVAL_REG,Timestamp phase value regsiter"
hexmask.long.byte 0x00 0.--7. 1. "SYNCTIMESTAMPPHASEVAL,Value to sync TS gen phase within a symbol with"
group.long 0x10304++0x03
line.long 0x00 "FTDF_SYNCTIMESTAMPTHR_REG,Threshold timestamp generator"
hexmask.long 0x00 0.--31. 1. "SYNCTIMESTAMPTHR,Threshold for synchronize TS gen"
group.long 0x10308++0x03
line.long 0x00 "FTDF_SYNCTIMESTAMPVAL_REG,Value timestamp generator"
hexmask.long 0x00 0.--31. 1. "SYNCTIMESTAMPVAL,Value to sync TS gen with"
group.long 0x1030C++0x03
line.long 0x00 "FTDF_TIMER_CONTROL_1_REG,Timer control register"
bitfld.long 0x00 1. "SYNCTIMESTAMPENA,If set the TimeStampThr is enabled to generate a sync of the TS gen" "0,1"
group.long 0x10074++0x03
line.long 0x00 "FTDF_TIMESTAMPCURRPHASEVAL_REG,Value of timestamp generator phase within a symbol"
hexmask.long.byte 0x00 0.--7. 1. "TIMESTAMPCURRPHASEVAL,Value of captured TS gen phase within a symbol"
group.long 0x1005C++0x03
line.long 0x00 "FTDF_TIMESTAMPCURRVAL_REG,Value of timestamp generator"
hexmask.long 0x00 0.--31. 1. "TIMESTAMPCURRVAL,Value of captured TS gen"
group.long 0x10160++0x03
line.long 0x00 "FTDF_TSCH_CONTROL_0_REG,Lmac tsch control register"
hexmask.long.word 0x00 16.--31. 1. "MACTSRXWAIT,The times to wait for start of frame"
hexmask.long.word 0x00 0.--15. 1. "MACTSTXACKDELAY,End of Rx frame to start of Ack"
group.long 0x10164++0x03
line.long 0x00 "FTDF_TSCH_CONTROL_1_REG,Lmac tsch control register"
hexmask.long.word 0x00 0.--15. 1. "MACTSRXTX,The time between the CCA and the TX of a frame"
group.long 0x10168++0x03
line.long 0x00 "FTDF_TSCH_CONTROL_2_REG,Lmac tsch control register"
hexmask.long.word 0x00 16.--31. 1. "MACTSACKWAIT,The minimum time to wait for start of an Acknowledgement"
hexmask.long.word 0x00 0.--15. 1. "MACTSRXACKDELAY,End of frame to when the transmitter shall listen for Acknowledgement"
group.long 0x10394++0x03
line.long 0x00 "FTDF_TXBYTE_E_REG,Transmit first byte register"
bitfld.long 0x00 1. "TX_LAST_SYMBOL_E,Indicates the last symbol of a frame is transmitted" "0,1"
bitfld.long 0x00 0. "TXBYTE_E,Indicates the first byte of a frame is transmitted" "0,1"
group.long 0x10398++0x03
line.long 0x00 "FTDF_TXBYTE_M_REG,Transmit first byte mask register"
bitfld.long 0x00 1. "TX_LAST_SYMBOL_M,Mask bit for event &quot tx_last_symbol_e&quot" "0,1"
bitfld.long 0x00 0. "TXBYTE_M,Mask bit for event &quot txbyte_e&quot" "0,1"
group.long 0x10034++0x03
line.long 0x00 "FTDF_TXPIPEPROPDELAY_REG,Prop delay transmit register"
hexmask.long.byte 0x00 0.--7. 1. "TXPIPEPROPDELAY,Prop delay of tx pipe start to DPHY"
group.long 0x10484++0x03
line.long 0x00 "FTDF_TX_CLEAR_OS_REG,One shot register to clear flag"
bitfld.long 0x00 0.--3. "TX_FLAG_CLEAR,To clear tx_flag_stat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10240++0x03
line.long 0x00 "FTDF_TX_CONTROL_0_REG,Transmit control register"
bitfld.long 0x00 12.--14. "MACMAXCSMABACKOFFS,Maximum number of CSMA-CA backoffs (range 0-5)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "MACMINBE,Minimum Backoff Exponent (range 0-macMaxBE)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "MACMAXBE,Maximum Backoff Exponent (range 3-8)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DBGTXTRANSPARENTMODE,If 1 the MPDU octets pass transparently through the MAC in the transmit direction (for debug purpose)" "0,1"
group.long 0x00++0x03
line.long 0x00 "FTDF_TX_FIFO_0_0_REG,Address transmit fifo 0"
hexmask.long 0x00 0.--31. 1. "TX_FIFO,Transmit fifo buffer contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x80++0x03
line.long 0x00 "FTDF_TX_FIFO_1_0_REG,Address transmit fifo 1"
hexmask.long 0x00 0.--31. 1. "TX_FIFO,Transmit fifo buffer contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x100++0x03
line.long 0x00 "FTDF_TX_FIFO_2_0_REG,Address transmit fifo 2"
hexmask.long 0x00 0.--31. 1. "TX_FIFO,Transmit fifo buffer contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x180++0x03
line.long 0x00 "FTDF_TX_FIFO_3_0_REG,Address transmit fifo 3"
hexmask.long 0x00 0.--31. 1. "TX_FIFO,Transmit fifo buffer contains 32 addresses per entry (32b x 32a = 128B)"
group.long 0x10404++0x03
line.long 0x00 "FTDF_TX_FLAG_CLEAR_E_0_REG,Clear flag register 0"
bitfld.long 0x00 0. "TX_FLAG_CLEAR_E,When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set" "0,1"
group.long 0x10424++0x03
line.long 0x00 "FTDF_TX_FLAG_CLEAR_E_1_REG,Clear flag register 1"
bitfld.long 0x00 0. "TX_FLAG_CLEAR_E,When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set" "0,1"
group.long 0x10444++0x03
line.long 0x00 "FTDF_TX_FLAG_CLEAR_E_2_REG,Clear flag register 2"
bitfld.long 0x00 0. "TX_FLAG_CLEAR_E,When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set" "0,1"
group.long 0x10464++0x03
line.long 0x00 "FTDF_TX_FLAG_CLEAR_E_3_REG,Clear flag register 3"
bitfld.long 0x00 0. "TX_FLAG_CLEAR_E,When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set" "0,1"
group.long 0x10408++0x03
line.long 0x00 "FTDF_TX_FLAG_CLEAR_M_0_REG,Mask flag register 0"
bitfld.long 0x00 0. "TX_FLAG_CLEAR_M,Mask bit for event &quot tx_flag_clear_e&quot" "0,1"
group.long 0x10428++0x03
line.long 0x00 "FTDF_TX_FLAG_CLEAR_M_1_REG,Mask flag register 1"
bitfld.long 0x00 0. "TX_FLAG_CLEAR_M,Mask bit for event &quot tx_flag_clear_e&quot" "0,1"
group.long 0x10448++0x03
line.long 0x00 "FTDF_TX_FLAG_CLEAR_M_2_REG,Clear flag register 2"
bitfld.long 0x00 0. "TX_FLAG_CLEAR_M,Mask bit for event &quot tx_flag_clear_e&quot" "0,1"
group.long 0x10468++0x03
line.long 0x00 "FTDF_TX_FLAG_CLEAR_M_3_REG,Clear flag register 3"
bitfld.long 0x00 0. "TX_FLAG_CLEAR_M,Mask bit for event &quot tx_flag_clear_e&quot" "0,1"
group.long 0x10400++0x03
line.long 0x00 "FTDF_TX_FLAG_S_0_REG,Transmit packet ready for transmission register 0"
rbitfld.long 0x00 0. "TX_FLAG_STAT,Packet is ready for transmission" "0,1"
group.long 0x10420++0x03
line.long 0x00 "FTDF_TX_FLAG_S_1_REG,Transmit packet ready for transmission register 1"
rbitfld.long 0x00 0. "TX_FLAG_STAT,Packet is ready for transmission" "0,1"
group.long 0x10440++0x03
line.long 0x00 "FTDF_TX_FLAG_S_2_REG,Transmit packet ready for transmission register 2"
rbitfld.long 0x00 0. "TX_FLAG_STAT,Packet is ready for transmission" "0,1"
group.long 0x10460++0x03
line.long 0x00 "FTDF_TX_FLAG_S_3_REG,Transmit packet ready for transmission register 3"
rbitfld.long 0x00 0. "TX_FLAG_STAT,Packet is ready for transmission" "0,1"
group.long 0x200++0x03
line.long 0x00 "FTDF_TX_META_DATA_0_0_REG,Transmit metadata register 0"
bitfld.long 0x00 30. "CRC16_ENA,Indicates whether CRC16 insertion must be enabled or not" "0: No hardware inserted CRC16,1: Hardware inserts CRC16"
bitfld.long 0x00 28. "ACKREQUEST,Indicates whether an acknowledge is expected from the recipient of this packet" "0,1"
newline
bitfld.long 0x00 26. "CSMACA_ENA,Indicates whether a CSMA-CA is required for the transmission of this packet" "0,1"
bitfld.long 0x00 23.--25. "FRAMETYPE,Data/Cmd/Ack etc" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22. "PHYATTR_HSI,HighSide injection" "0,1"
bitfld.long 0x00 19.--21. "PHYATTR_RF_GPIO_PINS,Slot-basis signals mapped on GPIO via PPA" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--18. "PHYATTR_CALCAP,CalCap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11.--14. "PHYATTR_CN,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7.--10. "PHYATTR_DEM_PTI,DEM packet information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--6. 1. "FRAME_LENGTH,Frame length"
group.long 0x210++0x03
line.long 0x00 "FTDF_TX_META_DATA_0_1_REG,Transmit metadata register 1"
bitfld.long 0x00 30. "CRC16_ENA,Indicates whether CRC16 insertion must be enabled or not" "0: No hardware inserted CRC16,1: Hardware inserts CRC16"
bitfld.long 0x00 28. "ACKREQUEST,Indicates whether an acknowledge is expected from the recipient of this packet" "0,1"
newline
bitfld.long 0x00 26. "CSMACA_ENA,Indicates whether a CSMA-CA is required for the transmission of this packet" "0,1"
bitfld.long 0x00 23.--25. "FRAMETYPE,Data/Cmd/Ack etc" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22. "PHYATTR_HSI,HighSide injection" "0,1"
bitfld.long 0x00 19.--21. "PHYATTR_RF_GPIO_PINS,Slot-basis signals mapped on GPIO via PPA" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--18. "PHYATTR_CALCAP,CalCap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11.--14. "PHYATTR_CN,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7.--10. "PHYATTR_DEM_PTI,DEM packet information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--6. 1. "FRAME_LENGTH,Frame length"
group.long 0x220++0x03
line.long 0x00 "FTDF_TX_META_DATA_0_2_REG,Transmit metadata register 2"
bitfld.long 0x00 30. "CRC16_ENA,Indicates whether CRC16 insertion must be enabled or not" "0: No hardware inserted CRC16,1: Hardware inserts CRC16"
bitfld.long 0x00 28. "ACKREQUEST,Indicates whether an acknowledge is expected from the recipient of this packet" "0,1"
newline
bitfld.long 0x00 26. "CSMACA_ENA,Indicates whether a CSMA-CA is required for the transmission of this packet" "0,1"
bitfld.long 0x00 23.--25. "FRAMETYPE,Data/Cmd/Ack etc" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22. "PHYATTR_HSI,HighSide injection" "0,1"
bitfld.long 0x00 19.--21. "PHYATTR_RF_GPIO_PINS,Slot-basis signals mapped on GPIO via PPA" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--18. "PHYATTR_CALCAP,CalCap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11.--14. "PHYATTR_CN,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7.--10. "PHYATTR_DEM_PTI,DEM packet information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--6. 1. "FRAME_LENGTH,Frame length"
group.long 0x230++0x03
line.long 0x00 "FTDF_TX_META_DATA_0_3_REG,Transmit metadata register 3"
bitfld.long 0x00 30. "CRC16_ENA,Indicates whether CRC16 insertion must be enabled or not" "0: No hardware inserted CRC16,1: Hardware inserts CRC16"
bitfld.long 0x00 28. "ACKREQUEST,Indicates whether an acknowledge is expected from the recipient of this packet" "0,1"
newline
bitfld.long 0x00 26. "CSMACA_ENA,Indicates whether a CSMA-CA is required for the transmission of this packet" "0,1"
bitfld.long 0x00 23.--25. "FRAMETYPE,Data/Cmd/Ack etc" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 22. "PHYATTR_HSI,HighSide injection" "0,1"
bitfld.long 0x00 19.--21. "PHYATTR_RF_GPIO_PINS,Slot-basis signals mapped on GPIO via PPA" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--18. "PHYATTR_CALCAP,CalCap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11.--14. "PHYATTR_CN,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7.--10. "PHYATTR_DEM_PTI,DEM packet information" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--6. 1. "FRAME_LENGTH,Frame length"
group.long 0x204++0x03
line.long 0x00 "FTDF_TX_META_DATA_1_0_REG,Transmit metadata register 0"
hexmask.long.byte 0x00 0.--7. 1. "MACSN,Sequence Number of this packet"
group.long 0x214++0x03
line.long 0x00 "FTDF_TX_META_DATA_1_1_REG,Transmit metadata register 1"
hexmask.long.byte 0x00 0.--7. 1. "MACSN,Sequence Number of this packet"
group.long 0x224++0x03
line.long 0x00 "FTDF_TX_META_DATA_1_2_REG,Transmit metadata register 2"
hexmask.long.byte 0x00 0.--7. 1. "MACSN,Sequence Number of this packet"
group.long 0x234++0x03
line.long 0x00 "FTDF_TX_META_DATA_1_3_REG,Transmit metadata register 3"
hexmask.long.byte 0x00 0.--7. 1. "MACSN,Sequence Number of this packet"
group.long 0x10410++0x03
line.long 0x00 "FTDF_TX_PRIORITY_0_REG,Transmit priority register 0"
bitfld.long 0x00 4. "ISWAKEUP,A basic wake-up frame can be generated by the UMAC in the Tx buffer" "0,1"
bitfld.long 0x00 0.--3. "TX_PRIORITY,Priority of packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10430++0x03
line.long 0x00 "FTDF_TX_PRIORITY_1_REG,Transmit priority register 1"
bitfld.long 0x00 4. "ISWAKEUP,A basic wake-up frame can be generated by the UMAC in the Tx buffer" "0,1"
bitfld.long 0x00 0.--3. "TX_PRIORITY,Priority of packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10450++0x03
line.long 0x00 "FTDF_TX_PRIORITY_2_REG,Transmit priority register 2"
bitfld.long 0x00 4. "ISWAKEUP,A basic wake-up frame can be generated by the UMAC in the Tx buffer" "0,1"
bitfld.long 0x00 0.--3. "TX_PRIORITY,Priority of packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10470++0x03
line.long 0x00 "FTDF_TX_PRIORITY_3_REG,Transmit priority register 3"
bitfld.long 0x00 4. "ISWAKEUP,A basic wake-up frame can be generated by the UMAC in the Tx buffer" "0,1"
bitfld.long 0x00 0.--3. "TX_PRIORITY,Priority of packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x03
line.long 0x00 "FTDF_TX_RETURN_STATUS_0_0_REG,Transmit status register 0"
hexmask.long 0x00 0.--31. 1. "TXTIMESTAMP,Transmit Timestamp The TimeStamp of the transmitted packet"
group.long 0x250++0x03
line.long 0x00 "FTDF_TX_RETURN_STATUS_0_1_REG,Transmit status register 1"
hexmask.long 0x00 0.--31. 1. "TXTIMESTAMP,Transmit Timestamp The TimeStamp of the transmitted packet"
group.long 0x260++0x03
line.long 0x00 "FTDF_TX_RETURN_STATUS_0_2_REG,Transmit status register 2"
hexmask.long 0x00 0.--31. 1. "TXTIMESTAMP,Transmit Timestamp The TimeStamp of the transmitted packet"
group.long 0x270++0x03
line.long 0x00 "FTDF_TX_RETURN_STATUS_0_3_REG,Transmit status register 3"
hexmask.long 0x00 0.--31. 1. "TXTIMESTAMP,Transmit Timestamp The TimeStamp of the transmitted packet"
group.long 0x244++0x03
line.long 0x00 "FTDF_TX_RETURN_STATUS_1_0_REG,Transmit status register 0"
rbitfld.long 0x00 2.--4. "CSMACANRRETRIES,Number of CSMA-CA retries" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 1. "CSMACAFAIL,CSMA-CA status" "0: SUCCESS,1: FAIL"
newline
rbitfld.long 0x00 0. "ACKFAIL,Acknowledgement status" "0: SUCCESS,1: FAIL"
group.long 0x254++0x03
line.long 0x00 "FTDF_TX_RETURN_STATUS_1_1_REG,Transmit status register 1"
rbitfld.long 0x00 2.--4. "CSMACANRRETRIES,Number of CSMA-CA retries" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 1. "CSMACAFAIL,CSMA-CA status" "0: SUCCESS,1: FAIL"
newline
rbitfld.long 0x00 0. "ACKFAIL,Acknowledgement status" "0: SUCCESS,1: FAIL"
group.long 0x264++0x03
line.long 0x00 "FTDF_TX_RETURN_STATUS_1_2_REG,Transmit status register 2"
rbitfld.long 0x00 2.--4. "CSMACANRRETRIES,Number of CSMA-CA retries" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 1. "CSMACAFAIL,CSMA-CA status" "0: SUCCESS,1: FAIL"
newline
rbitfld.long 0x00 0. "ACKFAIL,Acknowledgement status" "0: SUCCESS,1: FAIL"
group.long 0x274++0x03
line.long 0x00 "FTDF_TX_RETURN_STATUS_1_3_REG,Transmit status register 3"
rbitfld.long 0x00 2.--4. "CSMACANRRETRIES,Number of CSMA-CA retries" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 1. "CSMACAFAIL,CSMA-CA status" "0: SUCCESS,1: FAIL"
newline
rbitfld.long 0x00 0. "ACKFAIL,Acknowledgement status" "0: SUCCESS,1: FAIL"
group.long 0x10480++0x03
line.long 0x00 "FTDF_TX_SET_OS_REG,One shot register to set flag"
bitfld.long 0x00 0.--3. "TX_FLAG_SET,To set tx_flag_stat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x11000++0x03
line.long 0x00 "FTDF_WAKEUPINTTHR_REG,Treshold value Wakeup timer"
hexmask.long 0x00 0.--31. 1. "WAKEUPINTTHR,Threshold for wake-up interrupt"
group.long 0x11004++0x03
line.long 0x00 "FTDF_WAKEUP_CONTROL_REG,Wakeup timer vcontrol register"
bitfld.long 0x00 1. "WAKEUPENABLE,If set the WakeUpIntThr is enabled to generate an interrupt" "0,1"
bitfld.long 0x00 0. "WAKEUPTIMERENABLE,A '1' Enables the wakeup timer" "0,1"
tree.end
tree "GP_TIMERS"
base ad:0x50003400
group.word 0x18++0x01
line.word 0x00 "BREATH_CFG_REG,Breath configuration register"
hexmask.word.byte 0x00 8.--15. 1. "BRTH_STEP,Defines the number of PWM periods minus 1 duty cycle will be changed"
hexmask.word.byte 0x00 0.--7. 1. "BRTH_DIV,Defines the division factor of the system clock to get to the PWM frequency.( = Sys Clock / (value+1)"
group.word 0x1E++0x01
line.word 0x00 "BREATH_CTRL_REG,Breath control register"
bitfld.word 0x00 1. "BRTH_PWM_POL,Define the output polarity" "0,1"
bitfld.word 0x00 0. "BRTH_EN,'1' enable the Breath operation" "0,1"
group.word 0x1A++0x01
line.word 0x00 "BREATH_DUTY_MAX_REG,Breath max duty cycle register"
hexmask.word.byte 0x00 0.--7. 1. "BRTH_DUTY_MAX,Defines the maximum duty cycle of the PWM breath function"
group.word 0x1C++0x01
line.word 0x00 "BREATH_DUTY_MIN_REG,Breath min duty cycle register"
hexmask.word.byte 0x00 0.--7. 1. "BRTH_DUTY_MIN,Defines the minimum duty cycle of the PWM breath function"
group.word 0x0E++0x01
line.word 0x00 "PWM2_END_CYCLE,Defines end Cycle for PWM2"
hexmask.word 0x00 0.--13. 1. "END_CYCLE,Define the cycle in which the PWM becomes low"
group.word 0x08++0x01
line.word 0x00 "PWM2_START_CYCLE,Defines start Cycle for PWM2"
hexmask.word 0x00 0.--13. 1. "START_CYCLE,Define the cycle in which the PWM becomes high"
group.word 0x10++0x01
line.word 0x00 "PWM3_END_CYCLE,Defines end Cycle for PWM3"
hexmask.word 0x00 0.--13. 1. "END_CYCLE,Define the cycle in which the PWM becomes low"
group.word 0x0A++0x01
line.word 0x00 "PWM3_START_CYCLE,Defines start Cycle for PWM3"
hexmask.word 0x00 0.--13. 1. "START_CYCLE,Define the cycle in which the PWM becomes high"
group.word 0x12++0x01
line.word 0x00 "PWM4_END_CYCLE,Defines end Cycle for PWM4"
hexmask.word 0x00 0.--13. 1. "END_CYCLE,Define the cycle in which the PWM becomes low"
group.word 0x0C++0x01
line.word 0x00 "PWM4_START_CYCLE,Defines start Cycle for PWM4"
hexmask.word 0x00 0.--13. 1. "START_CYCLE,Define the cycle in which the PWM becomes high"
group.word 0x00++0x01
line.word 0x00 "TIMER0_CTRL_REG,Timer0 control register"
bitfld.word 0x00 3. "PWM_MODE," "0,1"
bitfld.word 0x00 2. "TIM0_CLK_DIV," "0,1"
newline
bitfld.word 0x00 1. "TIM0_CLK_SEL," "0,1"
bitfld.word 0x00 0. "TIM0_CTRL," "0,1"
group.word 0x02++0x01
line.word 0x00 "TIMER0_ON_REG,Timer0 on control register"
hexmask.word 0x00 0.--15. 1. "TIM0_ON,Timer0 On reload value: If read the actual counter value ON_CNTer is returned"
group.word 0x04++0x01
line.word 0x00 "TIMER0_RELOAD_M_REG,16 bits reload value for Timer0"
hexmask.word 0x00 0.--15. 1. "TIM0_M,Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned"
group.word 0x06++0x01
line.word 0x00 "TIMER0_RELOAD_N_REG,16 bits reload value for Timer0"
hexmask.word 0x00 0.--15. 1. "TIM0_N,Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned"
group.word 0x16++0x01
line.word 0x00 "TRIPLE_PWM_CTRL_REG,PWM 2 3 4 Control register"
bitfld.word 0x00 2. "HW_PAUSE_EN,'1' = HW can pause PWM 2 3 4" "0,1"
bitfld.word 0x00 1. "SW_PAUSE_EN,'1' = PWM 2 3 4 is paused" "0,1"
newline
bitfld.word 0x00 0. "TRIPLE_PWM_ENABLE,'1' = PWM 2 3 4 is enabled" "0,1"
group.word 0x14++0x01
line.word 0x00 "TRIPLE_PWM_FREQUENCY,Defines the PMW2 3 4 frequency"
hexmask.word 0x00 0.--13. 1. "FREQ,Freq for PWM 2 3 4 period = timer_clk * ( FREQ+1)"
tree.end
tree "GPADC"
base ad:0x50001900
group.word 0x0A++0x01
line.word 0x00 "GP_ADC_CLEAR_INT_REG,General Purpose ADC Clear Interrupt Register"
hexmask.word 0x00 0.--15. 1. "GP_ADC_CLR_INT,Writing any value to this register will clear the ADC_INT interrupt"
group.word 0x02++0x01
line.word 0x00 "GP_ADC_CTRL2_REG,General Purpose ADC Second Control Register"
bitfld.word 0x00 12.--15. "GP_ADC_STORE_DEL," "?,1: Data is stored two ADC_CLK cycles after..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Data is stored sixteen ADC_CLK cycles after"
bitfld.word 0x00 8.--11. "GP_ADC_SMPL_TIME," "?,1: The sample time is 1*32 ADC_CLK cycles,2: The sample time is 2*32 ADC_CLK cycles,?,?,?,?,?,?,?,?,?,?,?,?,15: The sample time is 15*32 ADC_CLK cycles"
newline
bitfld.word 0x00 5.--7. "GP_ADC_CONV_NRS," "?,1: 2 samples are taken,2: 4 samples are taken,?,?,?,?,7: 128 samples are taken"
bitfld.word 0x00 3. "GP_ADC_DMA_EN," "0,1"
newline
bitfld.word 0x00 2. "GP_ADC_I20U," "0,1"
bitfld.word 0x00 1. "GP_ADC_IDYN," "0,1"
newline
bitfld.word 0x00 0. "GP_ADC_ATTN3X," "0,1"
group.word 0x04++0x01
line.word 0x00 "GP_ADC_CTRL3_REG,General Purpose ADC Third Control Register"
abitfld.word 0x00 8.--15. "GP_ADC_INTERVAL,Defines the interval between two ADC conversions in case GP_ADC_CONT is set" "0x00=0: No extra delay between two conversions,0x01=1: 1.024ms interval between two conversions,0x02=2: 2.048ms interval between two conversions,0xFF=255: 261.12ms interval between two.."
abitfld.word 0x00 0.--7. "GP_ADC_EN_DEL,Defines the delay for enabling the ADC after enabling the LDO" "0x00=0: Not allowed,0x01=1: 32x ADC_CLK period"
group.word 0x00++0x01
line.word 0x00 "GP_ADC_CTRL_REG,General Purpose ADC Control Register"
bitfld.word 0x00 15. "GP_ADC_LDO_ZERO," "0,1"
bitfld.word 0x00 14. "GP_ADC_CHOP," "0,1"
newline
bitfld.word 0x00 13. "GP_ADC_SIGN," "0,1"
bitfld.word 0x00 8.--12. "GP_ADC_SEL,ADC input selection" "0: P1[2] vs P1[4] All other combinations are P1[3],1: P1[4],2: P1[3],3: P0[7],4: AVS,5: Internal VDD_REF (used for offset calibration),6: VDCDC (see DCDC_TEST_0_REG.DCDC_OUTPUT_MONITOR,7: V33 (GP_ADC_ATTN3X scaler automatically..,8: V33 (GP_ADC_ATTN3X scaler automatically..,9: VBAT (5V to 1.2V scaler selected),?,?,?,?,?,?,16: P0[6],17: P1[0],18: P1[5],19: P2[4] All other combinations are reserved,?..."
newline
bitfld.word 0x00 7. "GP_ADC_MUTE," "0,1"
bitfld.word 0x00 6. "GP_ADC_SE," "0,1"
newline
bitfld.word 0x00 5. "GP_ADC_MINT," "0,1"
rbitfld.word 0x00 4. "GP_ADC_INT," "0,1"
newline
bitfld.word 0x00 3. "GP_ADC_CLK_SEL," "0,1"
bitfld.word 0x00 2. "GP_ADC_CONT," "0,1"
newline
bitfld.word 0x00 1. "GP_ADC_START," "0,1"
bitfld.word 0x00 0. "GP_ADC_EN," "0,1"
group.word 0x08++0x01
line.word 0x00 "GP_ADC_OFFN_REG,General Purpose ADC Negative Offset Register"
hexmask.word 0x00 0.--9. 1. "GP_ADC_OFFN,Offset adjust of 'negative' array of ADC-network (effective if GP_ADC_SE=0 or GP_ADC_SE=1 AND GP_ADC_SIGN=1 )"
group.word 0x06++0x01
line.word 0x00 "GP_ADC_OFFP_REG,General Purpose ADC Positive Offset Register"
hexmask.word 0x00 0.--9. 1. "GP_ADC_OFFP,Offset adjust of 'positive' array of ADC-network (effective if GP_ADC_SE=0 or GP_ADC_SE=1 AND GP_ADC_SIGN=0 )"
group.word 0x0C++0x01
line.word 0x00 "GP_ADC_RESULT_REG,General Purpose ADC Result Register"
hexmask.word 0x00 0.--15. 1. "GP_ADC_VAL,Returns the 10 up to 16 bits linear value of the last AD conversion"
tree.end
tree "GPIO"
base ad:0x50003000
group.word 0xD0++0x01
line.word 0x00 "GPIO_CLK_SEL,Select which clock to map on port in PPA"
bitfld.word 0x00 0.--2. "FUNC_CLOCK_SEL,Select which clock to map when PID = FUNC_CLOCK" "0: XTAL32K,1: RC32K,2: RCX,3: XTAL16M,4: RC16M,5: DIVN,6: Reserved,7: Reserved"
group.word 0x1E++0x01
line.word 0x00 "P00_MODE_REG,P00 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,Function of port" "0: GPIO PUPD (see above),1: UART_RX,2: UART_TX,3: UART_IRDA_RX,4: UART_IRDA_TX,5: UART2_RX,6: UART2_TX,7: UART2_IRDA_RX,8: UART2_IRDA_TX,9: UART2_CTSN,10: UART2_RTSN,11: SPI_DI,12: SPI_DO,13: SPI_CLK,14: SPI_EN,15: SPI2_DI,16: SPI2_DO,17: SPI2_CLK,18: SPI2_EN,19: I2C_SCL,20: I2C_SDA,21: I2C2_SCL,22: I2C2_SDA,23: PWM0,24: PWM1,25: PWM2,26: PWM3,27: PWM4,28: BLE_DIAG (ble_diag_0: P2_0,29: FTDF_DIAG (ftdf_diag_0: P1_4,30: PCM_DI,31: PCM_DO,32: PCM_FSC,33: PCM_CLK,34: PDM_DI,35: PDM_DO,36: PDM_CLK,37: USB_SOF,38: XTAL32 (only for P2[1:0]),39: QD_CHA_X,40: QD_CHB_X,41: QD_CHA_Y,42: QD_CHB_Y,43: QD_CHA_Z,44: QD_CHB_Z,45: IR_OUT,46: BREATH,47: KB_ROW,48: COEX_EXT_ACT0,49: COEX_EXT_ACT1,50: COEX_SMART_ACT,51: COEX_SMART_PRI,52: CLOCK,53: ONESHOT,54: PWM5,55: PORT0_DCF,56: PORT1_DCF,57: PORT2_DCF,58: PORT3_DCF,59: PORT4_DCF,60: RF_ANT_TRIM[0],61: RF_ANT_TRIM[1],62: RF_ANT_TRIM[2],?..."
group.word 0x20++0x01
line.word 0x00 "P01_MODE_REG,P01 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x22++0x01
line.word 0x00 "P02_MODE_REG,P02 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x24++0x01
line.word 0x00 "P03_MODE_REG,P03 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x26++0x01
line.word 0x00 "P04_MODE_REG,P04 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x28++0x01
line.word 0x00 "P05_MODE_REG,P05 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x2A++0x01
line.word 0x00 "P06_MODE_REG,P06 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x2C++0x01
line.word 0x00 "P07_MODE_REG,P07 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x00++0x01
line.word 0x00 "P0_DATA_REG,P0 Data input / output Register"
hexmask.word.byte 0x00 0.--7. 1. "P0_DATA,Set P0 output register when written Returns the value of P0 port when"
group.word 0xC0++0x01
line.word 0x00 "P0_PADPWR_CTRL_REG,P0 Output Power Control Register"
bitfld.word 0x00 6.--7. "P0_OUT_CTRL," "0,1,2,3"
group.word 0x14++0x01
line.word 0x00 "P0_RESET_DATA_REG,P0 Reset port pins Register"
hexmask.word.byte 0x00 0.--7. 1. "P0_RESET,Writing a 1 to P0[y] sets P0[y] to 0"
group.word 0x0A++0x01
line.word 0x00 "P0_SET_DATA_REG,P0 Set port pins Register"
hexmask.word.byte 0x00 0.--7. 1. "P0_SET,Writing a 1 to P0[y] sets P0[y] to 1"
group.word 0x2E++0x01
line.word 0x00 "P10_MODE_REG,P10 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x30++0x01
line.word 0x00 "P11_MODE_REG,P11 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x32++0x01
line.word 0x00 "P12_MODE_REG,P12 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x34++0x01
line.word 0x00 "P13_MODE_REG,P13 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x36++0x01
line.word 0x00 "P14_MODE_REG,P14 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x38++0x01
line.word 0x00 "P15_MODE_REG,P15 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x3A++0x01
line.word 0x00 "P16_MODE_REG,P24 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x3C++0x01
line.word 0x00 "P17_MODE_REG,P25 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x02++0x01
line.word 0x00 "P1_DATA_REG,P1 Data input / output Register"
hexmask.word.byte 0x00 0.--7. 1. "P1_DATA,Set P1 output register when written Returns the value of P1 port when"
group.word 0xC2++0x01
line.word 0x00 "P1_PADPWR_CTRL_REG,P1 Output Power Control Register"
hexmask.word.byte 0x00 0.--7. 1. "P1_OUT_CTRL,"
group.word 0x16++0x01
line.word 0x00 "P1_RESET_DATA_REG,P1 Reset port pins Register"
hexmask.word.byte 0x00 0.--7. 1. "P1_RESET,Writing a 1 to P1[y] sets P1[y] to 0"
group.word 0x0C++0x01
line.word 0x00 "P1_SET_DATA_REG,P1 Set port pins Register"
hexmask.word.byte 0x00 0.--7. 1. "P1_SET,Writing a 1 to P1[y] sets P1[y] to 1"
group.word 0x3E++0x01
line.word 0x00 "P20_MODE_REG,P20 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x40++0x01
line.word 0x00 "P21_MODE_REG,P21 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x42++0x01
line.word 0x00 "P22_MODE_REG,P22 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x44++0x01
line.word 0x00 "P23_MODE_REG,P23 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x46++0x01
line.word 0x00 "P24_MODE_REG,P24 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x04++0x01
line.word 0x00 "P2_DATA_REG,P2 Data input / output Register"
bitfld.word 0x00 0.--4. "P2_DATA,Set P2 output register when written Returns the value of P2 port when" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0xC4++0x01
line.word 0x00 "P2_PADPWR_CTRL_REG,P2 Output Power Control Register"
bitfld.word 0x00 0.--4. "P2_OUT_CTRL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x18++0x01
line.word 0x00 "P2_RESET_DATA_REG,P2 Reset port pins Register"
bitfld.word 0x00 0.--4. "P2_RESET,Writing a 1 to P2[y] sets P2[y] to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x0E++0x01
line.word 0x00 "P2_SET_DATA_REG,P2 Set port pins Register"
bitfld.word 0x00 0.--4. "P2_SET,Writing a 1 to P2[y] sets P2[y] to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x4E++0x01
line.word 0x00 "P30_MODE_REG,P30 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x50++0x01
line.word 0x00 "P31_MODE_REG,P31 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x52++0x01
line.word 0x00 "P32_MODE_REG,P32 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x54++0x01
line.word 0x00 "P33_MODE_REG,P33 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x56++0x01
line.word 0x00 "P34_MODE_REG,P34 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x58++0x01
line.word 0x00 "P35_MODE_REG,P35 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x5A++0x01
line.word 0x00 "P36_MODE_REG,P36 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x5C++0x01
line.word 0x00 "P37_MODE_REG,P37 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x06++0x01
line.word 0x00 "P3_DATA_REG,P3 Data input / output Register"
hexmask.word.byte 0x00 0.--7. 1. "P3_DATA,Set P3 output register when written Returns the value of P3 port when"
group.word 0xC6++0x01
line.word 0x00 "P3_PADPWR_CTRL_REG,P3 Output Power Control Register"
hexmask.word.byte 0x00 0.--7. 1. "P3_OUT_CTRL,"
group.word 0x1A++0x01
line.word 0x00 "P3_RESET_DATA_REG,P3 Reset port pins Register"
hexmask.word.byte 0x00 0.--7. 1. "P3_RESET,Writing a 1 to P3[y] sets P3[y] to 0"
group.word 0x10++0x01
line.word 0x00 "P3_SET_DATA_REG,P3 Set port pins Register"
hexmask.word.byte 0x00 0.--7. 1. "P3_SET,Writing a 1 to P3[y] sets P3[y] to 1"
group.word 0x5E++0x01
line.word 0x00 "P40_MODE_REG,P40 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x60++0x01
line.word 0x00 "P41_MODE_REG,P41 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x62++0x01
line.word 0x00 "P42_MODE_REG,P42 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x64++0x01
line.word 0x00 "P43_MODE_REG,P43 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x66++0x01
line.word 0x00 "P44_MODE_REG,P44 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x68++0x01
line.word 0x00 "P45_MODE_REG,P45 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x6A++0x01
line.word 0x00 "P46_MODE_REG,P46 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x6C++0x01
line.word 0x00 "P47_MODE_REG,P47 Mode Register"
bitfld.word 0x00 10. "PPOD," "0,1"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input pull-down selected,3: Output no resistors selected In ADC mode these"
newline
bitfld.word 0x00 0.--5. "PID,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x08++0x01
line.word 0x00 "P4_DATA_REG,P4 Data input / output Register"
hexmask.word.byte 0x00 0.--7. 1. "P4_DATA,Set P4 output register when written Returns the value of P4 port when"
group.word 0xC8++0x01
line.word 0x00 "P4_PADPWR_CTRL_REG,P4 Output Power Control Register"
hexmask.word.byte 0x00 0.--7. 1. "P4_OUT_CTRL,"
group.word 0x1C++0x01
line.word 0x00 "P4_RESET_DATA_REG,P4 Reset port pins Register"
hexmask.word.byte 0x00 0.--7. 1. "P4_RESET,Writing a 1 to P4[y] sets P4[y] to 0"
group.word 0x12++0x01
line.word 0x00 "P4_SET_DATA_REG,P4 Set port pins Register"
hexmask.word.byte 0x00 0.--7. 1. "P4_SET,Writing a 1 to P4[y] sets P4[y] to 1"
tree.end
tree "GPREG"
base ad:0x50003300
group.word 0x04++0x01
line.word 0x00 "DEBUG_REG,Various debug information register"
bitfld.word 0x00 0. "DEBUGS_FREEZE_EN,Default '1' freezing of the on-chip timers is enabled when the Cortex-M0 is halted in DEBUG State" "0,1"
group.word 0x0A++0x01
line.word 0x00 "ECC_BASE_ADDR_REG,Base address of the ECC Crypto memory register"
hexmask.word.byte 0x00 0.--6. 1. "ECC_BASE_ADDR,Contains the base address of the ECC Crypto memory"
group.word 0x08++0x01
line.word 0x00 "GP_CONTROL_REG,General purpose system control register"
hexmask.word.byte 0x00 8.--15. 1. "BLE_DEEPSLDUR_MONITOR,The 8 LSBs of the current value of the BLE Timer DEEPSLDUR"
rbitfld.word 0x00 2. "BLE_WAKEUP_LP_IRQ,The current value of the BLE_WAKEUP_LP_IRQ interrupt request" "0,1"
newline
bitfld.word 0x00 1. "BLE_H2H_BRIDGE_BYPASS,If '1' the AHB-to-AHB bridge is bypassed needed to access the BLE Register file only when the system clock source is the XTAL and both hclk and ble_hclk are running at 16MHz i.e" "0,1"
bitfld.word 0x00 0. "BLE_WAKEUP_REQ,If '1' the BLE wakes up" "0,1"
group.word 0x06++0x01
line.word 0x00 "GP_STATUS_REG,General purpose system status register"
bitfld.word 0x00 0. "CAL_PHASE,If '1' it designates that the chip is in Calibration Phase i.e" "0,1"
group.word 0x0C++0x01
line.word 0x00 "LED_CONTROL_REG,Controls muxing and enabling of the LEDs"
bitfld.word 0x00 5. "LED3_EN," "0,1"
bitfld.word 0x00 4. "LED2_EN," "0,1"
newline
bitfld.word 0x00 3. "LED1_EN," "0,1"
bitfld.word 0x00 2. "LED3_SRC_SEL," "0,1"
newline
bitfld.word 0x00 1. "LED2_SRC_SEL," "0,1"
bitfld.word 0x00 0. "LED1_SRC_SEL," "0,1"
group.word 0x10++0x01
line.word 0x00 "PLL_SYS_CTRL1_REG,System PLL control register 1"
hexmask.word.byte 0x00 8.--14. 1. "PLL_R_DIV,PLL Output dvider R (x means divide by x 0 means divide by 1)"
bitfld.word 0x00 2. "LDO_PLL_VREF_HOLD," "0,1"
newline
bitfld.word 0x00 1. "LDO_PLL_ENABLE," "0,1"
bitfld.word 0x00 0. "PLL_EN," "0,1"
group.word 0x12++0x01
line.word 0x00 "PLL_SYS_CTRL2_REG,System PLL control register 2"
bitfld.word 0x00 14. "PLL_SEL_MIN_CUR_INT," "0,1"
bitfld.word 0x00 12.--13. "PLL_DEL_SEL,PLL manual delay value for Phase Frequency Detector" "0: 0.493,1: 0.814,2: 1.13 ns <,3: 1.44 ns"
newline
hexmask.word.byte 0x00 0.--6. 1. "PLL_N_DIV,PLL Loop divider N (x means divide by x 0 means divide by 1)"
group.word 0x14++0x01
line.word 0x00 "PLL_SYS_CTRL3_REG,System PLL control register 3"
bitfld.word 0x00 15. "PLL_RECALIB,Recalibrate" "0,1"
bitfld.word 0x00 10.--14. "PLL_START_DEL,Programmable delay time for the loop filter voltage preset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--4. "PLL_ICP_SEL,PLL charge pump current select One LSB is 5uA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x16++0x01
line.word 0x00 "PLL_SYS_STATUS_REG,System PLL status register"
rbitfld.word 0x00 11. "PLL_CALIBR_END,Indicates that calibration has finished" "0,1"
rbitfld.word 0x00 5.--10. "PLL_PLL_BEST_MIN_CUR,Calibrated VCO frequency band" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.word 0x00 1. "LDO_PLL_OK," "0,1"
rbitfld.word 0x00 0. "PLL_LOCK_FINE," "0,1"
group.word 0x18++0x01
line.word 0x00 "PLL_SYS_TEST_REG,System PLL test register"
bitfld.word 0x00 13.--15. "PLL_LOCK_DET_RES_CNT,Lock measurement time in <tbd> clock cycle of xx usec" "0: <tbd> usec,?,?,?,?,?,?,7: <tbd> usec"
bitfld.word 0x00 11. "PLL_SEL_R_DIV_TEST,Select test mode for output divider R Maps PLL_R_DIV input on pins <tbd> and divider output on pin <tbd>" "0,1"
newline
bitfld.word 0x00 10. "PLL_SEL_N_DIV_TEST,Select test mode for loop divider N" "0,1"
bitfld.word 0x00 9. "PLL_CHANGE," "0,1"
newline
bitfld.word 0x00 8. "PLL_OPEN_LOOP," "0,1"
bitfld.word 0x00 7. "PLL_TEST_VCTR," "0,1"
newline
bitfld.word 0x00 1.--6. "PLL_MIN_CURRENT,VCO current trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0. "PLL_DIS_LOOPFILT," "0,1"
group.word 0x02++0x01
line.word 0x00 "RESET_FREEZE_REG,Controls unfreezing of various timers/counters (incl. DMA and USB)"
bitfld.word 0x00 7. "FRZ_SWTIM2,If '1' the SW Timer (TIMER2) continues '0' is discarded" "0,1"
bitfld.word 0x00 6. "FRZ_SWTIM1,If '1' the SW Timer (TIMER1) continues '0' is discarded" "0,1"
newline
bitfld.word 0x00 5. "FRZ_DMA,If '1' the DMA continues '0' is discarded" "0,1"
bitfld.word 0x00 4. "FRZ_USB,If '1' the USB continues '0' is discarded" "0,1"
newline
bitfld.word 0x00 3. "FRZ_WDOG,If '1' the watchdog timer continues '0' is discarded" "0,1"
bitfld.word 0x00 2. "FRZ_BLETIM,If '1' the BLE master clock continues '0' is discarded" "0,1"
newline
bitfld.word 0x00 1. "FRZ_SWTIM0,If '1' the SW Timer (TIMER0) continues '0' is discarded" "0,1"
bitfld.word 0x00 0. "FRZ_WKUPTIM,If '1' the Wake Up Timer continues '0' is discarded" "0,1"
group.word 0x00++0x01
line.word 0x00 "SET_FREEZE_REG,Controls freezing of various timers/counters (incl. DMA and USB)"
bitfld.word 0x00 7. "FRZ_SWTIM2,If '1' the SW Timer (TIMER2) is frozen '0' is discarded" "0,1"
bitfld.word 0x00 6. "FRZ_SWTIM1,If '1' the SW Timer (TIMER1) is frozen '0' is discarded" "0,1"
newline
bitfld.word 0x00 5. "FRZ_DMA,If '1' the DMA is frozen '0' is discarded" "0,1"
bitfld.word 0x00 4. "FRZ_USB,If '1' the USB is frozen '0' is discarded" "0,1"
newline
bitfld.word 0x00 3. "FRZ_WDOG,If '1' the watchdog timer is frozen '0' is discarded" "0,1"
bitfld.word 0x00 2. "FRZ_BLETIM,If '1' the BLE master clock is frozen '0' is discarded" "0,1"
newline
bitfld.word 0x00 1. "FRZ_SWTIM0,If '1' the SW Timer (TIMER0) is frozen '0' is discarded" "0,1"
bitfld.word 0x00 0. "FRZ_WKUPTIM,If '1' the Wake Up Timer is frozen '0' is discarded" "0,1"
tree.end
tree "I2C"
base ad:0x50001400
group.word 0x98++0x01
line.word 0x00 "I2C_ACK_GENERAL_CALL_REG,I2C ACK General Call Register"
bitfld.word 0x00 0. "ACK_GEN_CALL,ACK General Call" "0,1"
group.word 0x5C++0x01
line.word 0x00 "I2C_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register"
rbitfld.word 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.word 0x68++0x01
line.word 0x00 "I2C_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register"
rbitfld.word 0x00 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register" "0,1"
group.word 0x40++0x01
line.word 0x00 "I2C_CLR_INTR_REG,Clear Combined and Individual Interrupt Register"
rbitfld.word 0x00 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the I2C_TX_ABRT_SOURCE register" "0,1"
group.word 0x50++0x01
line.word 0x00 "I2C_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register"
rbitfld.word 0x00 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x58++0x01
line.word 0x00 "I2C_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x48++0x01
line.word 0x00 "I2C_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x44++0x01
line.word 0x00 "I2C_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x64++0x01
line.word 0x00 "I2C_CLR_START_DET_REG,Clear START_DET Interrupt Register"
rbitfld.word 0x00 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register" "0,1"
group.word 0x60++0x01
line.word 0x00 "I2C_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register"
rbitfld.word 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.word 0x54++0x01
line.word 0x00 "I2C_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register"
rbitfld.word 0x00 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the I2C_TX_ABRT_SOURCE register" "0,1"
group.word 0x4C++0x01
line.word 0x00 "I2C_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register"
rbitfld.word 0x00 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0xFA++0x01
line.word 0x00 "I2C_COMP2_VERSION,I2C Component2 Version Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP2_VERSION,"
group.word 0xF4++0x01
line.word 0x00 "I2C_COMP_PARAM1_REG,Component Parameter Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP_PARAM1,"
group.word 0xF6++0x01
line.word 0x00 "I2C_COMP_PARAM2_REG,Component Parameter Register 2"
hexmask.word 0x00 0.--15. 1. "IC_COMP_PARAM2,"
group.word 0xFE++0x01
line.word 0x00 "I2C_COMP_TYPE2_REG,I2C Component2 Type Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP2_TYPE,"
group.word 0xFC++0x01
line.word 0x00 "I2C_COMP_TYPE_REG,I2C Component Type Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP_TYPE,"
group.word 0xF8++0x01
line.word 0x00 "I2C_COMP_VERSION_REG,I2C Component Version Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP_VERSION,"
group.word 0x00++0x01
line.word 0x00 "I2C_CON_REG,I2C Control Register"
bitfld.word 0x00 6. "I2C_SLAVE_DISABLE,Slave enabled or disabled after reset is applied which means software does not have to configure the slave" "0: slave is enabled,1: slave is disabled Software should ensure that"
newline
bitfld.word 0x00 5. "I2C_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master" "0: disable,1: enable"
newline
bitfld.word 0x00 4. "I2C_10BITADDR_MASTER,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.word 0x00 3. "I2C_10BITADDR_SLAVE,When acting as a slave this bit controls whether the controller responds to 7- or 10-bit addresses" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.word 0x00 1.--2. "I2C_SPEED,These bits control at which speed the controller operates" "?,1: standard mode (100 kbit/s),2: fast mode (400 kbit/s),?..."
newline
bitfld.word 0x00 0. "I2C_MASTER_MODE,This bit controls whether the controller master is enabled" "0: master disabled,1: master enabled Software should ensure that"
group.word 0x10++0x01
line.word 0x00 "I2C_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register"
bitfld.word 0x00 8. "CMD,This bit controls whether a read or a write is performed" "0: Write When,1: "
newline
hexmask.word.byte 0x00 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus"
group.word 0x88++0x01
line.word 0x00 "I2C_DMA_CR_REG,DMA Control Register"
bitfld.word 0x00 1. "TDMAE,Transmit DMA Enable" "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.word 0x00 0. "RDMAE,Receive DMA Enable" "0: Receive DMA disabled,1: Receive DMA enabled"
group.word 0x90++0x01
line.word 0x00 "I2C_DMA_RDLR_REG,I2C Receive Data Level Register"
bitfld.word 0x00 0.--4. "DMARDL,Receive Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x8C++0x01
line.word 0x00 "I2C_DMA_TDLR_REG,DMA Transmit Data Level Register"
bitfld.word 0x00 0.--4. "DMATDL,Transmit Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x6C++0x01
line.word 0x00 "I2C_ENABLE_REG,I2C Enable Register"
bitfld.word 0x00 1. "I2C_ABORT," "0,1"
newline
bitfld.word 0x00 0. "CTRL_ENABLE,Controls whether the controller is enabled" "0: Disables the controller (TX and RX FIFOs are,1: Enables the controller Software can disable the"
group.word 0x9C++0x01
line.word 0x00 "I2C_ENABLE_STATUS_REG,I2C Enable Status Register"
rbitfld.word 0x00 2. "SLV_RX_DATA_LOST,Slave Received Data Lost" "0,1"
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rbitfld.word 0x00 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive)" "0,1"
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rbitfld.word 0x00 0. "IC_EN,ic_en Status" "0,1"
group.word 0x1C++0x01
line.word 0x00 "I2C_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register"
hexmask.word 0x00 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x20++0x01
line.word 0x00 "I2C_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register"
hexmask.word 0x00 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x0C++0x01
line.word 0x00 "I2C_HS_MADDR_REG,I2C High Speed Master Mode Code Address Register"
bitfld.word 0x00 0.--2. "IIC_HS_MAR,This bit field holds the value of the I2C HS mode master code" "0,1,2,3,4,5,6,7"
group.word 0xA0++0x01
line.word 0x00 "I2C_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size"
hexmask.word.byte 0x00 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.word 0x30++0x01
line.word 0x00 "I2C_INTR_MASK_REG,I2C Interrupt Mask Register"
bitfld.word 0x00 11. "M_GEN_CALL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 10. "M_START_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 9. "M_STOP_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 8. "M_ACTIVITY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 7. "M_RX_DONE,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 6. "M_TX_ABRT,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 5. "M_RD_REQ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 4. "M_TX_EMPTY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 3. "M_TX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 2. "M_RX_FULL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 1. "M_RX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 0. "M_RX_UNDER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
group.word 0x2C++0x01
line.word 0x00 "I2C_INTR_STAT_REG,I2C Interrupt Status Register"
rbitfld.word 0x00 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
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rbitfld.word 0x00 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
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rbitfld.word 0x00 9. "R_STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
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rbitfld.word 0x00 8. "R_ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
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rbitfld.word 0x00 7. "R_RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
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rbitfld.word 0x00 6. "R_TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
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rbitfld.word 0x00 5. "R_RD_REQ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
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rbitfld.word 0x00 4. "R_TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
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rbitfld.word 0x00 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
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rbitfld.word 0x00 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
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rbitfld.word 0x00 1. "R_RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
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rbitfld.word 0x00 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.word 0x34++0x01
line.word 0x00 "I2C_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register"
rbitfld.word 0x00 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
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rbitfld.word 0x00 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
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rbitfld.word 0x00 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
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rbitfld.word 0x00 8. "ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
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rbitfld.word 0x00 7. "RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
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rbitfld.word 0x00 6. "TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
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rbitfld.word 0x00 5. "RD_REQ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
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rbitfld.word 0x00 4. "TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
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rbitfld.word 0x00 3. "TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
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rbitfld.word 0x00 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
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rbitfld.word 0x00 1. "RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
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rbitfld.word 0x00 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.word 0x78++0x01
line.word 0x00 "I2C_RXFLR_REG,I2C Receive FIFO Level Register"
rbitfld.word 0x00 0.--5. "RXFLR,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x38++0x01
line.word 0x00 "I2C_RX_TL_REG,I2C Receive FIFO Threshold Register"
bitfld.word 0x00 0.--4. "RX_TL,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x08++0x01
line.word 0x00 "I2C_SAR_REG,I2C Slave Address Register"
hexmask.word 0x00 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave"
group.word 0x7C++0x01
line.word 0x00 "I2C_SDA_HOLD_REG,I2C SDA Hold Time Length Register"
hexmask.word 0x00 0.--15. 1. "IC_SDA_HOLD,SDA Hold time"
group.word 0x94++0x01
line.word 0x00 "I2C_SDA_SETUP_REG,I2C SDA Setup Register"
hexmask.word.byte 0x00 0.--7. 1. "SDA_SETUP,SDA Setup"
group.word 0x14++0x01
line.word 0x00 "I2C_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register"
hexmask.word 0x00 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x18++0x01
line.word 0x00 "I2C_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register"
hexmask.word 0x00 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x70++0x01
line.word 0x00 "I2C_STATUS_REG,I2C Status Register"
rbitfld.word 0x00 6. "SLV_ACTIVITY,Slave FSM Activity Status" "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave.."
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rbitfld.word 0x00 5. "MST_ACTIVITY,Master FSM Activity Status" "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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rbitfld.word 0x00 4. "RFF,Receive FIFO Completely Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
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rbitfld.word 0x00 3. "RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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rbitfld.word 0x00 2. "TFE,Transmit FIFO Completely Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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rbitfld.word 0x00 1. "TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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rbitfld.word 0x00 0. "I2C_ACTIVITY,I2C Activity Status" "0,1"
group.word 0x04++0x01
line.word 0x00 "I2C_TAR_REG,I2C Target Address Register"
bitfld.word 0x00 11. "SPECIAL,This bit indicates whether software performs a General Call or START BYTE command" "0: ignore bit 10 GC_OR_START and use IC_TAR..,1: perform special I2C command as specified in"
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bitfld.word 0x00 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a General Call or START byte command is to be performed by the controller" "0: General Call Address - after,1: START BYTE"
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hexmask.word 0x00 0.--9. 1. "IC_TAR,This is the target address for any master transaction"
group.word 0x74++0x01
line.word 0x00 "I2C_TXFLR_REG,I2C Transmit FIFO Level Register"
rbitfld.word 0x00 0.--5. "TXFLR,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x80++0x01
line.word 0x00 "I2C_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register"
rbitfld.word 0x00 15. "ABRT_SLVRD_INTX," "0,1"
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rbitfld.word 0x00 14. "ABRT_SLV_ARBLOST," "0,1"
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rbitfld.word 0x00 13. "ABRT_SLVFLUSH_TXFIFO," "0,1"
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rbitfld.word 0x00 12. "ARB_LOST," "0,1"
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rbitfld.word 0x00 11. "ABRT_MASTER_DIS," "0,1"
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rbitfld.word 0x00 10. "ABRT_10B_RD_NORSTRT," "0,1"
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rbitfld.word 0x00 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1) the SPECIAL bit must be cleared (I2C_TAR[11]) or the GC_OR_START bit must be cleared (I2C_TAR[10])" "0,1"
newline
rbitfld.word 0x00 8. "ABRT_HS_NORSTRT," "0,1"
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rbitfld.word 0x00 7. "ABRT_SBYTE_ACKDET," "0,1"
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rbitfld.word 0x00 6. "ABRT_HS_ACKDET," "0,1"
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rbitfld.word 0x00 5. "ABRT_GCALL_READ," "0,1"
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rbitfld.word 0x00 4. "ABRT_GCALL_NOACK," "0,1"
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rbitfld.word 0x00 3. "ABRT_TXDATA_NOACK," "0,1"
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rbitfld.word 0x00 2. "ABRT_10ADDR2_NOACK," "0,1"
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rbitfld.word 0x00 1. "ABRT_10ADDR1_NOACK," "0,1"
newline
rbitfld.word 0x00 0. "ABRT_7B_ADDR_NOACK," "0,1"
group.word 0x3C++0x01
line.word 0x00 "I2C_TX_TL_REG,I2C Transmit FIFO Threshold Register"
bitfld.word 0x00 0.--4. "TX_TL,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "I2C2"
base ad:0x50001500
group.word 0x98++0x01
line.word 0x00 "I2C2_ACK_GENERAL_CALL_REG,I2C ACK General Call Register"
bitfld.word 0x00 0. "ACK_GEN_CALL,ACK General Call" "0,1"
group.word 0x5C++0x01
line.word 0x00 "I2C2_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register"
rbitfld.word 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.word 0x68++0x01
line.word 0x00 "I2C2_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register"
rbitfld.word 0x00 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register" "0,1"
group.word 0x40++0x01
line.word 0x00 "I2C2_CLR_INTR_REG,Clear Combined and Individual Interrupt Register"
rbitfld.word 0x00 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the I2C_TX_ABRT_SOURCE register" "0,1"
group.word 0x50++0x01
line.word 0x00 "I2C2_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register"
rbitfld.word 0x00 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x58++0x01
line.word 0x00 "I2C2_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x48++0x01
line.word 0x00 "I2C2_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x44++0x01
line.word 0x00 "I2C2_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x64++0x01
line.word 0x00 "I2C2_CLR_START_DET_REG,Clear START_DET Interrupt Register"
rbitfld.word 0x00 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register" "0,1"
group.word 0x60++0x01
line.word 0x00 "I2C2_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register"
rbitfld.word 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.word 0x54++0x01
line.word 0x00 "I2C2_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register"
rbitfld.word 0x00 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the I2C_TX_ABRT_SOURCE register" "0,1"
group.word 0x4C++0x01
line.word 0x00 "I2C2_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register"
rbitfld.word 0x00 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0xFA++0x01
line.word 0x00 "I2C2_COMP2_VERSION,I2C Component2 Version Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP2_VERSION,"
group.word 0xF4++0x01
line.word 0x00 "I2C2_COMP_PARAM1_REG,Component Parameter Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP_PARAM1,"
group.word 0xF6++0x01
line.word 0x00 "I2C2_COMP_PARAM2_REG,Component Parameter Register 2"
hexmask.word 0x00 0.--15. 1. "IC_COMP_PARAM2,"
group.word 0xFE++0x01
line.word 0x00 "I2C2_COMP_TYPE2_REG,I2C Component2 Type Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP2_TYPE,"
group.word 0xFC++0x01
line.word 0x00 "I2C2_COMP_TYPE_REG,I2C Component Type Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP_TYPE,"
group.word 0xF8++0x01
line.word 0x00 "I2C2_COMP_VERSION_REG,I2C Component Version Register"
hexmask.word 0x00 0.--15. 1. "IC_COMP_VERSION,"
group.word 0x00++0x01
line.word 0x00 "I2C2_CON_REG,I2C Control Register"
bitfld.word 0x00 6. "I2C_SLAVE_DISABLE,Slave enabled or disabled after reset is applied which means software does not have to configure the slave" "0: slave is enabled,1: slave is disabled Software should ensure that"
newline
bitfld.word 0x00 5. "I2C_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master" "0: disable,1: enable"
newline
bitfld.word 0x00 4. "I2C_10BITADDR_MASTER,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.word 0x00 3. "I2C_10BITADDR_SLAVE,When acting as a slave this bit controls whether the controller responds to 7- or 10-bit addresses" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.word 0x00 1.--2. "I2C_SPEED,These bits control at which speed the controller operates" "?,1: standard mode (100 kbit/s),2: fast mode (400 kbit/s),?..."
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bitfld.word 0x00 0. "I2C_MASTER_MODE,This bit controls whether the controller master is enabled" "0: master disabled,1: master enabled Software should ensure that"
group.word 0x10++0x01
line.word 0x00 "I2C2_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register"
bitfld.word 0x00 8. "CMD,This bit controls whether a read or a write is performed" "0: Write When,1: "
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hexmask.word.byte 0x00 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus"
group.word 0x88++0x01
line.word 0x00 "I2C2_DMA_CR_REG,DMA Control Register"
bitfld.word 0x00 1. "TDMAE,Transmit DMA Enable" "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.word 0x00 0. "RDMAE,Receive DMA Enable" "0: Receive DMA disabled,1: Receive DMA enabled"
group.word 0x90++0x01
line.word 0x00 "I2C2_DMA_RDLR_REG,I2C Receive Data Level Register"
bitfld.word 0x00 0.--4. "DMARDL,Receive Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x8C++0x01
line.word 0x00 "I2C2_DMA_TDLR_REG,DMA Transmit Data Level Register"
bitfld.word 0x00 0.--4. "DMATDL,Transmit Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x6C++0x01
line.word 0x00 "I2C2_ENABLE_REG,I2C Enable Register"
bitfld.word 0x00 1. "I2C_ABORT," "0,1"
newline
bitfld.word 0x00 0. "CTRL_ENABLE,Controls whether the controller is enabled" "0: Disables the controller (TX and RX FIFOs are,1: Enables the controller Software can disable the"
group.word 0x9C++0x01
line.word 0x00 "I2C2_ENABLE_STATUS_REG,I2C Enable Status Register"
rbitfld.word 0x00 2. "SLV_RX_DATA_LOST,Slave Received Data Lost" "0,1"
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rbitfld.word 0x00 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive)" "0,1"
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rbitfld.word 0x00 0. "IC_EN,ic_en Status" "0,1"
group.word 0x1C++0x01
line.word 0x00 "I2C2_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register"
hexmask.word 0x00 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x20++0x01
line.word 0x00 "I2C2_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register"
hexmask.word 0x00 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x0C++0x01
line.word 0x00 "I2C2_HS_MADDR_REG,I2C High Speed Master Mode Code Address Register"
bitfld.word 0x00 0.--2. "IIC_HS_MAR,This bit field holds the value of the I2C HS mode master code" "0,1,2,3,4,5,6,7"
group.word 0xA0++0x01
line.word 0x00 "I2C2_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size"
hexmask.word.byte 0x00 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.word 0x30++0x01
line.word 0x00 "I2C2_INTR_MASK_REG,I2C Interrupt Mask Register"
bitfld.word 0x00 11. "M_GEN_CALL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 10. "M_START_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 9. "M_STOP_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 8. "M_ACTIVITY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 7. "M_RX_DONE,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 6. "M_TX_ABRT,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 5. "M_RD_REQ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 4. "M_TX_EMPTY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 3. "M_TX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 2. "M_RX_FULL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 1. "M_RX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
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bitfld.word 0x00 0. "M_RX_UNDER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
group.word 0x2C++0x01
line.word 0x00 "I2C2_INTR_STAT_REG,I2C Interrupt Status Register"
rbitfld.word 0x00 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
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rbitfld.word 0x00 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
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rbitfld.word 0x00 9. "R_STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
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rbitfld.word 0x00 8. "R_ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
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rbitfld.word 0x00 7. "R_RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
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rbitfld.word 0x00 6. "R_TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
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rbitfld.word 0x00 5. "R_RD_REQ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
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rbitfld.word 0x00 4. "R_TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
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rbitfld.word 0x00 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
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rbitfld.word 0x00 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
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rbitfld.word 0x00 1. "R_RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
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rbitfld.word 0x00 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.word 0x34++0x01
line.word 0x00 "I2C2_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register"
rbitfld.word 0x00 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
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rbitfld.word 0x00 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.word 0x00 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
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rbitfld.word 0x00 8. "ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
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rbitfld.word 0x00 7. "RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.word 0x00 6. "TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
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rbitfld.word 0x00 5. "RD_REQ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
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rbitfld.word 0x00 4. "TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
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rbitfld.word 0x00 3. "TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
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rbitfld.word 0x00 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
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rbitfld.word 0x00 1. "RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
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rbitfld.word 0x00 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.word 0x78++0x01
line.word 0x00 "I2C2_RXFLR_REG,I2C Receive FIFO Level Register"
rbitfld.word 0x00 0.--5. "RXFLR,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x38++0x01
line.word 0x00 "I2C2_RX_TL_REG,I2C Receive FIFO Threshold Register"
bitfld.word 0x00 0.--4. "RX_TL,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x08++0x01
line.word 0x00 "I2C2_SAR_REG,I2C Slave Address Register"
hexmask.word 0x00 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave"
group.word 0x7C++0x01
line.word 0x00 "I2C2_SDA_HOLD_REG,I2C SDA Hold Time Length Register"
hexmask.word 0x00 0.--15. 1. "IC_SDA_HOLD,SDA Hold time"
group.word 0x94++0x01
line.word 0x00 "I2C2_SDA_SETUP_REG,I2C SDA Setup Register"
hexmask.word.byte 0x00 0.--7. 1. "SDA_SETUP,SDA Setup"
group.word 0x14++0x01
line.word 0x00 "I2C2_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register"
hexmask.word 0x00 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x18++0x01
line.word 0x00 "I2C2_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register"
hexmask.word 0x00 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x70++0x01
line.word 0x00 "I2C2_STATUS_REG,I2C Status Register"
rbitfld.word 0x00 6. "SLV_ACTIVITY,Slave FSM Activity Status" "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave.."
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rbitfld.word 0x00 5. "MST_ACTIVITY,Master FSM Activity Status" "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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rbitfld.word 0x00 4. "RFF,Receive FIFO Completely Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
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rbitfld.word 0x00 3. "RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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rbitfld.word 0x00 2. "TFE,Transmit FIFO Completely Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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rbitfld.word 0x00 1. "TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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rbitfld.word 0x00 0. "I2C_ACTIVITY,I2C Activity Status" "0,1"
group.word 0x04++0x01
line.word 0x00 "I2C2_TAR_REG,I2C Target Address Register"
bitfld.word 0x00 11. "SPECIAL,This bit indicates whether software performs a General Call or START BYTE command" "0: ignore bit 10 GC_OR_START and use IC_TAR..,1: perform special I2C command as specified in"
newline
bitfld.word 0x00 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a General Call or START byte command is to be performed by the controller" "0: General Call Address - after,1: START BYTE"
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hexmask.word 0x00 0.--9. 1. "IC_TAR,This is the target address for any master transaction"
group.word 0x74++0x01
line.word 0x00 "I2C2_TXFLR_REG,I2C Transmit FIFO Level Register"
rbitfld.word 0x00 0.--5. "TXFLR,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x80++0x01
line.word 0x00 "I2C2_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register"
rbitfld.word 0x00 15. "ABRT_SLVRD_INTX," "0,1"
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rbitfld.word 0x00 14. "ABRT_SLV_ARBLOST," "0,1"
newline
rbitfld.word 0x00 13. "ABRT_SLVFLUSH_TXFIFO," "0,1"
newline
rbitfld.word 0x00 12. "ARB_LOST," "0,1"
newline
rbitfld.word 0x00 11. "ABRT_MASTER_DIS," "0,1"
newline
rbitfld.word 0x00 10. "ABRT_10B_RD_NORSTRT," "0,1"
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rbitfld.word 0x00 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1) the SPECIAL bit must be cleared (I2C_TAR[11]) or the GC_OR_START bit must be cleared (I2C_TAR[10])" "0,1"
newline
rbitfld.word 0x00 8. "ABRT_HS_NORSTRT," "0,1"
newline
rbitfld.word 0x00 7. "ABRT_SBYTE_ACKDET," "0,1"
newline
rbitfld.word 0x00 6. "ABRT_HS_ACKDET," "0,1"
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rbitfld.word 0x00 5. "ABRT_GCALL_READ," "0,1"
newline
rbitfld.word 0x00 4. "ABRT_GCALL_NOACK," "0,1"
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rbitfld.word 0x00 3. "ABRT_TXDATA_NOACK," "0,1"
newline
rbitfld.word 0x00 2. "ABRT_10ADDR2_NOACK," "0,1"
newline
rbitfld.word 0x00 1. "ABRT_10ADDR1_NOACK," "0,1"
newline
rbitfld.word 0x00 0. "ABRT_7B_ADDR_NOACK," "0,1"
group.word 0x3C++0x01
line.word 0x00 "I2C2_TX_TL_REG,I2C Transmit FIFO Threshold Register"
bitfld.word 0x00 0.--4. "TX_TL,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "IR"
base ad:0x50001700
group.word 0x08++0x01
line.word 0x00 "IR_CTRL_REG,IR control register"
bitfld.word 0x00 8. "IR_IRQ_EN," "0,1"
bitfld.word 0x00 7. "IR_LOGIC_ONE_FORMAT," "0,1"
newline
bitfld.word 0x00 6. "IR_LOGIC_ZERO_FORMAT," "0,1"
bitfld.word 0x00 5. "IR_INVERT_OUTPUT," "0,1"
newline
bitfld.word 0x00 4. "IR_REPEAT_TYPE," "0,1"
bitfld.word 0x00 3. "IR_TX_START," "0,1"
newline
bitfld.word 0x00 2. "IR_ENABLE," "0,1"
bitfld.word 0x00 1. "IR_REP_FIFO_RESET," "0,1"
newline
bitfld.word 0x00 0. "IR_CODE_FIFO_RESET," "0,1"
group.word 0x02++0x01
line.word 0x00 "IR_FREQ_CARRIER_OFF_REG,Defnes the carrier signal low duration"
hexmask.word 0x00 0.--9. 1. "IR_FREQ_CARRIER_OFF,Defines the carrier signal low duration in IR_clk cycles"
group.word 0x00++0x01
line.word 0x00 "IR_FREQ_CARRIER_ON_REG,Defines the carrier signal high duration"
hexmask.word 0x00 0.--9. 1. "IR_FREQ_CARRIER_ON,Defines the carrier signal high duration in IR_clk cycles"
group.word 0x12++0x01
line.word 0x00 "IR_IRQ_STATUS_REG,IR interrupt status register"
rbitfld.word 0x00 0. "IR_IRQ_ACK,When read Interrupt line is cleared" "0,1"
group.word 0x04++0x01
line.word 0x00 "IR_LOGIC_ONE_TIME_REG,Defines the logic one waveform"
hexmask.word.byte 0x00 8.--15. 1. "IR_LOGIC_ONE_MARK,Defines the mark duration in carrier clock cycles"
hexmask.word.byte 0x00 0.--7. 1. "IR_LOGIC_ONE_SPACE,Defines the space duration in carrier clock cycles"
group.word 0x06++0x01
line.word 0x00 "IR_LOGIC_ZERO_TIME_REG,Defines the logic zero wavefrom"
hexmask.word.byte 0x00 8.--15. 1. "IR_LOGIC_ZERO_MARK,Defines the mark duration in carrier clock cycles"
hexmask.word.byte 0x00 0.--7. 1. "IR_LOGIC_ZERO_SPACE,Defines the space duration in carrier clock cycles"
group.word 0x0E++0x01
line.word 0x00 "IR_MAIN_FIFO_REG,Main fifo write register"
hexmask.word 0x00 0.--15. 1. "IR_CODE_FIFO_DATA,Code FIFO data write port"
group.word 0x10++0x01
line.word 0x00 "IR_REPEAT_FIFO_REG,Repeat fifo write register"
hexmask.word 0x00 0.--15. 1. "IR_REPEAT_FIFO_DATA,Repeat FIFO data write port"
group.word 0x0C++0x01
line.word 0x00 "IR_REPEAT_TIME_REG,Defines the repeat time"
hexmask.word 0x00 0.--15. 1. "IR_REPEAT_TIME,Defines the repeat time in carrier clock cycles"
group.word 0x0A++0x01
line.word 0x00 "IR_STATUS_REG,IR status register"
rbitfld.word 0x00 10. "IR_BUSY," "0,1"
rbitfld.word 0x00 6.--9. "IR_REP_FIFO_WRDS,Contains the amount of words in Repeat FIFO (updated only on write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.word 0x00 0.--5. "IR_CODE_FIFO_WRDS,Contains the amount of words in Code FIFO (updated only on write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "KBSCAN"
base ad:0x50001600
group.word 0x02++0x01
line.word 0x00 "KBSCN_CTRL2_REG,Keyboard scanner control 2 register"
hexmask.word 0x00 0.--15. 1. "KBSCN_ROW_ACTIVE_TIME,Define the row active time in keyboard clock cycles"
group.word 0x00++0x01
line.word 0x00 "KBSCN_CTRL_REG,Keyboard scanner control register"
bitfld.word 0x00 14. "KBSCN_RESET_FIFO,'1' reset fifo read always '0'" "0,1"
bitfld.word 0x00 12.--13. "KBSCN_CLKDIV,Defines keyboard clk" "0,1,2,3"
newline
bitfld.word 0x00 11. "KBSCN_INACTIVE_EN,'1' After inactive time the keyboard scanner stops the key maxtrix scan" "0,1"
hexmask.word.byte 0x00 4.--10. 1. "KBSCN_INACTIVE_TIME,Defines the inactive time in scan cycles"
newline
bitfld.word 0x00 3. "KBSCN_IRQ_FIFO_MASK,'1' Enable IRQ for fifo over and under flow" "0,1"
bitfld.word 0x00 2. "KBSCN_IRQ_INACTIVE_MASK,'1' : Enable IRQ for inactive" "0,1"
newline
bitfld.word 0x00 1. "KBSCN_IRQ_MESSAGE_MASK,'1' : Enable IRQ for message" "0,1"
bitfld.word 0x00 0. "KBSCN_EN,'1' : Enable keyboard scanner Auto clear when inactive enable and inactive case" "0,1"
group.word 0x06++0x01
line.word 0x00 "KBSCN_DEBOUNCE_REG,Defines the debounce time for key press and release"
bitfld.word 0x00 6.--11. "KBSCN_DEBOUNCE_PRESS_TIME,Defines the press debounce time in cycles of full matrix scan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 0.--5. "KBSCN_DEBOUNCE_RELEASE_TIME,Defines the press debounce time in cycles of full matrix scan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x04++0x01
line.word 0x00 "KBSCN_MATRIX_SIZE_REG,Defines the number of rows and columns of the matrix"
bitfld.word 0x00 4.--8. "KBSCN_MATRIX_COLUMN,Defines the number of the columns of the keyboard matrix minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--3. "KBSCN_MATRIX_ROW,Defines the number of the rows of the keyboard matrix minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x0A++0x01
line.word 0x00 "KBSCN_MESSAGE_KEY_REG,Returns a key message from the message queue"
rbitfld.word 0x00 10. "KBSCN_LAST_ENTRY,'1' : this message is the last of the group message else '0'" "0,1"
rbitfld.word 0x00 9. "KBSCN_KEY_STATE,'0' : New key state is release '1' : New key state is press" "0,1"
newline
rbitfld.word 0x00 4.--8. "KBSCN_KEYID_COLUMN,Defines the column id of key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.word 0x00 0.--3. "KBSCN_KEYID_ROW,Defines the row id of key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x0C++0x01
line.word 0x00 "KBSCN_P00_MODE_REG,Defines the keyboard mode for P00"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x0E++0x01
line.word 0x00 "KBSCN_P01_MODE_REG,Defines the keyboard mode for P01"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x10++0x01
line.word 0x00 "KBSCN_P02_MODE_REG,Defines the keyboard mode for P02"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x12++0x01
line.word 0x00 "KBSCN_P03_MODE_REG,Defines the keyboard mode for P03"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x14++0x01
line.word 0x00 "KBSCN_P04_MODE_REG,Defines the keyboard mode for P04"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x16++0x01
line.word 0x00 "KBSCN_P05_MODE_REG,Defines the keyboard mode for P05"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x18++0x01
line.word 0x00 "KBSCN_P06_MODE_REG,Defines the keyboard mode for P06"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1A++0x01
line.word 0x00 "KBSCN_P07_MODE_REG,Defines the keyboard mode for P07"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1C++0x01
line.word 0x00 "KBSCN_P10_MODE_REG,Defines the keyboard mode for P10"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1E++0x01
line.word 0x00 "KBSCN_P11_MODE_REG,Defines the keyboard mode for P11"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x20++0x01
line.word 0x00 "KBSCN_P12_MODE_REG,Defines the keyboard mode for P12"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x22++0x01
line.word 0x00 "KBSCN_P13_MODE_REG,Defines the keyboard mode for P13"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x24++0x01
line.word 0x00 "KBSCN_P14_MODE_REG,Defines the keyboard mode for P14"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x26++0x01
line.word 0x00 "KBSCN_P15_MODE_REG,Defines the keyboard mode for P15"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x28++0x01
line.word 0x00 "KBSCN_P16_MODE_REG,Defines the keyboard mode for P16"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2A++0x01
line.word 0x00 "KBSCN_P17_MODE_REG,Defines the keyboard mode for P17"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2C++0x01
line.word 0x00 "KBSCN_P20_MODE_REG,Defines the keyboard mode for P20"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2E++0x01
line.word 0x00 "KBSCN_P21_MODE_REG,Defines the keyboard mode for P21"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x30++0x01
line.word 0x00 "KBSCN_P22_MODE_REG,Defines the keyboard mode for P22"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x32++0x01
line.word 0x00 "KBSCN_P23_MODE_REG,Defines the keyboard mode for P23"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x34++0x01
line.word 0x00 "KBSCN_P24_MODE_REG,Defines the keyboard mode for P24"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x3C++0x01
line.word 0x00 "KBSCN_P30_MODE_REG,Defines the keyboard mode for P30"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x3E++0x01
line.word 0x00 "KBSCN_P31_MODE_REG,Defines the keyboard mode for P31"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x40++0x01
line.word 0x00 "KBSCN_P32_MODE_REG,Defines the keyboard mode for P32"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x42++0x01
line.word 0x00 "KBSCN_P33_MODE_REG,Defines the keyboard mode for P33"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x44++0x01
line.word 0x00 "KBSCN_P34_MODE_REG,Defines the keyboard mode for P34"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x46++0x01
line.word 0x00 "KBSCN_P35_MODE_REG,Defines the keyboard mode for P35"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x48++0x01
line.word 0x00 "KBSCN_P36_MODE_REG,Defines the keyboard mode for P36"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x4A++0x01
line.word 0x00 "KBSCN_P37_MODE_REG,Defines the keyboard mode for P37"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x4C++0x01
line.word 0x00 "KBSCN_P40_MODE_REG,Defines the keyboard mode for P40"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x4E++0x01
line.word 0x00 "KBSCN_P41_MODE_REG,Defines the keyboard mode for P41"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x50++0x01
line.word 0x00 "KBSCN_P42_MODE_REG,Defines the keyboard mode for P42"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x52++0x01
line.word 0x00 "KBSCN_P43_MODE_REG,Defines the keyboard mode for P43"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x54++0x01
line.word 0x00 "KBSCN_P44_MODE_REG,Defines the keyboard mode for P44"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x56++0x01
line.word 0x00 "KBSCN_P45_MODE_REG,Defines the keyboard mode for P45"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
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bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x58++0x01
line.word 0x00 "KBSCN_P46_MODE_REG,Defines the keyboard mode for P46"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x5A++0x01
line.word 0x00 "KBSCN_P47_MODE_REG,Defines the keyboard mode for P47"
bitfld.word 0x00 6. "KBSCN_GPIO_EN,'1' GPIO is enable for row or column" "0,1"
bitfld.word 0x00 5. "KBSCN_ROW,'1' GPIO is row '0' GPIO is column" "0,1"
newline
bitfld.word 0x00 0.--4. "KBSCN_MODE,Defines the row/column index that has to be connected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x08++0x01
line.word 0x00 "KBSCN_STATUS_REG,keyboard scanner Interrupt status register"
rbitfld.word 0x00 8. "KBSCN_FIFO_UNDERFL,'1' Fifo Underflow occurred" "0,1"
rbitfld.word 0x00 7. "KBSCN_FIFO_OVERFL,'1' Fifo Overflow occurred" "0,1"
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rbitfld.word 0x00 2.--6. "KBSCN_NUM_MESSAGE,Defines how many messages there are in the fifo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.word 0x00 1. "KBSCN_INACTIVE_IRQ_STATUS,There is no keyboard activity for a predefined time" "0,1"
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rbitfld.word 0x00 0. "KBSCN_MES_IRQ_STATUS,There is at least one last message in the fifo" "0,1"
tree.end
tree "OTPC"
base ad:0x7F40000
group.long 0x0C++0x03
line.long 0x00 "OTPC_AHBADR_REG,AHB master start address"
hexmask.long 0x00 2.--31. 1. "OTPC_AHBADR,It is the AHB address used by the AHB master interface of the controller (the bits [31:2])"
group.long 0x10++0x03
line.long 0x00 "OTPC_CELADR_REG,Macrocell start address"
hexmask.long.word 0x00 0.--13. 1. "OTPC_CELADR,It represents an OTP address where the OTP word width should be considered equal to 32-bits"
group.long 0x18++0x03
line.long 0x00 "OTPC_FFPRT_REG,Ports access to fifo logic"
hexmask.long 0x00 0.--31. 1. "OTPC_FFPRT,Provides access to the fifo through an access port"
group.long 0x1C++0x03
line.long 0x00 "OTPC_FFRD_REG,The data which have taken with the latest read from the OTPC_FFPRT_REG"
hexmask.long 0x00 0.--31. 1. "OTPC_FFRD,Contains the value which taken from the fifo after a read of the OTPC_FFPRT_REG register"
group.long 0x00++0x03
line.long 0x00 "OTPC_MODE_REG,Mode register"
bitfld.long 0x00 9. "OTPC_MODE_RLD_RR_REQ,Write with 1 in order to be requested the reloading of the repair records" "0,1"
newline
bitfld.long 0x00 8. "OTPC_MODE_USE_SP_ROWS,Selects the memory area of the OTP cell that will be used" "0: Uses the normal memory area of the OTP cell,1: Uses the spare rows of the OTP cell This"
newline
bitfld.long 0x00 6. "OTPC_MODE_ERR_RESP_DIS,When is performed a read from the OTP memory in the MREAD mode a double error is likely be detected during the retrieving of the data from the OTP" "0: The OTP controller generates an ERROR response,1: Only the OTPC_STAT_REG[OTPC_STAT_RERROR] is"
newline
bitfld.long 0x00 5. "OTPC_MODE_FIFO_FLUSH,By writing with 1 removes any content from the fifo" "0,1"
newline
bitfld.long 0x00 4. "OTPC_MODE_USE_DMA,Selects the use of the dma when the controller is configured in one of the modes: AREAD or APROG" "0: The dma is not used,1: The dma is used"
newline
bitfld.long 0x00 0.--2. "OTPC_MODE_MODE,Defines the mode of operation of the OTPC controller" "0: STBY mode,1: MREAD mode,2: MPROG mode,3: AREAD mode,4: APROG mode,5: TBLANK mode,6: TDEC mode,7: TWR mode"
group.long 0x14++0x03
line.long 0x00 "OTPC_NWORDS_REG,Number of words"
hexmask.long.word 0x00 0.--13. 1. "OTPC_NWORDS,The number of words (minus one) for reading /programming during the AREAD/APROG mode"
group.long 0x04++0x03
line.long 0x00 "OTPC_PCTRL_REG,Bit-programming control register"
bitfld.long 0x00 15. "OTPC_PCTRL_PSTART,Write with '1' to trigger the programming of one OTP word in the case where the MPROG mode is selected" "0,1"
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bitfld.long 0x00 14. "OTPC_PCTRL_PRETRY,It distinguishes the first attempt of a programming of an OTP position from a retry of programming" "0: A new value will be programmed in a blank OTP,1: The programming that is applied is not the.."
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hexmask.long.word 0x00 0.--12. 1. "OTPC_PCTRL_WADDR,Defines the OTP position where will be programmed the 64-bits that are contained into the registers OTPC_PWORDx_REG"
group.long 0x24++0x03
line.long 0x00 "OTPC_PWORDH_REG,The 32 higher bits of the 64-bit word that will be programmed when the MPROG mode is used"
hexmask.long 0x00 0.--31. 1. "OTPC_PWORDH,Contains the upper 32 bits that can be programmed with the help of the OTPC_PCTRL_REG while the controller is in MPROG mode"
group.long 0x20++0x03
line.long 0x00 "OTPC_PWORDL_REG,The 32 lower bits of the 64-bit word that will be programmed when the MPROG mode is used"
hexmask.long 0x00 0.--31. 1. "OTPC_PWORDL,Contains the lower 32 bits that can be programmed with the help of the OTPC_PCTRL_REG while the controller is in MPROG mode"
group.long 0x08++0x03
line.long 0x00 "OTPC_STAT_REG,Status register"
hexmask.long.word 0x00 16.--29. 1. "OTPC_STAT_NWORDS,It contains the live value of the number of (32 bits) words that remain to be processed by the controller"
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rbitfld.long 0x00 8.--11. "OTPC_STAT_FWORDS,Indicates the number of words which contained in the fifo of the controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "OTPC_STAT_RERROR,Indicates that during a normal reading (MREAD or AREAD) was reported a double error by the SECDED logic" "0,1"
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rbitfld.long 0x00 6. "OTPC_STAT_ARDY,Should be used to monitor the progress of the AREAD and APROG modes" "0: One of the APROG or AREAD mode is selected,1: The controller is not in an active AREAD or"
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rbitfld.long 0x00 5. "OTPC_STAT_TERROR,Indicates the result of a test sequence" "0: The test sequence ends with no error,1: The test sequence has failed"
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rbitfld.long 0x00 4. "OTPC_STAT_TRDY,Indicates the state of a test mode" "0: The controller is busy,1: There is no active test mode"
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rbitfld.long 0x00 3. "OTPC_STAT_PZERO,Indicates that the programming sequence has been avoided during a programming request due to that the word that should be programmed is equal to zero" "0: At least one bit has been programmed into the..,1: The programming has not been performed"
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rbitfld.long 0x00 2. "OTPC_STAT_PERR_COR,Indicates that a correctable error has been occurred during the word programming process" "0: There is no correctable error in the,1: The process of word - programming reported a"
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rbitfld.long 0x00 1. "OTPC_STAT_PERR_UNC,Indicates that an uncorrectable error has been occurred during the word programming process" "0: There is no uncorrectable error in the,1: The process of word-programming failed due to.."
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rbitfld.long 0x00 0. "OTPC_STAT_PRDY,Indicates the state of a bit-programming process" "0: The controller is busy,1: The logic which performs bit-programming is.."
group.long 0x28++0x03
line.long 0x00 "OTPC_TIM1_REG,Various timing parameters of the OTP cell"
bitfld.long 0x00 31. "OTPC_TIM1_CC_T_25NS,The number of hclk_c clock periods (minus one) that give a time interval at least higher than 25ns" "0,1"
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bitfld.long 0x00 27.--30. "OTPC_TIM1_CC_T_200NS,The number of hclk_c clock periods (minus one) that give a time interval at least higher than 200ns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 22.--26. "OTPC_TIM1_CC_T_500NS,The number of hclk_c clock periods (minus one) that give a time interval at least higher than 500ns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--21. "OTPC_TIM1_CC_T_1US,The number of hclk_c clock periods (minus one) that give a time interval at least higher than 1us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 8.--15. 1. "OTPC_TIM1_CC_T_PW,The number of hclk_c clock periods (minus one) that give a time interval that is - at least higher than 4.8us - and lower than 5.2 us It is preferred the programmed value to give a time interval equal to 5us"
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hexmask.long.byte 0x00 0.--7. 1. "OTPC_TIM1_CC_T_CADX,The number of hclk_c clock periods (minus one) that give a time interval at least higher than 2us.It is used as a wait time each time where the OTP cell is enabled"
group.long 0x2C++0x03
line.long 0x00 "OTPC_TIM2_REG,Various timing parameters of the OTP cell"
bitfld.long 0x00 23. "OTPC_TIM2_RDENL_PROT,This bit has meaning only when the OTPC_TIM1_CC_T_25NS = 1 otherwise has no functionality" "0: The minimum number of clock cycles for which..,1: The minimum number of clock cycles for which.."
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hexmask.long.byte 0x00 16.--22. 1. "OTPC_TIM2_CC_T_BCHK,The number of hclk_c clock periods (minus one) that give a time interval between 100ns and 200ns"
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hexmask.long.word 0x00 0.--9. 1. "OTPC_TIM2_CC_STBY_THR,This register controls a power saving feature which is applicable only in MREAD mode"
tree.end
tree "QSPIC"
base ad:0xC000000
group.long 0x30++0x03
line.long 0x00 "QSPIC_BURSTBRK_REG,Read break sequence in Auto mode"
bitfld.long 0x00 20. "QSPIC_SEC_HF_DS,Disable output during the transmission of the second half (QSPIC_BRK_WRD[3:0])" "0: The controller drives the QSPI bus during the,1: The controller leaves the QSPI bus in Hi-Z"
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bitfld.long 0x00 18.--19. "QSPIC_BRK_TX_MD,The mode of the QSPI Bus during the transmission of the burst break sequence" "0: Single,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 17. "QSPIC_BRK_SZ,The size of Burst Break Sequence" "0: One byte (Send QSPIC_BRK_WRD[15:8]),1: Two bytes (Send QSPIC_BRK_WRD[15:0])"
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bitfld.long 0x00 16. "QSPIC_BRK_EN,Controls the application of a special command (read burst break sequence) that is used in order to force the device to abandon the continuous read mode" "0: The special command is not applied,1: the previous command that has been applied in"
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hexmask.long.word 0x00 0.--15. 1. "QSPIC_BRK_WRD,This is the value of a special command (read burst break sequence) that is applied by the controller to the external memory device in order to force the memory device to abandon the continuous read mode"
group.long 0x0C++0x03
line.long 0x00 "QSPIC_BURSTCMDA_REG,The way of reading in Auto mode (command register A)"
bitfld.long 0x00 30.--31. "QSPIC_DMY_TX_MD,It describes the mode of the SPI bus during the Dummy bytes phase" "0: Single SPI,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 28.--29. "QSPIC_EXT_TX_MD,It describes the mode of the SPI bus during the Extra Byte phase" "0: Single SPI,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 26.--27. "QSPIC_ADR_TX_MD,It describes the mode of the SPI bus during the address phase" "0: Single SPI,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 24.--25. "QSPIC_INST_TX_MD,It describes the mode of the SPI bus during the instruction phase" "0: Single SPI,1: Dual,2: Quad,3: Reserved"
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hexmask.long.byte 0x00 16.--23. 1. "QSPIC_EXT_BYTE,The value of an extra byte which will be transferred after address (only if QSPIC_EXT_BYTE_EN= 1)"
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hexmask.long.byte 0x00 8.--15. 1. "QSPIC_INST_WB,Instruction Value for Wrapping Burst"
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hexmask.long.byte 0x00 0.--7. 1. "QSPIC_INST,Instruction Value for Incremental Burst or Single read access"
group.long 0x10++0x03
line.long 0x00 "QSPIC_BURSTCMDB_REG,The way of reading in Auto mode (command register B)"
bitfld.long 0x00 15. "QSPIC_DMY_FORCE,By setting this bit the number of dummy bytes is forced to be equal to 3" "0: The number of dummy bytes is controlled by the,1: Three dummy bytes are used"
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bitfld.long 0x00 12.--14. "QSPIC_CS_HIGH_MIN,Between the transmissions of two different instructions to the flash memory the SPI bus stays in idle state (QSPI_CS high) for at least this number of QSPI_SCK clock cycles" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 10.--11. "QSPIC_WRAP_SIZE,It describes the selected data size of a wrapping burst (QSPIC_WRAP_MD)" "0: byte access (8-bits),1: half word access (16 bits),2: word access (32-bits),3: Reserved"
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bitfld.long 0x00 8.--9. "QSPIC_WRAP_LEN,It describes the selected length of a wrapping burst (QSPIC_WRAP_MD)" "0,1,2,3"
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bitfld.long 0x00 7. "QSPIC_WRAP_MD,Wrap mode" "0: The QSPIC_INST is the selected instruction at,1: The QSPIC_INST_WB is the selected instruction.."
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bitfld.long 0x00 6. "QSPIC_INST_MD,Instruction mode" "0: Transmit instruction at any burst access,1: Transmit instruction only in the first access"
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bitfld.long 0x00 4.--5. "QSPIC_DMY_NUM,Number of Dummy Bytes" "0: Zero Dummy Bytes (Don't Send Dummy Bytes),1: Send 1 Dummy Byte,2: Send 2 Dummy Bytes,3: Send 4 Dummy Bytes When QSPIC_DMY_FORCE is"
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bitfld.long 0x00 3. "QSPIC_EXT_HF_DS,Extra Half Disable Output" "0: if QSPIC_EXT_BYTE_EN=1 is transmitted the,1: if QSPIC_EXT_BYTE_EN=1 the output is disabled"
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bitfld.long 0x00 2. "QSPIC_EXT_BYTE_EN,Extra Byte Enable" "0: Don't Send QSPIC_EXT_BYTE,1: Send QSPIC_EXT_BYTE"
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bitfld.long 0x00 0.--1. "QSPIC_DAT_RX_MD,It describes the mode of the SPI bus during the data phase" "0: Single SPI,1: Dual,2: Quad,3: Reserved"
group.long 0x38++0x03
line.long 0x00 "QSPIC_CHCKERASE_REG,Check erase progress in Auto mode"
hexmask.long 0x00 0.--31. 1. "QSPIC_CHCKERASE,Writing any value to this register during erasing forces the controller to read the flash memory status register"
group.long 0x00++0x03
line.long 0x00 "QSPIC_CTRLBUS_REG,SPI Bus control register for the Manual mode"
bitfld.long 0x00 4. "QSPIC_DIS_CS,Write 1 to disable the chip select (active low) when the controller is in Manual mode" "0,1"
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bitfld.long 0x00 3. "QSPIC_EN_CS,Write 1 to enable the chip select (active low) when the controller is in Manual mode" "0,1"
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bitfld.long 0x00 2. "QSPIC_SET_QUAD,Write 1 to set the bus mode in Quad mode when the controller is in Manual mode" "0,1"
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bitfld.long 0x00 1. "QSPIC_SET_DUAL,Write 1 to set the bus mode in Dual mode when the controller is in Manual mode" "0,1"
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bitfld.long 0x00 0. "QSPIC_SET_SINGLE,Write 1 to set the bus mode in Single SPI mode when the controller is in Manual mode" "0,1"
group.long 0x04++0x03
line.long 0x00 "QSPIC_CTRLMODE_REG,Mode Control register"
bitfld.long 0x00 13. "QSPIC_USE_32BA,Controls the length of the address that the external memory device uses" "0: The external memory device uses 24 bits address,1: The external memory device uses 32 bits address"
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bitfld.long 0x00 12. "QSPIC_FORCENSEQ_EN,Controls the way with which is addressed by the QSPI controller a burst request from the AMBA bus" "0: The controller translates a burst access on the,1: The controller will split a burst access on the"
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bitfld.long 0x00 9.--11. "QSPIC_PCLK_MD,Read pipe clock delay relative to the falling edge of QSPI_SCK" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8. "QSPIC_RPIPE_EN,Controls the use of the data read pipe" "0: The read pipe is disabled the sampling clock is,1: The read pipe is enabled"
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bitfld.long 0x00 7. "QSPIC_RXD_NEG,Defines the clock edge that is used for the capturing of the received data when the read pipe is not active (QSPIC_RPIPE_EN = 0)" "0: Sampling of the received data with the positive,1: Sampling of the received data with the negative"
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bitfld.long 0x00 6. "QSPIC_HRDY_MD,This configuration bit is useful when the frequency of the QSPI clock is much lower than the clock of the AMBA bus in order to not locks the AMBA bus for a long time" "0: Adds wait states via hready signal when an,1: The controller don't adds wait states via the"
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bitfld.long 0x00 5. "QSPIC_IO3_DAT,The value of QSPI_IO3 pad if QSPI_IO3_OEN is 1" "0,1"
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bitfld.long 0x00 4. "QSPIC_IO2_DAT,The value of QSPI_IO2 pad if QSPI_IO2_OEN is 1" "0,1"
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bitfld.long 0x00 3. "QSPIC_IO3_OEN,QSPI_IO3 output enable" "0: The QSPI_IO3 pad is input,1: The QSPI_IO3 pad is output"
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bitfld.long 0x00 2. "QSPIC_IO2_OEN,QSPI_IO2 output enable" "0: The QSPI_IO2 pad is input,1: The QSPI_IO2 pad is output"
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bitfld.long 0x00 1. "QSPIC_CLK_MD,Mode of the generated QSPI_SCK clock" "0: Use Mode 0 for the QSPI_CLK,1: Use Mode 3 for the QSPI_CLK"
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bitfld.long 0x00 0. "QSPIC_AUTO_MD,Mode of operation" "0: The Manual Mode is selected,1: The Auto Mode is selected"
group.long 0x20++0x03
line.long 0x00 "QSPIC_DUMMYDATA_REG,Send dummy clocks to SPI Bus for the Manual mode"
hexmask.long 0x00 0.--31. 1. "QSPIC_DUMMYDATA,Writing to this register generates a number of clock pulses to the SPI bus"
group.long 0x28++0x03
line.long 0x00 "QSPIC_ERASECMDA_REG,The way of erasing in Auto mode (command register A)"
hexmask.long.byte 0x00 24.--31. 1. "QSPIC_RES_INST,The code value of the erase resume instruction"
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hexmask.long.byte 0x00 16.--23. 1. "QSPIC_SUS_INST,The code value of the erase suspend instruction"
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hexmask.long.byte 0x00 8.--15. 1. "QSPIC_WEN_INST,The code value of the write enable instruction"
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hexmask.long.byte 0x00 0.--7. 1. "QSPIC_ERS_INST,The code value of the erase instruction"
group.long 0x2C++0x03
line.long 0x00 "QSPIC_ERASECMDB_REG,The way of erasing in Auto mode (command register B)"
bitfld.long 0x00 24.--29. "QSPIC_RESSUS_DLY,Defines a timer that counts the minimum allowed delay between an erase suspend command and the previous erase resume command (or the initial erase command)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--19. "QSPIC_ERSRES_HLD,The controller must stay without flash memory reading requests for this number of AMBA hclk clock cycles before to perform the command of erase or erase resume" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10.--14. "QSPIC_ERS_CS_HI,After the execution of instructions: write enable erase erase suspend and erase resume the QSPI_CS remains high for at least this number of qspi bus clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "QSPIC_EAD_TX_MD,The mode of the QSPI Bus during the address phase of the erase instruction" "0: Single,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 6.--7. "QSPIC_RES_TX_MD,The mode of the QSPI Bus during the transmission of the resume instruction" "0: Single,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 4.--5. "QSPIC_SUS_TX_MD,The mode of the QSPI Bus during the transmission of the suspend instruction" "0: Single,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 2.--3. "QSPIC_WEN_TX_MD,The mode of the QSPI Bus during the transmission of the write enable instruction" "0: Single,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 0.--1. "QSPIC_ERS_TX_MD,The mode of the QSPI Bus during the instruction phase of the erase instruction" "0: Single,1: Dual,2: Quad,3: Reserved"
group.long 0x24++0x03
line.long 0x00 "QSPIC_ERASECTRL_REG,QSPI Erase control register"
rbitfld.long 0x00 25.--27. "QSPIC_ERS_STATE,It shows the progress of sector/block erasing (read only)" "0: No Erase,1: Pending erase request,2: Erase procedure is running,3: Suspended Erase procedure,4: Finishing the Erase procedure 101..111 =..,?..."
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bitfld.long 0x00 24. "QSPIC_ERASE_EN,During Manual mode (QSPIC_AUTO_MD = 0)" "0,1"
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hexmask.long.tbyte 0x00 4.--23. 1. "QSPIC_ERS_ADDR,Defines the address of the block/sector that is requested to be erased"
group.long 0x3C++0x03
line.long 0x00 "QSPIC_GP_REG,QSPI General Purpose control register"
bitfld.long 0x00 3.--4. "QSPIC_PADS_SLEW,QSPI pads slew rate control" "0: Rise=1.7 V/ns Fall=1.9 V/ns (weak),1: Rise=2.0 V/ns Fall=2.3 V/ns,2: Rise=2.3 V/ns Fall=2.6 V/ns,3: Rise=2.4 V/ns Fall=2.7 V/ns (strong) Conditions"
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bitfld.long 0x00 1.--2. "QSPIC_PADS_DRV,QSPI pads drive current" "0: 4 mA,1: 8 mA,2: 12 mA,3: 16 mA"
group.long 0x1C++0x03
line.long 0x00 "QSPIC_READDATA_REG,Read data from SPI Bus for the Manual mode"
hexmask.long 0x00 0.--31. 1. "QSPIC_READDATA,A read access at this register generates a data transfer from the external memory device to the QSPIC controller"
group.long 0x08++0x03
line.long 0x00 "QSPIC_RECVDATA_REG,Received data for the Manual mode"
hexmask.long 0x00 0.--31. 1. "QSPIC_RECVDATA,This register contains the received data when the QSPIC_READDATA_REG register is used in Manual mode in order to be retrieved data from the external memory device and QSPIC_HRDY_MD=1 && QSPIC_BUSY=0"
group.long 0x34++0x03
line.long 0x00 "QSPIC_STATUSCMD_REG,The way of reading the status of external device in Auto mode"
bitfld.long 0x00 22. "QSPIC_STSDLY_SEL,Defines the timer which is used to count the delay that it has to wait before to read the FLASH Status Register after an erase or an erase resume command" "0: The delay is controlled by the QSPIC_RESSTS_DLY,1: The delay is controlled by the QSPIC_RESSUS_DLY"
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bitfld.long 0x00 16.--21. "QSPIC_RESSTS_DLY,Defines a timer that counts the minimum required delay between the reading of the status register and of the previous erase or erase resume instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "QSPIC_BUSY_VAL,Defines the value of the Busy bit which means that the flash is busy" "0: The flash is busy when the Busy bit is equal..,1: The flash is busy when the Busy bit is equal.."
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bitfld.long 0x00 12.--14. "QSPIC_BUSY_POS,It describes who from the bits of status represents the Busy bit (7 - 0)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 10.--11. "QSPIC_RSTAT_RX_MD,The mode of the QSPI Bus during the receive status phase of the read status instruction" "0: Single,1: Dual,2: Quad,3: Reserved"
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bitfld.long 0x00 8.--9. "QSPIC_RSTAT_TX_MD,The mode of the QSPI Bus during the instruction phase of the read status instruction" "0: Single,1: Dual,2: Quad,3: Reserved"
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hexmask.long.byte 0x00 0.--7. 1. "QSPIC_RSTAT_INST,The code value of the read status instruction"
group.long 0x14++0x03
line.long 0x00 "QSPIC_STATUS_REG,The status register of the QSPI controller"
bitfld.long 0x00 0. "QSPIC_BUSY,The status of the SPI Bus" "0: The SPI Bus is idle,1: The SPI Bus is active"
group.long 0x40++0x03
line.long 0x00 "QSPIC_UCODE_START,QSPIC uCode memory"
hexmask.long 0x00 0.--31. 1. "QSPIC_UCODE_X,The first position of the memory (16 words x 32 bits) where a microcode should be placed ( X = 0 to 15)"
group.long 0x18++0x03
line.long 0x00 "QSPIC_WRITEDATA_REG,Write data to SPI Bus for the Manual mode"
hexmask.long 0x00 0.--31. 1. "QSPIC_WRITEDATA,Writing to this register is generating a data transfer from the controller to the external memory device"
tree.end
tree "QUAD"
base ad:0x50001A00
group.word 0x08++0x01
line.word 0x00 "QDEC_CLOCKDIV_REG,Quad decoder clock divider register"
hexmask.word 0x00 0.--9. 1. "clock_divider,Contains the number of the input clock cycles minus one that are required to generate one logic clock cycle"
group.word 0x00++0x01
line.word 0x00 "QDEC_CTRL_REG,Quad decoder control register"
bitfld.word 0x00 12. "CHZ_PORT_EN,'1' : Enable channel" "0,1"
bitfld.word 0x00 11. "CHY_PORT_EN,'1' : Enable channel" "0,1"
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bitfld.word 0x00 10. "CHX_PORT_EN,'1' : Enable channel" "0,1"
hexmask.word.byte 0x00 3.--9. 1. "QD_IRQ_THRES,The number of events on either counter (X or Y or Z) that need to be reached before an interrupt is generated"
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rbitfld.word 0x00 2. "QD_IRQ_STATUS,Interrupt Status" "0,1"
bitfld.word 0x00 1. "QD_IRQ_CLR,Writing 1 to this bit clears the interrupt" "0,1"
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bitfld.word 0x00 0. "QD_IRQ_MASK," "0,1"
group.word 0x02++0x01
line.word 0x00 "QDEC_XCNT_REG,Counter value of the X Axis"
hexmask.word 0x00 0.--15. 1. "X_counter,Contains a signed value of the events"
group.word 0x04++0x01
line.word 0x00 "QDEC_YCNT_REG,Counter value of the Y Axis"
hexmask.word 0x00 0.--15. 1. "Y_counter,Contains a signed value of the events"
group.word 0x06++0x01
line.word 0x00 "QDEC_ZCNT_REG,Counter value of the Z Axis"
hexmask.word 0x00 0.--15. 1. "Z_counter,Contains a signed value of the events"
tree.end
tree "SPI"
base ad:0x50001200
group.word 0x06++0x01
line.word 0x00 "SPI_CLEAR_INT_REG,SPI clear interrupt register"
hexmask.word 0x00 0.--15. 1. "SPI_CLEAR_INT,Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT] Reading returns 0"
group.word 0x00++0x01
line.word 0x00 "SPI_CTRL_REG,SPI control register 0"
bitfld.word 0x00 15. "SPI_EN_CTRL," "0,1"
bitfld.word 0x00 14. "SPI_MINT," "0,1"
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rbitfld.word 0x00 13. "SPI_INT_BIT," "0,1"
rbitfld.word 0x00 12. "SPI_DI,Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)" "0,1"
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rbitfld.word 0x00 11. "SPI_TXH," "0,1"
bitfld.word 0x00 10. "SPI_FORCE_DO," "0,1"
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bitfld.word 0x00 9. "SPI_RST," "0,1"
bitfld.word 0x00 7.--8. "SPI_WORD," "?,1: 16 bit mode only SPI_RX_TX_REG0 used,2: 32 bits mode SPI_RX_TX_REG0 & SPI_RX_TX_REG1..,3: 9 bits mode"
newline
bitfld.word 0x00 6. "SPI_SMN,Master/slave mode" "0: Master,1: Slave(SPI1 only)"
bitfld.word 0x00 5. "SPI_DO,Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1" "0,1"
newline
bitfld.word 0x00 3.--4. "SPI_CLK,Select SPI_CLK clock output frequency in master mode" "0: SPI_CLK / 8,1: SPI_CLK / 4,2: SPI_CLK / 2,3: SPI_CLK / 14"
bitfld.word 0x00 2. "SPI_POL,Select SPI_CLK polarity" "0: SPI_CLK is initially low,1: SPI_CLK is initially high"
newline
bitfld.word 0x00 1. "SPI_PHA,Select SPI_CLK phase" "0,1"
bitfld.word 0x00 0. "SPI_ON," "0,1"
group.word 0x08++0x01
line.word 0x00 "SPI_CTRL_REG1,SPI control register 1"
bitfld.word 0x00 4. "SPI_9BIT_VAL,Determines the value of the first bit in 9 bits SPI mode" "0,1"
rbitfld.word 0x00 3. "SPI_BUSY," "0,1"
newline
bitfld.word 0x00 2. "SPI_PRIORITY," "0,1"
bitfld.word 0x00 0.--1. "SPI_FIFO_MODE," "?,1: RX-FIFO used (Read Only Mode) TX-FIFO single,2: TX-FIFO used (Write Only Mode) RX-FIFO single,3: No FIFOs used (backwards compatible mode)"
group.word 0x02++0x01
line.word 0x00 "SPI_RX_TX_REG0,SPI RX/TX register0"
hexmask.word 0x00 0.--15. 1. "SPI_DATA0,Write: SPI_TX_REG0 output register 0 (TX-FIFO) Read: SPI_RX_REG0 input register 0 (RX-FIFO) In 8 or 9 bits mode bits 15 to 8 are not used they contain old data"
group.word 0x04++0x01
line.word 0x00 "SPI_RX_TX_REG1,SPI RX/TX register1"
hexmask.word 0x00 0.--15. 1. "SPI_DATA1,Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO) Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO) In 8 or 9 or 16 bits mode bits this register is not used"
tree.end
tree "SPI2"
base ad:0x50001300
group.word 0x06++0x01
line.word 0x00 "SPI2_CLEAR_INT_REG,SPI clear interrupt register"
hexmask.word 0x00 0.--15. 1. "SPI_CLEAR_INT,Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT] Reading returns 0"
group.word 0x00++0x01
line.word 0x00 "SPI2_CTRL_REG,SPI control register 0"
bitfld.word 0x00 15. "SPI_EN_CTRL," "0,1"
bitfld.word 0x00 14. "SPI_MINT," "0,1"
newline
rbitfld.word 0x00 13. "SPI_INT_BIT," "0,1"
rbitfld.word 0x00 12. "SPI_DI,Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)" "0,1"
newline
rbitfld.word 0x00 11. "SPI_TXH," "0,1"
bitfld.word 0x00 10. "SPI_FORCE_DO," "0,1"
newline
bitfld.word 0x00 9. "SPI_RST," "0,1"
bitfld.word 0x00 7.--8. "SPI_WORD," "?,1: 16 bit mode only SPI_RX_TX_REG0 used,2: 32 bits mode SPI_RX_TX_REG0 & SPI_RX_TX_REG1..,3: 9 bits mode"
newline
bitfld.word 0x00 6. "SPI_SMN,Master/slave mode" "0: Master,1: Slave(SPI1 only)"
bitfld.word 0x00 5. "SPI_DO,Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1" "0,1"
newline
bitfld.word 0x00 3.--4. "SPI_CLK,Select SPI_CLK clock output frequency in master mode" "0: SPI_CLK / 8,1: SPI_CLK / 4,2: SPI_CLK / 2,3: SPI_CLK / 14"
bitfld.word 0x00 2. "SPI_POL,Select SPI_CLK polarity" "0: SPI_CLK is initially low,1: SPI_CLK is initially high"
newline
bitfld.word 0x00 1. "SPI_PHA,Select SPI_CLK phase" "0,1"
bitfld.word 0x00 0. "SPI_ON," "0,1"
group.word 0x08++0x01
line.word 0x00 "SPI2_CTRL_REG1,SPI control register 1"
bitfld.word 0x00 4. "SPI_9BIT_VAL,Determines the value of the first bit in 9 bits SPI mode" "0,1"
rbitfld.word 0x00 3. "SPI_BUSY," "0,1"
newline
bitfld.word 0x00 2. "SPI_PRIORITY," "0,1"
bitfld.word 0x00 0.--1. "SPI_FIFO_MODE," "?,1: RX-FIFO used (Read Only Mode) TX-FIFO single,2: TX-FIFO used (Write Only Mode) RX-FIFO single,3: No FIFOs used (backwards compatible mode)"
group.word 0x02++0x01
line.word 0x00 "SPI2_RX_TX_REG0,SPI RX/TX register0"
hexmask.word 0x00 0.--15. 1. "SPI_DATA0,Write: SPI_TX_REG0 output register 0 (TX-FIFO) Read: SPI_RX_REG0 input register 0 (RX-FIFO) In 8 or 9 bits mode bits 15 to 8 are not used they contain old data"
group.word 0x04++0x01
line.word 0x00 "SPI2_RX_TX_REG1,SPI RX/TX register1"
hexmask.word 0x00 0.--15. 1. "SPI_DATA1,Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO) Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO) In 8 or 9 or 16 bits mode bits this register is not used"
tree.end
tree "TIMER1"
base ad:0x50000200
group.word 0x10++0x01
line.word 0x00 "CAPTIM_CAPTURE_GPIO1_REG,Capture Timer value for event on GPIO1"
hexmask.word 0x00 0.--15. 1. "CAPTIM_CAPTURE_GPIO1,Gives the Capture time for event on GPIO1"
group.word 0x12++0x01
line.word 0x00 "CAPTIM_CAPTURE_GPIO2_REG,Capture Timer value for event on GPIO2"
hexmask.word 0x00 0.--15. 1. "CAPTIM_CAPTURE_GPIO2,Gives the Capture time for event on GPIO2"
group.word 0x00++0x01
line.word 0x00 "CAPTIM_CTRL_REG,Capture Timer control register"
bitfld.word 0x00 7. "CAPTIM_SYS_CLK_EN,'1' When Capture Timer use the system clock else use the clock 32KHz" "0,1"
bitfld.word 0x00 6. "CAPTIM_FREE_RUN_MODE_EN,Only when timer counts up if it is '1' timer does not zero when reaches to reload value" "0,1"
newline
bitfld.word 0x00 5. "CAPTIM_IRQ_EN,'1' When Capture timer IRQ unmask '0' masked" "0,1"
bitfld.word 0x00 4. "CAPTIM_IN2_EVENT_FALL_EN,'1' When Input1 event type is falling edge '0' rising edge" "0,1"
newline
bitfld.word 0x00 3. "CAPTIM_IN1_EVENT_FALL_EN,'1' When Input2 event type is falling edge '0' rising edge" "0,1"
bitfld.word 0x00 2. "CAPTIM_COUNT_DOWN_EN,'1' when timer counts down '0' count up" "0,1"
newline
bitfld.word 0x00 1. "CAPTIM_ONESHOT_MODE_EN,'1' Capture Timer in OneShot mode '0' Capture/Timer mode" "0,1"
bitfld.word 0x00 0. "CAPTIM_EN,'1' Capture Timer enabled else disabled" "0,1"
group.word 0x06++0x01
line.word 0x00 "CAPTIM_GPIO1_CONF_REG,Capture Timer gpio1 selection"
bitfld.word 0x00 0.--5. "CAPTIM_GPIO1_CONF,Select one of the 37 GPIOs as IN1 Valid value 0-37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x08++0x01
line.word 0x00 "CAPTIM_GPIO2_CONF_REG,Capture Timer gpio2 selection"
bitfld.word 0x00 0.--5. "CAPTIM_GPIO2_CONF,Select one of the 37 GPIOs as IN2 Valid value 0-37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x0E++0x01
line.word 0x00 "CAPTIM_PRESCALER_REG,Capture Timer prescaler value"
hexmask.word 0x00 0.--15. 1. "CAPTIM_PRESCALER,Define the timer count frequncy"
group.word 0x14++0x01
line.word 0x00 "CAPTIM_PRESCALER_VAL_REG,Capture Timer interrupt status register"
hexmask.word 0x00 0.--15. 1. "CAPTIM_PRESCALER_VAL,Gives the current prescaler value"
group.word 0x18++0x01
line.word 0x00 "CAPTIM_PWM_DC_REG,Capture Timer pwm dc register"
hexmask.word 0x00 0.--15. 1. "CAPTIM_PWM_DC,Define the PWM duty cyucle = pwm_dc / ( pwm_freq+1)"
group.word 0x16++0x01
line.word 0x00 "CAPTIM_PWM_FREQ_REG,Capture Timer pwm frequency register"
hexmask.word 0x00 0.--15. 1. "CAPTIM_PWM_FREQ,Define the PWM frequency"
group.word 0x0A++0x01
line.word 0x00 "CAPTIM_RELOAD_REG,Capture Timer reload value and Delay in shot mode"
hexmask.word 0x00 0.--15. 1. "CAPTIM_RELOAD,Reload or max value in timer mode Delay phase duration in oneshot mode"
group.word 0x0C++0x01
line.word 0x00 "CAPTIM_SHOTWIDTH_REG,Capture Timer Shot duration in shot mode"
hexmask.word 0x00 0.--15. 1. "CAPTIM_SHOTWIDTH,Shot phase duration in oneshot mode"
group.word 0x04++0x01
line.word 0x00 "CAPTIM_STATUS_REG,Capture Timer status register"
rbitfld.word 0x00 2.--3. "CAPTIM_ONESHOT_PHASE," "?,1: Delay phase,2: Start Shot,3: Shot phase"
rbitfld.word 0x00 1. "CAPTIM_IN2_STATE,Gives the logic level of the IN1" "0,1"
newline
rbitfld.word 0x00 0. "CAPTIM_IN1_STATE,Gives the logic level of the IN2" "0,1"
group.word 0x02++0x01
line.word 0x00 "CAPTIM_TIMER_VAL_REG,Capture Timer counter value"
hexmask.word 0x00 0.--15. 1. "CAPTIM_TIMER_VALUE,Gives the current timer value"
tree.end
tree "TRNG"
base ad:0x50005000
group.long 0x00++0x03
line.long 0x00 "TRNG_CTRL_REG,TRNG control register"
bitfld.long 0x00 1. "TRNG_MODE," "0,1"
bitfld.long 0x00 0. "TRNG_ENABLE," "0,1"
group.long 0x04++0x03
line.long 0x00 "TRNG_FIFOLVL_REG,TRNG FIFO level register"
rbitfld.long 0x00 5. "TRNG_FIFOFULL," "0,1"
rbitfld.long 0x00 0.--4. "TRNG_FIFOLVL,Number of 32 bit words of random data in the FIFO (max 31) until the FIFO is full" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "TRNG_VER_REG,TRNG Version register"
hexmask.long.byte 0x00 24.--31. 1. "TRNG_MAJ,Major version number"
hexmask.long.byte 0x00 16.--23. 1. "TRNG_MIN,Minor version number"
newline
hexmask.long.word 0x00 0.--15. 1. "TRNG_SVN,SVN revision number"
tree.end
tree "UART"
base ad:0x50001000
group.word 0xF4++0x01
line.word 0x00 "UART_CPR_REG,Component Parameter Register"
hexmask.word 0x00 0.--15. 1. "CPR,Component Parameter Register"
group.long 0xFC++0x03
line.long 0x00 "UART_CTR_REG,Component Type Register"
hexmask.long 0x00 0.--31. 1. "CTR,Component Type Register"
group.word 0xC0++0x01
line.word 0x00 "UART_DLF_REG,Divisor Latch Fraction Register"
bitfld.word 0x00 0.--3. "UART_DLF,The fractional value is added to integer value set by DLH DLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x01
line.word 0x00 "UART_DMASA_REG,DMA Software Acknowledge"
bitfld.word 0x00 0. "DMASA,This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition" "0,1"
group.word 0x04++0x01
line.word 0x00 "UART_IER_DLH_REG,Interrupt Enable Register/Divisor Latch High"
bitfld.word 0x00 7. "PTIME_dlh7,Interrupt Enable Register: PTIME Programmable THRE Interrupt Mode Enable" "0: disabled,1: enabled"
bitfld.word 0x00 4.--6. "dlh6_4,Divisor Latch (High): DLH6 to DLH4 Bits 6 to 4 of the upper part of a 16-bit read/write Divisor Latch register that contains the baud rate divisor for the UART" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 3. "EDSSI_dlh3,Interrupt Enable Register: EDSSI Enable Modem Status Interrupt" "0: disabled,1: enabled Divisor Latch"
bitfld.word 0x00 2. "ELSI_dhl2,Interrupt Enable Register: ELSI Enable Receiver Line Status Interrupt" "0: disabled,1: enabled Divisor Latch"
newline
bitfld.word 0x00 1. "ETBEI_dlh1,Interrupt Enable Register: ETBEI Enable Transmit Holding Register Empty Interrupt" "0: disabled,1: enabled Divisor Latch"
bitfld.word 0x00 0. "ERBFI_dlh0,Interrupt Enable Register: ERBFI Enable Received Data Available Interrupt" "0: disabled,1: enabled Divisor Latch"
group.word 0x08++0x01
line.word 0x00 "UART_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register"
abitfld.word 0x00 0.--15. "IIR_FCR,Interrupt Identification Register: Bits[7:6] returns 00" "0x0001=1: no interrupt pending,0x000A=10: THR empty,0x0064=100: received data available,0x006E=110: receiver line status,0x006F=111: busy detect,0x044C=1100: character timeout"
group.word 0x0C++0x01
line.word 0x00 "UART_LCR_REG,Line Control Register"
bitfld.word 0x00 7. "UART_DLAB,Divisor Latch Access Bit" "0,1"
bitfld.word 0x00 6. "UART_BC,Break Control Bit" "0,1"
newline
bitfld.word 0x00 4. "UART_EPS,Even Parity Select" "0,1"
bitfld.word 0x00 3. "UART_PEN,Parity Enable" "0: parity disabled,1: parity enabled"
newline
bitfld.word 0x00 2. "UART_STOP,Number of stop bits" "0: 1 stop bit,1: 1.5 stop bits when DLS"
bitfld.word 0x00 0.--1. "UART_DLS,Data Length Select" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.word 0x14++0x01
line.word 0x00 "UART_LSR_REG,Line Status Register"
rbitfld.word 0x00 6. "UART_TEMT,Transmitter Empty bit" "0,1"
rbitfld.word 0x00 5. "UART_THRE,Transmit Holding Register Empty bit" "0,1"
newline
rbitfld.word 0x00 4. "UART_BI,Break Interrupt bit" "0,1"
rbitfld.word 0x00 3. "UART_FE,Framing Error bit" "0: no framing error,1: framing error Reading the LSR clears the FE bit"
newline
rbitfld.word 0x00 2. "UART_PE,Parity Error bit" "0: no parity error,1: parity error Reading the LSR clears the PE"
rbitfld.word 0x00 1. "UART_OE,Overrun error bit" "0: no overrun error,1: overrun error Reading the LSR clears the OE bit"
newline
rbitfld.word 0x00 0. "UART_DR,Data Ready bit" "0: no data ready,1: data ready This bit is cleared when"
group.word 0x10++0x01
line.word 0x00 "UART_MCR_REG,Modem Control Register"
bitfld.word 0x00 6. "UART_SIRE,SIR Mode Enable" "0: IrDA SIR Mode disabled,1: IrDA SIR Mode enabled"
bitfld.word 0x00 4. "UART_LB,LoopBack Bit" "0,1"
newline
bitfld.word 0x00 3. "UART_OUT2,OUT2" "0: out2_n de-asserted (logic 1),1: out2_n asserted (logic 0) Note that in Loopback"
bitfld.word 0x00 2. "UART_OUT1,OUT1" "0: out1_n de-asserted (logic 1),1: out1_n asserted (logic 0) Note that in Loopback"
group.word 0x00++0x01
line.word 0x00 "UART_RBR_THR_DLL_REG,Receive Buffer Register/Transmit Holding Register/Divisor Latch Low"
hexmask.word.byte 0x00 0.--7. 1. "RBR_THR_DLL,Receive Buffer Register: (RBR)"
group.word 0x90++0x01
line.word 0x00 "UART_SBCR_REG,Shadow Break Control Register"
bitfld.word 0x00 0. "UART_SHADOW_BREAK_CONTROL,Shadow Break Control Bit" "0,1"
group.word 0x1C++0x01
line.word 0x00 "UART_SCR_REG,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. "UART_SCRATCH_PAD,This register is for programmers to use as a temporary storage space"
group.word 0x88++0x01
line.word 0x00 "UART_SRR_REG,Software Reset Register"
bitfld.word 0x00 0. "UART_UR,UART Reset" "0,1"
group.long 0xF8++0x03
line.long 0x00 "UART_UCV_REG,Component Version"
hexmask.long 0x00 0.--31. 1. "UCV,Component Version"
group.word 0x7C++0x01
line.word 0x00 "UART_USR_REG,UART Status register"
rbitfld.word 0x00 0. "UART_BUSY,UART Busy" "0: DW_apb_uart is idle or inactive,1: DW_apb_uart is busy (actively transferring.."
tree.end
tree "UART2"
base ad:0x50001100
group.word 0xF4++0x01
line.word 0x00 "UART2_CPR_REG,Component Parameter Register"
hexmask.word 0x00 0.--15. 1. "CPR,Component Parameter Register"
group.long 0xFC++0x03
line.long 0x00 "UART2_CTR_REG,Component Type Register"
hexmask.long 0x00 0.--31. 1. "CTR,Component Type Register"
group.word 0xC0++0x01
line.word 0x00 "UART2_DLF_REG,Divisor Latch Fraction Register"
bitfld.word 0x00 0.--3. "UART_DLF,The fractional value is added to integer value set by DLH DLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x01
line.word 0x00 "UART2_DMASA_REG,DMA Software Acknowledge"
bitfld.word 0x00 0. "DMASA,This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition" "0,1"
group.word 0x70++0x01
line.word 0x00 "UART2_FAR_REG,FIFO Access Register"
rbitfld.word 0x00 0. "UART_FAR,Description: Writes will have no effect when FIFO_ACCESS == No always readable" "0: FIFO access mode disabled,1: FIFO access mode enabled Note that when the.."
group.word 0xA4++0x01
line.word 0x00 "UART2_HTX_REG,Halt TX"
bitfld.word 0x00 0. "UART_HALT_TX,This register is use to halt transmissions for testing so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled" "0: Halt TX disabled,1: Halt TX enabled Note if FIFOs are implemented"
group.word 0x04++0x01
line.word 0x00 "UART2_IER_DLH_REG,Interrupt Enable Register/Divisor Latch High"
bitfld.word 0x00 7. "PTIME_dlh7,Interrupt Enable Register: PTIME Programmable THRE Interrupt Mode Enable" "0: disabled,1: enabled"
newline
bitfld.word 0x00 4.--6. "dlh6_4,Divisor Latch (High): DLH6 to DLH4 Bits 6 to 4 of the upper part of a 16-bit read/write Divisor Latch register that contains the baud rate divisor for the UART" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 3. "EDSSI_dlh3,Interrupt Enable Register: EDSSI Enable Modem Status Interrupt" "0: disabled,1: enabled Divisor Latch"
newline
bitfld.word 0x00 2. "ELSI_dhl2,Interrupt Enable Register: ELSI Enable Receiver Line Status Interrupt" "0: disabled,1: enabled Divisor Latch"
newline
bitfld.word 0x00 1. "ETBEI_dlh1,Interrupt Enable Register: ETBEI Enable Transmit Holding Register Empty Interrupt" "0: disabled,1: enabled Divisor Latch"
newline
bitfld.word 0x00 0. "ERBFI_dlh0,Interrupt Enable Register: ERBFI Enable Received Data Available Interrupt" "0: disabled,1: enabled Divisor Latch"
group.word 0x08++0x01
line.word 0x00 "UART2_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register"
abitfld.word 0x00 0.--15. "IIR_FCR,Interrupt Identification Register reading this register FIFO Control Register writing to this register" "0x0000=0: mode 0,0x0001=1: mode 1 Bit[2] XMIT FIFO Reset (or..,0x000A=10: FIFO 1/4 full,0x000B=11: FIFO 1/2 full Bit[3] DMA Mode (or DMAM),0x0064=100: received data available,0x006E=110: receiver line status,0x006F=111: busy detect,0x044C=1100: character timeout"
group.word 0x0C++0x01
line.word 0x00 "UART2_LCR_REG,Line Control Register"
bitfld.word 0x00 7. "UART_DLAB,Divisor Latch Access Bit" "0,1"
newline
bitfld.word 0x00 6. "UART_BC,Break Control Bit" "0,1"
newline
bitfld.word 0x00 4. "UART_EPS,Even Parity Select" "0,1"
newline
bitfld.word 0x00 3. "UART_PEN,Parity Enable" "0: parity disabled,1: parity enabled"
newline
bitfld.word 0x00 2. "UART_STOP,Number of stop bits" "0: 1 stop bit,1: 1.5 stop bits when DLS"
newline
bitfld.word 0x00 0.--1. "UART_DLS,Data Length Select" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.word 0x14++0x01
line.word 0x00 "UART2_LSR_REG,Line Status Register"
rbitfld.word 0x00 7. "UART_RFE,Receiver FIFO Error bit" "0: no error in RX FIFO,1: error in RX FIFO This bit is cleared when the"
newline
rbitfld.word 0x00 6. "UART_TEMT,Transmitter Empty bit" "0,1"
newline
rbitfld.word 0x00 5. "UART_THRE,Transmit Holding Register Empty bit" "0,1"
newline
rbitfld.word 0x00 4. "UART_BI,Break Interrupt bit" "0,1"
newline
rbitfld.word 0x00 3. "UART_FE,Framing Error bit" "0: no framing error,1: framing error Reading the LSR clears the FE bit"
newline
rbitfld.word 0x00 2. "UART_PE,Parity Error bit" "0: no parity error,1: parity error Reading the LSR clears the PE"
newline
rbitfld.word 0x00 1. "UART_OE,Overrun error bit" "0: no overrun error,1: overrun error Reading the LSR clears the OE bit"
newline
rbitfld.word 0x00 0. "UART_DR,Data Ready bit" "0: no data ready,1: data ready This bit is cleared when"
group.word 0x10++0x01
line.word 0x00 "UART2_MCR_REG,Modem Control Register"
bitfld.word 0x00 6. "UART_SIRE,SIR Mode Enable" "0: IrDA SIR Mode disabled,1: IrDA SIR Mode enabled"
newline
bitfld.word 0x00 5. "UART_AFCE,Auto Flow Control Enable" "0: Auto Flow Control Mode disabled,1: Auto Flow Control Mode enabled"
newline
bitfld.word 0x00 4. "UART_LB,LoopBack Bit" "0,1"
newline
bitfld.word 0x00 3. "UART_OUT2,OUT2" "0: out2_n de-asserted (logic 1),1: out2_n asserted (logic 0) Note that in Loopback"
newline
bitfld.word 0x00 2. "UART_OUT1,OUT1" "0: out1_n de-asserted (logic 1),1: out1_n asserted (logic 0) Note that in Loopback"
newline
bitfld.word 0x00 1. "UART_RTS,Request to Send" "0,1"
group.word 0x18++0x01
line.word 0x00 "UART2_MSR_REG,Modem Status Register"
rbitfld.word 0x00 4. "UART_CTS,Clear to Send" "0: cts_n input is de-asserted (logic 1),1: cts_n input is asserted (logic 0) In Loopback"
newline
rbitfld.word 0x00 0. "UART_DCTS,Delta Clear to Send" "0: no change on cts_n since last read of MSR,1: change on cts_n since last read of MSR Reading"
group.word 0x00++0x01
line.word 0x00 "UART2_RBR_THR_DLL_REG,Receive Buffer Register/Transmit Holding Register/Divisor Latch Low"
hexmask.word.byte 0x00 0.--7. 1. "RBR_THR_DLL,Receive Buffer Register: (RBR)"
group.word 0x84++0x01
line.word 0x00 "UART2_RFL_REG,Receive FIFO Level"
hexmask.word 0x00 0.--15. 1. "UART_RECEIVE_FIFO_LEVEL,Receive FIFO Level"
group.word 0x90++0x01
line.word 0x00 "UART2_SBCR_REG,Shadow Break Control Register"
bitfld.word 0x00 0. "UART_SHADOW_BREAK_CONTROL,Shadow Break Control Bit" "0,1"
group.word 0x1C++0x01
line.word 0x00 "UART2_SCR_REG,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. "UART_SCRATCH_PAD,This register is for programmers to use as a temporary storage space"
group.word 0x94++0x01
line.word 0x00 "UART2_SDMAM_REG,Shadow DMA Mode"
bitfld.word 0x00 0. "UART_SHADOW_DMA_MODE,Shadow DMA Mode" "0: mode 0,1: mode 1"
group.word 0x98++0x01
line.word 0x00 "UART2_SFE_REG,Shadow FIFO Enable"
bitfld.word 0x00 0. "UART_SHADOW_FIFO_ENABLE,Shadow FIFO Enable" "0,1"
group.word 0x30++0x01
line.word 0x00 "UART2_SRBR_STHR0_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x58++0x01
line.word 0x00 "UART2_SRBR_STHR10_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x5C++0x01
line.word 0x00 "UART2_SRBR_STHR11_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x60++0x01
line.word 0x00 "UART2_SRBR_STHR12_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x64++0x01
line.word 0x00 "UART2_SRBR_STHR13_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x68++0x01
line.word 0x00 "UART2_SRBR_STHR14_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x6C++0x01
line.word 0x00 "UART2_SRBR_STHR15_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x34++0x01
line.word 0x00 "UART2_SRBR_STHR1_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x38++0x01
line.word 0x00 "UART2_SRBR_STHR2_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x3C++0x01
line.word 0x00 "UART2_SRBR_STHR3_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x40++0x01
line.word 0x00 "UART2_SRBR_STHR4_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x44++0x01
line.word 0x00 "UART2_SRBR_STHR5_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x48++0x01
line.word 0x00 "UART2_SRBR_STHR6_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x4C++0x01
line.word 0x00 "UART2_SRBR_STHR7_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x50++0x01
line.word 0x00 "UART2_SRBR_STHR8_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x54++0x01
line.word 0x00 "UART2_SRBR_STHR9_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x88++0x01
line.word 0x00 "UART2_SRR_REG,Software Reset Register"
bitfld.word 0x00 2. "UART_XFR,XMIT FIFO Reset" "0,1"
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bitfld.word 0x00 1. "UART_RFR,RCVR FIFO Reset" "0,1"
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bitfld.word 0x00 0. "UART_UR,UART Reset" "0,1"
group.word 0x8C++0x01
line.word 0x00 "UART2_SRTS_REG,Shadow Request to Send"
bitfld.word 0x00 0. "UART_SHADOW_REQUEST_TO_SEND,Shadow Request to Send" "0,1"
group.word 0x9C++0x01
line.word 0x00 "UART2_SRT_REG,Shadow RCVR Trigger"
bitfld.word 0x00 0.--1. "UART_SHADOW_RCVR_TRIGGER,Shadow RCVR Trigger" "0: 1 character in the FIFO,1: FIFO ? full,2: FIFO ? full,3: FIFO 2 less than full"
group.word 0xA0++0x01
line.word 0x00 "UART2_STET_REG,Shadow TX Empty Trigger"
bitfld.word 0x00 0.--1. "UART_SHADOW_TX_EMPTY_TRIGGER,Shadow TX Empty Trigger" "0: FIFO empty,1: 2 characters in the FIFO,2: FIFO ? full,3: FIFO ? full"
group.word 0x80++0x01
line.word 0x00 "UART2_TFL_REG,Transmit FIFO Level"
hexmask.word 0x00 0.--15. 1. "UART_TRANSMIT_FIFO_LEVEL,Transmit FIFO Level"
group.long 0xF8++0x03
line.long 0x00 "UART2_UCV_REG,Component Version"
hexmask.long 0x00 0.--31. 1. "UCV,Component Version"
group.word 0x7C++0x01
line.word 0x00 "UART2_USR_REG,UART Status Register"
rbitfld.word 0x00 4. "UART_RFF,Receive FIFO Full" "0: Receive FIFO not full,1: Receive FIFO Full This bit is cleared when the"
newline
rbitfld.word 0x00 3. "UART_RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty This bit is cleared"
newline
rbitfld.word 0x00 2. "UART_TFE,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty This bit is cleared when"
newline
rbitfld.word 0x00 1. "UART_TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full This bit is cleared"
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rbitfld.word 0x00 0. "UART_BUSY,UART Busy" "0: DW_apb_uart is idle or inactive,1: DW_apb_uart is busy (actively transferring.."
tree.end
tree "USB"
base ad:0x50001800
group.word 0x10++0x01
line.word 0x00 "USB_ALTEV_REG,Alternate Event Register"
bitfld.word 0x00 7. "USB_RESUME,Resume Resume signalling is detected on the USB when the device is in Suspend state (NFS in the NFSR register is set to SUSPEND) and a non IDLE signal is present on the USB indicating that this device should begin it's wake-up sequence and.." "0,1"
bitfld.word 0x00 6. "USB_RESET,Reset This bit is set to 1 when 2.5 ?? s of SEO have been detected on the upstream port" "0,1"
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bitfld.word 0x00 5. "USB_SD5,Suspend Detect 5 ms This bit is set to 1 after 5 ms of IDLE have been detected on the upstream port indicating that this device is permitted to perform a remote wake-up operation" "0,1"
bitfld.word 0x00 4. "USB_SD3,Suspend Detect 3 ms This bit is set to 1 after 3 ms of IDLE have been detected on the upstream port indicating that the device should be suspended" "0,1"
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bitfld.word 0x00 3. "USB_EOP,End of Packet A valid EOP sequence was been detected on the USB" "0,1"
group.word 0x12++0x01
line.word 0x00 "USB_ALTMSK_REG,Alternate Mask Register"
bitfld.word 0x00 7. "USB_M_RESUME,A bit set to 1 in this register enables automatic setting of the ALT bit in the MAEV register when the respective event in the ALTEV register occurs" "0,1"
bitfld.word 0x00 6. "USB_M_RESET,Same Bit Definition as ALTEV Register" "0,1"
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bitfld.word 0x00 5. "USB_M_SD5,Same Bit Definition as ALTEV Register" "0,1"
bitfld.word 0x00 4. "USB_M_SD3,Same Bit Definition as ALTEV Register" "0,1"
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bitfld.word 0x00 3. "USB_M_EOP,Same Bit Definition as ALTEV Register" "0,1"
group.word 0xD4++0x01
line.word 0x00 "USB_CHARGER_CTRL_REG,USB Charger Control Register"
bitfld.word 0x00 5. "IDM_SINK_ON," "0,1"
bitfld.word 0x00 4. "IDP_SINK_ON," "0,1"
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bitfld.word 0x00 3. "VDM_SRC_ON," "0,1"
bitfld.word 0x00 2. "VDP_SRC_ON," "0,1"
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bitfld.word 0x00 1. "IDP_SRC_ON," "0,1"
bitfld.word 0x00 0. "USB_CHARGE_ON," "0,1"
group.word 0xD6++0x01
line.word 0x00 "USB_CHARGER_STAT_REG,USB Charger Status Register"
rbitfld.word 0x00 5. "USB_DM_VAL2," "0,1"
rbitfld.word 0x00 4. "USB_DP_VAL2," "0,1"
newline
rbitfld.word 0x00 3. "USB_DM_VAL," "0,1"
rbitfld.word 0x00 2. "USB_DP_VAL," "0,1"
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rbitfld.word 0x00 1. "USB_CHG_DET," "0,1"
rbitfld.word 0x00 0. "USB_DCP_DET," "0,1"
group.word 0xD0++0x01
line.word 0x00 "USB_DMA_CTRL_REG,USB DMA control register"
bitfld.word 0x00 6. "USB_DMA_EN," "0,1"
bitfld.word 0x00 3.--5. "USB_DMA_TX," "?,1: DMA channels 1 is connected Tx USB Endpoint 3,2: DMA channels 1 is connected Tx USB Endpoint 5,?..."
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bitfld.word 0x00 0.--2. "USB_DMA_RX," "?,1: DMA channels 0 is connected Rx USB Endpoint 4,2: DMA channels 0 is connected Rx USB Endpoint 6,?..."
group.word 0x48++0x01
line.word 0x00 "USB_EP0_NAK_REG,EP0 INNAK and OUTNAK Register"
rbitfld.word 0x00 1. "USB_EP0_OUTNAK,End point 0 OUT NAK This bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1) in response to an OUT token" "0,1"
rbitfld.word 0x00 0. "USB_EP0_INNAK,End point 0 IN NAK This bit is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1) in response to an IN token" "0,1"
group.word 0x40++0x01
line.word 0x00 "USB_EPC0_REG,Endpoint Control 0 Register"
bitfld.word 0x00 7. "USB_STALL,Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: - The transmit FIFO is enabled and an IN token is received" "0,1"
bitfld.word 0x00 6. "USB_DEF,Default Address When set to 1 the device responds to the default address regardless of the contents of FAR6-0/EP03-0 fields" "0,1"
newline
rbitfld.word 0x00 0.--3. "USB_EP,Endpoint Address This field holds the 4-bit Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x50++0x01
line.word 0x00 "USB_EPC1_REG,Endpoint Control Register 1"
bitfld.word 0x00 7. "USB_STALL,Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received" "0,1"
bitfld.word 0x00 5. "USB_ISO,Isochronous When this bit is set to 1 the endpoint is isochronous" "0,1"
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bitfld.word 0x00 4. "USB_EP_EN,Endpoint Enable When this bit is set to 1 the EP[3:0] field is used in address comparison together with the AD[6:0] field in the FAR register" "0,1"
bitfld.word 0x00 0.--3. "USB_EP,Endpoint Address This 4-bit field holds the endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x58++0x01
line.word 0x00 "USB_EPC2_REG,Endpoint Control Register 2"
bitfld.word 0x00 7. "USB_STALL,Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received" "0,1"
bitfld.word 0x00 5. "USB_ISO,Isochronous When this bit is set to 1 the endpoint is isochronous" "0,1"
newline
bitfld.word 0x00 4. "USB_EP_EN,Endpoint Enable When this bit is set to 1 the EP[3:0] field is used in address comparison together with the AD[6:0] field in the FAR register" "0,1"
bitfld.word 0x00 0.--3. "USB_EP,Endpoint Address This 4-bit field holds the endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x60++0x01
line.word 0x00 "USB_EPC3_REG,Endpoint Control Register 3"
bitfld.word 0x00 7. "USB_STALL,Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received" "0,1"
bitfld.word 0x00 5. "USB_ISO,Isochronous When this bit is set to 1 the endpoint is isochronous" "0,1"
newline
bitfld.word 0x00 4. "USB_EP_EN,Endpoint Enable When this bit is set to 1 the EP[3:0] field is used in address comparison together with the AD[6:0] field in the FAR register" "0,1"
bitfld.word 0x00 0.--3. "USB_EP,Endpoint Address This 4-bit field holds the endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x68++0x01
line.word 0x00 "USB_EPC4_REG,Endpoint Control Register 4"
bitfld.word 0x00 7. "USB_STALL,Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received" "0,1"
bitfld.word 0x00 5. "USB_ISO,Isochronous When this bit is set to 1 the endpoint is isochronous" "0,1"
newline
bitfld.word 0x00 4. "USB_EP_EN,Endpoint Enable When this bit is set to 1 the EP[3:0] field is used in address comparison together with the AD[6:0] field in the FAR register" "0,1"
bitfld.word 0x00 0.--3. "USB_EP,Endpoint Address This 4-bit field holds the endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x70++0x01
line.word 0x00 "USB_EPC5_REG,Endpoint Control Register 5"
bitfld.word 0x00 7. "USB_STALL,Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received" "0,1"
bitfld.word 0x00 5. "USB_ISO,Isochronous When this bit is set to 1 the endpoint is isochronous" "0,1"
newline
bitfld.word 0x00 4. "USB_EP_EN,Endpoint Enable When this bit is set to 1 the EP[3:0] field is used in address comparison together with the AD[6:0] field in the FAR register" "0,1"
bitfld.word 0x00 0.--3. "USB_EP,Endpoint Address This 4-bit field holds the endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x78++0x01
line.word 0x00 "USB_EPC6_REG,Endpoint Control Register 6"
bitfld.word 0x00 7. "USB_STALL,Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received" "0,1"
bitfld.word 0x00 5. "USB_ISO,Isochronous When this bit is set to 1 the endpoint is isochronous" "0,1"
newline
bitfld.word 0x00 4. "USB_EP_EN,Endpoint Enable When this bit is set to 1 the EP[3:0] field is used in address comparison together with the AD[6:0] field in the FAR register" "0,1"
bitfld.word 0x00 0.--3. "USB_EP,Endpoint Address This 4-bit field holds the endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x08++0x01
line.word 0x00 "USB_FAR_REG,Function Address Register"
bitfld.word 0x00 7. "USB_AD_EN,Address Enable When set to 1 USB address field bits 6-0 are used in address comparison (see &quot Address detection&quot on page 218 for a description)" "0,1"
hexmask.word.byte 0x00 0.--6. 1. "USB_AD,Address This field holds the 7-bit function address used to transmit and receive all tokens addressed to this device"
group.word 0x24++0x01
line.word 0x00 "USB_FNH_REG,Frame Number High Byte Register"
rbitfld.word 0x00 7. "USB_MF,Missed SOF Flag This flag is set to 1 when the frame number in a valid received SOF does not match the expected next value or when an SOF is not received within 12060 bit times" "0,1"
rbitfld.word 0x00 6. "USB_UL,Unlock Flag This bit indicates that at least two frames were received without an expected frame number or that no valid SOF was received within 12060 bit times" "0,1"
newline
rbitfld.word 0x00 5. "USB_RFC,Reset Frame Count Writing a 1 to this bit resets the frame number to 00016 after which this bit clears itself to 0 again" "0,1"
rbitfld.word 0x00 0.--2. "USB_FN_10_8,Frame Number This 3-bit field contains the three most significant bits (MSB) of the current frame number received in the last SOF packet" "0,1,2,3,4,5,6,7"
group.word 0x26++0x01
line.word 0x00 "USB_FNL_REG,Frame Number Low Byte Register"
hexmask.word.byte 0x00 0.--7. 1. "USB_FN,The Frame Number Low Byte Register holds the low byte of the frame number"
group.word 0x20++0x01
line.word 0x00 "USB_FWEV_REG,FIFO Warning Event Register"
rbitfld.word 0x00 4.--6. "USB_RXWARN31,Receive Warning n: 3:1 The bit n is set to 1 when the respective receive endpoint FIFO reaches the warning limit as specified by the RFWL bits of the respective EPCx register" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--2. "USB_TXWARN31,Transmit Warning n: 3:1 The bit n is set to 1 when the respective transmit endpoint FIFO reaches the warning limit as specified by the TFWL bits of the respective TXCn register and transmission from the respective endpoint is enabled" "0,1,2,3,4,5,6,7"
group.word 0x22++0x01
line.word 0x00 "USB_FWMSK_REG,FIFO Warning Mask Register"
bitfld.word 0x00 4.--6. "USB_M_RXWARN31,The FIFO Warning Mask Register selects which FWEV bits are reported in the MAEV register" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "USB_M_TXWARN31,The FIFO Warning Mask Register selects which FWEV bits are reported in the MAEV register" "0,1,2,3,4,5,6,7"
group.word 0x0C++0x01
line.word 0x00 "USB_MAEV_REG,Main Event Register"
bitfld.word 0x00 11. "USB_CH_EV,USB Charger event This bit is set if one of the bits in USB_CHARGER_STAT_REG[2-0] change" "0,1"
bitfld.word 0x00 10. "USB_EP0_NAK,Endpoint 0 NAK Event This bit is an OR of EP0_NAK_REG[EP0_OUTNAK] and EP0_NAK_REG[EP0_INNAK] bits" "0,1"
newline
bitfld.word 0x00 9. "USB_EP0_RX,Endpoint 0 Receive Event This bit is a copy of the RXS0[RX_LAST] and is cleared to 0 when this RXS0 register is" "0,1"
bitfld.word 0x00 8. "USB_EP0_TX,Endpoint 0 Transmit Event This bit is a copy of the TXS0[TX_DONE] bit and is cleared to 0 when the TXS0 register is" "0,1"
newline
bitfld.word 0x00 7. "USB_INTR,Master Interrupt Enable This bit is hardwired to 0 in the Main Event (MAEV) register bit 7 in the Main Mask (MAMSK) register is the Master Interrupt Enable" "0,1"
bitfld.word 0x00 6. "USB_RX_EV,Receive Event This bit is set to 1 if any of the unmasked bits in the Receive Event (RXEV) register is set to 1" "0,1"
newline
bitfld.word 0x00 5. "USB_ULD,Unlocked/Locked Detected This bit is set to 1 when the frame timer has either entered unlocked condition from a locked condition or has re-entered a locked condition from an unlocked condition as determined by the UL bit in the Frame Number (FNH.." "0,1"
bitfld.word 0x00 4. "USB_NAK,Negative Acknowledge Event This bit indicates that one of the unmasked NAK Event (NAKEV) register bits has been set to 1" "0,1"
newline
bitfld.word 0x00 3. "USB_FRAME,Frame Event This bit is set to 1 if the frame counter is updated with a new value" "0,1"
bitfld.word 0x00 2. "USB_TX_EV,Transmit Event This bit is set to 1 if any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOn or TXUNDRNn) is set to 1" "0,1"
newline
bitfld.word 0x00 1. "USB_ALT,Alternate Event This bit indicates that one of the unmasked ALTEV register bits has been set to 1" "0,1"
bitfld.word 0x00 0. "USB_WARN,Warning Event This bit indicates that one of the unmasked bits in the FIFO Warning Event (FWEV) register has been set to 1" "0,1"
group.word 0x0E++0x01
line.word 0x00 "USB_MAMSK_REG,Main Mask Register"
bitfld.word 0x00 11. "USB_M_CH_EV,The Main Mask Register masks out events reported in the MAEV registers" "0,1"
bitfld.word 0x00 10. "USB_M_EP0_NAK,Same Bit Definition as MAEV Register" "0,1"
newline
bitfld.word 0x00 9. "USB_M_EP0_RX,Same Bit Definition as MAEV Register" "0,1"
bitfld.word 0x00 8. "USB_M_EP0_TX,Same Bit Definition as MAEV Register" "0,1"
newline
bitfld.word 0x00 7. "USB_M_INTR,Same Bit Definition as MAEV Register" "0,1"
bitfld.word 0x00 6. "USB_M_RX_EV,Same Bit Definition as MAEV Register" "0,1"
newline
bitfld.word 0x00 5. "USB_M_ULD,Same Bit Definition as MAEV Register" "0,1"
bitfld.word 0x00 4. "USB_M_NAK,Same Bit Definition as MAEV Register" "0,1"
newline
bitfld.word 0x00 3. "USB_M_FRAME,Same Bit Definition as MAEV Register" "0,1"
bitfld.word 0x00 2. "USB_M_TX_EV,Same Bit Definition as MAEV Register" "0,1"
newline
bitfld.word 0x00 1. "USB_M_ALT,Same Bit Definition as MAEV Register" "0,1"
bitfld.word 0x00 0. "USB_M_WARN,Same Bit Definition as MAEV Register" "0,1"
group.word 0x00++0x01
line.word 0x00 "USB_MCTRL_REG,Main Control Register)"
bitfld.word 0x00 4. "LSMODE,Low Speed Mode This bit enables USB 1.5 Mbit/s low speed and swaps D+ and D- pull-up resistors" "0,1"
bitfld.word 0x00 3. "USB_NAT,Node Attached This bit indicates that this node is ready to be detected as attached to USB" "0,1"
newline
bitfld.word 0x00 1. "USB_DBG,Debug Mode" "0,1"
bitfld.word 0x00 0. "USBEN,USB EnableSetting this bit to 1 enables the Full/Low Speed USB node" "0,1"
group.word 0x1C++0x01
line.word 0x00 "USB_NAKEV_REG,NAK Event Register"
rbitfld.word 0x00 4.--6. "USB_OUT31,OUT n: 3:1 The bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1 and EP_EN in the EPCx register is set to 1) in response to an OUT token" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--2. "USB_IN31,IN n: 3:1 The bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Address FAR register is set to 1 and EP_EN in the Endpoint Control EPCx register is set to 1) in response to an.." "0,1,2,3,4,5,6,7"
group.word 0x1E++0x01
line.word 0x00 "USB_NAKMSK_REG,NAK Mask Register"
bitfld.word 0x00 4.--6. "USB_M_OUT31,When set and the corresponding bit in the NAKEV register is set the NAK bit in the MAEV register is set" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "USB_M_IN31,Same Bit Definition as NAKEV Register" "0,1,2,3,4,5,6,7"
group.word 0x0A++0x01
line.word 0x00 "USB_NFSR_REG,Node Functional State Register"
bitfld.word 0x00 0.--1. "USB_NFS,The Node Functional State Register reports and controls the current functional state of the USB node" "0: NodeReset,1: NodeResume In this state resume &quot K&quot,2: NodeOperational This is the normal operational,3: NodeSuspend Suspend state should be entered by"
group.word 0x4E++0x01
line.word 0x00 "USB_RXC0_REG,Receive Command 0 Register"
bitfld.word 0x00 3. "USB_FLUSH,Flush Writing a 1 to this bit flushes all data from the control endpoint FIFOs resets the endpoint to Idle state clears the FIFO read and write pointer and then clears itself" "0,1"
bitfld.word 0x00 2. "USB_IGN_SETUP,Ignore SETUP Tokens When this bit is set to 1 the endpoint ignores any SETUP tokens directed to its configured address" "0,1"
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bitfld.word 0x00 1. "USB_IGN_OUT,Ignore OUT Tokens When this bit is set to 1 the endpoint ignores any OUT tokens directed to its configured address" "0,1"
bitfld.word 0x00 0. "USB_RX_EN,Receive Enable OUT packet reception is disabled after every data packet is received or when a STALL handshake is returned in response to an OUT token" "0,1"
group.word 0x5E++0x01
line.word 0x00 "USB_RXC1_REG,Receive Command Register 1"
bitfld.word 0x00 5.--6. "USB_RFWL,Receive FIFO Warning Limit These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs" "0: RFWL disabled,1: Less than 5 bytes remaining in FIFO,2: Less than 9 bytes remaining in FIFO,3: Less than 17 bytes remaining in FIFO"
bitfld.word 0x00 3. "USB_FLUSH,Flush FIFO Writing a 1 to this bit flushes all data from the corresponding receive FIFO resets the endpoint to Idle state and resets both the FIFO read and write pointers" "0,1"
newline
bitfld.word 0x00 2. "USB_IGN_SETUP,Ignore SETUP Tokens When this bit is set to 1 the endpoint ignores any SETUP tokens directed to its configured address" "0,1"
bitfld.word 0x00 0. "USB_RX_EN,Receive Enable OUT packet cannot be received after every data packet is received or when a STALL handshake is returned in response to an OUT token" "0,1"
group.word 0x6E++0x01
line.word 0x00 "USB_RXC2_REG,Receive Command Register 2"
bitfld.word 0x00 5.--6. "USB_RFWL,Receive FIFO Warning Limit These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs" "0: RFWL disabled,1: Less than 5 bytes remaining in FIFO,2: Less than 9 bytes remaining in FIFO,3: Less than 17 bytes remaining in FIFO"
bitfld.word 0x00 3. "USB_FLUSH,Flush FIFO Writing a 1 to this bit flushes all data from the corresponding receive FIFO resets the endpoint to Idle state and resets both the FIFO read and write pointers" "0,1"
newline
bitfld.word 0x00 2. "USB_IGN_SETUP,Ignore SETUP Tokens When this bit is set to 1 the endpoint ignores any SETUP tokens directed to its configured address" "0,1"
bitfld.word 0x00 0. "USB_RX_EN,Receive Enable OUT packet cannot be received after every data packet is received or when a STALL handshake is returned in response to an OUT token" "0,1"
group.word 0x7E++0x01
line.word 0x00 "USB_RXC3_REG,Receive Command Register 3"
bitfld.word 0x00 5.--6. "USB_RFWL,Receive FIFO Warning Limit These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs" "0: RFWL disabled,1: Less than 5 bytes remaining in FIFO,2: Less than 9 bytes remaining in FIFO,3: Less than 17 bytes remaining in FIFO"
bitfld.word 0x00 3. "USB_FLUSH,Flush FIFO Writing a 1 to this bit flushes all data from the corresponding receive FIFO resets the endpoint to Idle state and resets both the FIFO read and write pointers" "0,1"
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bitfld.word 0x00 2. "USB_IGN_SETUP,Ignore SETUP Tokens When this bit is set to 1 the endpoint ignores any SETUP tokens directed to its configured address" "0,1"
bitfld.word 0x00 0. "USB_RX_EN,Receive Enable OUT packet cannot be received after every data packet is received or when a STALL handshake is returned in response to an OUT token" "0,1"
group.word 0x4A++0x01
line.word 0x00 "USB_RXD0_REG,Receive Data 0 Register"
hexmask.word.byte 0x00 0.--7. 1. "USB_RXFD,Receive FIFO Data Byte See &quot Bidirectional Control Endpoint FIFO0&quot on page 220 for a description of data handling"
group.word 0x5A++0x01
line.word 0x00 "USB_RXD1_REG,Receive Data Register 1"
hexmask.word.byte 0x00 0.--7. 1. "USB_RXFD,Receive FIFO Data Byte See &quot Receive Endpoint FIFO&quot on page 223 for a description of Endpoint FIFO data handling.The firmware should expect to read only the packet payload data"
group.word 0x6A++0x01
line.word 0x00 "USB_RXD2_REG,Receive Data Register 2"
hexmask.word.byte 0x00 0.--7. 1. "USB_RXFD,Receive FIFO Data Byte See &quot Receive Endpoint FIFO&quot on page 223 for a description of Endpoint FIFO data handling.The firmware should expect to read only the packet payload data"
group.word 0x7A++0x01
line.word 0x00 "USB_RXD3_REG,Receive Data Register 3"
hexmask.word.byte 0x00 0.--7. 1. "USB_RXFD,Receive FIFO Data Byte See &quot Receive Endpoint FIFO&quot on page 223 for a description of Endpoint FIFO data handling.The firmware should expect to read only the packet payload data"
group.word 0x18++0x01
line.word 0x00 "USB_RXEV_REG,Receive Event Register"
rbitfld.word 0x00 4.--6. "USB_RXOVRRN31,Receive Overrun n: 3:1 The bit n is set to 1 in the event of an overrun condition in the corresponding receive FIFO n" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--2. "USB_RXFIFO31,Receive FIFO n: 3:1 The bit n is set to 1 whenever either RX_ERR or RX_LAST in the respective Receive Status register (RXSn) is set to 1" "0,1,2,3,4,5,6,7"
group.word 0x1A++0x01
line.word 0x00 "USB_RXMSK_REG,Receive Mask Register"
bitfld.word 0x00 4.--6. "USB_M_RXOVRRN31,The Receive Mask Register is used to select the bits of the RXEV registers which causes the RX_EV bit in the MAEV register to be set to 1" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "USB_M_RXFIFO31,Same Bit Definition as RXEV Register" "0,1,2,3,4,5,6,7"
group.word 0x4C++0x01
line.word 0x00 "USB_RXS0_REG,Receive Status 0 Register"
rbitfld.word 0x00 6. "USB_SETUP,Setup This bit indicates that the setup packet has been received" "0,1"
rbitfld.word 0x00 5. "USB_TOGGLE_RX0,Toggle This bit specified the PID used when receiving the packet" "0,1"
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rbitfld.word 0x00 4. "USB_RX_LAST,Receive Last Bytes This bit indicates that an ACK was sent upon completion of a successful receive operation" "0,1"
rbitfld.word 0x00 0.--3. "USB_RCOUNT,Receive Count This 4-bit field contains the number of bytes presently in the RX FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x5C++0x01
line.word 0x00 "USB_RXS1_REG,Receive Status Register 1"
rbitfld.word 0x00 7. "USB_RX_ERR,Receive Error When set to 1 this bit indicates a media error such as bit-stuffing or CRC" "0,1"
rbitfld.word 0x00 6. "USB_SETUP,Setup This bit indicates that the setup packet has been received" "0,1"
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rbitfld.word 0x00 5. "USB_TOGGLE_RX,Toggle The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used" "0,1"
rbitfld.word 0x00 4. "USB_RX_LAST,Receive Last This bit indicates that an ACK was sent upon completion of a successful receive operation" "0,1"
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rbitfld.word 0x00 0.--3. "USB_RCOUNT,Receive Counter This 4-bit field contains the number of bytes presently in the endpoint receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x6C++0x01
line.word 0x00 "USB_RXS2_REG,Receive Status Register 2"
rbitfld.word 0x00 7. "USB_RX_ERR,Receive Error When set to 1 this bit indicates a media error such as bit-stuffing or CRC" "0,1"
rbitfld.word 0x00 6. "USB_SETUP,Setup This bit indicates that the setup packet has been received" "0,1"
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rbitfld.word 0x00 5. "USB_TOGGLE_RX,Toggle The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used" "0,1"
rbitfld.word 0x00 4. "USB_RX_LAST,Receive Last This bit indicates that an ACK was sent upon completion of a successful receive operation" "0,1"
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rbitfld.word 0x00 0.--3. "USB_RCOUNT,Receive Counter This 4-bit field contains the number of bytes presently in the endpoint receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x7C++0x01
line.word 0x00 "USB_RXS3_REG,Receive Status Register 3"
rbitfld.word 0x00 7. "USB_RX_ERR,Receive Error When set to 1 this bit indicates a media error such as bit-stuffing or CRC" "0,1"
rbitfld.word 0x00 6. "USB_SETUP,Setup This bit indicates that the setup packet has been received" "0,1"
newline
rbitfld.word 0x00 5. "USB_TOGGLE_RX,Toggle The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used" "0,1"
rbitfld.word 0x00 4. "USB_RX_LAST,Receive Last This bit indicates that an ACK was sent upon completion of a successful receive operation" "0,1"
newline
rbitfld.word 0x00 0.--3. "USB_RCOUNT,Receive Counter This 4-bit field contains the number of bytes presently in the endpoint receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x04++0x01
line.word 0x00 "USB_TCR_REG,Transceiver configuration Register"
bitfld.word 0x00 5.--7. "USB_VADJ,Reference Voltage/ Threshold voltage AdjustControls the single-ended receiver threshold" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--4. "USB_CADJ,Transmitter Current Adjust Controls the driver edge rate control current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x46++0x01
line.word 0x00 "USB_TXC0_REG,Transmit command 0 Register"
bitfld.word 0x00 4. "USB_IGN_IN,Ignore IN Tokens When this bit is set to 1 the endpoint will ignore any IN tokens directed to its configured address" "0,1"
bitfld.word 0x00 3. "USB_FLUSH,Flush FIFO Writing a 1 to this bit flushes all data from the control endpoint FIFOs resets the endpoint to Idle state clears the FIFO read and write pointer and then clears itself" "0,1"
newline
bitfld.word 0x00 2. "USB_TOGGLE_TX0,Toggle This bit specifies the PID used when transmitting the packet" "0,1"
bitfld.word 0x00 0. "USB_TX_EN,Transmission Enable This bit enables data transmission from the FIFO" "0,1"
group.word 0x56++0x01
line.word 0x00 "USB_TXC1_REG,Transmit Command Register 1"
bitfld.word 0x00 7. "USB_IGN_ISOMSK,Ignore ISO Mask This bit has an effect only if the endpoint is set to be isochronous" "0,1"
bitfld.word 0x00 5.--6. "USB_TFWL,Transmit FIFO Warning Limit These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs" "0: TFWL disabled,1: Less than 5 bytes remaining in FIFO,2: Less than 9 bytes remaining in FIFO,3: Less than 17 bytes remaining in FIFO"
newline
bitfld.word 0x00 4. "USB_RFF,Refill FIFO Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer" "0,1"
bitfld.word 0x00 3. "USB_FLUSH,Flush FIFO Writing a 1 to this bit flushes all data from the corresponding transmit FIFO resets the endpoint to Idle state and clears both the FIFO read and write pointers" "0,1"
newline
bitfld.word 0x00 2. "USB_TOGGLE_TX,Toggle The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used" "0,1"
bitfld.word 0x00 1. "USB_LAST,Last Byte Setting this bit to 1 indicates that the entire packet has been written into the FIFO" "0,1"
newline
bitfld.word 0x00 0. "USB_TX_EN,Transmission Enable This bit enables data transmission from the FIFO" "0,1"
group.word 0x66++0x01
line.word 0x00 "USB_TXC2_REG,Transmit Command Register 2"
bitfld.word 0x00 7. "USB_IGN_ISOMSK,Ignore ISO Mask This bit has an effect only if the endpoint is set to be isochronous" "0,1"
bitfld.word 0x00 5.--6. "USB_TFWL,Transmit FIFO Warning Limit These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs" "0: TFWL disabled,1: Less than 5 bytes remaining in FIFO,2: Less than 9 bytes remaining in FIFO,3: Less than 17 bytes remaining in FIFO"
newline
bitfld.word 0x00 4. "USB_RFF,Refill FIFO Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer" "0,1"
bitfld.word 0x00 3. "USB_FLUSH,Flush FIFO Writing a 1 to this bit flushes all data from the corresponding transmit FIFO resets the endpoint to Idle state and clears both the FIFO read and write pointers" "0,1"
newline
bitfld.word 0x00 2. "USB_TOGGLE_TX,Toggle The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used" "0,1"
bitfld.word 0x00 1. "USB_LAST,Last Byte Setting this bit to 1 indicates that the entire packet has been written into the FIFO" "0,1"
newline
bitfld.word 0x00 0. "USB_TX_EN,Transmission Enable This bit enables data transmission from the FIFO" "0,1"
group.word 0x76++0x01
line.word 0x00 "USB_TXC3_REG,Transmit Command Register 3"
bitfld.word 0x00 7. "USB_IGN_ISOMSK,Ignore ISO Mask This bit has an effect only if the endpoint is set to be isochronous" "0,1"
bitfld.word 0x00 5.--6. "USB_TFWL,Transmit FIFO Warning Limit These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs" "0: TFWL disabled,1: Less than 5 bytes remaining in FIFO,2: Less than 9 bytes remaining in FIFO,3: Less than 17 bytes remaining in FIFO"
newline
bitfld.word 0x00 4. "USB_RFF,Refill FIFO Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer" "0,1"
bitfld.word 0x00 3. "USB_FLUSH,Flush FIFO Writing a 1 to this bit flushes all data from the corresponding transmit FIFO resets the endpoint to Idle state and clears both the FIFO read and write pointers" "0,1"
newline
bitfld.word 0x00 2. "USB_TOGGLE_TX,Toggle The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used" "0,1"
bitfld.word 0x00 1. "USB_LAST,Last Byte Setting this bit to 1 indicates that the entire packet has been written into the FIFO" "0,1"
newline
bitfld.word 0x00 0. "USB_TX_EN,Transmission Enable This bit enables data transmission from the FIFO" "0,1"
group.word 0x42++0x01
line.word 0x00 "USB_TXD0_REG,Transmit Data 0 Register"
hexmask.word.byte 0x00 0.--7. 1. "USB_TXFD,Transmit FIFO Data Byte See &quot Bidirectional Control Endpoint FIFO0&quot on page 220 for a description of data handling"
group.word 0x52++0x01
line.word 0x00 "USB_TXD1_REG,Transmit Data Register 1"
hexmask.word.byte 0x00 0.--7. 1. "USB_TXFD,Transmit FIFO Data Byte See &quot Transmit Endpoint FIFOs&quot on page 222 for a description of endpoint FIFO data handling"
group.word 0x62++0x01
line.word 0x00 "USB_TXD2_REG,Transmit Data Register 2"
hexmask.word.byte 0x00 0.--7. 1. "USB_TXFD,Transmit FIFO Data Byte See &quot Transmit Endpoint FIFOs&quot on page 222 for a description of endpoint FIFO data handling"
group.word 0x72++0x01
line.word 0x00 "USB_TXD3_REG,Transmit Data Register 3"
hexmask.word.byte 0x00 0.--7. 1. "USB_TXFD,Transmit FIFO Data Byte See &quot Transmit Endpoint FIFOs&quot on page 222 for a description of endpoint FIFO data handling"
group.word 0x14++0x01
line.word 0x00 "USB_TXEV_REG,Transmit Event Register"
rbitfld.word 0x00 4.--6. "USB_TXUDRRN31,Transmit Underrun n: 3:1 The bit n is a copy of the respective TX_URUN bit from the corresponding Transmit Status register (TXSn)" "0,1,2,3,4,5,6,7"
rbitfld.word 0x00 0.--2. "USB_TXFIFO31,Transmit FIFO n: 3:1 The bit n is a copy of the TX_DONE bit from the corresponding Transmit Status register (TXSn)" "0,1,2,3,4,5,6,7"
group.word 0x16++0x01
line.word 0x00 "USB_TXMSK_REG,Transmit Mask Register"
bitfld.word 0x00 4.--6. "USB_M_TXUDRRN31,The Transmit Mask Register is used to select the bits of the TXEV registers which causes the TX_EV bit in the MAEV register to be set to 1" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "USB_M_TXFIFO31,Same Bit Definition as TXEV Register" "0,1,2,3,4,5,6,7"
group.word 0x44++0x01
line.word 0x00 "USB_TXS0_REG,Transmit Status 0 Register"
rbitfld.word 0x00 6. "USB_ACK_STAT,Acknowledge Status This bit indicates the status as received from the host of the ACK for the packet previously sent" "0,1"
rbitfld.word 0x00 5. "USB_TX_DONE,Transmission Done When set to 1 this bit indicates that a packet has completed transmission" "0,1"
newline
rbitfld.word 0x00 0.--4. "USB_TCOUNT,Transmission Count This 5-bit field indicates the number of empty bytes available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x54++0x01
line.word 0x00 "USB_TXS1_REG,Transmit Status Register 1"
rbitfld.word 0x00 7. "USB_TX_URUN,Transmit FIFO Underrun This bit is set to 1 if the transmit FIFO becomes empty during a transmission and no new data is written to the FIFO" "0,1"
rbitfld.word 0x00 6. "USB_ACK_STAT,Acknowledge Status This bit is interpreted when TX_DONE is set" "0,1"
newline
rbitfld.word 0x00 5. "USB_TX_DONE,Transmission Done When set to 1 this bit indicates that the endpoint responded to a USB packet" "0,1"
rbitfld.word 0x00 0.--4. "USB_TCOUNT,Transmission Count This 5-bit field holds the number of empty bytes available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x64++0x01
line.word 0x00 "USB_TXS2_REG,Transmit Status Register 2"
rbitfld.word 0x00 7. "USB_TX_URUN,Transmit FIFO Underrun This bit is set to 1 if the transmit FIFO becomes empty during a transmission and no new data is written to the FIFO" "0,1"
rbitfld.word 0x00 6. "USB_ACK_STAT,Acknowledge Status This bit is interpreted when TX_DONE is set" "0,1"
newline
rbitfld.word 0x00 5. "USB_TX_DONE,Transmission Done When set to 1 this bit indicates that the endpoint responded to a USB packet" "0,1"
rbitfld.word 0x00 0.--4. "USB_TCOUNT,Transmission Count This 5-bit field holds the number of empty bytes available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x74++0x01
line.word 0x00 "USB_TXS3_REG,Transmit Status Register 3"
rbitfld.word 0x00 7. "USB_TX_URUN,Transmit FIFO Underrun This bit is set to 1 if the transmit FIFO becomes empty during a transmission and no new data is written to the FIFO" "0,1"
rbitfld.word 0x00 6. "USB_ACK_STAT,Acknowledge Status This bit is interpreted when TX_DONE is set" "0,1"
newline
rbitfld.word 0x00 5. "USB_TX_DONE,Transmission Done When set to 1 this bit indicates that the endpoint responded to a USB packet" "0,1"
rbitfld.word 0x00 0.--4. "USB_TCOUNT,Transmission Count This 5-bit field holds the number of empty bytes available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x06++0x01
line.word 0x00 "USB_UTR_REG,USB test Register (for test purpose only)"
bitfld.word 0x00 7. "USB_DIAG,Diagnostic enable '0': Normal operational" "0,1"
bitfld.word 0x00 6. "USB_NCRC,No CRC16 When this bit is set to 1 all packets transmitted by the Full/Low Speed USB node are sent without a trailing CRC16" "0,1"
newline
bitfld.word 0x00 5. "USB_SF,Short Frame Enables the Frame timer to lock and track short non-compliant USB frame sizes" "0,1"
bitfld.word 0x00 0.--4. "USB_UTR_RES,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x3E++0x01
line.word 0x00 "USB_UX20CDR_REG,Transceiver 2.0 Configuration and Diagnostics Register(for test purpose only)"
rbitfld.word 0x00 7. "RPU_TEST7,Test bit" "0,1"
bitfld.word 0x00 6. "RPU_TEST_SW2," "0,1"
newline
bitfld.word 0x00 5. "RPU_TEST_SW1," "0,1"
bitfld.word 0x00 4. "RPU_TEST_EN,Pull-Up Resistor Test Enable" "0: Normal operation,1: Enables the test features controlled by"
newline
bitfld.word 0x00 2. "RPU_TEST_SW1DM," "0,1"
bitfld.word 0x00 1. "RPU_RCDELAY,Test bit must be kept 0" "0,1"
newline
bitfld.word 0x00 0. "RPU_SSPROTEN,Test bit must be kept 0" "0,1"
group.word 0x02++0x01
line.word 0x00 "USB_XCVDIAG_REG,Transceiver diagnostic Register (for test purpose only)"
rbitfld.word 0x00 7. "USB_VPIN,With Bit0 = 1 this bit shows the level of the USB_Dp receive data from transceiver i.e" "0,1"
rbitfld.word 0x00 6. "USB_VMIN,With Bit0 = 1 this bit shows the level USB_Dm receive data from transceiver i.e" "0,1"
newline
rbitfld.word 0x00 5. "USB_RCV,With Bit0 = 1 this bit shows the differential level of the receive comparator" "0,1"
bitfld.word 0x00 3. "USB_XCV_TXEN,With Bit0 = 1 this bit enables test Bits 2 1" "0,1"
newline
bitfld.word 0x00 2. "USB_XCV_TXn,With Bit3" "0,1"
bitfld.word 0x00 1. "USB_XCV_TXp,With Bit3" "0,1"
newline
bitfld.word 0x00 0. "USB_XCV_TEST,Enable USB_XCVDIAG_REG" "0: Normal operation test bits disabled,1: Enable test bits 7 6 5 3 2 1 (Note 48)"
tree.end
tree "WAKEUP"
base ad:0x50000100
group.word 0x02++0x01
line.word 0x00 "WKUP_COMPARE_REG,Number of events before wakeup interrupt"
hexmask.word.byte 0x00 0.--7. 1. "COMPARE,The number of events that have to be counted before the wakeup interrupt will be given"
group.word 0x06++0x01
line.word 0x00 "WKUP_COUNTER_REG,Actual number of events of the wakeup counter"
hexmask.word.byte 0x00 0.--7. 1. "EVENT_VALUE,This value represents the number of events that have been counted so far"
group.word 0x00++0x01
line.word 0x00 "WKUP_CTRL_REG,Control register for the wakeup counter"
bitfld.word 0x00 7. "WKUP_ENABLE_IRQ," "0,1"
bitfld.word 0x00 6. "WKUP_SFT_KEYHIT," "0,1"
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bitfld.word 0x00 0.--5. "WKUP_DEB_VALUE,Keyboard debounce time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x14++0x01
line.word 0x00 "WKUP_POL_P0_REG,select the sesitivity polarity for each P0 input"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_POL_P0,"
group.word 0x16++0x01
line.word 0x00 "WKUP_POL_P1_REG,select the sesitivity polarity for each P1 input"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_POL_P1,"
group.word 0x18++0x01
line.word 0x00 "WKUP_POL_P2_REG,select the sesitivity polarity for each P2 input"
bitfld.word 0x00 0.--4. "WKUP_POL_P2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1A++0x01
line.word 0x00 "WKUP_POL_P3_REG,select the sesitivity polarity for each P3 input"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_POL_P3,"
group.word 0x1C++0x01
line.word 0x00 "WKUP_POL_P4_REG,select the sesitivity polarity for each P3 input"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_POL_P4,"
group.word 0x08++0x01
line.word 0x00 "WKUP_RESET_CNTR_REG,Reset the event counter"
hexmask.word 0x00 0.--15. 1. "WKUP_CNTR_RST,writing any value to this register will reset the event counter"
group.word 0x04++0x01
line.word 0x00 "WKUP_RESET_IRQ_REG,Reset wakeup interrupt"
hexmask.word 0x00 0.--15. 1. "WKUP_IRQ_RST,writing any value to this register will reset the interrupt"
group.word 0x0A++0x01
line.word 0x00 "WKUP_SELECT_P0_REG,select which inputs from P0 port can trigger wkup counter"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_SELECT_P0,"
group.word 0x0C++0x01
line.word 0x00 "WKUP_SELECT_P1_REG,select which inputs from P1 port can trigger wkup counter"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_SELECT_P1,"
group.word 0x0E++0x01
line.word 0x00 "WKUP_SELECT_P2_REG,select which inputs from P2 port can trigger wkup counter"
bitfld.word 0x00 0.--4. "WKUP_SELECT_P2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x10++0x01
line.word 0x00 "WKUP_SELECT_P3_REG,select which inputs from P3 port can trigger wkup counter"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_SELECT_P3,"
group.word 0x12++0x01
line.word 0x00 "WKUP_SELECT_P4_REG,select which inputs from P4 port can trigger wkup counter"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_SELECT_P4,"
tree.end
tree "WDOG"
base ad:0x50003100
group.word 0x02++0x01
line.word 0x00 "WATCHDOG_CTRL_REG,Watchdog control register"
bitfld.word 0x00 0. "NMI_RST," "0,1"
group.word 0x00++0x01
line.word 0x00 "WATCHDOG_REG,Watchdog timer register"
hexmask.word.byte 0x00 9.--15. 1. "WDOG_WEN,0000.000 = Write enable for Watchdog timer else Write disable"
bitfld.word 0x00 8. "WDOG_VAL_NEG," "0,1"
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hexmask.word.byte 0x00 0.--7. 1. "WDOG_VAL,Write: Watchdog timer reload value"
tree.end
tree.end
tree "SCB (Cortex M0 SCB registers)"
base ad:0xE000ED00
group.long 0x00++0x03
line.long 0x00 "CPUID,CPUID base register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,IMPLEMENTER[7:0] bits (Implementer code)"
rbitfld.long 0x00 20.--23. "VARIANT,VARIANT[3:0] bits (Variant number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 16.--19. "CONSTANT,CONSTANT[3:0] bits (Reads as 0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "PARTNO,PARTNO[11:0] bits (Part number of the processor core)"
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rbitfld.long 0x00 0.--3. "REVISION,REVISION[3:0] bits (Revision number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "ICSR,Interrupt control and state register"
bitfld.long 0x00 31. "NMIPENDSET,NMI set-pending bit" "0,1"
bitfld.long 0x00 28. "PENDSVSET,PendSV set-pending bit" "0,1"
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bitfld.long 0x00 27. "PENDSVCLR,PendSV clear-pending bit" "0,1"
bitfld.long 0x00 26. "PENDSTSET,SysTick exception set-pending bit" "0,1"
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bitfld.long 0x00 25. "PENDSTCLR,SysTick exception clear-pending bit" "0,1"
bitfld.long 0x00 22. "ISRPENDING,Interrupt pending flag excluding NMI and Faults" "0,1"
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bitfld.long 0x00 12.--17. "VECTPENDING,VECTPENDING[5:0] bits (Pending vector)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "VECTACTIVE,VECTACTIVE[5:0] bits (Active vector)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x0C++0x03
line.long 0x00 "AIRCR,Application interrupt and reset control register"
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,VECTKEY[15:0] bits (Register key)"
bitfld.long 0x00 15. "ENDIANESS,Data endianness bit" "0,1"
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bitfld.long 0x00 2. "SYSRESETREQ,System reset request" "0,1"
bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for Debug use" "0,1"
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bitfld.long 0x00 0. "VECTRESET,Reserved for Debug use" "0,1"
group.long 0x10++0x03
line.long 0x00 "SCR,System control register"
bitfld.long 0x00 4. "SEVEONPEND,Send event on pending bit" "0,1"
bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep" "0,1"
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bitfld.long 0x00 1. "SLEEPONEXIT,Configures sleep-on-exit when returning from Handler mode to Thread mode" "0,1"
group.long 0x14++0x03
line.long 0x00 "CCR,Configuration and control register"
bitfld.long 0x00 9. "STKALIGN,Configures stack alignment on exception entry" "0,1"
bitfld.long 0x00 3. "UNALIGN_TRP,Enables unaligned access traps" "0,1"
group.long 0x1C++0x03
line.long 0x00 "SHPR2,System handler priority register 2"
hexmask.long.byte 0x00 24.--31. 1. "PRI_11,PRI_11[7:0] bits (Priority of system handler 11 SVCall)"
group.long 0x20++0x03
line.long 0x00 "SHPR3,System handler priority register 3"
hexmask.long.byte 0x00 24.--31. 1. "PRI_15,PRI_15[7:0] bits (Priority of system handler 15 SysTick exception)"
hexmask.long.byte 0x00 16.--23. 1. "PRI_14,PRI_14[7:0] bits (Priority of system handler 14 PendSV)"
tree.end
tree "SYSTICK (Cortex M0 SysTick registers)"
base ad:0xE000E010
group.long 0x00++0x03
line.long 0x00 "CTRL,SysTick Control and Status register"
bitfld.long 0x00 16. "COUNTFLAG,Timer counted to 0 since last time this was" "0,1"
bitfld.long 0x00 2. "CLKSOURCE,Clock source selection" "0,1"
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bitfld.long 0x00 1. "TICKINT,SysTick exception request enable" "0,1"
bitfld.long 0x00 0. "ENABLE,SysTick Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "LOAD,SysTick Reload value register"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,RELOAD[23:0] bits (Reload value)"
group.long 0x08++0x03
line.long 0x00 "VAL,SysTick Current value register"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,CURRENT[23:0] bits (Current counter value)"
rgroup.long 0x0C++0x03
line.long 0x00 "CALIB,SysTick Calibration value register"
bitfld.long 0x00 31. "NOREF,Indicates that a separate reference clock is provided" "0,1"
bitfld.long 0x00 30. "SKEW,Indicates whether the TENMS value is exact" "0,1"
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hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,TENMS[23:0] bits (Calibration value)"
tree.end
autoindent.off
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