woody/Gen4_R-Car_Trace32
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
main
Gen4_R-Car_Trace32/2_Trunk/perda14586.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

3258 lines
221 KiB
Plaintext
Raw Permalink Blame History

; --------------------------------------------------------------------------------
; @Title: DA14586 On-Chip Peripherals
; @Props: Released
; @Author: DAB
; @Changelog: 2022-02-16 DAB
; @Manufacturer: Dialog Semiconductor
; @Doc: SVD generated based on: DA14586.svd (Ver 0.2)
; @Core: Cortex-M0
; @Chip: DA14586
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perda14586.per 14328 2022-02-16 16:20:32Z kwisniewski $
config 16. 8.
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "NVIC_GROUP (Cortex M0 NVIC registers)"
base ad:0xE000E100
group.long 0x00++0x03
line.long 0x00 "ISER,Interrupt set-enable register"
bitfld.long 0x00 20. "DMA_IRQn,DMA Interrupt (set-enable bit)" "0,1"
bitfld.long 0x00 19. "SRC_OUT_IRQn,Sample rate converter output Interrupt (set-enable bit)" "0,1"
newline
bitfld.long 0x00 18. "SRC_IN_IRQn,Sample rate converter input Interrupt (set-enable bit)" "0,1"
bitfld.long 0x00 17. "PCM_IRQn,PCM Interrupt (set-enable bit)" "0,1"
newline
bitfld.long 0x00 16. "WKUP_QUADEC_IRQn,Combined Wake up Capture Timer GPIO and QuadDecoder interrupt (set-enable bit)" "0,1"
bitfld.long 0x00 15. "SWTIM_IRQn,Software timer Interrupt (set-enable bit)" "0,1"
newline
bitfld.long 0x00 14. "GPIO4_IRQn,GPIO4 interrupt through debounce (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 13. "GPIO3_IRQn,IGPIO3 interrupt through debounce (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 12. "GPIO2_IRQn,GPIO2 interrupt through debounce (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 11. "GPIO1_IRQn,GPIO1 interrupt through debounce (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 10. "GPIO0_IRQn,GPIO0 interrupt through debounce (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 9. "RFCAL_IRQn,RFCAL_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 8. "BLE_RF_DIAG_IRQn,BLE baseband or Radio diagnostic (Interrupt set-enable bit))" "0,1"
bitfld.long 0x00 7. "KEYBRD_IRQn,KEYBRD_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 6. "ADC_IRQn,ADC_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 5. "SPI_IRQn,SPI_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 4. "I2C_IRQn,I2C_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 3. "UART2_IRQn,UART2_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 2. "UART_IRQn,UART_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 1. "BLE_GEN_IRQn,BLE_GEN_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 0. "BLE_WAKEUP_LP_IRQn,BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit)" "0,1"
group.long 0x80++0x03
line.long 0x00 "ICER,Interrupt clear-enable register"
bitfld.long 0x00 20. "DMA_IRQn,DMA Interrupt (clear-enable bit)" "0,1"
bitfld.long 0x00 19. "SRC_OUT_IRQn,Sample rate converter output Interrupt (clear-enable bit)" "0,1"
newline
bitfld.long 0x00 18. "SRC_IN_IRQn,Sample rate converter input Interrupt (clear-enable bit)" "0,1"
bitfld.long 0x00 17. "PCM_IRQn,PCM Interrupt (clear-enable bit)" "0,1"
newline
bitfld.long 0x00 16. "WKUP_QUADEC_IRQn,Combined Wake up Capture Timer GPIO and QuadDecoder interrupt (clear-enable bit)" "0,1"
bitfld.long 0x00 15. "SWTIM_IRQn,Software timer Interrupt (clear-enable bit)" "0,1"
newline
bitfld.long 0x00 14. "GPIO4_IRQn,GPIO4 interrupt through debounce (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 13. "GPIO3_IRQn,IGPIO3 interrupt through debounce (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 12. "GPIO2_IRQn,GPIO2 interrupt through debounce (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 11. "GPIO1_IRQn,GPIO1 interrupt through debounce (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 10. "GPIO0_IRQn,GPIO0 interrupt through debounce (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 9. "RFCAL_IRQn,RFCAL_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 8. "BLE_RF_DIAG_IRQn,BLE baseband or Radio diagnostic (Interrupt clear-enable bit))" "0,1"
bitfld.long 0x00 7. "KEYBRD_IRQn,KEYBRD_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 6. "ADC_IRQn,ADC_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 5. "SPI_IRQn,SPI_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 4. "I2C_IRQn,I2C_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 3. "UART2_IRQn,UART2_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 2. "UART_IRQn,UART_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 1. "BLE_GEN_IRQn,BLE_GEN_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 0. "BLE_WAKEUP_LP_IRQn,BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit)" "0,1"
group.long 0x100++0x03
line.long 0x00 "ISPR,Interrupt set-pending register"
bitfld.long 0x00 20. "DMA_IRQn,DMA Interrupt (set-pending bit)" "0,1"
bitfld.long 0x00 19. "SRC_OUT_IRQn,Sample rate converter output Interrupt (set-pending bit)" "0,1"
newline
bitfld.long 0x00 18. "SRC_IN_IRQn,Sample rate converter input Interrupt (set-pending bit)" "0,1"
bitfld.long 0x00 17. "PCM_IRQn,PCM Interrupt (set-pending bit)" "0,1"
newline
bitfld.long 0x00 16. "WKUP_QUADEC_IRQn,Combined Wake up Capture Timer GPIO and QuadDecoder interrupt (set-pending bit)" "0,1"
bitfld.long 0x00 15. "SWTIM_IRQn,Software timer Interrupt (set-pending bit)" "0,1"
newline
bitfld.long 0x00 14. "GPIO4_IRQn,GPIO4 interrupt through debounce (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 13. "GPIO3_IRQn,IGPIO3 interrupt through debounce (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 12. "GPIO2_IRQn,GPIO2 interrupt through debounce (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 11. "GPIO1_IRQn,GPIO1 interrupt through debounce (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 10. "GPIO0_IRQn,GPIO0 interrupt through debounce (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 9. "RFCAL_IRQn,RFCAL_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 8. "BLE_RF_DIAG_IRQn,BLE baseband or Radio diagnostic (Interrupt set-pending bit))" "0,1"
bitfld.long 0x00 7. "KEYBRD_IRQn,KEYBRD_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 6. "ADC_IRQn,ADC_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 5. "SPI_IRQn,SPI_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 4. "I2C_IRQn,I2C_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 3. "UART2_IRQn,UART2_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 2. "UART_IRQn,UART_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 1. "BLE_GEN_IRQn,BLE_GEN_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 0. "BLE_WAKEUP_LP_IRQn,BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit)" "0,1"
group.long 0x180++0x03
line.long 0x00 "ICPR,Interrupt clear-pending register"
bitfld.long 0x00 20. "DMA_IRQn,DMA Interrupt (clear-pending bit)" "0,1"
bitfld.long 0x00 19. "SRC_OUT_IRQn,Sample rate converter output Interrupt (clear-pending bit)" "0,1"
newline
bitfld.long 0x00 18. "SRC_IN_IRQn,Sample rate converter input Interrupt (clear-pending bit)" "0,1"
bitfld.long 0x00 17. "PCM_IRQn,PCM Interrupt (clear-pending bit)" "0,1"
newline
bitfld.long 0x00 16. "WKUP_QUADEC_IRQn,Combined Wake up Capture Timer GPIO and QuadDecoder interrupt (clear-pending bit)" "0,1"
bitfld.long 0x00 15. "SWTIM_IRQn,Software timer Interrupt (clear-pending bit)" "0,1"
newline
bitfld.long 0x00 14. "GPIO4_IRQn,GPIO4 interrupt through debounce (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 13. "GPIO3_IRQn,IGPIO3 interrupt through debounce (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 12. "GPIO2_IRQn,GPIO2 interrupt through debounce (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 11. "GPIO1_IRQn,GPIO1 interrupt through debounce (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 10. "GPIO0_IRQn,GPIO0 interrupt through debounce (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 9. "RFCAL_IRQn,RFCAL_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 8. "BLE_RF_DIAG_IRQn,BLE baseband or Radio diagnostic (Interrupt clear-pending bit))" "0,1"
bitfld.long 0x00 7. "KEYBRD_IRQn,KEYBRD_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 6. "ADC_IRQn,ADC_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 5. "SPI_IRQn,SPI_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 4. "I2C_IRQn,I2C_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 3. "UART2_IRQn,UART2_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 2. "UART_IRQn,UART_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 1. "BLE_GEN_IRQn,BLE_GEN_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 0. "BLE_WAKEUP_LP_IRQn,BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit)" "0,1"
group.long 0x300++0x03
line.long 0x00 "IPR0,Interrupt priority register 0"
hexmask.long.byte 0x00 24.--31. 1. "UART2_IRQn_prio,UART2_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "UART_IRQn_prio,UART_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "BLE_GEN_IRQn_prio,BLE_GEN_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "BLE_WAKEUP_LP_IRQn_prio,BLE_WAKEUP_LP_IRQn[7:0] bits (Interrupt priority)"
group.long 0x304++0x03
line.long 0x00 "IPR1,Interrupt priority register 1"
hexmask.long.byte 0x00 24.--31. 1. "KEYBRD_IRQn_prio,KEYBRD_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "ADC_IRQn_prio,ADC_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "SPI_IRQn_prio,SPI_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "I2C_IRQn_prio,I2C_IRQn[7:0] bits (Interrupt priority)"
group.long 0x308++0x03
line.long 0x00 "IPR2,Interrupt priority register 2"
hexmask.long.byte 0x00 24.--31. 1. "GPIO1_IRQn_prio,GPIO1_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "GPIO0_IRQn_prio,GPIO0_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "RF_CAL_IRQn_prio,RF_CAL_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "BLE_RF_DIAG_IRQn_prio,BLE_RF_DIAG_IRQn[7:0] bits (Interrupt priority)"
group.long 0x30C++0x03
line.long 0x00 "IPR3,Interrupt priority register 3"
hexmask.long.byte 0x00 24.--31. 1. "KEYBRD_IRQn_prio,KEYBRD_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "ADC_IRQn_prio,ADC_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "SPI2_IRQn_prio,SPI2_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "SPI_IRQn_prio,SPI_IRQn[7:0] bits (Interrupt priority)"
group.long 0x310++0x03
line.long 0x00 "IPR4,Interrupt priority register 4"
hexmask.long.byte 0x00 24.--31. 1. "SWTIM_IRQn_prio,SWTIM_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "GPIO4_IRQn_prio,GPIO4_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "GPIO3_IRQn_prio,GPIO3_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "GPIO2_IRQn_prio,GPIO2_IRQn[7:0] bits (Interrupt priority)"
group.long 0x314++0x03
line.long 0x00 "IPR5,Interrupt priority register 5"
hexmask.long.byte 0x00 24.--31. 1. "SRC_OUT_IRQn_prio,SRC_OUT_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. "SRC_IN_IRQn_prio,SRC_IN_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 8.--15. 1. "PCM_IRQn_prio,PCM_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 0.--7. 1. "WKUP_QUADEC_IRQn_prio,WKUP_QUADEC_IRQn[7:0] bits (Interrupt priority)"
group.long 0x318++0x03
line.long 0x00 "IPR6,Interrupt priority register 6"
hexmask.long.byte 0x00 0.--7. 1. "DMA_IRQn_prio,DMA_IRQn[7:0] bits (Interrupt priority)"
tree.end
tree "PERIPHERAL_REGISTERS (adc580_bif_nl01 registers)"
tree "ADC580_BIF_NL01"
base ad:0x50001500
group.word 0x08++0x01
line.word 0x00 "GP_ADC_CLEAR_INT_REG,General Purpose ADC Clear Interrupt Register"
hexmask.word 0x00 0.--15. 1. "GP_ADC_CLR_INT,Writing any value to this register will clear the ADC_INT interrupt"
group.word 0x02++0x01
line.word 0x00 "GP_ADC_CTRL2_REG,General Purpose ADC Second Control Register"
bitfld.word 0x00 3. "GP_ADC_I20U,Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC" "0,1"
bitfld.word 0x00 2. "GP_ADC_IDYN,Enables dynamic load current at the ADC LDO to minimize ripple on the reference voltage of the ADC" "0,1"
newline
bitfld.word 0x00 1. "GP_ADC_ATTN3X," "0,1"
bitfld.word 0x00 0. "GP_ADC_DELAY_EN,Enables delay function for several signals" "0,1"
group.word 0x00++0x01
line.word 0x00 "GP_ADC_CTRL_REG,General Purpose ADC Control Register"
bitfld.word 0x00 15. "GP_ADC_LDO_ZERO,Forces LDO-output to 0V" "0,1"
bitfld.word 0x00 14. "GP_ADC_LDO_EN,Turns on LDO" "0,1"
newline
bitfld.word 0x00 13. "GP_ADC_CHOP,Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC Highly recommended for DC-measurements" "0,1"
bitfld.word 0x00 12. "GP_ADC_MUTE,Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC)" "0,1"
newline
bitfld.word 0x00 11. "GP_ADC_SE," "0,1"
bitfld.word 0x00 10. "GP_ADC_SIGN," "0,1"
newline
bitfld.word 0x00 6.--9. "GP_ADC_SEL,ADC input selection which must be set before the GP_ADC_START bit is enabled" "0: P0[0] vs P0[1] All other,1: P0[1],2: P0[2],3: P0[3],4: AVS,5: VDD_REF,6: VDD_RTT (=VDD_REF),7: VBAT3V,8: VDCDC,9: VBAT1V All other combinations are,?..."
bitfld.word 0x00 5. "GP_ADC_MINT," "0,1"
newline
rbitfld.word 0x00 4. "GP_ADC_INT," "0,1"
bitfld.word 0x00 3. "GP_ADC_CLK_SEL," "0,1"
newline
bitfld.word 0x00 2. "GP_ADC_TEST,Reserved keep 0" "0,1"
bitfld.word 0x00 1. "GP_ADC_START," "0,1"
newline
bitfld.word 0x00 0. "GP_ADC_EN," "0,1"
group.word 0x0E++0x01
line.word 0x00 "GP_ADC_DELAY2_REG,General Purpose ADC Second Delay Register"
hexmask.word.byte 0x00 8.--15. 1. "DEL_ADC_START,Defines the delay for the GP_ADC_START bit"
hexmask.word.byte 0x00 0.--7. 1. "DEL_ADC_EN,Defines the delay for the GP_ADC_EN bit"
group.word 0x0C++0x01
line.word 0x00 "GP_ADC_DELAY_REG,General Purpose ADC Delay Register"
hexmask.word.byte 0x00 0.--7. 1. "DEL_LDO_EN,Defines the delay before the LDO enable (GP_ADC_LDO_EN)"
group.word 0x06++0x01
line.word 0x00 "GP_ADC_OFFN_REG,General Purpose ADC Negative Offset Register"
hexmask.word 0x00 0.--9. 1. "GP_ADC_OFFN,Offset adjust of 'negative' array of ADC-network (effective if 'GP_ADC_SE=0' or 'GP_ADC_SE=1 AND GP_ADC_SIGN=1')"
group.word 0x04++0x01
line.word 0x00 "GP_ADC_OFFP_REG,General Purpose ADC Positive Offset Register"
hexmask.word 0x00 0.--9. 1. "GP_ADC_OFFP,Offset adjust of 'positive' array of ADC-network (effective if 'GP_ADC_SE=0' or 'GP_ADC_SE=1 AND GP_ADC_SIGN=0')"
group.word 0x0A++0x01
line.word 0x00 "GP_ADC_RESULT_REG,General Purpose ADC Result Register"
hexmask.word 0x00 0.--9. 1. "GP_ADC_VAL,Returns the 10 bits linear value of the last AD conversion"
tree.end
tree "AMBACORE580_PATCH_GR00"
base ad:0x40008400
group.long 0x10++0x03
line.long 0x00 "PATCH_ADDR0_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_ADDR,This is the value which will be compared to the address on the AHB"
group.long 0x18++0x03
line.long 0x00 "PATCH_ADDR1_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_ADDR,This is the value which will be compared to the address on the AHB"
group.long 0x20++0x03
line.long 0x00 "PATCH_ADDR2_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_ADDR,This is the value which will be compared to the address on the AHB"
group.long 0x28++0x03
line.long 0x00 "PATCH_ADDR3_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_ADDR,This is the value which will be compared to the address on the AHB"
group.long 0x30++0x03
line.long 0x00 "PATCH_ADDR4_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_ADDR,This is the value which will be compared to the address on the AHB"
group.long 0x38++0x03
line.long 0x00 "PATCH_ADDR5_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_ADDR,This is the value which will be compared to the address on the AHB"
group.long 0x40++0x03
line.long 0x00 "PATCH_ADDR6_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_ADDR,This is the value which will be compared to the address on the AHB"
group.long 0x48++0x03
line.long 0x00 "PATCH_ADDR7_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_ADDR,This is the value which will be compared to the address on the AHB"
group.long 0x14++0x03
line.long 0x00 "PATCH_DATA0_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_DATA,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG"
group.long 0x1C++0x03
line.long 0x00 "PATCH_DATA1_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_DATA,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG"
group.long 0x24++0x03
line.long 0x00 "PATCH_DATA2_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_DATA,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG"
group.long 0x2C++0x03
line.long 0x00 "PATCH_DATA3_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_DATA,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG"
group.long 0x34++0x03
line.long 0x00 "PATCH_DATA4_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_DATA,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG"
group.long 0x3C++0x03
line.long 0x00 "PATCH_DATA5_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_DATA,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG"
group.long 0x44++0x03
line.long 0x00 "PATCH_DATA6_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_DATA,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG"
group.long 0x4C++0x03
line.long 0x00 "PATCH_DATA7_REG,Patch entry"
hexmask.long 0x00 0.--31. 1. "PATCH_DATA,This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG"
group.long 0x00++0x03
line.long 0x00 "PATCH_VALID_REG,Validity Control Register"
hexmask.long.byte 0x00 0.--7. 1. "PATCH_VALID,Indicates which patch entry is valid"
group.long 0x08++0x03
line.long 0x00 "PATCH_VALID_RESET_REG,Validity Reset Control Register"
hexmask.long.byte 0x00 0.--7. 1. "PATCH_VALID_RESET,Writing a bit with 1 will clear the corresponding bit of PATCH_VALID_REG to 0"
group.long 0x04++0x03
line.long 0x00 "PATCH_VALID_SET_REG,Validity Set Control Register"
hexmask.long.byte 0x00 0.--7. 1. "PATCH_VALID_SET,Writing a bit with 1 will set the corresponding bit of PATCH_VALID_REG to 1"
tree.end
tree "ANAMISC580_NL01"
base ad:0x50001600
group.word 0x02++0x01
line.word 0x00 "CLK_REF_CNT_REG,Count value for oscillator calibration"
hexmask.word 0x00 0.--15. 1. "REF_CNT_VAL,Indicates the calibration time with a decrement counter to 1"
group.word 0x00++0x01
line.word 0x00 "CLK_REF_SEL_REG,Select clock for oscillator calibration"
bitfld.word 0x00 2. "REF_CAL_START,Writing a '1' starts a calibration" "0,1"
bitfld.word 0x00 0.--1. "REF_CLK_SEL,Select clock input for calibration" "0: RC32K oscillator,1: RC16M oscillator,2: XTAL32K oscillator,3: RCX oscillator"
group.word 0x06++0x01
line.word 0x00 "CLK_REF_VAL_H_REG,XTAL16M reference cycles upper 16 bits"
hexmask.word 0x00 0.--15. 1. "XTAL_CNT_VAL,Returns the upper 16 bits of XTAL16 clock cycles during the calibration time defined with REF_CNT_VAL"
group.word 0x04++0x01
line.word 0x00 "CLK_REF_VAL_L_REG,XTAL16M reference cycles lower 16 bits"
hexmask.word 0x00 0.--15. 1. "XTAL_CNT_VAL,Returns the lower 16 bits of XTAL16 clock cycles during the calibration time defined with REF_CNT_VAL"
tree.end
tree "BLE580_GR01"
base ad:0x40000000
group.long 0xA4++0x03
line.long 0x00 "BLE_ACTSCANSTAT_REG,Active scan register"
hexmask.long.word 0x00 16.--24. 1. "BACKOFF,Active scan mode back-off counter initialization value"
newline
hexmask.long.word 0x00 0.--8. 1. "UPPERLIMIT,Active scan mode upper limit counter value"
group.long 0x90++0x03
line.long 0x00 "BLE_ADVCHMAP_REG,Advertising Channel Map"
bitfld.long 0x00 0.--2. "ADVCHMAP,Advertising Channel Map defined as per the advertising connection settings" "0: Do not use data channel i+37,1: Use data channel i+37,?..."
group.long 0xA0++0x03
line.long 0x00 "BLE_ADVTIM_REG,Advertising Packet Interval"
hexmask.long.word 0x00 0.--13. 1. "ADVINT,Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent"
group.long 0xC0++0x03
line.long 0x00 "BLE_AESCNTL_REG,Start AES register"
bitfld.long 0x00 0. "AES_START,Writing a 1 starts AES-128 ciphering process" "0,1"
group.long 0xD0++0x03
line.long 0x00 "BLE_AESKEY127_96_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. "AESKEY127_96,AES encryption 128-bit key"
group.long 0xC4++0x03
line.long 0x00 "BLE_AESKEY31_0_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. "AESKEY31_0,AES encryption 128-bit key"
group.long 0xC8++0x03
line.long 0x00 "BLE_AESKEY63_32_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. "AESKEY63_32,AES encryption 128-bit key"
group.long 0xCC++0x03
line.long 0x00 "BLE_AESKEY95_64_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. "AESKEY95_64,AES encryption 128-bit key"
group.long 0xD4++0x03
line.long 0x00 "BLE_AESPTR_REG,Pointer to the block to encrypt/decrypt"
hexmask.long.word 0x00 0.--15. 1. "AESPTR,Pointer to the memory zone where the block to encrypt/decrypt is stored"
group.long 0x44++0x03
line.long 0x00 "BLE_BASETIMECNTCORR_REG,Base Time Counter"
hexmask.long 0x00 0.--26. 1. "BASETIMECNTCORR,Base Time Counter correction value"
group.long 0x1C++0x03
line.long 0x00 "BLE_BASETIMECNT_REG,Base time reference counter"
hexmask.long 0x00 0.--26. 1. "BASETIMECNT,Value of the 625us base time reference counter"
group.long 0x24++0x03
line.long 0x00 "BLE_BDADDRL_REG,BLE device address LSB register"
hexmask.long 0x00 0.--31. 1. "BDADDRL,Bluetooth Low Energy Device Address"
group.long 0x28++0x03
line.long 0x00 "BLE_BDADDRU_REG,BLE device address MSB register"
bitfld.long 0x00 16. "PRIV_NPUB,Bluetooth Low Energy Device Address privacy indicator" "0: Public Bluetooth Device Address,1: Private Bluetooth Device Address"
newline
hexmask.long.word 0x00 0.--15. 1. "BDADDRU,Bluetooth Low Energy Device Address"
group.long 0x200++0x03
line.long 0x00 "BLE_CNTL2_REG,BLE Control Register 2"
bitfld.long 0x00 21. "BLE_RSSI_SEL," "0,1"
newline
rbitfld.long 0x00 20. "WAKEUPLPSTAT,The status of the BLE_WAKEUP_LP_IRQ" "0,1"
newline
bitfld.long 0x00 19. "SW_RPL_SPI,Keep to 0" "0,1"
newline
bitfld.long 0x00 18. "BB_ONLY,Keep to 0" "0,1"
newline
bitfld.long 0x00 17. "RADIO_ONLY,Keep to 0" "0,1"
newline
bitfld.long 0x00 9.--14. "BLE_CLK_SEL,BLE Clock Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8. "RADIO_PWRDN_ALLOW,This active high signal indicates when it is allowed for the BLE core (embedded in the Radio sub-System power domain) to be powered down" "0,1"
newline
bitfld.long 0x00 7. "MON_LP_CLK,The SW can only write a '0' to this bit" "0,1"
newline
rbitfld.long 0x00 6. "BLE_CLK_STAT," "0,1"
newline
bitfld.long 0x00 5. "DIAGPORT_REVERSE,BLE/RADIO Diagnostic Port Reverse order" "0,1"
newline
bitfld.long 0x00 3.--4. "DIAGPORT_SEL,BLE/RADIO Diagnostic Port Selection" "0: {BLE_DIAG2[7:5] BLE_DIAG1[4:3] BLE_DIAG0[2:0]},1: {BLE_DIAG2[7:5] BLE_DIAG1[4:3] BLE_DIAG0[2],2: RADIO_DIAG0[7:0],3: RADIO_DIAG1[7:0]"
newline
bitfld.long 0x00 2. "EMACCERRMSK,Exchange Memory Access Error Mask: When cleared to '0' the EM_ACC_ERR will not cause an BLE_ERROR_IRQ interrupt" "0,1"
newline
bitfld.long 0x00 1. "EMACCERRACK,Exchange Memory Access Error Acknowledge" "0,1"
newline
rbitfld.long 0x00 0. "EMACCERRSTAT,Exchange Memory Access Error Status: The bit is read-only and can be cleared only by writing a '1' at EMACCERRACK bitfield" "0,1"
group.long 0x2C++0x03
line.long 0x00 "BLE_CURRENTRXDESCPTR_REG,Rx Descriptor Pointer for the Receive Buffer Chained List"
hexmask.long.word 0x00 0.--13. 1. "CURRENTRXDESCPTR,Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List"
group.long 0x58++0x03
line.long 0x00 "BLE_DEBUGADDMAX_REG,Upper limit for the memory zone"
hexmask.long.word 0x00 0.--15. 1. "ADDMAX,Upper limit for the memory zone"
group.long 0x5C++0x03
line.long 0x00 "BLE_DEBUGADDMIN_REG,Lower limit for the memory zone"
hexmask.long.word 0x00 0.--15. 1. "ADDMIN,Lower limit for the memory zone"
group.long 0x30++0x03
line.long 0x00 "BLE_DEEPSLCNTL_REG,Deep-Sleep control register"
bitfld.long 0x00 31. "EXTWKUPDSB,External Wake-Up disable" "0: BLE Core can be woken by external wake-up,1: BLE Core cannot be woken up by external wake-up"
newline
rbitfld.long 0x00 15. "DEEP_SLEEP_STAT,Indicator of current Deep Sleep clock mux status" "0: BLE Core is not yet in Deep Sleep Mode,1: BLE Core is in Deep Sleep Mode (only Low Power"
newline
bitfld.long 0x00 4. "SOFT_WAKEUP_REQ,Wake Up Request from BLE Software" "0,1"
newline
bitfld.long 0x00 3. "DEEP_SLEEP_CORR_EN,625us base time reference integer and fractional part correction" "0,1"
newline
bitfld.long 0x00 2. "DEEP_SLEEP_ON," "0,1"
newline
bitfld.long 0x00 0.--1. "DEEP_SLEEP_IRQ_EN,Always set to '3' when DEEP_SLEEP_ON is set to '1'" "0,1,2,3"
group.long 0x38++0x03
line.long 0x00 "BLE_DEEPSLSTAT_REG,Duration of the last deep sleep phase register"
hexmask.long 0x00 0.--31. 1. "DEEPSLDUR,Actual duration of the last deep sleep phase measured in Low Power Clock cycles"
group.long 0x34++0x03
line.long 0x00 "BLE_DEEPSLWKUP_REG,Time (measured in Low Power clock cycles) in Deep Sleep Mode before waking-up the device"
hexmask.long 0x00 0.--31. 1. "DEEPSLTIME,Determines the time in Low Power Clock cycles to spend in Deep Sleep Mode before waking-up the device"
group.long 0x50++0x03
line.long 0x00 "BLE_DIAGCNTL_REG,Diagnostics Register"
bitfld.long 0x00 31. "DIAG3_EN," "0,1"
newline
bitfld.long 0x00 24.--29. "DIAG3,Only relevant when DIAG3_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 23. "DIAG2_EN," "0,1"
newline
bitfld.long 0x00 16.--21. "DIAG2,Only relevant when DIAG2_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15. "DIAG1_EN," "0,1"
newline
bitfld.long 0x00 8.--13. "DIAG1,Only relevant when DIAG1_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 7. "DIAG0_EN," "0,1"
newline
bitfld.long 0x00 0.--5. "DIAG0,Only relevant when DIAG0_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x03
line.long 0x00 "BLE_DIAGSTAT_REG,Debug use only"
hexmask.long.byte 0x00 24.--31. 1. "DIAG3STAT,Directly connected to ble_dbg3[7:0] output"
newline
hexmask.long.byte 0x00 16.--23. 1. "DIAG2STAT,Directly connected to ble_dbg2[7:0] output"
newline
hexmask.long.byte 0x00 8.--15. 1. "DIAG1STAT,Directly connected to ble_dbg1[7:0] output"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIAG0STAT,Directly connected to ble_dbg0[7:0] output"
group.long 0x3C++0x03
line.long 0x00 "BLE_ENBPRESET_REG,Time in low power oscillator cycles register"
hexmask.long.word 0x00 21.--31. 1. "TWEXT,Minimum and recommended value is 'TWIRQ_RESET + 1'"
newline
hexmask.long.word 0x00 10.--20. 1. "TWIRQ_SET,Minimum value is 'TWIRQ_RESET + 1'"
newline
hexmask.long.word 0x00 0.--9. 1. "TWIRQ_RESET,Recommended value is 1"
group.long 0x60++0x03
line.long 0x00 "BLE_ERRORTYPESTAT_REG,Error Type Status registers"
rbitfld.long 0x00 11. "CSFORMAT_ERROR,Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 10. "CSTXPTR_ERROR,Indicates whether CS-TXPTR is null this is a major software programming failure" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 8. "RADIO_EMACC_ERROR,Radio Controller Exchange Memory access error happens when Exchange Memory access are not served in time and data are corrupted" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 7. "LLCHMAP_ERROR,Link Layer Channel Map error happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 6. "IFS_UNDERRUN,Inter Frame Space Under run occurs if IFS time is not enough to update and read Control Structure/Descriptors and/or White List parsing is not finished and/or Decryption time is too long to be finished on time" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 5. "RXCRYPT_ERROR,Real Time Decryption Error happens when decryption is not finished before IFS time" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 4. "WHITELIST_ERROR,White List Timeout Error occurs if White List parsing is not finished on time" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 3. "APFM_ERROR,Anticipated Pre-Fetch Mechanism error happens when 3 consecutive Exchange Table entry have been programmed" "0: no error,1: Error occured"
newline
rbitfld.long 0x00 2. "TXDESC_ERROR,Tx Descriptor Error happens when fetched Tx Descriptor has TXDONE bit not set" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 1. "PKTCNTL_EMACC_ERROR,Packet Controller Exchange Memory access error happens when Exchange Memory access are not served in time and Tx/Rx data are corrupted" "0: No error,1: Error occurred"
newline
rbitfld.long 0x00 0. "TXCRYPT_ERROR,Real Time Encryption Error happens when encryption is not finished before Tx Payload has to be sent" "0: No error,1: Error occurred"
group.long 0x40++0x03
line.long 0x00 "BLE_FINECNTCORR_REG,Phase correction value register"
hexmask.long.word 0x00 0.--9. 1. "FINECNTCORR,Phase correction value for the 625usec reference counter (i.e Fine Counter) in us"
group.long 0x20++0x03
line.long 0x00 "BLE_FINETIMECNT_REG,Fine time reference counter"
hexmask.long.word 0x00 0.--9. 1. "FINECNT,Value of the current usec fine time reference counter"
group.long 0xF8++0x03
line.long 0x00 "BLE_FINETIMTGT_REG,Fine Timer Target value"
hexmask.long 0x00 0.--26. 1. "FINETARGET,Fine Timer Target value on which a BLE_FINETGTIM_IRQ must be generated"
group.long 0xF4++0x03
line.long 0x00 "BLE_GROSSTIMTGT_REG,Gross Timer Target value"
hexmask.long.word 0x00 0.--15. 1. "GROSSTARGET,Gross Timer Target value on which a BLE_GROSSTGTIM_IRQ must be generated"
group.long 0x18++0x03
line.long 0x00 "BLE_INTACK_REG,Interrupt acknowledge register"
bitfld.long 0x00 8. "RADIOCNTLINTACK,Radio Controller interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt" "0,1"
newline
bitfld.long 0x00 7. "FINETGTIMINTACK,Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt" "0,1"
newline
bitfld.long 0x00 6. "GROSSTGTIMINTACK,Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt" "0,1"
newline
bitfld.long 0x00 5. "ERRORINTACK,Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt" "0,1"
newline
bitfld.long 0x00 4. "CRYPTINTACK,Encryption/Decryption interrupt acknowledgement bit Software writing 1 acknowledges the Encryption / Decryption interrupt" "0,1"
newline
bitfld.long 0x00 3. "EVENTINTACK,End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt" "0,1"
newline
bitfld.long 0x00 2. "SLPINTACK,End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt" "0,1"
newline
bitfld.long 0x00 1. "RXINTACK,Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt" "0,1"
newline
bitfld.long 0x00 0. "CSCNTINTACK,625us base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt" "0,1"
group.long 0x0C++0x03
line.long 0x00 "BLE_INTCNTL_REG,Interrupt controller register"
hexmask.long.word 0x00 16.--31. 1. "INTCSCNTL,Selection of the CS counter that generates an interrupt"
newline
bitfld.long 0x00 15. "CSCNTDEVMSK,CSCNT interrupt mask during event" "0: CSCNT Interrupt not generated during events,1: CSCNT Interrupt generated during events"
newline
bitfld.long 0x00 8. "RADIOCNTLINTMSK,Radio Controller interrupt mask" "0: Interrupt not generated,1: Interrupt generated"
newline
bitfld.long 0x00 7. "FINETGTIMINTMSK,Fine Target Timer Mask" "0: Interrupt not generated,1: Interrupt generated"
newline
bitfld.long 0x00 6. "GROSSTGTIMINTMSK,Gross Target Timer Mask" "0: Interrupt not generated,1: Interrupt generated"
newline
bitfld.long 0x00 5. "ERRORINTMSK,Error Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
newline
bitfld.long 0x00 4. "CRYPTINTMSK,Encryption / Decryption Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
newline
bitfld.long 0x00 3. "EVENTINTMSK,End of event Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
newline
bitfld.long 0x00 2. "SLPINTMSK,Sleep Mode Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
newline
bitfld.long 0x00 1. "RXINTMSK,Rx Interrupt Mask" "0: Interrupt not generated,1: Interrupt generated"
newline
bitfld.long 0x00 0. "CSCNTINTMSK,625usec Base Time Interrupt Mask\n" "0: Interrupt not generated\n,1: Interrupt generated"
group.long 0x14++0x03
line.long 0x00 "BLE_INTRAWSTAT_REG,Interrupt raw status register"
rbitfld.long 0x00 8. "RADIOCNTLINTRAWSTAT,Radio Controller interrupt raw status" "0: No Gross Target Timer interrupt,1: A Gross Target Timer interrupt is pending"
newline
rbitfld.long 0x00 7. "FINETGTIMINTRAWSTAT,Fine Target Timer Error interrupt raw status" "0: No Fine Target Timer interrupt,1: A Fine Target Timer interrupt is pending"
newline
rbitfld.long 0x00 6. "GROSSTGTIMINTRAWSTAT,Gross Target Timer interrupt raw status" "0: No Gross Target Timer interrupt,1: A Gross Target Timer interrupt is pending"
newline
rbitfld.long 0x00 5. "ERRORINTRAWSTAT,Error interrupt raw status" "0: No Error interrupt,1: An Error interrupt is pending"
newline
rbitfld.long 0x00 4. "CRYPTINTRAWSTAT,Encryption/Decryption interrupt raw status" "0: No Encryption / Decryption interrupt,1: An Encryption / Decryption interrupt is pending"
newline
rbitfld.long 0x00 3. "EVENTINTRAWSTAT,End of Event interrupt raw status" "0: No End of Advertising / Scanning / Connection,1: An End of Advertising / Scanning / Connection"
newline
rbitfld.long 0x00 2. "SLPINTRAWSTAT,Sleep interrupt raw status" "0: No End of Sleep Mode interrupt,1: An End of Sleep Mode interrupt is pending"
newline
rbitfld.long 0x00 1. "RXINTRAWSTAT,Packet Reception interrupt raw status" "0: No Rx interrupt,1: An Rx interrupt is pending"
newline
rbitfld.long 0x00 0. "CSCNTINTRAWSTAT,625us base time reference interrupt raw status" "0: No 625us Base Time interrupt,1: A 625us Base Time interrupt is pending"
group.long 0x10++0x03
line.long 0x00 "BLE_INTSTAT_REG,Interrupt status register"
rbitfld.long 0x00 8. "RADIOCNTLINTSTAT,Radio Controller interrupt status" "0: No Gross Target Timer interrupt,1: A Gross Target Timer interrupt is pending"
newline
rbitfld.long 0x00 7. "FINETGTIMINTSTAT,Masked Fine Target Timer Error interrupt status" "0: No Fine Target Timer interrupt,1: A Fine Target Timer interrupt is pending"
newline
rbitfld.long 0x00 6. "GROSSTGTIMINTSTAT,Masked Gross Target Timer interrupt status" "0: No Gross Target Timer interrupt,1: A Gross Target Timer interrupt is pending"
newline
rbitfld.long 0x00 5. "ERRORINTSTAT,Masked Error interrupt status" "0: No Error interrupt,1: An Error interrupt is pending"
newline
rbitfld.long 0x00 4. "CRYPTINTSTAT,Masked Encryption/Decryption interrupt status" "0: No Encryption / Decryption interrupt,1: An Encryption / Decryption interrupt is pending"
newline
rbitfld.long 0x00 3. "EVENTINTSTAT,Masked End of Event interrupt status" "0: No End of Advertising / Scanning / Connection,1: An End of Advertising / Scanning / Connection"
newline
rbitfld.long 0x00 2. "SLPINTSTAT,Masked Sleep interrupt status" "0: No End of Sleep Mode interrupt,1: An End of Sleep Mode interrupt is pending"
newline
rbitfld.long 0x00 1. "RXINTSTAT,Masked Packet Reception interrupt status" "0: No Rx interrupt,1: An Rx interrupt is pending"
newline
rbitfld.long 0x00 0. "CSCNTINTSTAT,Masked 625us base time reference interrupt status" "0: No 625us Base Time interrupt,1: A 625us Base Time interrupt is pending"
group.long 0x70++0x03
line.long 0x00 "BLE_RADIOCNTL0_REG,Radio interface control register"
bitfld.long 0x00 22. "DPCORR_EN,Enable the use of delayed DC compensated data path in Radio Correlator block" "0: Disable Must be,1: Enable"
group.long 0x74++0x03
line.long 0x00 "BLE_RADIOCNTL1_REG,Radio interface control register"
bitfld.long 0x00 16.--20. "XRFSEL,Extended radio selection field Must be set to '00011'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80++0x03
line.long 0x00 "BLE_RADIOPWRUPDN_REG,RX/TX power up/down phase register"
hexmask.long.byte 0x00 24.--30. 1. "RTRIP_DELAY,Defines round trip delay value"
newline
hexmask.long.byte 0x00 16.--23. 1. "RXPWRUP,This register holds the length in us of the Rx power up phase for the current radio device"
newline
bitfld.long 0x00 8.--11. "TXPWRDN,This register extends the length in us of the Tx power down phase for the current radio device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 0.--7. 1. "TXPWRUP,This register holds the length in us of the Tx power up phase for the current radio device"
group.long 0xE0++0x03
line.long 0x00 "BLE_RFTESTCNTL_REG,RF Testing Register"
bitfld.long 0x00 31. "INFINITERX,Applicable for all frame format" "0: Normal mode of operation,1: Infinite Rx window"
newline
bitfld.long 0x00 15. "INFINITETX,Applicable for all frame format" "0: Normal mode of operation,1: Infinite Tx packet / Normal start of a packet"
newline
bitfld.long 0x00 14. "TXLENGTHSRC,Applicable only in Tx/Rx RF Test mode" "0: Normal mode of operation,1: Uses RFTESTCNTL-TXLENGTH packet length (can"
newline
bitfld.long 0x00 13. "PRBSTYPE,Applicable only in Tx/Rx RF Test mode" "0: Tx Packet Payload are PRBS9 type,1: Tx Packet Payload are PRBS15 type PRBS9 is"
newline
bitfld.long 0x00 12. "TXPLDSRC,Applicable only in Tx/Rx RF Test mode" "0: Tx Packet Payload source is the Control..,1: Tx Packet Payload are PRBS generator"
newline
hexmask.long.word 0x00 0.--8. 1. "TXLENGTH,Applicable only in Tx/Rx RF Test mode Tx packet length in number of byte"
group.long 0x204++0x03
line.long 0x00 "BLE_RF_DIAGIRQ_REG,BLE/RF Diagnostic IRQ Control Register"
rbitfld.long 0x00 31. "DIAGIRQ_STAT_3,Same as DIAGIRQ_STAT_0" "0,1"
newline
bitfld.long 0x00 30. "DIAGIRQ_EDGE_3,Same as DIAGIRQ_EDGE_0" "0,1"
newline
bitfld.long 0x00 27.--29. "DIAGIRQ_BSEL_3,Same as DIAGIRQ_BSEL_0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 25.--26. "DIAGIRQ_WSEL_3,Same as DIAGIRQ_WSEL_0" "0,1,2,3"
newline
bitfld.long 0x00 24. "DIAGIRQ_MASK_3,Same as DIAGIRQ_MASK_0" "0,1"
newline
rbitfld.long 0x00 23. "DIAGIRQ_STAT_2,Same as DIAGIRQ_STAT_0" "0,1"
newline
bitfld.long 0x00 22. "DIAGIRQ_EDGE_2,Same as DIAGIRQ_EDGE_0" "0,1"
newline
bitfld.long 0x00 19.--21. "DIAGIRQ_BSEL_2,Same as DIAGIRQ_BSEL_0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--18. "DIAGIRQ_WSEL_2,Same as DIAGIRQ_WSEL_0" "0,1,2,3"
newline
bitfld.long 0x00 16. "DIAGIRQ_MASK_2,Same as DIAGIRQ_MASK_0" "0,1"
newline
rbitfld.long 0x00 15. "DIAGIRQ_STAT_1,Same as DIAGIRQ_STAT_0" "0,1"
newline
bitfld.long 0x00 14. "DIAGIRQ_EDGE_1,Same as DIAGIRQ_EDGE_0" "0,1"
newline
bitfld.long 0x00 11.--13. "DIAGIRQ_BSEL_1,Same as DIAGIRQ_BSEL_0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--10. "DIAGIRQ_WSEL_1,Same as DIAGIRQ_WSEL_0" "0,1,2,3"
newline
bitfld.long 0x00 8. "DIAGIRQ_MASK_1,Same as DIAGIRQ_MASK_0" "0,1"
newline
rbitfld.long 0x00 7. "DIAGIRQ_STAT_0,Diagnostic IRQ Status 0 This bit is read only" "0,1"
newline
bitfld.long 0x00 6. "DIAGIRQ_EDGE_0,Diagnostic IRQ Edge 0 Selects the edge of the selected bit (refer to DIAGIRQ_BSEL_0) that will trigger the assertion of DIAGIRQ_STAT_0" "0,1"
newline
bitfld.long 0x00 3.--5. "DIAGIRQ_BSEL_0,Diagnostic IRQ Bit Select 0 Selects the bit of the 8-bit bus (as selected by the DIAGIRQ_WSEL_0) that will be used for the IRQ generation" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 1.--2. "DIAGIRQ_WSEL_0,Diagnostic IRQ Word Select 0 Selects the 8-bit diagnostic bus that will be used for the IRQ generation" "0: Selects the BLE_DIAG0,1: Selects the BLE_DIAG1,2: Selects the RADIO_DIAG0,3: Selects the RADIO_DIAG1"
newline
bitfld.long 0x00 0. "DIAGIRQ_MASK_0,Diagnostic IRQ Mask 0 When set to '1' a BLE_RF_DIAG_IRQ will be generated on each rise of the DIAGIRQ_STAT_0 bit" "0,1"
group.long 0x00++0x03
line.long 0x00 "BLE_RWBTLECNTL_REG,BLE Control register"
bitfld.long 0x00 31. "MASTER_SOFT_RST,Reset the complete system except registers and timing generator when written with a 1" "0,1"
newline
bitfld.long 0x00 30. "MASTER_TGSOFT_RST,Reset the timing generator when written with a 1" "0,1"
newline
bitfld.long 0x00 29. "REG_SOFT_RST,Reset the complete register block when written with a 1" "0,1"
newline
bitfld.long 0x00 26. "RFTEST_ABORT,Abort the current RF Testing defined as per CS-FORMAT when written with a 1" "0,1"
newline
bitfld.long 0x00 25. "ADVERT_ABORT,Abort the current Advertising event when written with a 1" "0,1"
newline
bitfld.long 0x00 24. "SCAN_ABORT,Abort the current scan window when written with a 1" "0,1"
newline
bitfld.long 0x00 22. "MD_DSB," "0,1"
newline
bitfld.long 0x00 21. "SN_DSB," "0,1"
newline
bitfld.long 0x00 20. "NESN_DSB," "0,1"
newline
bitfld.long 0x00 19. "CRYPT_DSB," "0,1"
newline
bitfld.long 0x00 18. "WHIT_DSB," "0,1"
newline
bitfld.long 0x00 17. "CRC_DSB," "0,1"
newline
bitfld.long 0x00 16. "HOP_REMAP_DSB," "0,1"
newline
bitfld.long 0x00 12. "TXWINOFFSEL,Applicable only if device is in Initiator mode" "0: Window Offset field in CONNECT_REQ comes from..,1: Window Offset field in CONNECT_REQ comes from"
newline
bitfld.long 0x00 11. "RXDESCPTRSEL," "0,1"
newline
bitfld.long 0x00 10. "ADVERRFILT_EN,Advertising Channels Error Filtering Enable control" "0: BLE Core reports all errors to BLE Software,1: BLE Core reports only correctly received packet"
newline
bitfld.long 0x00 9. "WLSYNC_EN," "0,1"
newline
bitfld.long 0x00 8. "RWBLE_EN," "0,1"
newline
bitfld.long 0x00 4.--7. "RXWINSZDEF,Default Rx Window size in us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--2. "SYNCERR,Indicates the maximum number of errors allowed to recognize the synchronization word" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "BLE_RWBTLECONF_REG,Configuration register"
rbitfld.long 0x00 24.--29. "ADD_WIDTH,Value of the BLE_ADDRESS_WIDTH parameter converted into binary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x00 16.--22. 1. "RFIF,Supported radio interfaces"
newline
rbitfld.long 0x00 8.--13. "CLK_SEL,Operating Frequency (in MHz)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 5. "DMMODE," "0,1"
newline
rbitfld.long 0x00 4. "INTMODE," "0,1"
newline
rbitfld.long 0x00 3. "WLAN," "0,1"
newline
rbitfld.long 0x00 2. "USEDBG," "0,1"
newline
rbitfld.long 0x00 1. "USECRYPT," "0,1"
newline
rbitfld.long 0x00 0. "BUSWIDTH,Processor bus width" "0: 16 bits,1: 32 bits"
group.long 0xDC++0x03
line.long 0x00 "BLE_RXMICVAL_REG,AES / CCM plain MIC value"
hexmask.long 0x00 0.--31. 1. "RXMICVAL,AES / CCM plain MIC value"
group.long 0xFC++0x03
line.long 0x00 "BLE_SAMPLECLK_REG,Samples the Base Time Counter"
bitfld.long 0x00 0. "SAMP,Writing a 1 samples the Base Time Counter value in BASETIMECNT register" "0,1"
group.long 0x64++0x03
line.long 0x00 "BLE_SWPROFILING_REG,Software Profiling register"
hexmask.long 0x00 0.--31. 1. "SWPROFVAL,Software Profiling register: used by BLE Software for profiling purpose: this value is copied on Diagnostic port"
group.long 0xF0++0x03
line.long 0x00 "BLE_TIMGENCNTL_REG,Timing Generator Register"
hexmask.long.byte 0x00 0.--7. 1. "PREFTECH_TIME,Defines Exchange Table pre-fetch instant in us"
group.long 0xD8++0x03
line.long 0x00 "BLE_TXMICVAL_REG,AES / CCM plain MIC value"
hexmask.long 0x00 0.--31. 1. "TXMICVAL,AES / CCM plain MIC value"
group.long 0x04++0x03
line.long 0x00 "BLE_VERSION_REG,Version register"
hexmask.long.byte 0x00 24.--31. 1. "TYP,BLE Core Type - 0x6 means BT4.0 (i.e correspond LL version assigned number)"
newline
hexmask.long.byte 0x00 16.--23. 1. "REL,BLE Core version - Major release number.(Correspond to FS v1.11)"
newline
hexmask.long.byte 0x00 8.--15. 1. "UPG,BLE Core upgrade - Upgrade number"
newline
hexmask.long.byte 0x00 0.--7. 1. "BUILD,BLE Core Build - Build number"
group.long 0xB8++0x03
line.long 0x00 "BLE_WLNBDEV_REG,Devices in white list"
hexmask.long.byte 0x00 8.--15. 1. "NBPRIVDEV,Number of private devices in the white list"
newline
hexmask.long.byte 0x00 0.--7. 1. "NBPUBDEV,Number of public devices in the white list"
group.long 0xB4++0x03
line.long 0x00 "BLE_WLPRIVADDPTR_REG,Start address of private devices list"
hexmask.long.word 0x00 0.--15. 1. "WLPRIVADDPTR,Start address pointer of the private devices white list"
group.long 0xB0++0x03
line.long 0x00 "BLE_WLPUBADDPTR_REG,Start address of public devices list"
hexmask.long.word 0x00 0.--15. 1. "WLPUBADDPTR,Start address pointer of the public devices white list"
tree.end
tree "CHIP_VERSION"
base ad:0x50003200
group.byte 0x05++0x00
line.byte 0x00 "CHIP_CONFIG1_REG,Chip configuration register 1"
hexmask.byte 0x00 0.--7. 1. "CHIP_CONFIG1,First character of Chip Configuration '0M2' in ASCII"
group.byte 0x06++0x00
line.byte 0x00 "CHIP_CONFIG2_REG,Chip configuration register 2"
hexmask.byte 0x00 0.--7. 1. "CHIP_CONFIG2,Second character of Chip Configuration '0M2' in ASCII"
group.byte 0x07++0x00
line.byte 0x00 "CHIP_CONFIG3_REG,Chip configuration register 3"
hexmask.byte 0x00 0.--7. 1. "CHIP_CONFIG3,Third character of Chip Configuration '0M2' in ASCII"
group.byte 0x00++0x00
line.byte 0x00 "CHIP_ID1_REG,Chip identification register 1"
hexmask.byte 0x00 0.--7. 1. "CHIP_ID1,First character of device type '580' in ASCII"
group.byte 0x01++0x00
line.byte 0x00 "CHIP_ID2_REG,Chip identification register 2"
hexmask.byte 0x00 0.--7. 1. "CHIP_ID2,Second character of device type '580' in ASCII"
group.byte 0x02++0x00
line.byte 0x00 "CHIP_ID3_REG,Chip identification register 3"
hexmask.byte 0x00 0.--7. 1. "CHIP_ID3,Third character of device type '580' in ASCII"
group.byte 0x04++0x00
line.byte 0x00 "CHIP_REVISION_REG,Chip revision register"
abitfld.byte 0x00 0.--7. "REVISION_ID,Chip version corresponds with type number in ASCII" "0x41=65: 'A',0x42=66: 'B'"
group.byte 0x03++0x00
line.byte 0x00 "CHIP_SWC_REG,Software compatibility register"
rbitfld.byte 0x00 0.--3. "CHIP_SWC,SoftWare Compatibility code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x0A++0x00
line.byte 0x00 "CHIP_TEST1_REG,Chip test register 1"
group.byte 0x0B++0x00
line.byte 0x00 "CHIP_TEST2_REG,Chip test register 2"
tree.end
tree "CRG580_DCDC_NL01"
base ad:0x50000080
group.word 0x06++0x01
line.word 0x00 "DCDC_CAL1_REG,DCDC first calibration register"
bitfld.word 0x00 0.--5. "DCDC_CAL1,When DCDC_AUTO_CAL[0] is '0' this register is used to change the offset of the current sensing comparators in the DCDC-converter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x08++0x01
line.word 0x00 "DCDC_CAL2_REG,DCDC second calibration register"
bitfld.word 0x00 0.--5. "DCDC_CAL2,When DCDC_AUTO_CAL[1] is '0' this register is used to change the offset of the current sensing comparators in the DCDC-converter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x0A++0x01
line.word 0x00 "DCDC_CAL3_REG,DCDC thirth calibration register"
bitfld.word 0x00 0.--5. "DCDC_CAL3,When DCDC_AUTO_CAL[2] is '0' this register is used to change the offset of the current sensing comparators in the DCDC-converter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x02++0x01
line.word 0x00 "DCDC_CTRL2_REG,DCDC second control register"
bitfld.word 0x00 12.--15. "DCDC_VOLT_LEV,Nominal output voltage of the DCDC-converter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 9.--11. "DCDC_VBAT3V_LEV,Nominal VBAT3V output voltage of the boost converter" "?,?,?,3: 1.8V + N*25mV,4: 2.4V,5: 2.5V,6: 2.62V,7: 2.76V (Note: MSB"
newline
bitfld.word 0x00 7.--8. "DCDC_TON,This defines the minimum on-time of the comparators" "0,1,2,3"
bitfld.word 0x00 3.--6. "DCDC_CUR_LIM,Current limit in the switches of the DCDC-converter (approximate values): N x 10mA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--2. "DCDC_AUTO_CAL,Control of the automatic calibration of the DCDC-converter" "0,1,2,3,4,5,6,7"
group.word 0x04++0x01
line.word 0x00 "DCDC_CTRL3_REG,DCDC thirth control register"
bitfld.word 0x00 3.--4. "DCDC_TIMEOUT," "0,1,2,3"
bitfld.word 0x00 1.--2. "DCDC_IDLE_CLK,Clock used as trigger for the idle state to check voltage" "0: 16 MHz,1: 4 MHz,2: 1 MHz,3: 250 kHz"
newline
bitfld.word 0x00 0. "BUCK_ENABLE,Enables the buck converter when the device becomes active and VBAT1V is connected to GND" "0,1"
group.word 0x00++0x01
line.word 0x00 "DCDC_CTRL_REG,DCDC control register"
bitfld.word 0x00 14.--15. "DCDC_TUNE,Tune-bits to compensate for parasitic resistance in the current sense circuit of the DCDC-converter" "0,1,2,3"
bitfld.word 0x00 12.--13. "DCDC_DRIVE_OSW,Drive level of the switch between SWITCH and VDCDC" "0: 100 percent,1: 66 percent,2: 33 percent,3: off"
newline
bitfld.word 0x00 10.--11. "DCDC_DRIVE_PSW,Drive level of the switch between SWITCH and VBAT3V" "0: 100 percent,1: 66 percent,2: 33 percent,3: off"
bitfld.word 0x00 8.--9. "DCDC_DRIVE_NSW,Drive level of the switch between SWITCH and GROUND" "0: 100 percent,1: 66 percent,2: 33 percent,3: off"
newline
bitfld.word 0x00 5.--7. "DCDC_MODE,Testmodes keep 000" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 1.--3. "DCDC_VBAT1V_LEV,If VBAT1V is below this level the boost converter will be disabled" "?,?,?,3: 1.0V,?,5: 0.8V,6: 0.6V,7: 0V (always"
tree.end
tree "CRG580_NL01"
base ad:0x50000000
group.word 0x2A++0x01
line.word 0x00 "ANA_STATUS_REG,Status bit of analog (power management) circuits"
rbitfld.word 0x00 9. "BOOST_SELECTED,Indicates that DCDC is in boost mode" "0,1"
newline
rbitfld.word 0x00 7. "BANDGAP_OK,Indicates that BANDGAP is OK" "0,1"
newline
rbitfld.word 0x00 6. "BOOST_VBAT_OK,Indicates that VBAT is above threshold while in BOOST converter mode" "0,1"
newline
rbitfld.word 0x00 5. "LDO_ANA_OK,Indicates that LDO_ANA is in regulation" "0,1"
newline
rbitfld.word 0x00 4. "LDO_VDD_OK,Indicates that LDO_VDD is in regulation" "0,1"
newline
rbitfld.word 0x00 3. "LDO_OTP_OK,Indicates that LDO_OTP is in regulation" "0,1"
newline
rbitfld.word 0x00 2. "VDCDC_OK,Indicates that VDCDC is above threshold" "0,1"
newline
rbitfld.word 0x00 1. "VBAT1V_OK,Indicates that VBAT1V is above threshold" "0,1"
newline
rbitfld.word 0x00 0. "VBAT1V_AVAILABLE,Indicates that VBAT1V is available" "0,1"
group.word 0x28++0x01
line.word 0x00 "BANDGAP_REG,Bandgap trimming"
bitfld.word 0x00 14. "BGR_LOWPOWER,Test-mode do not use" "0,1"
newline
bitfld.word 0x00 10.--13. "LDO_RET_TRIM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 5.--9. "BGR_ITRIM,Current trimming for bias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0.--4. "BGR_TRIM,Trim register for bandgap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x22++0x01
line.word 0x00 "CLK_16M_REG,16 MHz RC-oscillator register"
bitfld.word 0x00 9. "XTAL16_NOISE_FILT_ENABLE,Enables noise flter in 16 MHz crystal oscillator" "0,1"
newline
bitfld.word 0x00 8. "XTAL16_BIAS_SH_ENABLE,Enables Ibias sample/hold function in 16 MHz crystal oscillator" "0,1"
newline
bitfld.word 0x00 5.--7. "XTAL16_CUR_SET,Bias current for the 16 MHz XTAL oscillator" "0: minimum,?,?,?,?,?,?,7: maximum"
newline
bitfld.word 0x00 1.--4. "RC16M_TRIM,Controls the frequency of the RC16M oscillator" "0: lowest frequency,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: highest frequency"
newline
bitfld.word 0x00 0. "RC16M_ENABLE,Enables the 16 MHz RC oscillator" "0,1"
group.word 0x20++0x01
line.word 0x00 "CLK_32K_REG,32 kHz oscillator register"
bitfld.word 0x00 12. "XTAL32K_DISABLE_AMPREG,Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator" "0,1"
newline
bitfld.word 0x00 8.--11. "RC32K_TRIM,Controls the frequency of the RC32K oscillator" "0: lowest frequency,?,?,?,?,?,?,7: default,?,?,?,?,?,?,?,15: highest frequency"
newline
bitfld.word 0x00 7. "RC32K_ENABLE,Enables the 32 kHz RC oscillator" "0,1"
newline
bitfld.word 0x00 3.--6. "XTAL32K_CUR,Bias current for the 32kHz XTAL oscillator" "0: minimum,?,?,3: default,?,?,?,?,?,?,?,?,?,?,?,15: maximum For each"
newline
bitfld.word 0x00 1.--2. "XTAL32K_RBIAS,Setting for the bias resistor of the 32 kHz XTAL oscillator" "0: maximum,?,?,3: minimum Prefered"
newline
bitfld.word 0x00 0. "XTAL32K_ENABLE,Enables the 32 kHz XTAL oscillator" "0,1"
group.word 0x00++0x01
line.word 0x00 "CLK_AMBA_REG,HCLK PCLK divider and clock gates"
bitfld.word 0x00 7. "OTP_ENABLE,Clock enable for OTP controller" "0,1"
newline
bitfld.word 0x00 4.--5. "PCLK_DIV,APB interface clock (PCLK)" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8"
newline
bitfld.word 0x00 0.--1. "HCLK_DIV,AHB interface and microprocessor clock (HCLK)" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8"
group.word 0x0A++0x01
line.word 0x00 "CLK_CTRL_REG,Clock control register"
rbitfld.word 0x00 7. "RUNNING_AT_XTAL16M,Indicates that the XTAL16M clock is used as clock and may not be switched off" "0,1"
newline
rbitfld.word 0x00 6. "RUNNING_AT_RC16M,Indicates that the RC16M clock is used as clock" "0,1"
newline
rbitfld.word 0x00 5. "RUNNING_AT_32K,Indicates that either the RC32k or XTAL32k is being used as clock" "0,1"
newline
bitfld.word 0x00 3. "XTAL16M_SPIKE_FLT_DISABLE,Disable spikefilter in digital clock" "0,1"
newline
bitfld.word 0x00 2. "XTAL16M_DISABLE,Setting this bit instantaneously disables the 16 MHz crystal oscillator" "0,1"
newline
bitfld.word 0x00 0.--1. "SYS_CLK_SEL,Selects the clock source" "0: XTAL16M (check the XTAL16_SETTLED and,1: RC16M 0x2/0x3,?..."
group.word 0x02++0x01
line.word 0x00 "CLK_FREQ_TRIM_REG,Xtal frequency trimming register"
bitfld.word 0x00 8.--10. "COARSE_ADJ,Xtal frequency course trimming register" "0: lowest frequency,?,?,?,?,?,?,7: highest frequencyIncrement or decrement the"
newline
abitfld.word 0x00 0.--7. "FINE_ADJ,Xtal frequency fine trimming register" "0x00=0: lowest frequency,0xFF=255: highest frequency"
group.word 0x04++0x01
line.word 0x00 "CLK_PER_REG,Peripheral divider register"
bitfld.word 0x00 15. "QUAD_ENABLE,Enable the Quadrature clock" "0,1"
newline
bitfld.word 0x00 11. "SPI_ENABLE,Enable SPI clock" "0,1"
newline
bitfld.word 0x00 8.--9. "SPI_DIV,Division factor for SPI" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8"
newline
bitfld.word 0x00 7. "UART1_ENABLE,Enable UART1 clock" "0,1"
newline
bitfld.word 0x00 6. "UART2_ENABLE,Enable UART2 clock" "0,1"
newline
bitfld.word 0x00 5. "I2C_ENABLE,Enable I2C clock" "0,1"
newline
bitfld.word 0x00 4. "WAKEUPCT_ENABLE,Enable Wakeup CaptureTimer clock" "0,1"
newline
bitfld.word 0x00 3. "TMR_ENABLE,Enable TIMER0 and TIMER2 clock" "0,1"
newline
bitfld.word 0x00 0.--1. "TMR_DIV,Division factor for TIMER0 and TIMER2" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8"
group.word 0x08++0x01
line.word 0x00 "CLK_RADIO_REG,Radio PLL control register"
bitfld.word 0x00 7. "BLE_ENABLE,Enable the BLE core clocks" "0,1"
newline
bitfld.word 0x00 6. "BLE_LP_RESET,Reset for the BLE LP timer" "0,1"
newline
bitfld.word 0x00 4.--5. "BLE_DIV,Division factor for BLE core blocks" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8 The programmed"
newline
bitfld.word 0x00 3. "RFCU_ENABLE,Enable the RF control Unit clock" "0,1"
newline
bitfld.word 0x00 0.--1. "RFCU_DIV,Division factor for RF Control Unit" "0: divide by 1,1: divide by 2,2: divide by 4,3: divide by 8 The programmed"
group.word 0x24++0x01
line.word 0x00 "CLK_RCX20K_REG,RCX-oscillator control register"
bitfld.word 0x00 12. "RCX20K_SELECT,Selects RCX oscillator" "0: RC32K oscillator,1: RCX oscillator"
newline
bitfld.word 0x00 11. "RCX20K_ENABLE,Enable the RCX oscillator" "0,1"
newline
bitfld.word 0x00 10. "RCX20K_LOWF,Extra low frequency" "0,1"
newline
bitfld.word 0x00 8.--9. "RCX20K_BIAS,Bias control" "0,1,2,3"
newline
bitfld.word 0x00 4.--7. "RCX20K_NTC,Temperature control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "RCX20K_TRIM,Controls the frequency of the RCX oscillator" "0: lowest frequency,?,?,?,?,?,?,7: default,?,?,?,?,?,?,?,15: highest frequency"
group.word 0x10++0x01
line.word 0x00 "PMU_CTRL_REG,Power Management Unit control register"
bitfld.word 0x00 8.--11. "RETENTION_MODE,Select the retainability of the 4 retention RAM macros" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 7. "FORCE_BOOST,Force the DCDC into boost mode at next wakeup" "0,1"
newline
bitfld.word 0x00 6. "FORCE_BUCK,Force the DCDC into buck mode at next wakeup" "0,1"
newline
bitfld.word 0x00 4.--5. "OTP_COPY_DIV,Sets the HCLK division during OTP mirroring" "0,1,2,3"
newline
bitfld.word 0x00 2. "RADIO_SLEEP,Put the digital part of the radio in powerdown" "0,1"
newline
bitfld.word 0x00 1. "PERIPH_SLEEP,Put all peripherals (I2C UART SPI ADC) in powerdown" "0,1"
newline
bitfld.word 0x00 0. "RESET_ON_WAKEUP,Perform a Hardware Reset after waking up" "0,1"
group.word 0x30++0x01
line.word 0x00 "RF_IO_CTRL1_REG,(in CRG)"
abitfld.word 0x00 0.--7. "RFIO_TRIM1_CAP,Trim the RFIO input capacitance" "0x00=0: Minimum capacitance,0x0A=10: Nominal capacitance 1F"
group.word 0x32++0x01
line.word 0x00 "RF_LNA_CTRL1_REG,(in CRG)"
bitfld.word 0x00 6.--11. "LNA_TRIM_CD_HF,Trim the LNA output capacitance for CN > 19" "0: Minimum capacitance,?,?,?,?,?,?,?,?,?,10: Nominal capacitance 1F,?..."
newline
bitfld.word 0x00 0.--5. "LNA_TRIM_CD_LF,Trim the LNA output capacitance for CN" "0: Minimum capacitance,?,?,?,?,?,?,?,?,?,10: Nominal capacitance 1F,?..."
group.word 0x34++0x01
line.word 0x00 "RF_LNA_CTRL2_REG,(in CRG)"
bitfld.word 0x00 6.--11. "LNA_TRIM_GM_LO,Trim the LNA bias resistor for optimum transcunductance (gain) in AGC settings 2 and 3" "0: Minimum transconductance,?,?,?,?,?,?,?,?,?,10: Nominal transconductance 1F,?..."
newline
bitfld.word 0x00 0.--5. "LNA_TRIM_GM_HI,Trim the LNA bias resistor for optimum transcunductance (gain) in AGC settings 0 and 1" "0: Minimum transconductance,?,?,?,?,?,?,?,?,?,10: Nominal transconductance 1F,?..."
group.word 0x36++0x01
line.word 0x00 "RF_LNA_CTRL3_REG,(in CRG)"
bitfld.word 0x00 0.--4. "LNA_TRIM_CGS,Trim the LNA gate-source capacitance" "0: Minimum capacitance,?,?,?,?,?,?,?,?,?,10: Nominal capacitance 1F,?..."
group.word 0x38++0x01
line.word 0x00 "RF_RSSI_COMP_CTRL_REG,(in CRG)"
bitfld.word 0x00 12.--15. "RSSI_COMP00,RSSI compensation value for LNA gain setting 00 '0x0': -8 '0x1': -7 '0x2': -6 '0x3': -5 '0x4': -4 '0x5': -3 '0x6': -2 '0x7': -1 '0x8': 0 (reset) '0x9': 1 '0xA': 2 '0xB': 3 '0xC': 4 '0xD': 5 '0xE': 6 '0xF': 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 8.--11. "RSSI_COMP11,RSSI compensation value for LNA gain setting 11 relative to 00 Coding identical to RSSI_COMP01" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 4.--7. "RSSI_COMP10,RSSI compensation value for LNA gain setting 10 relative to 00 Coding identical to RSSI_COMP01" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0.--3. "RSSI_COMP01,RSSI compensation value for LNA gain setting 01 relative to 00 '0x0': -4 '0x1': -3 '0x2': -2 '0x3': -1 '0x4': 0 '0x5': 1 '0x6': 2 '0x7': 3 (reset) '0x8': 4 '0x9': 5 '0xA': 6 '0xB': 7 '0xC': 8 '0xD': 9 '0xE': 10 '0xF': 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x3A++0x01
line.word 0x00 "RF_VCO_CTRL_REG,"
bitfld.word 0x00 0.--3. "VCO_AMPL_SET,Set the desired amplitude of the VCO'0': minimum amplitude '4': default amplitude 'F': maximum amplitude" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x3E++0x01
line.word 0x00 "SPOTP_TEST_REG,(in CRG)"
bitfld.word 0x00 1. "LDO_OTP_WRITE,Bypass LDO and put VBAT directly on OTP_VDDIO" "0,1"
newline
bitfld.word 0x00 0. "SPOTP_ACTIVE,Enables the SPOTP testmode" "0,1"
group.word 0x12++0x01
line.word 0x00 "SYS_CTRL_REG,System Control register"
bitfld.word 0x00 15. "SW_RESET,Writing a '1' to this bit will reset the device except for: SYS_CTRL_REG CLK_FREQ_TRIM_REG" "0,1"
newline
bitfld.word 0x00 9. "TIMEOUT_DISABLE,Disables timeout in Power statemachine" "0,1"
newline
bitfld.word 0x00 7. "DEBUGGER_ENABLE,Enable the debugger" "0,1"
newline
bitfld.word 0x00 6. "OTPC_RESET_REQ,Reset request for the OTP controller" "0,1"
newline
bitfld.word 0x00 5. "PAD_LATCH_EN,Latches the control signals of the pads for state retention in powerdown mode" "0: Control signals are retained,1: Latch is transparant pad can be recontrolled"
newline
bitfld.word 0x00 4. "OTP_COPY,Enables OTP to SysRAM copy action after waking up PD_SYS" "0,1"
newline
bitfld.word 0x00 3. "CLK32_SOURCE,Sets the clock source of the 32 kHz clock" "0: RC-oscillator,1: 32 kHz crystal oscillator"
newline
bitfld.word 0x00 2. "RET_SYSRAM,Sets the development phase mode" "0,1"
newline
bitfld.word 0x00 0.--1. "REMAP_ADR0,Controls which memory is located at address 0x0000 for execution" "0: ROM,1: OTP,2: SysRAM,3: RetRAM"
group.word 0x14++0x01
line.word 0x00 "SYS_STAT_REG,System status register"
rbitfld.word 0x00 7. "XTAL16_SETTLED,Indicates that XTAL16 has had > 2 ms of settle time" "0,1"
newline
rbitfld.word 0x00 6. "XTAL16_TRIM_READY,Indicates that XTAL trimming mechanism is ready i.e" "0,1"
newline
rbitfld.word 0x00 5. "DBG_IS_UP,Indicates that PD_DBG is functional" "0,1"
newline
rbitfld.word 0x00 4. "DBG_IS_DOWN,Indicates that PD_DBG is in power down" "0,1"
newline
rbitfld.word 0x00 3. "PER_IS_UP,Indicates that PD_PER is functional" "0,1"
newline
rbitfld.word 0x00 2. "PER_IS_DOWN,Indicates that PD_PER is in power down" "0,1"
newline
rbitfld.word 0x00 1. "RAD_IS_UP,Indicates that PD_RAD is functional" "0,1"
newline
rbitfld.word 0x00 0. "RAD_IS_DOWN,Indicates that PD_RAD is in power down" "0,1"
group.word 0x16++0x01
line.word 0x00 "TRIM_CTRL_REG,Control trimming of the XTAL16M"
bitfld.word 0x00 4.--7. "TRIM_TIME,Defines the delay between XTAL16M enable and applying the CLK_FREQ_TRIM_REG in steps of 250 us" "0: apply directly,1: wait between 0 and 250 us,2: wait between 250 us and 500 us etc,?..."
newline
bitfld.word 0x00 0.--3. "SETTLE_TIME,Defines the delay between applying CLK_FREQ_TRIM_REG and XTAL16_SETTLED in steps of 250 us" "0: XTAL16_SETTLED is set direcly,1: wait between 0 and 250 us,2: wait between 250 us and 500 us etc,?..."
tree.end
tree "GPIO580_PORTS_NL01"
base ad:0x50003000
group.word 0xFA++0x01
line.word 0x00 "BIST_CTRL_REG,"
bitfld.word 0x00 12.--13. "RAM_BIST_PATTERN,Pattern to use for the BIST tests" "0: Use 0x5555 as test data,1: Use 0x5A5A as test data,2: Use 0x0000 as test data,3: Use 0x0F0F as test data"
rbitfld.word 0x00 11. "SYSRAM_BIST_BUSY,Read version of bist status" "0,1"
newline
rbitfld.word 0x00 10. "SYSRAM_BIST_FAIL,Read version of bist status" "0,1"
rbitfld.word 0x00 9. "SYSRAM_BIST_LINE_FAIL,Read version of bist status" "0,1"
newline
rbitfld.word 0x00 8. "RETRAM_BIST_BUSY,Read version of bist status" "0,1"
rbitfld.word 0x00 7. "RETRAM_BIST_FAIL,Read version of bist status" "0,1"
newline
rbitfld.word 0x00 6. "RETRAM_BIST_LINE_FAIL,Read version of bist status" "0,1"
rbitfld.word 0x00 5. "ROM_BIST_BUSY,Read version of bist status" "0,1"
newline
bitfld.word 0x00 4. "SHOW_BIST,Map bist results on pins: P0[7] = SYSRAM_BIST_BUSY P0[6] = SYSRAM_BIST_FAIL P0[5] = SYSRAM_BIST_LINE_FAIL P0[4] = RETRAM_BIST_BUSY P0[3] = RETRAM_BIST_FAIL P0[2] = RETRAM_BIST_LINE_FAIL P0[1] = ROM_BIST_BUSY" "0,1"
bitfld.word 0x00 3. "RAMBIST_ENABLE,Enable the RAM bists" "0,1"
newline
bitfld.word 0x00 2. "ROMBIST_ENABLE,Enable the ROM bist" "0,1"
bitfld.word 0x00 0.--1. "RAM_BIST_CONFIG,Bist configuration" "0: Perform all 8 phases,1: Perform only phase 1,2: Perform only phase 3 and 4,3: Perform only phase 6"
group.word 0x06++0x01
line.word 0x00 "P00_MODE_REG,P00 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,Function of port" "0: Port function PUPD as set above,1: UART1_RX,2: UART1_TX,3: UART2_RX,4: UART2_TX,5: SPI_DI,6: SPI_DO,7: SPI_CLK,8: SPI_EN,9: I2C_SCL,10: I2C_SDA,11: UART1_IRDA_RX,12: UART1_IRDA_TX,13: UART2_IRDA_RX,14: UART2_IRDA_TX,15: ADC (only for P0[3:0]),16: PWM0,17: PWM1,18: BLE_DIAG (only for P0[7:0]),19: UART1_CTSN,20: UART1_RTSN,21: UART2_CTSN,22: UART2_RTSN,23: PWM2,24: PWM3,25: PWM4,?..."
group.word 0x08++0x01
line.word 0x00 "P01_MODE_REG,P01 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,Function of port" "0: Port function PUPD as set above,1: UART1_RX,2: UART1_TX,3: UART2_RX,4: UART2_TX,5: SPI_DI,6: SPI_DO,7: SPI_CLK,8: SPI_EN,9: I2C_SCL,10: I2C_SDA,11: UART1_IRDA_RX,12: UART1_IRDA_TX,13: UART2_IRDA_RX,14: UART2_IRDA_TX,15: ADC (only for P0[3:0]),16: PWM0,17: PWM1,18: BLE_DIAG (only for P0[7:0]),19: UART1_CTSN,20: UART1_RTSN,21: UART2_CTSN,22: UART2_RTSN,23: PWM2,24: PWM3,25: PWM4,?..."
group.word 0x70++0x01
line.word 0x00 "P01_PADPWR_CTRL_REG,Ports 0 and 1 Output Power Control Register"
bitfld.word 0x00 8.--13. "P1_OUT_CTRL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.word.byte 0x00 0.--7. 1. "P0_OUT_CTRL,"
group.word 0x0A++0x01
line.word 0x00 "P02_MODE_REG,P02 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,Function of port" "0: Port function PUPD as set above,1: UART1_RX,2: UART1_TX,3: UART2_RX,4: UART2_TX,5: SPI_DI,6: SPI_DO,7: SPI_CLK,8: SPI_EN,9: I2C_SCL,10: I2C_SDA,11: UART1_IRDA_RX,12: UART1_IRDA_TX,13: UART2_IRDA_RX,14: UART2_IRDA_TX,15: ADC (only for P0[3:0]),16: PWM0,17: PWM1,18: BLE_DIAG (only for P0[7:0]),19: UART1_CTSN,20: UART1_RTSN,21: UART2_CTSN,22: UART2_RTSN,23: PWM2,24: PWM3,25: PWM4,?..."
group.word 0x0C++0x01
line.word 0x00 "P03_MODE_REG,P03 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,Function of port" "0: Port function PUPD as set above,1: UART1_RX,2: UART1_TX,3: UART2_RX,4: UART2_TX,5: SPI_DI,6: SPI_DO,7: SPI_CLK,8: SPI_EN,9: I2C_SCL,10: I2C_SDA,11: UART1_IRDA_RX,12: UART1_IRDA_TX,13: UART2_IRDA_RX,14: UART2_IRDA_TX,15: ADC (only for P0[3:0]),16: PWM0,17: PWM1,18: BLE_DIAG (only for P0[7:0]),19: UART1_CTSN,20: UART1_RTSN,21: UART2_CTSN,22: UART2_RTSN,23: PWM2,24: PWM3,25: PWM4,?..."
group.word 0x0E++0x01
line.word 0x00 "P04_MODE_REG,P04 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,Function of port" "0: Port function PUPD as set above,1: UART1_RX,2: UART1_TX,3: UART2_RX,4: UART2_TX,5: SPI_DI,6: SPI_DO,7: SPI_CLK,8: SPI_EN,9: I2C_SCL,10: I2C_SDA,11: UART1_IRDA_RX,12: UART1_IRDA_TX,13: UART2_IRDA_RX,14: UART2_IRDA_TX,15: ADC (only for P0[3:0]),16: PWM0,17: PWM1,18: BLE_DIAG (only for P0[7:0]),19: UART1_CTSN,20: UART1_RTSN,21: UART2_CTSN,22: UART2_RTSN,23: PWM2,24: PWM3,25: PWM4,?..."
group.word 0x10++0x01
line.word 0x00 "P05_MODE_REG,P05 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,Function of port" "0: Port function PUPD as set above,1: UART1_RX,2: UART1_TX,3: UART2_RX,4: UART2_TX,5: SPI_DI,6: SPI_DO,7: SPI_CLK,8: SPI_EN,9: I2C_SCL,10: I2C_SDA,11: UART1_IRDA_RX,12: UART1_IRDA_TX,13: UART2_IRDA_RX,14: UART2_IRDA_TX,15: ADC (only for P0[3:0]),16: PWM0,17: PWM1,18: BLE_DIAG (only for P0[7:0]),19: UART1_CTSN,20: UART1_RTSN,21: UART2_CTSN,22: UART2_RTSN,23: PWM2,24: PWM3,25: PWM4,?..."
group.word 0x12++0x01
line.word 0x00 "P06_MODE_REG,P06 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,Function of port" "0: Port function PUPD as set above,1: UART1_RX,2: UART1_TX,3: UART2_RX,4: UART2_TX,5: SPI_DI,6: SPI_DO,7: SPI_CLK,8: SPI_EN,9: I2C_SCL,10: I2C_SDA,11: UART1_IRDA_RX,12: UART1_IRDA_TX,13: UART2_IRDA_RX,14: UART2_IRDA_TX,15: ADC (only for P0[3:0]),16: PWM0,17: PWM1,18: BLE_DIAG (only for P0[7:0]),19: UART1_CTSN,20: UART1_RTSN,21: UART2_CTSN,22: UART2_RTSN,23: PWM2,24: PWM3,25: PWM4,?..."
group.word 0x14++0x01
line.word 0x00 "P07_MODE_REG,P07 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,Function of port" "0: Port function PUPD as set above,1: UART1_RX,2: UART1_TX,3: UART2_RX,4: UART2_TX,5: SPI_DI,6: SPI_DO,7: SPI_CLK,8: SPI_EN,9: I2C_SCL,10: I2C_SDA,11: UART1_IRDA_RX,12: UART1_IRDA_TX,13: UART2_IRDA_RX,14: UART2_IRDA_TX,15: ADC (only for P0[3:0]),16: PWM0,17: PWM1,18: BLE_DIAG (only for P0[7:0]),19: UART1_CTSN,20: UART1_RTSN,21: UART2_CTSN,22: UART2_RTSN,23: PWM2,24: PWM3,25: PWM4,?..."
group.word 0x00++0x01
line.word 0x00 "P0_DATA_REG,P0 Data input / output register"
hexmask.word.byte 0x00 0.--7. 1. "P0_DATA,Set P0 output register when written Returns the value of P0 port when"
group.word 0x04++0x01
line.word 0x00 "P0_RESET_DATA_REG,P0 Reset port pins register"
hexmask.word.byte 0x00 0.--7. 1. "P0_RESET,Writing a 1 to P0[y] sets P0[y] to 0"
group.word 0x02++0x01
line.word 0x00 "P0_SET_DATA_REG,P0 Set port pins register"
hexmask.word.byte 0x00 0.--7. 1. "P0_SET,Writing a 1 to P0[y] sets P0[y] to 1"
group.word 0x26++0x01
line.word 0x00 "P10_MODE_REG,P10 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x28++0x01
line.word 0x00 "P11_MODE_REG,P11 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2A++0x01
line.word 0x00 "P12_MODE_REG,P12 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2C++0x01
line.word 0x00 "P13_MODE_REG,P13 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x2E++0x01
line.word 0x00 "P14_MODE_REG,P14 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x30++0x01
line.word 0x00 "P15_MODE_REG,P15 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x20++0x01
line.word 0x00 "P1_DATA_REG,P1 Data input / output register"
hexmask.word.byte 0x00 0.--7. 1. "P1_DATA,Set P1 output register when written Returns the value of P1 port when"
group.word 0x24++0x01
line.word 0x00 "P1_RESET_DATA_REG,P1 Reset port pins register"
hexmask.word.byte 0x00 0.--7. 1. "P1_RESET,Writing a 1 to P1[y] sets P1[y] to 0"
group.word 0x22++0x01
line.word 0x00 "P1_SET_DATA_REG,P1 Set port pins register"
hexmask.word.byte 0x00 0.--7. 1. "P1_SET,Writing a 1 to P1[y] sets P1[y] to 1"
group.word 0x46++0x01
line.word 0x00 "P20_MODE_REG,P20 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x48++0x01
line.word 0x00 "P21_MODE_REG,P21 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x4A++0x01
line.word 0x00 "P22_MODE_REG,P22 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x4C++0x01
line.word 0x00 "P23_MODE_REG,P23 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x4E++0x01
line.word 0x00 "P24_MODE_REG,P24 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x50++0x01
line.word 0x00 "P25_MODE_REG,P25 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x52++0x01
line.word 0x00 "P26_MODE_REG,P26 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x54++0x01
line.word 0x00 "P27_MODE_REG,P27 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x56++0x01
line.word 0x00 "P28_MODE_REG,P28 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x58++0x01
line.word 0x00 "P29_MODE_REG,P29 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In analog mode"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x40++0x01
line.word 0x00 "P2_DATA_REG,P2 Data input / output register"
hexmask.word 0x00 0.--9. 1. "P2_DATA,Set P2 output register when written Returns the value of P2 port when"
group.word 0x72++0x01
line.word 0x00 "P2_PADPWR_CTRL_REG,Port 2 Output Power Control Register"
hexmask.word 0x00 0.--9. 1. "P2_OUT_CTRL,"
group.word 0x44++0x01
line.word 0x00 "P2_RESET_DATA_REG,P2 Reset port pins register"
hexmask.word 0x00 0.--9. 1. "P2_RESET,Writing a 1 to P2[y] sets P2[y] to 0"
group.word 0x42++0x01
line.word 0x00 "P2_SET_DATA_REG,P2 Set port pins register"
hexmask.word 0x00 0.--9. 1. "P2_SET,Writing a 1 to P2[y] sets P2[y] to 1"
group.word 0x86++0x01
line.word 0x00 "P30_MODE_REG,P30 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x88++0x01
line.word 0x00 "P31_MODE_REG,P31 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x8A++0x01
line.word 0x00 "P32_MODE_REG,P32 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x8C++0x01
line.word 0x00 "P33_MODE_REG,P33 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x8E++0x01
line.word 0x00 "P34_MODE_REG,P34 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x90++0x01
line.word 0x00 "P35_MODE_REG,P35 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x92++0x01
line.word 0x00 "P36_MODE_REG,P36 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x94++0x01
line.word 0x00 "P37_MODE_REG,P37 Mode Register"
bitfld.word 0x00 8.--9. "PUPD," "?,1: Input pull-up selected,2: Input Pull-down selected,3: Output no resistors selected In ADC mode these"
bitfld.word 0x00 0.--4. "PID,See P0x_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x80++0x01
line.word 0x00 "P3_DATA_REG,P3 Data input / output register"
hexmask.word.byte 0x00 0.--7. 1. "P3_DATA,Set P3 output register when written Returns the value of P3 port when"
group.word 0x74++0x01
line.word 0x00 "P3_PADPWR_CTRL_REG,Port 3 Output Power Control Register"
hexmask.word.byte 0x00 0.--7. 1. "P3_OUT_CTRL,"
group.word 0x84++0x01
line.word 0x00 "P3_RESET_DATA_REG,P3 Reset port pins register"
hexmask.word.byte 0x00 0.--7. 1. "P3_RESET,Writing a 1 to P0[y] sets P0[y] to 0"
group.word 0x82++0x01
line.word 0x00 "P3_SET_DATA_REG,P3 Set port pins register"
hexmask.word.byte 0x00 0.--7. 1. "P3_SET,Writing a 1 to P3[y] sets P3[y] to 1"
group.word 0xFE++0x01
line.word 0x00 "ROMBIST_RESULTH_REG,"
hexmask.word 0x00 0.--15. 1. "ROMBIST_RESULTH,Read version of bist status result[31:16]"
group.word 0xFC++0x01
line.word 0x00 "ROMBIST_RESULTL_REG,"
hexmask.word 0x00 0.--15. 1. "ROMBIST_RESULTL,Read version of bist status result[15:0]"
group.word 0xF2++0x01
line.word 0x00 "TEST_CTRL2_REG,"
bitfld.word 0x00 8.--9. "RF_IN_TESTMUX_CTRL,CConnect the RF input testbus to pins" "0,1,2,3"
bitfld.word 0x00 0.--3. "ANA_TESTMUX_CTRL,Control of analog test bus switches" "0: all switches open,1: only switch 1 closed,2: only switch 2 closed,3: only switch 3 closed,4: only switch 4 closed,5: switches 1 & 2 closed,6: switches 1 & 4 closed,7: switches 2 & 3 closed,8: switches 3 & 4 closed,?..."
group.word 0xF4++0x01
line.word 0x00 "TEST_CTRL3_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RF_TEST_OUT_PARAM,Select which test will be enabled on the block selected by the RF output testbus (see"
bitfld.word 0x00 0.--5. "RF_TEST_OUT_SEL,Select a radio block to have its testbus connected to P1[1] and P1[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0xF6++0x01
line.word 0x00 "TEST_CTRL4_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RF_TEST_IN_PARAM,Select which test will be enabled on the block selected by the RF output testbus (see"
bitfld.word 0x00 0.--2. "RF_TEST_IN_SEL,Select an RF block to have its test input connected to the input testbus at pins P0[0] and P0[3]" "0,1,2,3,4,5,6,7"
group.word 0xF8++0x01
line.word 0x00 "TEST_CTRL5_REG,"
bitfld.word 0x00 15. "DCDC_FORCE_IDLE,Keep the DCDC-converter in the idle state" "0,1"
bitfld.word 0x00 14. "DCDC_OUTSW,Close pMOS switch between 'switch' and 'vdcdc'" "0,1"
newline
bitfld.word 0x00 13. "DCDC_PSW,Close pMOS switch between 'switch' and 'vbat3v'" "0,1"
bitfld.word 0x00 12. "DCDC_NSW,Close nMOS switch between 'switch' and 'gnd'" "0,1"
newline
bitfld.word 0x00 8.--11. "TEST_STRUCT,4 bits to select which test-structure is mapped on P1[1]" "0: open,1: VDD (1.2V),2: 10uA into 66k = 5/3 x 40k (W/L=0.45/22.33),3: 1uA into 700k = 18.5 x 40k (W/L=0.45/22.33),4: 1uA(same as going into 700k),5: AVS (0V),6: 5uA into nMOST (svt) 2x1u/110n,7: 5uA into nMOST (hvt) 2x1u/110n,8: 5uA into nMOST (UD18) 2x1u/260n,9: 5uA into nMOST (OD33) 2x1u/500n a,?..."
bitfld.word 0x00 3. "TEST_OTP_VSS,VSS_OTP (0V) mapped on P1[2]" "0,1"
newline
bitfld.word 0x00 2. "TEST_OTP_OTA,Output of OTA inside LDO-OTP is mapped on P1[2]" "0,1"
bitfld.word 0x00 1. "TEST_OTP_VDD,VDD_OTP on P1[2] 1uA bias sink on P1[1]" "0,1"
newline
bitfld.word 0x00 0. "TEST_VDD,VDD on P1[1] VDD_REF (=ADC) on P1[2]" "0,1"
group.word 0xF0++0x01
line.word 0x00 "TEST_CTRL_REG,"
bitfld.word 0x00 6. "PLL_TST_MODE," "0,1"
bitfld.word 0x00 5. "SHOW_IF_RO," "0,1"
newline
bitfld.word 0x00 4. "XTAL16M_CAP_TEST_EN," "0,1"
bitfld.word 0x00 3. "SHOW_DC_COMP," "0: swn),1: swp"
newline
bitfld.word 0x00 2. "SHOW_DC_STATE," "0: swn),1: swp"
bitfld.word 0x00 1. "ENABLE_RFPT," "0,1"
newline
bitfld.word 0x00 0. "SHOW_CLOCKS," "0,1"
tree.end
tree "I2C580_NL00"
base ad:0x50001300
group.word 0x98++0x01
line.word 0x00 "I2C_ACK_GENERAL_CALL_REG,I2C ACK General Call Register"
bitfld.word 0x00 0. "ACK_GEN_CALL,ACK General Call" "0,1"
group.word 0x5C++0x01
line.word 0x00 "I2C_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register"
rbitfld.word 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.word 0x68++0x01
line.word 0x00 "I2C_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register"
rbitfld.word 0x00 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register" "0,1"
group.word 0x40++0x01
line.word 0x00 "I2C_CLR_INTR_REG,Clear Combined and Individual Interrupt Register"
rbitfld.word 0x00 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the I2C_TX_ABRT_SOURCE register" "0,1"
group.word 0x50++0x01
line.word 0x00 "I2C_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register"
rbitfld.word 0x00 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x58++0x01
line.word 0x00 "I2C_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x48++0x01
line.word 0x00 "I2C_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x44++0x01
line.word 0x00 "I2C_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register"
rbitfld.word 0x00 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x64++0x01
line.word 0x00 "I2C_CLR_START_DET_REG,Clear START_DET Interrupt Register"
rbitfld.word 0x00 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register" "0,1"
group.word 0x60++0x01
line.word 0x00 "I2C_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register"
rbitfld.word 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.word 0x54++0x01
line.word 0x00 "I2C_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register"
rbitfld.word 0x00 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the I2C_TX_ABRT_SOURCE register" "0,1"
group.word 0x4C++0x01
line.word 0x00 "I2C_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register"
rbitfld.word 0x00 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x00++0x01
line.word 0x00 "I2C_CON_REG,I2C Control Register"
bitfld.word 0x00 6. "I2C_SLAVE_DISABLE,Slave enabled or disabled after reset is applied which means software does not have to configure the slave" "0: slave is enabled,1: slave is disabled Software should ensure that"
newline
bitfld.word 0x00 5. "I2C_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master" "0: disable,1: enable"
newline
bitfld.word 0x00 4. "I2C_10BITADDR_MASTER,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.word 0x00 3. "I2C_10BITADDR_SLAVE,When acting as a slave this bit controls whether the controller responds to 7- or 10-bit addresses" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.word 0x00 1.--2. "I2C_SPEED,These bits control at which speed the controller operates" "?,1: standard mode (100 kbit/s),2: fast mode (400 kbit/s),?..."
newline
bitfld.word 0x00 0. "I2C_MASTER_MODE,This bit controls whether the controller master is enabled" "0: master disabled,1: master enabled Software should ensure that"
group.word 0x10++0x01
line.word 0x00 "I2C_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register"
bitfld.word 0x00 8. "CMD,This bit controls whether a read or a write is performed" "0: Write When,1: "
newline
hexmask.word.byte 0x00 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus"
group.word 0x6C++0x01
line.word 0x00 "I2C_ENABLE_REG,I2C Enable Register"
bitfld.word 0x00 0. "CTRL_ENABLE,Controls whether the controller is enabled" "0: Disables the controller (TX and RX FIFOs are,1: Enables the controller Software can disable the"
group.word 0x9C++0x01
line.word 0x00 "I2C_ENABLE_STATUS_REG,I2C Enable Status Register"
rbitfld.word 0x00 2. "SLV_RX_DATA_LOST,Slave Received Data Lost" "0,1"
newline
rbitfld.word 0x00 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive)" "0,1"
newline
rbitfld.word 0x00 0. "IC_EN,ic_en Status" "0,1"
group.word 0x1C++0x01
line.word 0x00 "I2C_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register"
hexmask.word 0x00 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x20++0x01
line.word 0x00 "I2C_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register"
hexmask.word 0x00 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0xA0++0x01
line.word 0x00 "I2C_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size"
hexmask.word.byte 0x00 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.word 0x30++0x01
line.word 0x00 "I2C_INTR_MASK_REG,I2C Interrupt Mask Register"
bitfld.word 0x00 11. "M_GEN_CALL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 10. "M_START_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 9. "M_STOP_DET,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 8. "M_ACTIVITY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 7. "M_RX_DONE,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 6. "M_TX_ABRT,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 5. "M_RD_REQ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 4. "M_TX_EMPTY,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 3. "M_TX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 2. "M_RX_FULL,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 1. "M_RX_OVER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 0. "M_RX_UNDER,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
group.word 0x2C++0x01
line.word 0x00 "I2C_INTR_STAT_REG,I2C Interrupt Status Register"
rbitfld.word 0x00 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
newline
rbitfld.word 0x00 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.word 0x00 9. "R_STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.word 0x00 8. "R_ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
newline
rbitfld.word 0x00 7. "R_RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.word 0x00 6. "R_TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
newline
rbitfld.word 0x00 5. "R_RD_REQ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
newline
rbitfld.word 0x00 4. "R_TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
newline
rbitfld.word 0x00 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
newline
rbitfld.word 0x00 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
newline
rbitfld.word 0x00 1. "R_RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
newline
rbitfld.word 0x00 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.word 0x34++0x01
line.word 0x00 "I2C_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register"
rbitfld.word 0x00 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0,1"
newline
rbitfld.word 0x00 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.word 0x00 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode" "0,1"
newline
rbitfld.word 0x00 8. "ACTIVITY,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
newline
rbitfld.word 0x00 7. "RX_DONE,When the controller is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0,1"
newline
rbitfld.word 0x00 6. "TX_ABRT,This bit indicates if the controller as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0,1"
newline
rbitfld.word 0x00 5. "RD_REQ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller" "0,1"
newline
rbitfld.word 0x00 4. "TX_EMPTY,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register" "0,1"
newline
rbitfld.word 0x00 3. "TX_OVER,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0,1"
newline
rbitfld.word 0x00 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
newline
rbitfld.word 0x00 1. "RX_OVER,Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device" "0,1"
newline
rbitfld.word 0x00 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0,1"
group.word 0x78++0x01
line.word 0x00 "I2C_RXFLR_REG,I2C Receive FIFO Level Register"
rbitfld.word 0x00 0.--5. "RXFLR,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x38++0x01
line.word 0x00 "I2C_RX_TL_REG,I2C Receive FIFO Threshold Register"
bitfld.word 0x00 0.--4. "RX_TL,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x08++0x01
line.word 0x00 "I2C_SAR_REG,I2C Slave Address Register"
hexmask.word 0x00 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave"
group.word 0x7C++0x01
line.word 0x00 "I2C_SDA_HOLD_REG,I2C SDA Hold Time Length Register"
hexmask.word 0x00 0.--15. 1. "IC_SDA_HOLD,SDA Hold time"
group.word 0x94++0x01
line.word 0x00 "I2C_SDA_SETUP_REG,I2C SDA Setup Register"
hexmask.word.byte 0x00 0.--7. 1. "SDA_SETUP,SDA Setup"
group.word 0x14++0x01
line.word 0x00 "I2C_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register"
hexmask.word 0x00 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x18++0x01
line.word 0x00 "I2C_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register"
hexmask.word 0x00 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x70++0x01
line.word 0x00 "I2C_STATUS_REG,I2C Status Register"
rbitfld.word 0x00 6. "SLV_ACTIVITY,Slave FSM Activity Status" "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave.."
newline
rbitfld.word 0x00 5. "MST_ACTIVITY,Master FSM Activity Status" "0:Master FSM is in IDLE state,1:Master FSM is not in IDLE state"
newline
rbitfld.word 0x00 4. "RFF,Receive FIFO Completely Full" "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
rbitfld.word 0x00 3. "RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
rbitfld.word 0x00 2. "TFE,Transmit FIFO Completely Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
rbitfld.word 0x00 1. "TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
newline
rbitfld.word 0x00 0. "I2C_ACTIVITY,I2C Activity Status" "0,1"
group.word 0x04++0x01
line.word 0x00 "I2C_TAR_REG,I2C Target Address Register"
bitfld.word 0x00 11. "SPECIAL,This bit indicates whether software performs a General Call or START BYTE command" "0: ignore bit 10 GC_OR_START and use IC_TAR..,1: perform special I2C command as specified in"
newline
bitfld.word 0x00 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a General Call or START byte command is to be performed by the controller" "0: General Call Address - after,1: START BYTE"
newline
hexmask.word 0x00 0.--9. 1. "IC_TAR,This is the target address for any master transaction"
group.word 0x74++0x01
line.word 0x00 "I2C_TXFLR_REG,I2C Transmit FIFO Level Register"
rbitfld.word 0x00 0.--5. "TXFLR,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x80++0x01
line.word 0x00 "I2C_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register"
rbitfld.word 0x00 15. "ABRT_SLVRD_INTX," "0,1"
newline
rbitfld.word 0x00 14. "ABRT_SLV_ARBLOST," "0,1"
newline
rbitfld.word 0x00 13. "ABRT_SLVFLUSH_TXFIFO," "0,1"
newline
rbitfld.word 0x00 12. "ARB_LOST," "0,1"
newline
rbitfld.word 0x00 11. "ABRT_MASTER_DIS," "0,1"
newline
rbitfld.word 0x00 10. "ABRT_10B_RD_NORSTRT," "0,1"
newline
rbitfld.word 0x00 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1) the SPECIAL bit must be cleared (I2C_TAR[11]) or the GC_OR_START bit must be cleared (I2C_TAR[10])" "0,1"
newline
rbitfld.word 0x00 8. "ABRT_HS_NORSTRT," "0,1"
newline
rbitfld.word 0x00 7. "ABRT_SBYTE_ACKDET," "0,1"
newline
rbitfld.word 0x00 6. "ABRT_HS_ACKDET," "0,1"
newline
rbitfld.word 0x00 5. "ABRT_GCALL_READ," "0,1"
newline
rbitfld.word 0x00 4. "ABRT_GCALL_NOACK," "0,1"
newline
rbitfld.word 0x00 3. "ABRT_TXDATA_NOACK," "0,1"
newline
rbitfld.word 0x00 2. "ABRT_10ADDR2_NOACK," "0,1"
newline
rbitfld.word 0x00 1. "ABRT_10ADDR1_NOACK," "0,1"
newline
rbitfld.word 0x00 0. "ABRT_7B_ADDR_NOACK," "0,1"
group.word 0x3C++0x01
line.word 0x00 "I2C_TX_TL_REG,I2C Transmit FIFO Threshold Register"
bitfld.word 0x00 0.--4. "RX_TL,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "KBRD580_NL01"
base ad:0x50001400
group.word 0x0C++0x01
line.word 0x00 "GPIO_DEBOUNCE_REG,debounce counter value for GPIO inputs"
bitfld.word 0x00 13. "DEB_ENABLE_KBRD,enables the debounce counter for the KBRD interface" "0,1"
bitfld.word 0x00 12. "DEB_ENABLE4,enables the debounce counter for GPIO IRQ4" "0,1"
newline
bitfld.word 0x00 11. "DEB_ENABLE3,enables the debounce counter for GPIO IRQ3" "0,1"
bitfld.word 0x00 10. "DEB_ENABLE2,enables the debounce counter for GPIO IRQ2" "0,1"
newline
bitfld.word 0x00 9. "DEB_ENABLE1,enables the debounce counter for GPIO IRQ1" "0,1"
bitfld.word 0x00 8. "DEB_ENABLE0,enables the debounce counter for GPIO IRQ0" "0,1"
newline
bitfld.word 0x00 0.--5. "DEB_VALUE,Keyboard debounce time if enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x10++0x01
line.word 0x00 "GPIO_INT_LEVEL_CTRL_REG,high or low level select for GPIO interrupts"
bitfld.word 0x00 12. "EDGE_LEVELn4,see EDGE_LEVELn0 but for GPIO IRQ4" "0,1"
bitfld.word 0x00 11. "EDGE_LEVELn3,see EDGE_LEVELn0 but for GPIO IRQ3" "0,1"
newline
bitfld.word 0x00 10. "EDGE_LEVELn2,see EDGE_LEVELn0 but for GPIO IRQ2" "0,1"
bitfld.word 0x00 9. "EDGE_LEVELn1,see EDGE_LEVELn0 but for GPIO IRQ1" "0,1"
newline
bitfld.word 0x00 8. "EDGE_LEVELn0," "0,1"
bitfld.word 0x00 4. "INPUT_LEVEL4,see INPUT_LEVEL0 but for GPIO IRQ4" "0,1"
newline
bitfld.word 0x00 3. "INPUT_LEVEL3,see INPUT_LEVEL0 but for GPIO IRQ3" "0,1"
bitfld.word 0x00 2. "INPUT_LEVEL2,see INPUT_LEVEL0 but for GPIO IRQ2" "0,1"
newline
bitfld.word 0x00 1. "INPUT_LEVEL1,see INPUT_LEVEL0 but for GPIO IRQ1" "0,1"
bitfld.word 0x00 0. "INPUT_LEVEL0," "0,1"
group.word 0x00++0x01
line.word 0x00 "GPIO_IRQ0_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ0"
bitfld.word 0x00 0.--5. "KBRD_IRQ0_SEL,input selection that can generate a GPIO interrupt" "0: no input selected,1: P0[0] is selected,2: P0[1] is selected,3: P0[2] is selected,4: P0[3] is selected,5: P0[4] is selected,6: P0[5] is selected,7: P0[6] is selected,8: P0[7] is selected,9: P1[0] is selected,10: P1[1] is selected,11: P1[2] is selected,12: P1[3] is selected,13: P1[4] is selected,14: P1[5] is selected,15: P2[0] is selected,16: P2[1] is selected,17: P2[2] is selected,18: P2[3] is selected,19: P2[4] is selected,20: P2[5] is selected,21: P2[6] is selected,22: P2[7] is selected,23: P2[8] is selected,24: P2[9] is selected,25: P3[0] is selected,26: P3[1] is selected,27: P3[2] is selected,28: P3[3] is selected,29: P3[4] is selected,30: P3[5] is selected,31: P3[6] is selected,32: P3[7] is selected all others,?..."
group.word 0x02++0x01
line.word 0x00 "GPIO_IRQ1_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ1"
bitfld.word 0x00 0.--5. "KBRD_IRQ1_SEL,see KBRD_IRQ0_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x04++0x01
line.word 0x00 "GPIO_IRQ2_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ2"
bitfld.word 0x00 0.--5. "KBRD_IRQ2_SEL,see KBRD_IRQ0_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x06++0x01
line.word 0x00 "GPIO_IRQ3_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ3"
bitfld.word 0x00 0.--5. "KBRD_IRQ3_SEL,see KBRD_IRQ0_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x08++0x01
line.word 0x00 "GPIO_IRQ4_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ4"
bitfld.word 0x00 0.--5. "KBRD_IRQ4_SEL,see KBRD_IRQ0_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x0E++0x01
line.word 0x00 "GPIO_RESET_IRQ_REG,GPIO interrupt reset register"
bitfld.word 0x00 5. "RESET_KBRD_IRQ,writing a 1 to this bit will reset the KBRD IRQ" "0,1"
bitfld.word 0x00 4. "RESET_GPIO4_IRQ,writing a 1 to this bit will reset the GPIO4 IRQ" "0,1"
newline
bitfld.word 0x00 3. "RESET_GPIO3_IRQ,writing a 1 to this bit will reset the GPIO3 IRQ" "0,1"
bitfld.word 0x00 2. "RESET_GPIO2_IRQ,writing a 1 to this bit will reset the GPIO2 IRQ" "0,1"
newline
bitfld.word 0x00 1. "RESET_GPIO1_IRQ,writing a 1 to this bit will reset the GPIO1 IRQ" "0,1"
bitfld.word 0x00 0. "RESET_GPIO0_IRQ,writing a 1 to this bit will reset the GPIO0 IRQ" "0,1"
group.word 0x12++0x01
line.word 0x00 "KBRD_IRQ_IN_SEL0_REG,GPIO interrupt selection for KBRD_IRQ for P0"
bitfld.word 0x00 15. "KBRD_REL," "0,1"
bitfld.word 0x00 14. "KBRD_LEVEL," "0,1"
newline
bitfld.word 0x00 8.--13. "KEY_REPEAT,While key is pressed automatically generate repeating KEYB_INT after specified time unequal to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 7. "KBRD_P07_EN,enable P0[7] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 6. "KBRD_P06_EN,enable P0[6] for the keyboard interrupt" "0,1"
bitfld.word 0x00 5. "KBRD_P05_EN,enable P0[5] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 4. "KBRD_P04_EN,enable P0[4] for the keyboard interrupt" "0,1"
bitfld.word 0x00 3. "KBRD_P03_EN,enable P0[3] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 2. "KBRD_P02_EN,enable P0[2] for the keyboard interrupt" "0,1"
bitfld.word 0x00 1. "KBRD_P01_EN,enable P0[1] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 0. "KBRD_P00_EN,enable P0[0] for the keyboard interrupt" "0,1"
group.word 0x14++0x01
line.word 0x00 "KBRD_IRQ_IN_SEL1_REG,GPIO interrupt selection for KBRD_IRQ for P1 and P2"
bitfld.word 0x00 15. "KBRD_P15_EN,enable P1[5] for the keyboard interrupt" "0,1"
bitfld.word 0x00 14. "KBRD_P14_EN,enable P1[4] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 13. "KBRD_P13_EN,enable P1[3] for the keyboard interrupt" "0,1"
bitfld.word 0x00 12. "KBRD_P12_EN,enable P1[2] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 11. "KBRD_P11_EN,enable P1[1] for the keyboard interrupt" "0,1"
bitfld.word 0x00 10. "KBRD_P10_EN,enable P1[0] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 9. "KBRD_P29_EN,enable P2[9] for the keyboard interrupt" "0,1"
bitfld.word 0x00 8. "KBRD_P28_EN,enable P2[8] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 7. "KBRD_P27_EN,enable P2[7] for the keyboard interrupt" "0,1"
bitfld.word 0x00 6. "KBRD_P26_EN,enable P2[6] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 5. "KBRD_P25_EN,enable P2[5] for the keyboard interrupt" "0,1"
bitfld.word 0x00 4. "KBRD_P24_EN,enable P2[4] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 3. "KBRD_P23_EN,enable P2[3] for the keyboard interrupt" "0,1"
bitfld.word 0x00 2. "KBRD_P22_EN,enable P2[2] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 1. "KBRD_P21_EN,enable P2[1] for the keyboard interrupt" "0,1"
bitfld.word 0x00 0. "KBRD_P20_EN,enable P2[0] for the keyboard interrupt" "0,1"
group.word 0x16++0x01
line.word 0x00 "KBRD_IRQ_IN_SEL2_REG,GPIO interrupt selection for KBRD_IRQ for P3"
bitfld.word 0x00 7. "KBRD_P37_EN,enable P3[7] for the keyboard interrupt" "0,1"
bitfld.word 0x00 6. "KBRD_P36_EN,enable P3[6] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 5. "KBRD_P35_EN,enable P3[5] for the keyboard interrupt" "0,1"
bitfld.word 0x00 4. "KBRD_P34_EN,enable P3[4] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 3. "KBRD_P33_EN,enable P3[3] for the keyboard interrupt" "0,1"
bitfld.word 0x00 2. "KBRD_P32_EN,enable P3[2] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 1. "KBRD_P31_EN,enable P3[1] for the keyboard interrupt" "0,1"
bitfld.word 0x00 0. "KBRD_P30_EN,enable P3[0] for the keyboard interrupt" "0,1"
tree.end
tree "OTPC580_GR01"
base ad:0x40008000
group.long 0x0C++0x03
line.long 0x00 "OTPC_AHBADR_REG,AHB master start address"
hexmask.long 0x00 2.--31. 1. "OTPC_AHBADR,Tthe AHB address used by the AHB master interface of the controller ( bits [31:2])"
group.long 0x10++0x03
line.long 0x00 "OTPC_CELADR_REG,Macrocell start address"
hexmask.long.word 0x00 0.--12. 1. "OTPC_CELADR,Defines a word address inside the macrocell"
group.long 0x18++0x03
line.long 0x00 "OTPC_FFPRT_REG,Ports access to fifo logic"
hexmask.long 0x00 0.--31. 1. "OTPC_FFPRT,Provides access to the fifo through an access port"
group.long 0x1C++0x03
line.long 0x00 "OTPC_FFRD_REG,Latest read data from the OTPC_FFPRT_REG"
hexmask.long 0x00 0.--31. 1. "OTPC_FFRD,Contains the value read from the fifo after a read of the OTPC_FFPRT_REG register"
group.long 0x00++0x03
line.long 0x00 "OTPC_MODE_REG,Mode register"
bitfld.long 0x00 28.--29. "OTPC_MODE_PRG_PORT_MUX,Selects the source that is connected to the prg_port port of the controller" "0: {16'd0 BANDGAP_REG[15:0]},1: {RF_RSSI_COMP_CTRL_REG[15:0] 8'd0,2: {3'd0 RF_LNA_CTRL3_REG[4:0],3: {28'd0 RF_VCO_CTRL_REG[3:0]} See"
bitfld.long 0x00 8. "OPTC_MODE_PRG_FAST,Defines the timing that will be used for all the programming activities (APROG MPROG and TWR)" "0: Selects the normal timing,1: Selects the fast timing"
newline
bitfld.long 0x00 7. "OTPC_MODE_PRG_PORT_SEL,Selects an alternative data source for the programming of the OTP macrocells when the controller is configured in APROG mode" "0: The fifo will be used as the data source,1: Only one word will programmed"
bitfld.long 0x00 6. "OTPC_MODE_TWO_CC_ACC,Defines the duration of each read from the OTP macrocells" "0: Reads 16 bits of data every one clock cycle,1: Reads 16 bits of data every two clock cycles"
newline
bitfld.long 0x00 5. "OTPC_MODE_FIFO_FLUSH,Writing 1 removes any content from the FIFO" "0,1"
bitfld.long 0x00 4. "OTPC_MODE_USE_DMA,Selects the use of the dma when the controller is configured in one of the modes: AREAD or APROG" "0: DMAis not used,1: DMA is used"
newline
bitfld.long 0x00 0.--2. "OTPC_MODE_MODE,Defines the mode of operation of the OTPC controller" "0: STBY mode,1: MREAD mode,2: MPROG mode,3: AREAD mode,4: APROG mode,5: Test mode,6: Test mode,7: Test mode"
group.long 0x14++0x03
line.long 0x00 "OTPC_NWORDS_REG,Number of words"
hexmask.long.word 0x00 0.--12. 1. "OTPC_NWORDS,The number of words (minus one) for reading/programming during the AREAD/APROG mode"
group.long 0x04++0x03
line.long 0x00 "OTPC_PCTRL_REG,Bit-programming control register"
bitfld.long 0x00 27. "OTPC_PCTRL_ENU,Enables the programming in the upper bank of the OTP" "0: Programming sequence is not applied in the..,1: Programming sequence is applied in the upper.."
bitfld.long 0x00 26. "OTPC_PCTRL_BITU,Defines the value of the selected bit in the upper bank after the programming sequence" "0,1"
newline
bitfld.long 0x00 25. "OTPC_PCTRL_ENL,Enables the programming in the lower bank" "0,1"
bitfld.long 0x00 24. "OTPC_PCTRL_BITL,Defines the value of the selected bit in the lower bank after the programming sequence" "0,1"
newline
bitfld.long 0x00 23. "OTPC_PCTRL_BSELU,Selects between the U1 and U0 byte for the programming sequence in the upper bank" "0: Program the U0 byte,1: Program the U1 byte"
bitfld.long 0x00 20.--22. "OTPC_PCTRL_BADRU,Selects the bit inside the Ux (x=0 1) byte which will be programmed in the upper bank" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19. "OTPC_PCTRL_BSELL,Selects between the L1 and L0 byte for the programming sequence in the lower bank" "0: Program the L0 byte,1: Program the L1 byte"
bitfld.long 0x00 16.--18. "OTPC_PCTRL_BADRL,Selects the bit inside the Lx (x=0 1) byte which will be programmed in the lower bank" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--12. 1. "OTPC_PCTRL_WADDR,Defines the address of a 32 bits word {U1 L1 U0 L0} in the macrocells where one or two bits will be programmed"
group.long 0x08++0x03
line.long 0x00 "OTPC_STAT_REG,Status register"
hexmask.long.word 0x00 16.--28. 1. "OTPC_STAT_NWORDS,Contains the current value of the words to be processed"
rbitfld.long 0x00 15. "OTPC_STAT_TERR_U,Indicates the upper bank as the source of a test error" "0: There is no test error in the upper bank,1: A test error has occured in the upper bank"
newline
rbitfld.long 0x00 14. "OTPC_STAT_TERR_L,Indicates the lower bank as the source of a test error" "0: There is no test error in the lower bank,1: A test error has occured in the lower bank"
rbitfld.long 0x00 13. "OTPC_STAT_PERR_U,Indicates the upper bank as the source of a programming error" "0: N programming error,1: A programming error has occured"
newline
rbitfld.long 0x00 12. "OTPC_STAT_PERR_L,Indicates the lower bank as the source of a programming error" "0: There is no programming error in the lower bank,1: A programming error has occured in the lower.."
rbitfld.long 0x00 8.--11. "OTPC_STAT_FWORDS,Indicates the number of words which contained in the fifo of the controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 4. "OTPC_STAT_ARDY,Monitors the progress of read or programming operations while in the AREAD or APROG modes" "0: The controller is busy while reading or,1: The controller is not busy in AREAD or APROG.."
rbitfld.long 0x00 3. "OTPC_STAT_TERROR,Indicates the result of a test sequence" "0: The test sequence ends with no error,1: The test sequence has failed"
newline
rbitfld.long 0x00 2. "OTPC_STAT_TRDY,Indicates the state of a test mode" "0: The controller is busy,1: There is no active test mode"
rbitfld.long 0x00 1. "OTPC_STAT_PERROR,Indicates that an error has occurred during the bit-programming process" "0: No error during the bit-programming process,1: The process of bit-programming failed"
newline
rbitfld.long 0x00 0. "OTPC_STAT_PRDY,Indicates the state of a bit-programming process" "0: The controller is busy,1: The logic which performs bit-programming is.."
tree.end
tree "QUADEC580_GR01"
base ad:0x50000200
group.word 0x06++0x01
line.word 0x00 "QDEC_CLOCKDIV_REG,Clock divider register"
hexmask.word 0x00 0.--9. 1. "clock_divider,Contains the number of the input clock cycles minus one that are required to generate one logic clock cycle"
group.word 0x08++0x01
line.word 0x00 "QDEC_CTRL2_REG,Quad Decoder control register"
bitfld.word 0x00 8.--11. "CHZ_PORT_SEL,Defines which GPIOs are mapped on Channel Z" "0: none,1: P0[0] -> CHZ_A P0[1] -> CHZ_B,2: P0[2] -> CHZ_A P0[3] -> CHZ_B,3: P0[4] -> CHZ_A P0[5] -> CHZ_B,4: P0[6] -> CHZ_A P0[7] -> CHZ_B,5: P1[0] -> CHZ_A P1[1] -> CHZ_B,6: P1[2] -> CHZ_A P1[3] -> CHZ_B,7: P2[3] -> CHZ_A P2[4] -> CHZ_B,8: P2[5] -> CHZ_A P2[6] -> CHZ_B,9: P2[7] -> CHZ_A P2[8] -> CHZ_B,10: P2[9] -> CHZ_A P2[0] -> CHZ_B 11..15,?..."
bitfld.word 0x00 4.--7. "CHY_PORT_SEL,Defines which GPIOs are mapped on Channel Y" "0: none,1: P0[0] -> CHY_A P0[1] -> CHY_B,2: P0[2] -> CHY_A P0[3] -> CHY_B,3: P0[4] -> CHY_A P0[5] -> CHY_B,4: P0[6] -> CHY_A P0[7] -> CHY_B,5: P1[0] -> CHY_A P1[1] -> CHY_B,6: P1[2] -> CHY_A P1[3] -> CHY_B,7: P2[3] -> CHY_A P2[4] -> CHY_B,8: P2[5] -> CHY_A P2[6] -> CHY_B,9: P2[7] -> CHY_A P2[8] -> CHY_B,10: P2[9] -> CHY_A P2[0] -> CHY_B 11..15,?..."
newline
bitfld.word 0x00 0.--3. "CHX_PORT_SEL,Defines which GPIOs are mapped on Channel X" "0: none,1: P0[0] -> CHX_A P0[1] -> CHX_B,2: P0[2] -> CHX_A P0[3] -> CHX_B,3: P0[4] -> CHX_A P0[5] -> CHX_B,4: P0[6] -> CHX_A P0[7] -> CHX_B,5: P1[0] -> CHX_A P1[1] -> CHX_B,6: P1[2] -> CHX_A P1[3] -> CHX_B,7: P2[3] -> CHX_A P2[4] -> CHX_B,8: P2[5] -> CHX_A P2[6] -> CHX_B,9: P2[7] -> CHX_A P2[8] -> CHX_B,10: P2[9] -> CHX_A P2[0] -> CHX_B 11..15,?..."
group.word 0x00++0x01
line.word 0x00 "QDEC_CTRL_REG,Quad Decoder control register"
hexmask.word.byte 0x00 3.--9. 1. "QD_IRQ_THRES,The number of events on either counter (X or Y) that need to be reached before an interrupt is generated"
rbitfld.word 0x00 2. "QD_IRQ_STATUS,Interrupt Status" "0,1"
newline
bitfld.word 0x00 1. "QD_IRQ_CLR,Writing 1 to this bit clears the interrupt" "0,1"
bitfld.word 0x00 0. "QD_IRQ_MASK," "0,1"
group.word 0x02++0x01
line.word 0x00 "QDEC_XCNT_REG,Counter value of the X Axis"
hexmask.word 0x00 0.--15. 1. "X_counter,Contains a signed value of the events"
group.word 0x04++0x01
line.word 0x00 "QDEC_YCNT_REG,Counter value of the Y Axis"
hexmask.word 0x00 0.--15. 1. "Y_counter,Contains a signed value of the events"
group.word 0x0A++0x01
line.word 0x00 "QDEC_ZCNT_REG,Z_counter"
hexmask.word 0x00 0.--15. 1. "Z_counter,Contains a signed value of the events"
tree.end
tree "R_RFCU580_NL01"
base ad:0x50002000
group.word 0x600++0x01
line.word 0x00 "BIAS_CTRL1_REG,"
bitfld.word 0x00 12.--15. "IFF_BIAS_SET,Tuning of the IF filter bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 8.--11. "VCO_BIAS_SET,Tuning of the VCO bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 4.--7. "CP_BIAS_SET,Tuning of the charge pump bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "MIX_BIAS_SET,Tuning of the mixer bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x310++0x01
line.word 0x00 "RF_ADCI_DC_OFFSET_REG,Must be Retained"
hexmask.word.byte 0x00 8.--15. 1. "ADC_OFFN_I_RD,DC offset compensation in the I path (inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)"
hexmask.word.byte 0x00 0.--7. 1. "ADC_OFFP_I_RD,DC offset compensation in the I path (non-inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)"
group.word 0x312++0x01
line.word 0x00 "RF_ADCQ_DC_OFFSET_REG,Must be Retained"
hexmask.word.byte 0x00 8.--15. 1. "ADC_OFFN_Q_RD,DC offset compensation in the Q path (inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)"
hexmask.word.byte 0x00 0.--7. 1. "ADC_OFFP_Q_RD,DC offset compensation in the Q path (non-inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)"
group.word 0x830++0x01
line.word 0x00 "RF_ADC_CTRL1_REG,"
bitfld.word 0x00 14. "ADC_SIGN,Change polarity of ADC input" "0,1"
bitfld.word 0x00 13. "ADC_MUTE," "0,1"
newline
bitfld.word 0x00 0. "ADC_DC_OFFSET_SEL," "0,1"
group.word 0x832++0x01
line.word 0x00 "RF_ADC_CTRL2_REG,"
hexmask.word.byte 0x00 8.--15. 1. "ADC_OFFN_I_WR,External value for the DC offset compensation in the I path negative side"
hexmask.word.byte 0x00 0.--7. 1. "ADC_OFFP_I_WR,External value for the DC offset compensation in the I path positive side"
group.word 0x834++0x01
line.word 0x00 "RF_ADC_CTRL3_REG,"
hexmask.word.byte 0x00 8.--15. 1. "ADC_OFFN_Q_WR,External value for the DC offset compensation in the Q path negative side"
hexmask.word.byte 0x00 0.--7. 1. "ADC_OFFP_Q_WR,External value for the DC offset compensation in the Q path positive side"
group.word 0x864++0x01
line.word 0x00 "RF_AFC_CTRL_REG,"
bitfld.word 0x00 6.--7. "POLE2,Choose the method to use for AFC tracking during the slot Description TBD" "0,1,2,3"
bitfld.word 0x00 4.--5. "POLE1,Choose the method to use for AFC tracking during the slot Description TBD" "0,1,2,3"
newline
bitfld.word 0x00 0.--3. "AFC_MODE,Choose the method to use for AFC tracking during the slot Description TBD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x860++0x01
line.word 0x00 "RF_AGC_CTRL1_REG,"
bitfld.word 0x00 14.--15. "AGC_MODE,Choose the method to use for AGC evaluation Description TBD" "0,1,2,3"
hexmask.word.byte 0x00 7.--13. 1. "AGC_TH_HIGH,AGC hysteresis high threshold (switch up one AGC_SETTING_R step when exceeding this level)"
newline
hexmask.word.byte 0x00 0.--6. 1. "AGC_TH_LOW,AGC hysteresis low threshold (switch down one AGC_SETTING_R step when dropping below this level)"
group.word 0x862++0x01
line.word 0x00 "RF_AGC_CTRL2_REG,"
bitfld.word 0x00 12. "SLOW_AGC,Enable the slow AGC mode (no consecutive AGC setting switches)" "0,1"
bitfld.word 0x00 8.--11. "AGCSETTING_WR,Fixed AGC setting to be used to configure LNA VGA1 and VGA2 when AGCSETTING_SEL = 1" "0: Highest gain in RF_AGC_LUT_01_REG,1: Lower gain in RF_AGC_LUT_01_REG,2: Still lower gain in,?..."
newline
bitfld.word 0x00 7. "AGCSETTING_SEL,LNA VGA1 and VGA2 gains '0': controlled by AGC'1': provided manually through AGCSETTING_WR" "0,1"
bitfld.word 0x00 6. "EN_FRZ_GAIN,'0': AGC always active'1': Freeze gain after Access Address detection" "0,1"
newline
bitfld.word 0x00 0.--5. "RSSI_TH,RSSI threshold for the packet detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x850++0x01
line.word 0x00 "RF_AGC_LUT_01_REG,"
bitfld.word 0x00 14.--15. "LNA_GAIN1,LNA gain setting while in AGC setting 0" "0,1,2,3"
bitfld.word 0x00 11.--13. "VGA1_GAIN1,VGA1 gain setting while in AGC setting 1" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 8.--10. "VGA2_GAIN1,VGA2 gain setting while in AGC setting 1" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6.--7. "LNA_GAIN0,LNA gain setting while in AGC setting 0" "0,1,2,3"
newline
bitfld.word 0x00 3.--5. "VGA1_GAIN0,VGA1 gain setting while in AGC setting 0" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "VGA2_GAIN0,VGA2 gain setting while in AGC setting 0" "0,1,2,3,4,5,6,7"
group.word 0x852++0x01
line.word 0x00 "RF_AGC_LUT_23_REG,"
bitfld.word 0x00 11.--13. "VGA1_GAIN3,VGA1 gain setting while in AGC setting 3" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 8.--10. "VGA2_GAIN3,VGA2 gain setting while in AGC setting 3" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 3.--5. "VGA1_GAIN2,VGA1 gain setting while in AGC setting 2" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "VGA2_GAIN2,VGA2 gain setting while in AGC setting 2" "0,1,2,3,4,5,6,7"
group.word 0x854++0x01
line.word 0x00 "RF_AGC_LUT_45_REG,"
bitfld.word 0x00 14.--15. "LNA_GAIN5,LNA gain setting while in AGC setting 5" "0,1,2,3"
bitfld.word 0x00 11.--13. "VGA1_GAIN5,VGA1 gain setting while in AGC setting 5" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 8.--10. "VGA2_GAIN5,VGA2 gain setting while in AGC setting 5" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6.--7. "LNA_GAIN4,LNA gain setting while in AGC setting 4" "0,1,2,3"
newline
bitfld.word 0x00 3.--5. "VGA1_GAIN4,VGA1 gain setting while in AGC setting 4" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "VGA2_GAIN4,VGA2 gain setting while in AGC setting 4" "0,1,2,3,4,5,6,7"
group.word 0x856++0x01
line.word 0x00 "RF_AGC_LUT_67_REG,"
bitfld.word 0x00 14.--15. "LNA_GAIN7,LNA gain setting while in AGC setting 7" "0,1,2,3"
bitfld.word 0x00 11.--13. "VGA1_GAIN7,VGA1 gain setting while in AGC setting 7" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 8.--10. "VGA2_GAIN7,VGA2 gain setting while in AGC setting 7" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6.--7. "LNA_GAIN6,LNA gain setting while in AGC setting 6" "0,1,2,3"
newline
bitfld.word 0x00 3.--5. "VGA1_GAIN6,VGA1 gain setting while in AGC setting 6" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "VGA2_GAIN6,VGA2 gain setting while in AGC setting 6" "0,1,2,3,4,5,6,7"
group.word 0x858++0x01
line.word 0x00 "RF_AGC_LUT_89_REG,"
bitfld.word 0x00 14.--15. "LNA_GAIN9,LNA gain setting while in AGC setting 9" "0,1,2,3"
bitfld.word 0x00 11.--13. "VGA1_GAIN9,VGA1 gain setting while in AGC setting 9" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 8.--10. "VGA2_GAIN9,VGA2 gain setting while in AGC setting 9" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6.--7. "LNA_GAIN8,LNA gain setting while in AGC setting 8" "0,1,2,3"
newline
bitfld.word 0x00 3.--5. "VGA1_GAIN8,VGA1 gain setting while in AGC setting 8" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "VGA2_GAIN8,VGA2 gain setting while in AGC setting 8" "0,1,2,3,4,5,6,7"
group.word 0x900++0x01
line.word 0x00 "RF_AGC_RESULT_REG,"
rbitfld.word 0x00 8.--11. "AGCSETTING_RD,AGC setting as automatically selected in receive mode to configure LNA VGA1 and VGA2" "0: Highest gain as configured in RF_AGC_LUT_01_REG,1: Lower gain as configured in RF_AGC_LUT_01_REG,2: Still lower gain as configured in,?..."
hexmask.word.byte 0x00 0.--7. 1. "AFC_RD,Frequency offset estimation (in 2s complement) with a resolution of approximately 5 kHz"
group.word 0x00++0x01
line.word 0x00 "RF_BMCW_REG,Changed functionality of bits [7:6]"
bitfld.word 0x00 8. "CN_SEL,Select between" "0: use BLE Frequency word (normal function),1: use CN_WR as channel number"
hexmask.word.byte 0x00 0.--7. 1. "CN_WR,[7:6] = offset to RFCAL_CAP_WR coarse calibraton LUT [5:0] = channel number"
group.word 0x60++0x01
line.word 0x00 "RF_CALCAP1_REG,"
hexmask.word 0x00 0.--15. 1. "VCO_CALCAP_LOW,Lowest 16 bits of vco_calcap"
group.word 0x62++0x01
line.word 0x00 "RF_CALCAP2_REG,"
rbitfld.word 0x00 0.--1. "VCO_CALCAP_HIGH,Highest 2 bits of vco_calcap" "0,1,2,3"
group.word 0x40++0x01
line.word 0x00 "RF_CALSTATE_REG,"
rbitfld.word 0x00 0.--3. "CALSTATE,Value of the calstate state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x200++0x01
line.word 0x00 "RF_CAL_CTRL_REG,"
bitfld.word 0x00 5. "VCO_CAL_DIS,Do not calibrate the VCO during Cal cycle" "0,1"
bitfld.word 0x00 4. "DC_OFFSET_CAL_DIS,Do not calibrate the VGA2 Offset during Cal cycle" "0,1"
newline
bitfld.word 0x00 3. "IFF_CAL_DIS,Do not calibrate the IFF center frequency during Cal cycle" "0,1"
bitfld.word 0x00 2. "MGAIN_CAL_DIS,Do not calibrate the VCO and Modulation Gain during Cal cycle" "0,1"
newline
rbitfld.word 0x00 1. "EO_CAL,End of calibration trigger" "0,1"
bitfld.word 0x00 0. "SO_CAL,Start of calibration trigger.Writing a 1 starts calibration.1Reading returns the calibration status (1 = busy calibrating)" "0,1"
group.word 0x512++0x01
line.word 0x00 "RF_CNTRL_TIMER_10_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x514++0x01
line.word 0x00 "RF_CNTRL_TIMER_11_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x516++0x01
line.word 0x00 "RF_CNTRL_TIMER_12_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x518++0x01
line.word 0x00 "RF_CNTRL_TIMER_13_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x51A++0x01
line.word 0x00 "RF_CNTRL_TIMER_14_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x500++0x01
line.word 0x00 "RF_CNTRL_TIMER_1_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x502++0x01
line.word 0x00 "RF_CNTRL_TIMER_2_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x504++0x01
line.word 0x00 "RF_CNTRL_TIMER_3_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x506++0x01
line.word 0x00 "RF_CNTRL_TIMER_4_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x508++0x01
line.word 0x00 "RF_CNTRL_TIMER_5_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x50A++0x01
line.word 0x00 "RF_CNTRL_TIMER_6_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x50C++0x01
line.word 0x00 "RF_CNTRL_TIMER_7_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x50E++0x01
line.word 0x00 "RF_CNTRL_TIMER_8_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0x510++0x01
line.word 0x00 "RF_CNTRL_TIMER_9_REG,"
hexmask.word.byte 0x00 8.--15. 1. "RESET_OFFSET,Offset w.r.t"
hexmask.word.byte 0x00 0.--7. 1. "SET_OFFSET,Offset w.r.t"
group.word 0xC50++0x01
line.word 0x00 "RF_CP_CTRL_REG,"
bitfld.word 0x00 12.--15. "CP_CUR_TX,CP current setting during PLL - Lock in TX mode" "0: 3.75 ?A bit,1: 3.75 ?A bit,2: 7.5 ?A bit,3: 30 ?A,?,?,?,7: 15 ?A (setting 1),?,?,?,11: 7.5 ?A (setting 2),?,?,?,15: 45 ?A (fastest setting 0)"
bitfld.word 0x00 8.--11. "CP_CUR_RX,CP current setting during PLL - lock in RX mode same coding as for CP_CUR_TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 4.--7. "CP_CUR_SET_TX,Chargepump current setting during PLL settling in TX mode same coding as for CP_CUR_TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CP_CUR_SET_RX,Chargepump current setting during PLL settling in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x866++0x01
line.word 0x00 "RF_DC_OFFSET_CTRL1_REG,"
hexmask.word.byte 0x00 8.--15. 1. "DCOFFSET_Q_WR,DC offset compensation value in Q channel valid when DCOFFSET_SEL = 1"
hexmask.word.byte 0x00 0.--7. 1. "DCOFFSET_I_WR,DC offset compensation value in I channel valid when DCOFFSET_SEL = 1"
group.word 0x868++0x01
line.word 0x00 "RF_DC_OFFSET_CTRL2_REG,"
bitfld.word 0x00 7.--8. "DCNGAIN,Number of gain settings for the full DC offset calibration" "0,1,2,3"
bitfld.word 0x00 4.--6. "DCNSTEP,Number of the steps per.gain setting for the full or partial DC offset calibrations" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 2.--3. "DCPOLE,Selects the pole of the digital high pass fitlers Encoding: TBD" "0,1,2,3"
bitfld.word 0x00 1. "DCPARCAL_EN,Enable flag for the partial DC offset calibration (executed when the demodulator is enabled)" "0,1"
newline
bitfld.word 0x00 0. "DCOFFSET_SEL,'0': Normal operation '1': Use the manual DC offset compensation values from RF_DC_OFFSET_CTRL1_REG" "0,1"
group.word 0x86A++0x01
line.word 0x00 "RF_DC_OFFSET_CTRL3_REG,"
hexmask.word.byte 0x00 8.--15. 1. "DCBETA_Q,Quadrature feedback gain for the DC offset calibration"
hexmask.word.byte 0x00 0.--7. 1. "DCBETA_I,Inphase feedback gain for the DC offset calibration"
group.word 0x86C++0x01
line.word 0x00 "RF_DC_OFFSET_CTRL4_REG,"
bitfld.word 0x00 12.--15. "DCAGCSETTING_FULL3,AGC setting for forth last the gain step for the full DC offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 8.--11. "DCAGCSETTING_FULL2,AGC setting for third last the gain step for the full DC offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 4.--7. "DCAGCSETTING_FULL1,AGC setting for second last the gain step for the full DC offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "DCAGCSETTING_FULL0,AGC setting for last the gain step for the full DC offset calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x314++0x01
line.word 0x00 "RF_DC_OFFSET_RESULT_REG,Must be Retained"
hexmask.word.byte 0x00 8.--15. 1. "DCOFFSET_Q_RD,DC offset compensation value in Q channel valid when DCOFFSET_SEL = 0"
hexmask.word.byte 0x00 0.--7. 1. "DCOFFSET_I_RD,DC offset compensation value in I channel valid when DCOFFSET_SEL = 0"
group.word 0x840++0x01
line.word 0x00 "RF_DEM_CTRL_REG,"
bitfld.word 0x00 6. "EQUAL_EN,Enable the equalizer in the demodulator" "0,1"
bitfld.word 0x00 2.--5. "MATCH0101_TH,Threshold for the 0101 pattern matching" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 1. "DEM_HSI_POL,Invert 'frequency' polarity of the demodulator" "0,1"
bitfld.word 0x00 0. "RXDATA_INV,'0': Normal operation '1': Invert the polarity of the received bits" "0,1"
group.word 0x412++0x01
line.word 0x00 "RF_ENABLE_CONFIG10_REG,"
hexmask.word.byte 0x00 8.--15. 1. "adc_en,Timing configuration for enable of the ADC"
hexmask.word.byte 0x00 0.--7. 1. "vco_en,Timing configuration for enable of the VCO"
group.word 0x414++0x01
line.word 0x00 "RF_ENABLE_CONFIG11_REG,"
hexmask.word.byte 0x00 8.--15. 1. "md_lobuf_en,Timing configuration for enable of main divider of the LO buffer"
hexmask.word.byte 0x00 0.--7. 1. "cp_en,Timing configuration for enable of CP"
group.word 0x416++0x01
line.word 0x00 "RF_ENABLE_CONFIG12_REG,"
hexmask.word.byte 0x00 8.--15. 1. "pfd_en,Timing configuration for the phase frequency detector"
hexmask.word.byte 0x00 0.--7. 1. "gauss_en,Timing configuration for the gauss module"
group.word 0x418++0x01
line.word 0x00 "RF_ENABLE_CONFIG13_REG,"
hexmask.word.byte 0x00 8.--15. 1. "rfio_en,Timing configuration for the rfio"
hexmask.word.byte 0x00 0.--7. 1. "lobuf_pa_en,Timing configuration for the PA lobuffer"
group.word 0x41A++0x01
line.word 0x00 "RF_ENABLE_CONFIG14_REG,"
hexmask.word.byte 0x00 8.--15. 1. "lobuf_rxiq_en,Timing configuration for the rxi lobuffer"
hexmask.word.byte 0x00 0.--7. 1. "div2_en,Timing configuration for the 2 divider"
group.word 0x41C++0x01
line.word 0x00 "RF_ENABLE_CONFIG15_REG,"
hexmask.word.byte 0x00 8.--15. 1. "cp_bias_sh_open,Timing configuration for the CP bias S/H switch"
hexmask.word.byte 0x00 0.--7. 1. "vco_bias_sh_open_en,Timing configuration for the VCO bias S/H switch"
group.word 0x41E++0x01
line.word 0x00 "RF_ENABLE_CONFIG16_REG,"
hexmask.word.byte 0x00 8.--15. 1. "iff_bias_sh_open_en,Timing configuration for iffmix bias S/H switch"
hexmask.word.byte 0x00 0.--7. 1. "gauss_bias_sh_open_en,Timing configuration for gauss bias S/H switch"
group.word 0x420++0x01
line.word 0x00 "RF_ENABLE_CONFIG17_REG,"
hexmask.word.byte 0x00 8.--15. 1. "mix_bias_sh_open_en,Timing configuration for pa bias S/H switch"
hexmask.word.byte 0x00 0.--7. 1. "plldig_en,Timing configuration for the plldig"
group.word 0x422++0x01
line.word 0x00 "RF_ENABLE_CONFIG18_REG,"
hexmask.word.byte 0x00 8.--15. 1. "pllclosed_en,Timing configuration for pllclosed"
hexmask.word.byte 0x00 0.--7. 1. "dem_en,Timing configuration for demodulator"
group.word 0x424++0x01
line.word 0x00 "RF_ENABLE_CONFIG19_REG,"
hexmask.word.byte 0x00 8.--15. 1. "ldo_zero_en,Timing configuration for radio LDO auto zero enable"
hexmask.word.byte 0x00 0.--7. 1. "cal_en,Timing configuration for calibration slot"
group.word 0x400++0x01
line.word 0x00 "RF_ENABLE_CONFIG1_REG,"
hexmask.word.byte 0x00 8.--15. 1. "lna_ldo_en,Timing configuration for enable of the lna ldo"
hexmask.word.byte 0x00 0.--7. 1. "lna_core_en,Timing configuration for enable of the lna core"
group.word 0x426++0x01
line.word 0x00 "RF_ENABLE_CONFIG20_REG,"
hexmask.word.byte 0x00 8.--15. 1. "tdc_en,Timing configuration for time to digital converter"
hexmask.word.byte 0x00 0.--7. 1. "ldo_rfio_en,Timing configuration for RFIO LDO"
group.word 0x428++0x01
line.word 0x00 "RF_ENABLE_CONFIG21_REG,"
hexmask.word.byte 0x00 8.--15. 1. "rfio_bias_en,Timing configuration for bias block for RFIO and RFPA"
hexmask.word.byte 0x00 0.--7. 1. "rfio_bias_sh_open,Timing configuration for S/H switch of bias block for RFIO/RFPA"
group.word 0x42A++0x01
line.word 0x00 "RF_ENABLE_CONFIG22_REG,"
hexmask.word.byte 0x00 8.--15. 1. "ldo_radio_en,Timing configuration for LDO for the radio IO buffer"
hexmask.word.byte 0x00 0.--7. 1. "adc_clk_en,Timing configuration for the enable of the ADC clock"
group.word 0x42C++0x01
line.word 0x00 "RF_ENABLE_CONFIG23_REG,"
hexmask.word.byte 0x00 8.--15. 1. "tr_pwm_off_en,Timing configuration for tr_pwm_off_en"
hexmask.word.byte 0x00 0.--7. 1. "spare_en_3,Timing configuration for spare_en_3"
group.word 0x402++0x01
line.word 0x00 "RF_ENABLE_CONFIG2_REG,"
hexmask.word.byte 0x00 8.--15. 1. "lna_cgm_en,Timing configuration for enable of the lna cgm"
hexmask.word.byte 0x00 0.--7. 1. "mix_ldo_en,Timing configuration for enable of the mix ldo"
group.word 0x404++0x01
line.word 0x00 "RF_ENABLE_CONFIG3_REG,"
hexmask.word.byte 0x00 8.--15. 1. "iff_ldo_en,Timing configuration for enable of the iff ldo"
hexmask.word.byte 0x00 0.--7. 1. "ifadc_ldo_en,Timing configuration for enable of the ifadc ldo"
group.word 0x406++0x01
line.word 0x00 "RF_ENABLE_CONFIG4_REG,"
hexmask.word.byte 0x00 8.--15. 1. "vco_ldo_en,Timing configuration for enable of the vco ldo"
hexmask.word.byte 0x00 0.--7. 1. "md_ldo_en,Timing configuration for enable of the md ldo"
group.word 0x408++0x01
line.word 0x00 "RF_ENABLE_CONFIG5_REG,"
hexmask.word.byte 0x00 8.--15. 1. "pfd_ldo_en,Timing configuration for enable of the pfd ldo"
hexmask.word.byte 0x00 0.--7. 1. "pa_ldo_en,Timing configuration for enable of the pa ldo"
group.word 0x40A++0x01
line.word 0x00 "RF_ENABLE_CONFIG6_REG,"
hexmask.word.byte 0x00 8.--15. 1. "cp_switch_en,Timing configuration for the dynamic CP current switching"
hexmask.word.byte 0x00 0.--7. 1. "vco_bias_en,Timing configuration for the VCO bias"
group.word 0x40C++0x01
line.word 0x00 "RF_ENABLE_CONFIG7_REG,"
hexmask.word.byte 0x00 8.--15. 1. "cp_bias_en,Timing configuration for enable of the CP bias"
hexmask.word.byte 0x00 0.--7. 1. "lna_ldo_zero,autozero control signal of the lna ldo"
group.word 0x40E++0x01
line.word 0x00 "RF_ENABLE_CONFIG8_REG,"
hexmask.word.byte 0x00 8.--15. 1. "pa_ramp_en,Timing configuration for enable of the PA ramp"
hexmask.word.byte 0x00 0.--7. 1. "pa_en,Timing configuration for enable of the PA"
group.word 0x410++0x01
line.word 0x00 "RF_ENABLE_CONFIG9_REG,"
hexmask.word.byte 0x00 8.--15. 1. "mix_en,Timing configuration for enable of the mixer"
hexmask.word.byte 0x00 0.--7. 1. "iff_en,Timing configuration for enable of the iff"
group.word 0x820++0x01
line.word 0x00 "RF_IFF_CTRL1_REG,"
bitfld.word 0x00 8. "IFF_DCOC_DAC_DIS,Disable the DC offset current DAC" "0,1"
bitfld.word 0x00 7. "RO_TO_PINS,'0': normal operation '1': Enable reference oscillator" "0,1"
newline
bitfld.word 0x00 6. "IF_MUTE,'0': normal operation '1': Mute IFF by short circuit of VGA1 input" "0,1"
bitfld.word 0x00 5. "IF_CAL_CAP_SEL,'0': use value as determined by IF calibration for IF filter '1': use the value written to IF_CAL_CAP for IF filter" "0,1"
newline
bitfld.word 0x00 0.--4. "IF_CAL_CAP_WR,External value for IF calibration capacitance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x300++0x01
line.word 0x00 "RF_IFF_RESULT_REG,Must be Retained"
rbitfld.word 0x00 0.--4. "IF_CAL_CAP_RD,IF calibration result capacitance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x204++0x01
line.word 0x00 "RF_IRQ_CTRL_REG,"
rbitfld.word 0x00 0. "EO_CAL_CLEAR,Writing any value to this bit clears eo_cal interrupt" "0,1"
group.word 0xC60++0x01
line.word 0x00 "RF_LF_CTRL_REG,"
bitfld.word 0x00 6. "LF_SHORT_R4,'0': R4 in place '1': R4 shorted C2 and C4 in parallel" "0,1"
bitfld.word 0x00 5. "LF_CAL_CAP_SEL,'0': Normal operation: use IF_CAL_CAP_RD (as determined by IF calibration) for the loop filter capacitance '1': use the value written to LF_CAL_CAP_WR" "0,1"
newline
bitfld.word 0x00 0.--4. "LF_CAL_CAP_WR,External value for loop filter calibration capacitance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0xC52++0x01
line.word 0x00 "RF_LF_RES_CTRL_REG,LF resistor setting"
bitfld.word 0x00 12.--15. "LF_RES_TX,Loopfilter resistor setting during PLL - Lock in TX mode 1xxx: 72 k (fastest setting 0) 01xx: 120 k (setting 1) 001x: 168 k (setting2) 000x: 240 k (slowest setting 3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 8.--11. "LF_RES_RX,Loopfilter resistor setting during PLL - Lock in RX mode same coding as for LF_RES_TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 4.--7. "LF_RES_SET_TX,Loopfilter resistor setting during PLL settling in TX mode same coding as for LF_RES_TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "LF_RES_SET_RX,Loopfilter resistor setting during PLL settling in RX mode same coding as for LF_RES_TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xC0A++0x01
line.word 0x00 "RF_MGAIN_CTRL2_REG,"
hexmask.word.byte 0x00 0.--6. 1. "MGAIN_TRANSMIT_LENGTH,Number of symbols for transmit0 and transmit1 length during mgain calibration"
group.word 0xC08++0x01
line.word 0x00 "RF_MGAIN_CTRL_REG,"
bitfld.word 0x00 13.--15. "KMOD_ALPHA,Kmod channel dependent trimming constant" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 11.--12. "MGAIN_AVER,Average over a number of comparator output values" "0: 1 value,1: 3 values,2: 5 values,3: 7 values"
newline
bitfld.word 0x00 10. "MGAIN_CMP_INV,Invert the output of the modulation gain comparator before usage" "0,1"
bitfld.word 0x00 9. "MGAIN_DBL_TRANSMIT,Length of a modulation gain calibration step" "0: 4 symbol periods,1: 8 symbol periods"
newline
bitfld.word 0x00 8. "GAUSS_GAIN_SEL," "0,1"
group.word 0xC10++0x01
line.word 0x00 "RF_MGC_CTRL_REG,"
bitfld.word 0x00 2.--3. "GAUSS_DAC_CTRL,Reserved bits for Gauss DAC settings" "0,1,2,3"
bitfld.word 0x00 1. "MGC_POLE_SW,Switch in an aditional pole on the mgc amplifer to have extra filtering of the loopfilter voltage" "0,1"
newline
bitfld.word 0x00 0. "MGC_GAIN_SET,Set the desired gain for the mgc calibration amplifier" "0,1"
group.word 0x810++0x01
line.word 0x00 "RF_MIXER_CTRL1_REG,"
bitfld.word 0x00 12.--15. "MIX_SPARE,Spare registers for mixer control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 8.--11. "MIX_TRIM_VCM,Trim the common mode voltage at the input of the TIA" "0: Minimum voltage,?,?,?,?,?,?,?,8: Nominal voltage F,?..."
newline
bitfld.word 0x00 4.--7. "MIX_TRIM_IBIAS,Trim the bias current of the TIA" "0: Minimum bias current,?,?,?,?,?,?,?,8: Nominal bias current F,?..."
bitfld.word 0x00 0.--3. "MIX_TRIM_GMBIAS,Trim the Mixer bias resistor for optimum transcunductance" "0: Minimum transconductance,?,?,?,?,?,?,?,8: Nominal transconductance F,?..."
group.word 0x812++0x01
line.word 0x00 "RF_MIXER_CTRL2_REG,"
bitfld.word 0x00 5. "MIX_CAL_CAP_SEL,'0': Normal operation: use IF_CAL_CAP_RD (as determined by IF calibration) for the loop filter capacitance '1': use the value written to MIX_CAL_CAP_WR" "0,1"
bitfld.word 0x00 0.--4. "MIX_CAL_CAP_WR,External value for calibration of mixer pole capacitance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x20++0x01
line.word 0x00 "RF_OVERRULE_REG,"
bitfld.word 0x00 3. "RX_EN_WR,Enable rx_en" "0,1"
bitfld.word 0x00 2. "RX_DIS_WR,Disable rx_en" "0,1"
newline
bitfld.word 0x00 1. "TX_EN_WR,Enable tx_en" "0,1"
bitfld.word 0x00 0. "TX_DIS_WR,Disable tx_en" "0,1"
group.word 0xA00++0x01
line.word 0x00 "RF_PA_CTRL_REG,Removed obsolete values of bits 10:7 pa_pw back to 4"
bitfld.word 0x00 11.--14. "LEVEL_LDO_RFPA,Control for PA supply voltage (output power)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 5.--6. "PA_RAMPSPEED,Ramping speed setting of the driver stage: '0x0': slowest (1.25 uA) '0x1': 2x faster (2.5 uA) '0x2': default ramping speed '0x3': fastest" "0,1,2,3"
newline
bitfld.word 0x00 2.--4. "PA_PW,Pulse width setting to control HD2 '0': not active '1': 48.8 percent duty cycle '2': 49.4 percent duty cycle '3': 49.7 percent duty cycle '4': 50 percent duty cycle (default) '5': 50.3 percent duty cycle '6': 50.6 percent duty cycle '7': 51.2.." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--1. "PA_GAIN,Sets gain/DC Current setting of the differential to single ended converter '0': smallest current setting (60 uA) '1': current setting 1 (80 uA) '2': default (100 uA) '3': largest current setting (120 uA)" "0,1,2,3"
group.word 0xC40++0x01
line.word 0x00 "RF_PFD_CTRL_REG,"
bitfld.word 0x00 3. "PFD_POLARITY,'0': Normal operation (UP: implies RCLK leads NCLK) '1': Inverted operation (UP: implies NCLK leads RCLK)" "0,1"
bitfld.word 0x00 2. "FIXED_CUR_EN,Enable manual override of PFD output '0': Normal operation '1': PFD ouput given by FIXED_CUR_SET" "0,1"
newline
bitfld.word 0x00 0.--1. "FIXED_CUR_SET,Set the PFD output in a fixed position such that the CP output current is constant'0': UP = 0 DN = 0 '1': UP = 0 DN = 1 '2': UP = 1 DN = 0 '3': UP = 1 DN = 1" "0,1,2,3"
group.word 0x870++0x01
line.word 0x00 "RF_RADIG_SPARE_REG,"
hexmask.word 0x00 3.--15. 1. "RADIG_SPARE,Spare bits to be defined later"
group.word 0x202++0x01
line.word 0x00 "RF_REF_OSC_REG,"
hexmask.word 0x00 6.--14. 1. "CNT_CLK,number of clock pulses corresponding to the value of CNT_RO"
bitfld.word 0x00 0.--5. "CNT_RO,number of reference oscillator periods that need to be counted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x902++0x01
line.word 0x00 "RF_RSSI_RESULT_REG,"
hexmask.word 0x00 6.--15. 1. "RSSI_AVG_RD,RSSI value measured in averaging mode in continuous RX mode (used for LNA selectivity calibration)"
rbitfld.word 0x00 0.--5. "RSSI_PH_RD,RSSI value measured in peak-hold mode during the preamble and Access Addres detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x80++0x01
line.word 0x00 "RF_SCAN_FEEDBACK_REG,"
rbitfld.word 0x00 4.--7. "CP_CUR,Cp_cur value during scan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.word 0x00 0.--3. "LF_RES,Lf_res value during scan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x602++0x01
line.word 0x00 "RF_SPARE1_REG,"
hexmask.word 0x00 1.--15. 1. "RF_SPARE1,Spare bits for radio"
bitfld.word 0x00 0. "IFF_REAL_MODE,Choose the transfer function mode of the IFF" "0: Normal operation (complex),1: Test mode (real approx. 16 dB less)"
group.word 0xC00++0x01
line.word 0x00 "RF_SYNTH_CTRL1_REG,"
bitfld.word 0x00 14. "PLL_HSI_POL,High Side Injection polarity" "0: LO frequency is lower than the wanted RF..,1: LO frequency is higher than the wanted RF"
bitfld.word 0x00 13. "CS,Channel Spacing" "0: 1MHz,1: 2MHz"
newline
bitfld.word 0x00 12. "SGN,Sign bit for the channel step" "0: positive,1: negative"
hexmask.word 0x00 0.--11. 1. "CHANNEL_ZERO,Channel 0 frequency in MHz"
group.word 0xC02++0x01
line.word 0x00 "RF_SYNTH_CTRL2_REG,"
bitfld.word 0x00 12. "BT_SEL," "0,1"
bitfld.word 0x00 11. "EO_PACKET_DIS,Disable the end of packet detection" "0: End of packet detection enabled,1: End of pakcet detection disabled"
newline
bitfld.word 0x00 10. "TXDATA_INV,Select polarity of the modulation prior to the pulse shaping" "0: Normal operation,1: Invert the modulation signal"
bitfld.word 0x00 9. "GAUSS_86,Select the output resolution in the analog signal path" "0: 8 bit resolution for the shaping signal,1: 6 bit resolution for the shaping signal"
newline
bitfld.word 0x00 8. "GAUSS_INV,Select polarity of the analog modulation path" "0: Normal operation,1: Invert the signal in the analog signal path"
bitfld.word 0x00 6.--7. "DELAY,Additional delay in analog signal path in RCLK cycles" "0,1,2,3"
newline
bitfld.word 0x00 4.--5. "MODINDEX,Modulation Index selection" "0: h = 1/2 (??f = 250 kHz),1: h = 1/4 (??f = 125 kHz),2: h = 17/32 (??f = 266 kHz),3: h = 35/64 (??f = 273 kHz)"
bitfld.word 0x00 2.--3. "SD_ORDER_TX,Order of the sigma-delta modulator in TX mode" "0,1,2,3"
newline
bitfld.word 0x00 0.--1. "SD_ORDER_RX,Order of the sigma-delta modulator in RX mode" "0,1,2,3"
group.word 0xC04++0x01
line.word 0x00 "RF_SYNTH_CTRL3_REG,"
bitfld.word 0x00 14. "MODVAL_SEL," "0,1"
hexmask.word 0x00 0.--13. 1. "MODVAL_WR,Externally provided modulation value in 2s complement ??f = 16 MHz x MODVAL_WR/16348"
group.word 0x318++0x01
line.word 0x00 "RF_SYNTH_RESULT2_REG,Must be Retained"
hexmask.word.byte 0x00 8.--14. 1. "CN_CAL_RD,Result of the modulation gain calibration (Retained)"
hexmask.word.byte 0x00 0.--7. 1. "GAUSS_GAIN_RD,Modulation gain after trimming (Not Retained)"
group.word 0x31A++0x01
line.word 0x00 "RF_SYNTH_RESULT3_REG,"
hexmask.word 0x00 0.--15. 1. "MDSTATE_RD,Content of the calibration counter"
group.word 0x316++0x01
line.word 0x00 "RF_SYNTH_RESULT_REG,Must be Retained"
rbitfld.word 0x00 8.--11. "VCO_FREQTRIM_RD,Result of the VCO calibration (Not Retained)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.word.byte 0x00 0.--7. 1. "GAUSS_GAIN_CAL_RD,Result of the modulation gain calibration (Retained)"
group.word 0xC70++0x01
line.word 0x00 "RF_TDC_CTRL_REG,TDC settings"
bitfld.word 0x00 12. "TDC_CONNECT,'0': Normal Operation (no measurement possible) '1': Connect the PFD inputs also to the TDC inputs" "0,1"
bitfld.word 0x00 10.--11. "REF_CTRL,Select how calibration is performed" "0,1,2,3"
newline
bitfld.word 0x00 9. "CAL_PH_2,Select calibration option 2 '0': normal operation (pfd measurement mode or cal mode 1) '1': measure the slow - fast oscillator period (calibration phase 2) ------- Note CAL_PH_1 must be 0 in this setting" "0,1"
bitfld.word 0x00 8. "CAL_PH_1,Select calibration option 1 '0': normal operation (pfd measurement or cal mode 2) '1': measure the fast oscillator period (calibration phase 1) ------- Note: CAL_PH_2 must be 0 in this setting" "0,1"
newline
bitfld.word 0x00 4.--7. "CTRL_SLOW,Trim the slow oscillator '0': Minimum frequency (default) 'F': Maximum frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CTRL_FAST,Trim the fast oscillator '0': mimimum frequency 'F': maximum frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xC06++0x01
line.word 0x00 "RF_VCOCAL_CTRL_REG,"
bitfld.word 0x00 5.--6. "VCOCAL_PERIOD,Length of a VCO calibration step" "0: 1 us,1: 2 us,2: 3 us,3: 4 us"
bitfld.word 0x00 4. "VCO_FREQTRIM_SEL," "0,1"
newline
bitfld.word 0x00 0.--3. "VCO_FREQTRIM_WR,Externally provided VCO calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xC20++0x01
line.word 0x00 "RF_VCOVAR_CTRL_REG,"
bitfld.word 0x00 14.--15. "MOD_VAR_V1,Bias voltage of the VCO Modulation varactor (high Vmod)" "0: low,1: mid,2: nominal,3: high"
bitfld.word 0x00 12.--13. "MOD_VAR_V0,Bias voltage of the VCO Modulation varactor (low Vmod)" "0: low,1: mid,2: nominal,3: high"
newline
bitfld.word 0x00 9.--11. "TUNE_VAR_V3,Bias voltage of the VCO Tuning varactor (high Vtune)" "?,1: low,2: nominal,?,4: high others,?..."
bitfld.word 0x00 6.--8. "TUNE_VAR_V2,Bias voltage of the VCO Tuning varactor (high-mid Vtune) Coding identical to TUNE_VAR_V3" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 3.--5. "TUNE_VAR_V1,Bias voltage of the VCO Tuning varactor (low-mid Vtune) Coding identical to TUNE_VAR_V3" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. "TUNE_VAR_V0,Bias voltage of the VCO Tuning varactor (low Vtune) Coding identical to TUNE_VAR_V3" "0,1,2,3,4,5,6,7"
group.word 0xC22++0x01
line.word 0x00 "RF_VCO_CALCAP_BIT14_REG,LUT entry for bit 14 of the VCO calibration capacitance"
hexmask.word 0x00 0.--15. 1. "VCO_CALCAP_BIT14,LUT entry for bit 14 of the VCO calibration capacitance"
group.word 0xC24++0x01
line.word 0x00 "RF_VCO_CALCAP_BIT15_REG,LUT entry for bit 15 of the VCO calibration capacitance"
hexmask.word 0x00 0.--15. 1. "VCO_CALCAP_BIT15,LUT entry for bit 15 of the VCO calibration capacitance"
tree.end
tree "RFPT580_GR01"
base ad:0x50003500
group.word 0x02++0x01
line.word 0x00 "RFPT_ADDR_REG,AHB master start address"
hexmask.word 0x00 2.--15. 1. "RFPT_ADDR,It is the AHB address used by the AHB-Lite master interface of the controller (the bits [15:2])"
group.word 0x00++0x01
line.word 0x00 "RFPT_CTRL_REG,Control register"
bitfld.word 0x00 1. "RFPT_PACK_SEL,Selects the source of data that will be captured" "0: Will capture the output of the two ADC,1: Will capture the output of the Phase Detector"
bitfld.word 0x00 0. "RFPT_PACK_EN,Starts the capturing of the data from the selected source ( RFPT_PACK_SEL )" "0: There is no capturing of data,1: The controller captures data"
group.word 0x04++0x01
line.word 0x00 "RFPT_LEN_REG,Data length register"
hexmask.word 0x00 0.--13. 1. "RFPT_LEN,The number of words (minus one) that should be transfered"
group.word 0x06++0x01
line.word 0x00 "RFPT_STAT_REG,Status register"
bitfld.word 0x00 1. "RFPT_OFLOW_STK,Indicates that during the transfer of the data at least one overflow has detected to the fifo" "0: The transfer completed without overflows,1: At least one overflow occured in the fifo"
rbitfld.word 0x00 0. "RFPT_ACTIVE,Indicates the state of the controller" "0: The controller is idle,1: The controller is active"
tree.end
tree "RISCUTIL580_GPREG_NL01"
base ad:0x50003300
group.word 0x04++0x01
line.word 0x00 "DEBUG_REG,Various debug information register"
bitfld.word 0x00 0. "DEBUGS_FREEZE_EN,Default '1' freezing of the on-chip timers is enabled when the Cortex-M0 is halted in DEBUG State" "0,1"
group.word 0x08++0x01
line.word 0x00 "GP_CONTROL_REG,General purpose system control register"
bitfld.word 0x00 1.--5. "EM_MAP,Select the mapping of the Exchange memory pages" "0: EM size 0 kB SysRAM size 42 kB,1: EM size 2 kB SysRAM size 48 kB,2: EM size 3 kB SysRAM size 47 kB,3: EM size 4 kB SysRAM size 46 kB,4: EM size 5 kB SysRAM size 45 kB,5: EM size 6 kB SysRAM size 44 kB,6: EM size 7 kB SysRAM size 43 kB,7: EM size 8 kB SysRAM size 42 kB,8: Reserved,9: EM size 4 kB SysRAM size 40 kB,10: EM size 5 kB SysRAM size 40 kB,11: EM size 6 kB SysRAM size 40 kB,12: EM size 7 kB SysRAM size 40 kB,13: EM size 8 kB SysRAM size 40 kB,14: EM size 9 kB SysRAM size 40 kB,15: EM size 10 kB SysRAM size 40 kB,16: Reserved,17: EM size 6 kB SysRAM size 38 kB,18: EM size 7 kB SysRAM size 38 kB,19: EM size 8 kB SysRAM size 38 kB,20: EM size 9 kB SysRAM size 38 kB,21: EM size 10 kB SysRAM size 38 kB,22: EM size 11 kB SysRAM size 38 kB,23: EM size 12 kB SysRAM size 38 kB other:..,?..."
bitfld.word 0x00 0. "BLE_WAKEUP_REQ,If '1' the BLE wakes up" "0,1"
group.word 0x06++0x01
line.word 0x00 "GP_STATUS_REG,General purpose system status register"
bitfld.word 0x00 0. "CAL_PHASE,If '1' it designates that the chip is in Calibration Phase i.e" "0,1"
group.word 0x02++0x01
line.word 0x00 "RESET_FREEZE_REG,Controls unfreezing of various timers/counters"
bitfld.word 0x00 3. "FRZ_WDOG,If '1' the watchdog timer continues '0' is discarded" "0,1"
bitfld.word 0x00 2. "FRZ_BLETIM,If '1' the the BLE master clock continues '0' is discarded" "0,1"
newline
bitfld.word 0x00 1. "FRZ_SWTIM,If '1' the SW Timer (TIMER0) continues '0' is discarded" "0,1"
bitfld.word 0x00 0. "FRZ_WKUPTIM,If '1' the Wake Up Timer continues '0' is discarded" "0,1"
group.word 0x00++0x01
line.word 0x00 "SET_FREEZE_REG,Controls freezing of various timers/counters"
bitfld.word 0x00 3. "FRZ_WDOG,If '1' the watchdog timer is frozen '0' is discarded" "0,1"
bitfld.word 0x00 2. "FRZ_BLETIM,If '1' the BLE master clock is frozen '0' is discarded" "0,1"
newline
bitfld.word 0x00 1. "FRZ_SWTIM,If '1' the SW Timer (TIMER0) is frozen '0' is discarded" "0,1"
bitfld.word 0x00 0. "FRZ_WKUPTIM,If '1' the Wake Up Timer is frozen '0' is discarded" "0,1"
tree.end
tree "RISCUTIL580_WDOG_NL00"
base ad:0x50003100
group.word 0x02++0x01
line.word 0x00 "WATCHDOG_CTRL_REG,Watchdog control register"
bitfld.word 0x00 0. "NMI_RST," "0,1"
group.word 0x00++0x01
line.word 0x00 "WATCHDOG_REG,Watchdog timer register"
hexmask.word.byte 0x00 9.--15. 1. "WDOG_WEN,0000.000 = Write enable for Watchdog timer else Write disable"
bitfld.word 0x00 8. "WDOG_VAL_NEG," "0,1"
newline
hexmask.word.byte 0x00 0.--7. 1. "WDOG_VAL,Write: Watchdog timer reload value"
tree.end
tree "SPI443_NL00"
base ad:0x50001200
group.word 0x06++0x01
line.word 0x00 "SPI_CLEAR_INT_REG,SPI clear interrupt register"
hexmask.word 0x00 0.--15. 1. "SPI_CLEAR_INT,Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT] Reading returns 0"
group.word 0x00++0x01
line.word 0x00 "SPI_CTRL_REG,SPI control register 0"
bitfld.word 0x00 15. "SPI_EN_CTRL," "0,1"
bitfld.word 0x00 14. "SPI_MINT," "0,1"
newline
rbitfld.word 0x00 13. "SPI_INT_BIT," "0,1"
rbitfld.word 0x00 12. "SPI_DI,Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)" "0,1"
newline
rbitfld.word 0x00 11. "SPI_TXH," "0,1"
bitfld.word 0x00 10. "SPI_FORCE_DO," "0,1"
newline
bitfld.word 0x00 9. "SPI_RST," "0,1"
bitfld.word 0x00 7.--8. "SPI_WORD," "?,1: 16 bit mode only SPI_RX_TX_REG0 used,2: 32 bits mode SPI_RX_TX_REG0 & SPI_RX_TX_REG1..,3: 9 bits mode"
newline
bitfld.word 0x00 6. "SPI_SMN,Master/slave mode" "0: Master,1: Slave(SPI1 only)"
bitfld.word 0x00 5. "SPI_DO,Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1" "0,1"
newline
bitfld.word 0x00 3.--4. "SPI_CLK,Select SPI_CLK clock frequency in master mode:00 = (XTAL) / (CLK_PER_REG *8)" "?,1: (XTAL) / (CLK_PER_REG *4),2: (XTAL) / (CLK_PER_REG *2),3: (XTAL) / (CLK_PER_REG *14)"
bitfld.word 0x00 2. "SPI_POL,Select SPI_CLK polarity" "0: SPI_CLK is initially low,1: SPI_CLK is initially high"
newline
bitfld.word 0x00 1. "SPI_PHA,Select SPI_CLK phase" "0,1"
bitfld.word 0x00 0. "SPI_ON," "0,1"
group.word 0x08++0x01
line.word 0x00 "SPI_CTRL_REG1,SPI control register 1"
bitfld.word 0x00 4. "SPI_9BIT_VAL,Determines the value of the first bit in 9 bits SPI mode" "0,1"
rbitfld.word 0x00 3. "SPI_BUSY," "0,1"
newline
bitfld.word 0x00 2. "SPI_PRIORITY," "0,1"
bitfld.word 0x00 0.--1. "SPI_FIFO_MODE," "?,1: RX-FIFO used (Read Only Mode) TX-FIFO single,2: TX-FIFO used (Write Only Mode) RX-FIFO single,3: No FIFOs used (backwards compatible mode)"
group.word 0x02++0x01
line.word 0x00 "SPI_RX_TX_REG0,SPI RX/TX register0"
hexmask.word 0x00 0.--15. 1. "SPI_DATA0,Write: SPI_TX_REG0 output register 0 (TX-FIFO) Read: SPI_RX_REG0 input register 0 (RX-FIFO) In 8 or 9 bits mode bits 15 to 8 are not used they contain old data"
group.word 0x04++0x01
line.word 0x00 "SPI_RX_TX_REG1,SPI RX/TX register1"
hexmask.word 0x00 0.--15. 1. "SPI_DATA1,Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO) Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO) In 8 or 9 or 16 bits mode bits this register is not used"
tree.end
tree "TMR580_NL01"
base ad:0x50003400
group.word 0x08++0x01
line.word 0x00 "PWM2_DUTY_CYCLE,Duty Cycle for PWM2"
hexmask.word 0x00 0.--13. 1. "DUTY_CYCLE,duty cycle for PWM"
group.word 0x0A++0x01
line.word 0x00 "PWM3_DUTY_CYCLE,Duty Cycle for PWM3"
hexmask.word 0x00 0.--13. 1. "DUTY_CYCLE,duty cycle for PWM"
group.word 0x0C++0x01
line.word 0x00 "PWM4_DUTY_CYCLE,Duty Cycle for PWM4"
hexmask.word 0x00 0.--13. 1. "DUTY_CYCLE,duty cycle for PWM"
group.word 0x00++0x01
line.word 0x00 "TIMER0_CTRL_REG,Timer0 control register"
bitfld.word 0x00 3. "PWM_MODE," "0,1"
bitfld.word 0x00 2. "TIM0_CLK_DIV," "0,1"
newline
bitfld.word 0x00 1. "TIM0_CLK_SEL," "0,1"
bitfld.word 0x00 0. "TIM0_CTRL," "0,1"
group.word 0x02++0x01
line.word 0x00 "TIMER0_ON_REG,Timer0 on control register"
hexmask.word 0x00 0.--15. 1. "TIM0_ON,Timer0 On reload value: If read the actual counter value ON_CNTer is returned"
group.word 0x04++0x01
line.word 0x00 "TIMER0_RELOAD_M_REG,16 bits reload value for Timer0"
hexmask.word 0x00 0.--15. 1. "TIM0_M,Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned"
group.word 0x06++0x01
line.word 0x00 "TIMER0_RELOAD_N_REG,16 bits reload value for Timer0"
hexmask.word 0x00 0.--15. 1. "TIM0_N,Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned"
group.word 0x10++0x01
line.word 0x00 "TRIPLE_PWM_CTRL_REG,PWM 2 3 4 Control"
bitfld.word 0x00 2. "HW_PAUSE_EN,'1' = HW can pause PWM 2 3 4" "0,1"
bitfld.word 0x00 1. "SW_PAUSE_EN,'1' = PWM 2 3 4 is paused" "0,1"
newline
bitfld.word 0x00 0. "TRIPLE_PWM_ENABLE,'1' = PWM 2 3 4 is enabled" "0,1"
group.word 0x0E++0x01
line.word 0x00 "TRIPLE_PWM_FREQUENCY,Frequency for PWM 2 3 and 4"
hexmask.word 0x00 0.--13. 1. "FREQ,Freq for PWM 2 3 4"
tree.end
tree "UART1"
base ad:0x50001000
group.word 0xF4++0x01
line.word 0x00 "UART_CPR_REG,Component Parameter Register"
hexmask.word 0x00 0.--15. 1. "CPR,Component Parameter Register"
group.word 0xFC++0x01
line.word 0x00 "UART_CTR_REG,Component Type Register"
hexmask.word 0x00 0.--15. 1. "CTR,Component Type Register"
group.word 0xA4++0x01
line.word 0x00 "UART_HTX_REG,Halt TX"
bitfld.word 0x00 0. "UART_HALT_TX,This register is use to halt transmissions for testing so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled" "0: Halt TX disabled,1: Halt TX enabled Note if FIFOs are implemented"
group.word 0x04++0x01
line.word 0x00 "UART_IER_DLH_REG,Interrupt Enable Register"
bitfld.word 0x00 7. "PTIME_dlh7,Interrupt Enable Register: PTIME Programmable THRE Interrupt Mode Enable" "0: disabled,1: enabled Divisor Latch"
bitfld.word 0x00 3. "EDSSI_dlh3,Interrupt Enable Register: EDSSI Enable Modem Status Interrupt" "0: disabled,1: enabled Divisor Latch"
newline
bitfld.word 0x00 2. "ELSI_dhl2,Interrupt Enable Register: ELSI Enable Receiver Line Status Interrupt" "0: disabled,1: enabled Divisor Latch"
bitfld.word 0x00 1. "ETBEI_dlh1,Interrupt Enable Register: ETBEI Enable Transmit Holding Register Empty Interrupt" "0: disabled,1: enabled Divisor Latch"
newline
bitfld.word 0x00 0. "ERBFI_dlh0,Interrupt Enable Register: ERBFI Enable Received Data Available Interrupt" "0: disabled,1: enabled Divisor Latch"
group.word 0x08++0x01
line.word 0x00 "UART_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register"
abitfld.word 0x00 0.--15. "IIR_FCR,Interrupt Identification Register reading this register FIFO Control Register writing to this register" "0x0000=0: mode 0,0x0001=1: mode 1 Bit[2] XMIT FIFO Reset (or..,0x000A=10: FIFO 1/4 full,0x000B=11: FIFO 1/2 full Bit[3] DMA Mode (or DMAM),0x0064=100: received data available,0x006E=110: receiver line status,0x006F=111: busy detect,0x044C=1100: character timeout"
group.word 0x0C++0x01
line.word 0x00 "UART_LCR_REG,Line Control Register"
bitfld.word 0x00 7. "UART_DLAB,Divisor Latch Access Bit" "0,1"
bitfld.word 0x00 6. "UART_BC,Break Control Bit" "0,1"
newline
bitfld.word 0x00 4. "UART_EPS,Even Parity Select" "0,1"
bitfld.word 0x00 3. "UART_PEN,Parity Enable" "0: parity disabled,1: parity enabled"
newline
bitfld.word 0x00 2. "UART_STOP,Number of stop bits" "0: 1 stop bit,1: 1.5 stop bits when DLS"
bitfld.word 0x00 0.--1. "UART_DLS,Data Length Select" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.word 0x24++0x01
line.word 0x00 "UART_LPDLH_REG,Low Power Divisor Latch High"
hexmask.word.byte 0x00 0.--7. 1. "UART_LPDLH,This register makes up the upper 8-bits of a 16-bit read/write Low Power Divisor Latch register that contains the baud rate divisor for the UART which must give a baud rate of 115.2K"
group.word 0x20++0x01
line.word 0x00 "UART_LPDLL_REG,Low Power Divisor Latch Low"
hexmask.word.byte 0x00 0.--7. 1. "UART_LPDLL,This register makes up the lower 8-bits of a 16-bit read/write Low Power Divisor Latch register that contains the baud rate divisor for the UART which must give a baud rate of 115.2K"
group.word 0x14++0x01
line.word 0x00 "UART_LSR_REG,Line Status Register"
rbitfld.word 0x00 7. "UART_RFE,Receiver FIFO Error bit" "0: no error in RX FIFO,1: error in RX FIFO This bit is cleared when the"
rbitfld.word 0x00 6. "UART_TEMT,Transmitter Empty bit" "0,1"
newline
rbitfld.word 0x00 5. "UART_THRE,Transmit Holding Register Empty bit" "0,1"
rbitfld.word 0x00 4. "UART_B1,Break Interrupt bit" "0,1"
newline
rbitfld.word 0x00 3. "UART_FE,Framing Error bit" "0: no framing error,1: framing error Reading the LSR clears the FE bit"
rbitfld.word 0x00 2. "UART_PE,Parity Error bit" "0: no parity error,1: parity error Reading the LSR clears the PE"
newline
rbitfld.word 0x00 1. "UART_OE,Overrun error bit" "0: no overrun error,1: overrun error Reading the LSR clears the OE bit"
rbitfld.word 0x00 0. "UART_DR,Data Ready bit" "0: no data ready,1: data ready This bit is cleared when"
group.word 0x10++0x01
line.word 0x00 "UART_MCR_REG,Modem Control Register"
bitfld.word 0x00 6. "UART_SIRE,SIR Mode Enable" "0: IrDA SIR Mode disabled,1: IrDA SIR Mode enabled"
bitfld.word 0x00 5. "UART_AFCE,Auto Flow Control Enable" "0: Auto Flow Control Mode disabled,1: Auto Flow Control Mode enabled"
newline
bitfld.word 0x00 4. "UART_LB,LoopBack Bit" "0,1"
bitfld.word 0x00 3. "UART_OUT2,OUT2" "0: out2_n de-asserted (logic 1),1: out2_n asserted (logic 0) Note that in Loopback"
newline
bitfld.word 0x00 2. "UART_OUT1,OUT1" "0: out1_n de-asserted (logic 1),1: out1_n asserted (logic 0) Note that in Loopback"
bitfld.word 0x00 1. "UART_RTS,Request to Send" "0,1"
group.word 0x18++0x01
line.word 0x00 "UART_MSR_REG,Modem Status Register"
rbitfld.word 0x00 7. "UART_DCD,Data Carrier Detect" "0: dcd_n input is de-asserted (logic 1),1: dcd_n input is asserted (logic 0) In Loopback"
rbitfld.word 0x00 6. "UART_R1,Ring Indicator" "0: ri_n input is de-asserted (logic 1),1: ri_n input is asserted (logic 0) In Loopback"
newline
rbitfld.word 0x00 4. "UART_CTS,Clear to Send" "0: cts_n input is de-asserted (logic 1),1: cts_n input is asserted (logic 0) In Loopback"
rbitfld.word 0x00 3. "UART_DDCD,Delta Data Carrier Detect" "0: no change on dcd_n since last read of MSR,1: change on dcd_n since last read of MSR Reading"
newline
rbitfld.word 0x00 2. "UART_TERI,Trailing Edge of Ring Indicator" "0: no change on ri_n since last read of MSR,1: change on ri_n since last read of MSR Reading"
rbitfld.word 0x00 0. "UART_DCTS,Delta Clear to Send" "0: no change on cts_n since last read of MSR,1: change on cts_n since last read of MSR Reading"
group.word 0x00++0x01
line.word 0x00 "UART_RBR_THR_DLL_REG,Receive Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "RBR_THR_DLL,Receive Buffer Register: This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode"
group.word 0x84++0x01
line.word 0x00 "UART_RFL_REG,Receive FIFO Level"
hexmask.word 0x00 0.--15. 1. "UART_RECEIVE_FIFO_LEVEL,Receive FIFO Level"
group.word 0x90++0x01
line.word 0x00 "UART_SBCR_REG,Shadow Break Control Register"
bitfld.word 0x00 0. "UART_SHADOW_BREAK_CONTROL,Shadow Break Control Bit" "0,1"
group.word 0x1C++0x01
line.word 0x00 "UART_SCR_REG,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. "UART_SCRATCH_PAD,This register is for programmers to use as a temporary storage space"
group.word 0x94++0x01
line.word 0x00 "UART_SDMAM_REG,Shadow DMA Mode"
bitfld.word 0x00 0. "UART_SHADOW_DMA_MODE,Shadow DMA Mode" "0: mode 0,1: mode 1"
group.word 0x98++0x01
line.word 0x00 "UART_SFE_REG,Shadow FIFO Enable"
bitfld.word 0x00 0. "UART_SHADOW_FIFO_ENABLE,Shadow FIFO Enable" "0,1"
group.word 0x30++0x01
line.word 0x00 "UART_SRBR_STHR0_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x58++0x01
line.word 0x00 "UART_SRBR_STHR10_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x5C++0x01
line.word 0x00 "UART_SRBR_STHR11_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x60++0x01
line.word 0x00 "UART_SRBR_STHR12_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x64++0x01
line.word 0x00 "UART_SRBR_STHR13_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x68++0x01
line.word 0x00 "UART_SRBR_STHR14_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x6C++0x01
line.word 0x00 "UART_SRBR_STHR15_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x34++0x01
line.word 0x00 "UART_SRBR_STHR1_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x38++0x01
line.word 0x00 "UART_SRBR_STHR2_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x3C++0x01
line.word 0x00 "UART_SRBR_STHR3_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x40++0x01
line.word 0x00 "UART_SRBR_STHR4_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x44++0x01
line.word 0x00 "UART_SRBR_STHR5_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x48++0x01
line.word 0x00 "UART_SRBR_STHR6_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x4C++0x01
line.word 0x00 "UART_SRBR_STHR7_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x50++0x01
line.word 0x00 "UART_SRBR_STHR8_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x54++0x01
line.word 0x00 "UART_SRBR_STHR9_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x88++0x01
line.word 0x00 "UART_SRR_REG,Software Reset Register"
bitfld.word 0x00 2. "UART_XFR,XMIT FIFO Reset" "0,1"
bitfld.word 0x00 1. "UART_RFR,RCVR FIFO Reset" "0,1"
newline
bitfld.word 0x00 0. "UART_UR,UART Reset" "0,1"
group.word 0x8C++0x01
line.word 0x00 "UART_SRTS_REG,Shadow Request to Send"
bitfld.word 0x00 0. "UART_SHADOW_REQUEST_TO_SEND,Shadow Request to Send" "0,1"
group.word 0x9C++0x01
line.word 0x00 "UART_SRT_REG,Shadow RCVR Trigger"
bitfld.word 0x00 0.--1. "UART_SHADOW_RCVR_TRIGGER,Shadow RCVR Trigger" "0: 1 character in the FIFO,1: FIFO ?? full,2: FIFO ?? full,3: FIFO 2 less than full"
group.word 0xA0++0x01
line.word 0x00 "UART_STET_REG,Shadow TX Empty Trigger"
bitfld.word 0x00 0.--1. "UART_SHADOW_TX_EMPTY_TRIGGER,Shadow TX Empty Trigger" "0: FIFO empty,1: 2 characters in the FIFO,2: FIFO ?? full,3: FIFO ?? full"
group.word 0x80++0x01
line.word 0x00 "UART_TFL_REG,Transmit FIFO Level"
hexmask.word 0x00 0.--15. 1. "UART_TRANSMIT_FIFO_LEVEL,Transmit FIFO Level"
group.word 0xF8++0x01
line.word 0x00 "UART_UCV_REG,Component Version"
hexmask.word 0x00 0.--15. 1. "UCV,Component Version"
group.word 0x7C++0x01
line.word 0x00 "UART_USR_REG,UART Status register"
rbitfld.word 0x00 4. "UART_RFF,Receive FIFO Full" "0: Receive FIFO not full,1: Receive FIFO Full This bit is cleared when the"
rbitfld.word 0x00 3. "UART_RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty This bit is cleared"
newline
rbitfld.word 0x00 2. "UART_TFE,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty This bit is cleared when"
rbitfld.word 0x00 1. "UART_TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full This bit is cleared"
tree.end
tree "UART2"
base ad:0x50001100
group.word 0xF4++0x01
line.word 0x00 "UART2_CPR_REG,Component Parameter Register"
hexmask.word 0x00 0.--15. 1. "CPR,Component Parameter Register"
group.word 0xFC++0x01
line.word 0x00 "UART2_CTR_REG,Component Type Register"
hexmask.word 0x00 0.--15. 1. "CTR,Component Type Register"
group.word 0xA4++0x01
line.word 0x00 "UART2_HTX_REG,Halt TX"
bitfld.word 0x00 0. "UART_HALT_TX,This register is use to halt transmissions for testing so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled" "0: Halt TX disabled,1: Halt TX enabled Note if FIFOs are implemented"
group.word 0x04++0x01
line.word 0x00 "UART2_IER_DLH_REG,Interrupt Enable Register"
bitfld.word 0x00 7. "PTIME_dlh7,Interrupt Enable Register: PTIME Programmable THRE Interrupt Mode Enable" "0: disabled,1: enabled Divisor Latch"
bitfld.word 0x00 3. "EDSSI_dlh3,Interrupt Enable Register: EDSSI Enable Modem Status Interrupt" "0: disabled,1: enabled Divisor Latch"
newline
bitfld.word 0x00 2. "ELSI_dhl2,Interrupt Enable Register: ELSI Enable Receiver Line Status Interrupt" "0: disabled,1: enabled Divisor Latch"
bitfld.word 0x00 1. "ETBEI_dlh1,Interrupt Enable Register: ETBEI Enable Transmit Holding Register Empty Interrupt" "0: disabled,1: enabled Divisor Latch"
newline
bitfld.word 0x00 0. "ERBFI_dlh0,Interrupt Enable Register: ERBFI Enable Received Data Available Interrupt" "0: disabled,1: enabled Divisor Latch"
group.word 0x08++0x01
line.word 0x00 "UART2_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register"
abitfld.word 0x00 0.--15. "IIR_FCR,Interrupt Identification Register reading this register FIFO Control Register writing to this register" "0x0000=0: mode 0,0x0001=1: mode 1 Bit[2] XMIT FIFO Reset (or..,0x000A=10: FIFO 1/4 full,0x000B=11: FIFO 1/2 full Bit[3] DMA Mode (or DMAM),0x0064=100: received data available,0x006E=110: receiver line status,0x006F=111: busy detect,0x044C=1100: character timeout"
group.word 0x0C++0x01
line.word 0x00 "UART2_LCR_REG,Line Control Register"
bitfld.word 0x00 7. "UART_DLAB,Divisor Latch Access Bit" "0,1"
bitfld.word 0x00 6. "UART_BC,Break Control Bit" "0,1"
newline
bitfld.word 0x00 4. "UART_EPS,Even Parity Select" "0,1"
bitfld.word 0x00 3. "UART_PEN,Parity Enable" "0: parity disabled,1: parity enabled"
newline
bitfld.word 0x00 2. "UART_STOP,Number of stop bits" "0: 1 stop bit,1: 1.5 stop bits when DLS"
bitfld.word 0x00 0.--1. "UART_DLS,Data Length Select" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.word 0x24++0x01
line.word 0x00 "UART2_LPDLH_REG,Low Power Divisor Latch High"
hexmask.word.byte 0x00 0.--7. 1. "UART_LPDLH,This register makes up the upper 8-bits of a 16-bit read/write Low Power Divisor Latch register that contains the baud rate divisor for the UART which must give a baud rate of 115.2K"
group.word 0x20++0x01
line.word 0x00 "UART2_LPDLL_REG,Low Power Divisor Latch Low"
hexmask.word.byte 0x00 0.--7. 1. "UART_LPDLL,This register makes up the lower 8-bits of a 16-bit read/write Low Power Divisor Latch register that contains the baud rate divisor for the UART which must give a baud rate of 115.2K"
group.word 0x14++0x01
line.word 0x00 "UART2_LSR_REG,Line Status Register"
rbitfld.word 0x00 7. "UART_RFE,Receiver FIFO Error bit" "0: no error in RX FIFO,1: error in RX FIFO This bit is cleared when the"
rbitfld.word 0x00 6. "UART_TEMT,Transmitter Empty bit" "0,1"
newline
rbitfld.word 0x00 5. "UART_THRE,Transmit Holding Register Empty bit" "0,1"
rbitfld.word 0x00 4. "UART_B1,Break Interrupt bit" "0,1"
newline
rbitfld.word 0x00 3. "UART_FE,Framing Error bit" "0: no framing error,1: framing error Reading the LSR clears the FE bit"
rbitfld.word 0x00 2. "UART_PE,Parity Error bit" "0: no parity error,1: parity error Reading the LSR clears the PE"
newline
rbitfld.word 0x00 1. "UART_OE,Overrun error bit" "0: no overrun error,1: overrun error Reading the LSR clears the OE bit"
rbitfld.word 0x00 0. "UART_DR,Data Ready bit" "0: no data ready,1: data ready This bit is cleared when"
group.word 0x10++0x01
line.word 0x00 "UART2_MCR_REG,Modem Control Register"
bitfld.word 0x00 6. "UART_SIRE,SIR Mode Enable" "0: IrDA SIR Mode disabled \n,1: IrDA SIR Mode enabled"
bitfld.word 0x00 5. "UART_AFCE,Auto Flow Control Enable" "0: Auto Flow Control Mode disabled,1: Auto Flow Control Mode enabled"
newline
bitfld.word 0x00 4. "UART_LB,LoopBack Bit" "0,1"
bitfld.word 0x00 3. "UART_OUT2,OUT2" "0: out2_n de-asserted (logic 1),1: out2_n asserted (logic 0) Note that in Loopback"
newline
bitfld.word 0x00 2. "UART_OUT1,OUT1" "0: out1_n de-asserted (logic 1),1: out1_n asserted (logic 0) Note that in Loopback"
bitfld.word 0x00 1. "UART_RTS,Request to Send" "0,1"
group.word 0x18++0x01
line.word 0x00 "UART2_MSR_REG,Modem Status Register"
rbitfld.word 0x00 7. "UART_DCD,Data Carrier Detect" "0: dcd_n input is de-asserted (logic 1),1: dcd_n input is asserted (logic 0) In Loopback"
rbitfld.word 0x00 6. "UART_R1,Ring Indicator" "0: ri_n input is de-asserted (logic 1),1: ri_n input is asserted (logic 0) In Loopback"
newline
rbitfld.word 0x00 4. "UART_CTS,Clear to Send" "0: cts_n input is de-asserted (logic 1),1: cts_n input is asserted (logic 0) In Loopback"
rbitfld.word 0x00 3. "UART_DDCD,Delta Data Carrier Detect" "0: no change on dcd_n since last read of MSR,1: change on dcd_n since last read of MSR Reading"
newline
rbitfld.word 0x00 2. "UART_TERI,Trailing Edge of Ring Indicator" "0: no change on ri_n since last read of MSR,1: change on ri_n since last read of MSR Reading"
rbitfld.word 0x00 0. "UART_DCTS,Delta Clear to Send" "0: no change on cts_n since last read of MSR,1: change on cts_n since last read of MSR Reading"
group.word 0x00++0x01
line.word 0x00 "UART2_RBR_THR_DLL_REG,Receive Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "RBR_THR_DLL,Receive Buffer Register: This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode"
group.word 0x84++0x01
line.word 0x00 "UART2_RFL_REG,Receive FIFO Level"
hexmask.word 0x00 0.--15. 1. "UART_RECEIVE_FIFO_LEVEL,Receive FIFO Level"
group.word 0x90++0x01
line.word 0x00 "UART2_SBCR_REG,Shadow Break Control Register"
bitfld.word 0x00 0. "UART_SHADOW_BREAK_CONTROL,Shadow Break Control Bit" "0,1"
group.word 0x1C++0x01
line.word 0x00 "UART2_SCR_REG,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. "UART_SCRATCH_PAD,This register is for programmers to use as a temporary storage space"
group.word 0x94++0x01
line.word 0x00 "UART2_SDMAM_REG,Shadow DMA Mode"
bitfld.word 0x00 0. "UART_SHADOW_DMA_MODE,Shadow DMA Mode" "0: mode 0,1: mode 1"
group.word 0x98++0x01
line.word 0x00 "UART2_SFE_REG,Shadow FIFO Enable"
bitfld.word 0x00 0. "UART_SHADOW_FIFO_ENABLE,Shadow FIFO Enable" "0,1"
group.word 0x30++0x01
line.word 0x00 "UART2_SRBR_STHR0_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x58++0x01
line.word 0x00 "UART2_SRBR_STHR10_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x5C++0x01
line.word 0x00 "UART2_SRBR_STHR11_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x60++0x01
line.word 0x00 "UART2_SRBR_STHR12_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x64++0x01
line.word 0x00 "UART2_SRBR_STHR13_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x68++0x01
line.word 0x00 "UART2_SRBR_STHR14_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x6C++0x01
line.word 0x00 "UART2_SRBR_STHR15_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x34++0x01
line.word 0x00 "UART2_SRBR_STHR1_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x38++0x01
line.word 0x00 "UART2_SRBR_STHR2_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x3C++0x01
line.word 0x00 "UART2_SRBR_STHR3_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x40++0x01
line.word 0x00 "UART2_SRBR_STHR4_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x44++0x01
line.word 0x00 "UART2_SRBR_STHR5_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x48++0x01
line.word 0x00 "UART2_SRBR_STHR6_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x4C++0x01
line.word 0x00 "UART2_SRBR_STHR7_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x50++0x01
line.word 0x00 "UART2_SRBR_STHR8_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x54++0x01
line.word 0x00 "UART2_SRBR_STHR9_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. "SRBR_STHRx,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master"
group.word 0x88++0x01
line.word 0x00 "UART2_SRR_REG,Software Reset Register"
bitfld.word 0x00 2. "UART_XFR,XMIT FIFO Reset" "0,1"
bitfld.word 0x00 1. "UART_RFR,RCVR FIFO Reset" "0,1"
newline
bitfld.word 0x00 0. "UART_UR,UART Reset" "0,1"
group.word 0x8C++0x01
line.word 0x00 "UART2_SRTS_REG,Shadow Request to Send"
bitfld.word 0x00 0. "UART_SHADOW_REQUEST_TO_SEND,Shadow Request to Send" "0,1"
group.word 0x9C++0x01
line.word 0x00 "UART2_SRT_REG,Shadow RCVR Trigger"
bitfld.word 0x00 0.--1. "UART_SHADOW_RCVR_TRIGGER,Shadow RCVR Trigger" "0: 1 character in the FIFO,1: FIFO ?? full,2: FIFO ?? full,3: FIFO 2 less than full"
group.word 0xA0++0x01
line.word 0x00 "UART2_STET_REG,Shadow TX Empty Trigger"
bitfld.word 0x00 0.--1. "UART_SHADOW_TX_EMPTY_TRIGGER,Shadow TX Empty Trigger" "0: FIFO empty,1: 2 characters in the FIFO,2: FIFO ?? full,3: FIFO ?? full"
group.word 0x80++0x01
line.word 0x00 "UART2_TFL_REG,Transmit FIFO Level"
hexmask.word 0x00 0.--15. 1. "UART_TRANSMIT_FIFO_LEVEL,Transmit FIFO Level"
group.word 0xF8++0x01
line.word 0x00 "UART2_UCV_REG,Component Version"
hexmask.word 0x00 0.--15. 1. "UCV,Component Version"
group.word 0x7C++0x01
line.word 0x00 "UART2_USR_REG,UART Status register"
rbitfld.word 0x00 4. "UART_RFF,Receive FIFO Full" "0: Receive FIFO not full,1: Receive FIFO Full This bit is cleared when the"
rbitfld.word 0x00 3. "UART_RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty This bit is cleared"
newline
rbitfld.word 0x00 2. "UART_TFE,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty This bit is cleared when"
rbitfld.word 0x00 1. "UART_TFNF,Transmit FIFO Not Full" "0: Transmit FIFO is full,1: Transmit FIFO is not full This bit is cleared"
tree.end
tree "WKUP580_NL01"
base ad:0x50000100
group.word 0x02++0x01
line.word 0x00 "WKUP_COMPARE_REG,Number of events before wakeup interrupt"
hexmask.word.byte 0x00 0.--7. 1. "COMPARE,The number of events that have to be counted before the wakeup interrupt will be given"
group.word 0x06++0x01
line.word 0x00 "WKUP_COUNTER_REG,Actual number of events of the wakeup counter"
hexmask.word.byte 0x00 0.--7. 1. "EVENT_VALUE,This value represents the number of events that have been counted so far"
group.word 0x00++0x01
line.word 0x00 "WKUP_CTRL_REG,Control register for the wakeup counter"
bitfld.word 0x00 7. "WKUP_ENABLE_IRQ," "0,1"
bitfld.word 0x00 6. "WKUP_SFT_KEYHIT," "0,1"
newline
bitfld.word 0x00 0.--5. "WKUP_DEB_VALUE,Keyboard debounce time (N*1 ms with N = 1 to 63)" "0: no debouncing 0x1 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: 1 ms to 63 ms debounce time"
group.word 0x12++0x01
line.word 0x00 "WKUP_POL_P0_REG,Select the sensitivity polarity for each P0 input"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_POL_P0,"
group.word 0x14++0x01
line.word 0x00 "WKUP_POL_P1_REG,Select the sensitivity polarity for each P1 input"
bitfld.word 0x00 0.--5. "WKUP_POL_P1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x16++0x01
line.word 0x00 "WKUP_POL_P2_REG,Select the sensitivity polarity for each P2 input"
hexmask.word 0x00 0.--9. 1. "WKUP_POL_P2,"
group.word 0x18++0x01
line.word 0x00 "WKUP_POL_P3_REG,Select the sensitivity polarity for each P3 input"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_POL_P3,"
group.word 0x08++0x01
line.word 0x00 "WKUP_RESET_CNTR_REG,Reset the event counter"
hexmask.word 0x00 0.--15. 1. "WKUP_CNTR_RST,writing any value to this register will reset the event counter"
group.word 0x04++0x01
line.word 0x00 "WKUP_RESET_IRQ_REG,Reset wakeup interrupt"
hexmask.word 0x00 0.--15. 1. "WKUP_IRQ_RST,writing any value to this register will reset the interrupt"
group.word 0x0A++0x01
line.word 0x00 "WKUP_SELECT_P0_REG,Select which inputs from P0 port can trigger wkup counter"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_SELECT_P0,"
group.word 0x0C++0x01
line.word 0x00 "WKUP_SELECT_P1_REG,Select which inputs from P1 port can trigger wkup counter"
bitfld.word 0x00 0.--5. "WKUP_SELECT_P1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x0E++0x01
line.word 0x00 "WKUP_SELECT_P2_REG,Select which inputs from P2 port can trigger wkup counter"
hexmask.word 0x00 0.--9. 1. "WKUP_SELECT_P2,"
group.word 0x10++0x01
line.word 0x00 "WKUP_SELECT_P3_REG,Select which inputs from P3 port can trigger wkup counter"
hexmask.word.byte 0x00 0.--7. 1. "WKUP_SELECT_P3,"
tree.end
tree.end
tree "SCB_GROUP (Cortex M0 SCB registers)"
base ad:0xE000ED00
group.long 0x00++0x03
line.long 0x00 "CPUID,CPUID base register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,IMPLEMENTER[7:0] bits (Implementer code)"
rbitfld.long 0x00 20.--23. "VARIANT,VARIANT[3:0] bits (Variant number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "CONSTANT,CONSTANT[3:0] bits (Reads as 0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "PARTNO,PARTNO[11:0] bits (Part number of the processor core)"
newline
rbitfld.long 0x00 0.--3. "REVISION,REVISION[3:0] bits (Revision number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "ICSR,Interrupt control and state register"
bitfld.long 0x00 31. "NMIPENDSET,NMI set-pending bit" "0,1"
bitfld.long 0x00 28. "PENDSVSET,PendSV set-pending bit" "0,1"
newline
bitfld.long 0x00 27. "PENDSVCLR,PendSV clear-pending bit" "0,1"
bitfld.long 0x00 26. "PENDSTSET,SysTick exception set-pending bit" "0,1"
newline
bitfld.long 0x00 25. "PENDSTCLR,SysTick exception clear-pending bit" "0,1"
bitfld.long 0x00 22. "ISRPENDING,Interrupt pending flag excluding NMI and Faults" "0,1"
newline
bitfld.long 0x00 12.--17. "VECTPENDING,VECTPENDING[5:0] bits (Pending vector)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "VECTACTIVE,VECTACTIVE[5:0] bits (Active vector)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x0C++0x03
line.long 0x00 "AIRCR,Application interrupt and reset control register"
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,VECTKEY[15:0] bits (Register key)"
bitfld.long 0x00 15. "ENDIANESS,Data endianness bit" "0,1"
newline
bitfld.long 0x00 2. "SYSRESETREQ,System reset request" "0,1"
bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for Debug use" "0,1"
newline
bitfld.long 0x00 0. "VECTRESET,Reserved for Debug use" "0,1"
group.long 0x10++0x03
line.long 0x00 "SCR,System control register"
bitfld.long 0x00 4. "SEVEONPEND,Send event on pending bit" "0,1"
bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep" "0,1"
newline
bitfld.long 0x00 1. "SLEEPONEXIT,Configures sleep-on-exit when returning from Handler mode to Thread mode" "0,1"
group.long 0x14++0x03
line.long 0x00 "CCR,Configuration and control register"
bitfld.long 0x00 9. "STKALIGN,Configures stack alignment on exception entry" "0,1"
bitfld.long 0x00 3. "UNALIGN_TRP,Enables unaligned access traps" "0,1"
group.long 0x1C++0x03
line.long 0x00 "SHPR2,System handler priority register 2"
hexmask.long.byte 0x00 24.--31. 1. "PRI_11,PRI_11[7:0] bits (Priority of system handler 11 SVCall)"
group.long 0x20++0x03
line.long 0x00 "SHPR3,System handler priority register 3"
hexmask.long.byte 0x00 24.--31. 1. "PRI_15,PRI_15[7:0] bits (Priority of system handler 15 SysTick exception)"
hexmask.long.byte 0x00 16.--23. 1. "PRI_14,PRI_14[7:0] bits (Priority of system handler 14 PendSV)"
tree.end
tree "SYSTICK (Cortex M0 SysTick registers)"
base ad:0xE000E010
group.long 0x00++0x03
line.long 0x00 "CTRL,SysTick Control and Status register"
bitfld.long 0x00 16. "COUNTFLAG,Timer counted to 0 since last time this was" "0,1"
bitfld.long 0x00 2. "CLKSOURCE,Clock source selection" "0,1"
newline
bitfld.long 0x00 1. "TICKINT,SysTick exception request enable" "0,1"
bitfld.long 0x00 0. "ENABLE,SysTick Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "LOAD,SysTick Reload value register"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,RELOAD[23:0] bits (Reload value)"
group.long 0x08++0x03
line.long 0x00 "VAL,SysTick Current value register"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,CURRENT[23:0] bits (Current counter value)"
rgroup.long 0x0C++0x03
line.long 0x00 "CALIB,SysTick Calibration value register"
bitfld.long 0x00 31. "NOREF,Indicates that a separate reference clock is provided" "0,1"
bitfld.long 0x00 30. "SKEW,Indicates whether the TENMS value is exact" "0,1"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,TENMS[23:0] bits (Calibration value)"
tree.end
autoindent.off
newline
Reference in New Issue View Git Blame Copy Permalink