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Gen4_R-Car_Trace32/2_Trunk/perda1453x.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: DA1453x On-Chip Peripherals
; @Props: Released
; @Author: KWI
; @Changelog: 2020-12-09 KWI
; @Manufacturer: Dialog Semiconductor
; @Doc: SVD generated based on DA14531.svd
; @Core: Cortex-M0P
; @Chip: DA14530, DA14531
; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perda1453x.per 12787 2021-01-21 17:45:52Z bwright $
config 16. 8.
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "NVIC (Cortex M0 NVIC registers)"
base ad:0xE000E100
width 6.
group.long 0x00++0x03
line.long 0x00 "ISER,Interrupt set-enable register"
bitfld.long 0x00 31. " Rsvd__irq__n ,Rsvd__irq__n (Reserved)" "0,1"
bitfld.long 0x00 30. " XTAL16RDY_IRQn ,XTAL16RDY_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 29. " DCDC_IRQn ,DCDC_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 28. " TRNG_IRQn ,TRNG_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 27. " RF_DIAG_IRQn ,RF_DIAG_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 26. " DMA_IRQn ,DMA_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 25. " VBUS_IRQn ,VBUS_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 24. " SRC_OUT_IRQn ,SRC_OUT_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 23. " SRC_IN_IRQn ,SRC_IN_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 22. " PCM_IRQn ,PCM_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 21. " USB_IRQn ,USB_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 20. " QUADEC_IRQn ,QUADEC_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 19. " SWTIM1_IRQn ,SWTIM1_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 18. " SWTIM0_IRQn ,SWTIM0_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 17. " WKUP_GPIO_IRQn ,WKUP_GPIO_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 16. " IRGEN_IRQn ,IRGEN_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 15. " KEYBRD_IRQn ,KEYBRD_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 14. " ADC_IRQn ,ADC_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 13. " SPI2_IRQn ,SPI2_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 12. " SPI_IRQn ,SPI_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 11. " I2C2_IRQn ,I2C2_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 10. " I2C_IRQn ,I2C_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 9. " UART2_IRQn ,UART2_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 8. " UART_IRQn ,UART_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 7. " MRM_IRQn ,MRM_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 6. " CRYPTO_IRQn ,CRYPTO_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 5. " COEX_IRQn ,COEX_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 4. " RFCAL_IRQn ,RFCAL_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 3. " FTDF_GEN_IRQn ,FTDF_GEN_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 2. " FTDF_WAKEUP_IRQn ,FTDF_WAKEUP_IRQn (Interrupt set-enable bit)" "0,1"
newline
bitfld.long 0x00 1. " BLE_GEN_IRQn ,BLE_GEN_IRQn (Interrupt set-enable bit)" "0,1"
bitfld.long 0x00 0. " BLE_WAKEUP_LP_IRQn ,BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit)" "0,1"
group.long 0x80++0x03
line.long 0x00 "ICER,Interrupt clear-enable register"
bitfld.long 0x00 31. " Rsvd__irq__n ,Rsvd__irq__n (Reserved)" "0,1"
bitfld.long 0x00 30. " XTAL16RDY_IRQn ,XTAL16RDY_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 29. " DCDC_IRQn ,DCDC_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 28. " TRNG_IRQn ,TRNG_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 27. " RF_DIAG_IRQn ,RF_DIAG_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 26. " DMA_IRQn ,DMA_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 25. " VBUS_IRQn ,VBUS_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 24. " SRC_OUT_IRQn ,SRC_OUT_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 23. " SRC_IN_IRQn ,SRC_IN_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 22. " PCM_IRQn ,PCM_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 21. " USB_IRQn ,USB_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 20. " QUADEC_IRQn ,QUADEC_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 19. " SWTIM1_IRQn ,SWTIM1_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 18. " SWTIM0_IRQn ,SWTIM0_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 17. " WKUP_GPIO_IRQn ,WKUP_GPIO_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 16. " IRGEN_IRQn ,IRGEN_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 15. " KEYBRD_IRQn ,KEYBRD_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 14. " ADC_IRQn ,ADC_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 13. " SPI2_IRQn ,SPI2_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 12. " SPI_IRQn ,SPI_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 11. " I2C2_IRQn ,I2C2_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 10. " I2C_IRQn ,I2C_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 9. " UART2_IRQn ,UART2_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 8. " UART_IRQn ,UART_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 7. " MRM_IRQn ,MRM_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 6. " CRYPTO_IRQn ,CRYPTO_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 5. " COEX_IRQn ,COEX_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 4. " RFCAL_IRQn ,RFCAL_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 3. " FTDF_GEN_IRQn ,FTDF_GEN_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 2. " FTDF_WAKEUP_IRQn ,FTDF_WAKEUP_IRQn (Interrupt clear-enable bit)" "0,1"
newline
bitfld.long 0x00 1. " BLE_GEN_IRQn ,BLE_GEN_IRQn (Interrupt clear-enable bit)" "0,1"
bitfld.long 0x00 0. " BLE_WAKEUP_LP_IRQn ,BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit)" "0,1"
group.long 0x100++0x03
line.long 0x00 "ISPR,Interrupt set-pending register"
bitfld.long 0x00 31. " Rsvd__irq__n ,Rsvd__irq__n (Reserved)" "0,1"
bitfld.long 0x00 30. " XTAL16RDY_IRQn ,XTAL16RDY_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 29. " DCDC_IRQn ,DCDC_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 28. " TRNG_IRQn ,TRNG_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 27. " RF_DIAG_IRQn ,RF_DIAG_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 26. " DMA_IRQn ,DMA_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 25. " VBUS_IRQn ,VBUS_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 24. " SRC_OUT_IRQn ,SRC_OUT_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 23. " SRC_IN_IRQn ,SRC_IN_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 22. " PCM_IRQn ,PCM_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 21. " USB_IRQn ,USB_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 20. " QUADEC_IRQn ,QUADEC_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 19. " SWTIM1_IRQn ,SWTIM1_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 18. " SWTIM0_IRQn ,SWTIM0_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 17. " WKUP_GPIO_IRQn ,WKUP_GPIO_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 16. " IRGEN_IRQn ,IRGEN_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 15. " KEYBRD_IRQn ,KEYBRD_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 14. " ADC_IRQn ,ADC_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 13. " SPI2_IRQn ,SPI2_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 12. " SPI_IRQn ,SPI_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 11. " I2C2_IRQn ,I2C2_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 10. " I2C_IRQn ,I2C_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 9. " UART2_IRQn ,UART2_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 8. " UART_IRQn ,UART_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 7. " MRM_IRQn ,MRM_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 6. " CRYPTO_IRQn ,CRYPTO_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 5. " COEX_IRQn ,COEX_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 4. " RFCAL_IRQn ,RFCAL_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 3. " FTDF_GEN_IRQn ,FTDF_GEN_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 2. " FTDF_WAKEUP_IRQn ,FTDF_WAKEUP_IRQn (Interrupt set-pending bit)" "0,1"
newline
bitfld.long 0x00 1. " BLE_GEN_IRQn ,BLE_GEN_IRQn (Interrupt set-pending bit)" "0,1"
bitfld.long 0x00 0. " BLE_WAKEUP_LP_IRQn ,BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit)" "0,1"
group.long 0x180++0x03
line.long 0x00 "ICPR,Interrupt clear-pending register"
bitfld.long 0x00 31. " Rsvd__irq__n ,Rsvd__irq__n (Reserved)" "0,1"
bitfld.long 0x00 30. " XTAL16RDY_IRQn ,XTAL16RDY_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 29. " DCDC_IRQn ,DCDC_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 28. " TRNG_IRQn ,TRNG_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 27. " RF_DIAG_IRQn ,RF_DIAG_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 26. " DMA_IRQn ,DMA_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 25. " VBUS_IRQn ,VBUS_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 24. " SRC_OUT_IRQn ,SRC_OUT_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 23. " SRC_IN_IRQn ,SRC_IN_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 22. " PCM_IRQn ,PCM_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 21. " USB_IRQn ,USB_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 20. " QUADEC_IRQn ,QUADEC_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 19. " SWTIM1_IRQn ,SWTIM1_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 18. " SWTIM0_IRQn ,SWTIM0_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 17. " WKUP_GPIO_IRQn ,WKUP_GPIO_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 16. " IRGEN_IRQn ,IRGEN_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 15. " KEYBRD_IRQn ,KEYBRD_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 14. " ADC_IRQn ,ADC_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 13. " SPI2_IRQn ,SPI2_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 12. " SPI_IRQn ,SPI_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 11. " I2C2_IRQn ,I2C2_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 10. " I2C_IRQn ,I2C_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 9. " UART2_IRQn ,UART2_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 8. " UART_IRQn ,UART_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 7. " MRM_IRQn ,MRM_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 6. " CRYPTO_IRQn ,CRYPTO_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 5. " COEX_IRQn ,COEX_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 4. " RFCAL_IRQn ,RFCAL_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 3. " FTDF_GEN_IRQn ,FTDF_GEN_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 2. " FTDF_WAKEUP_IRQn ,FTDF_WAKEUP_IRQn (Interrupt clear-pending bit)" "0,1"
newline
bitfld.long 0x00 1. " BLE_GEN_IRQn ,BLE_GEN_IRQn (Interrupt clear-pending bit)" "0,1"
bitfld.long 0x00 0. " BLE_WAKEUP_LP_IRQn ,BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit)" "0,1"
group.long 0x300++0x03
line.long 0x00 "IPR0,Interrupt priority register 0"
hexmask.long.byte 0x00 24.--31. 1. " FTDF_GEN_IRQn_prio ,FTDF_GEN_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. " FTDF_WAKEUP_IRQn_prio ,FTDF_WAKEUP_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 8.--15. 1. " BLE_GEN_IRQn_prio ,BLE_GEN_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 0.--7. 1. " BLE_WAKEUP_LP_IRQn_prio ,BLE_WAKEUP_LP_IRQn[7:0] bits (Interrupt priority)"
group.long 0x304++0x03
line.long 0x00 "IPR1,Interrupt priority register 1"
hexmask.long.byte 0x00 24.--31. 1. " MRM_IRQn_prio ,MRM_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. " CRYPTO_IRQn_prio ,CRYPTO_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 8.--15. 1. " COEX_IRQn_prio ,COEX_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 0.--7. 1. " RFCAL_IRQn_prio ,RFCAL_IRQn[7:0] bits (Interrupt priority)"
group.long 0x308++0x03
line.long 0x00 "IPR2,Interrupt priority register 2"
hexmask.long.byte 0x00 24.--31. 1. " I2C2_IRQn_prio ,I2C2_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. " I2C_IRQn_prio ,I2C_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 8.--15. 1. " UART2_IRQn_prio ,UART2_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 0.--7. 1. " UART_IRQn_prio ,UART_IRQn[7:0] bits (Interrupt priority)"
group.long 0x30C++0x03
line.long 0x00 "IPR3,Interrupt priority register 3"
hexmask.long.byte 0x00 24.--31. 1. " KEYBRD_IRQn_prio ,KEYBRD_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. " ADC_IRQn_prio ,ADC_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 8.--15. 1. " SPI2_IRQn_prio ,SPI2_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 0.--7. 1. " SPI_IRQn_prio ,SPI_IRQn[7:0] bits (Interrupt priority)"
group.long 0x310++0x03
line.long 0x00 "IPR4,Interrupt priority register 4"
hexmask.long.byte 0x00 24.--31. 1. " SWTIM1_IRQn_prio ,SWTIM1_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. " SWTIM0_IRQn_prio ,SWTIM0_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 8.--15. 1. " WKUP_GPIO_IRQn_prio ,WKUP_GPIO_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 0.--7. 1. " IRGEN_IRQn_prio ,IRGEN_IRQn[7:0] bits (Interrupt priority)"
group.long 0x314++0x03
line.long 0x00 "IPR5,Interrupt priority register 5"
hexmask.long.byte 0x00 24.--31. 1. " SRC_IN_IRQn_prio ,SRC_IN_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. " PCM_IRQn_prio ,PCM_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 8.--15. 1. " USB_IRQn_prio ,USB_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 0.--7. 1. " QUADEC_IRQn_prio ,QUADEC_IRQn[7:0] bits (Interrupt priority)"
group.long 0x318++0x03
line.long 0x00 "IPR6,Interrupt priority register 6"
hexmask.long.byte 0x00 24.--31. 1. " RF_DIAG_IRQn_prio ,RF_DIAG_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 16.--23. 1. " DMA_IRQn_prio ,DMA_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 8.--15. 1. " VBUS_IRQn_prio ,VBUS_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 0.--7. 1. " SRC_OUT_IRQn_prio ,SRC_OUT_IRQn[7:0] bits (Interrupt priority)"
group.long 0x31C++0x03
line.long 0x00 "IPR7,Interrupt priority register 7"
hexmask.long.byte 0x00 24.--31. 1. " RESERVED31_IRQn_DONT_USE ,RESERVED31_IRQn[7:0] bits (Reserved)"
hexmask.long.byte 0x00 16.--23. 1. " XTAL16RDY_IRQn_prio ,XTAL16RDY_IRQn[7:0] bits (Interrupt priority)"
hexmask.long.byte 0x00 8.--15. 1. " DCDC_IRQn_prio ,DCDC_IRQn[7:0] bits (Interrupt priority)"
newline
hexmask.long.byte 0x00 0.--7. 1. " TRNG_IRQn_prio ,TRNG_IRQn[7:0] bits (Interrupt priority)"
width 0x0B
tree.end
tree "SCB (Cortex M0 SCB registers)"
base ad:0xE000ED00
width 7.
group.long 0x00++0x03
line.long 0x00 "CPUID,CPUID base register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,IMPLEMENTER[7:0] bits (Implementer code)"
rbitfld.long 0x00 20.--23. " VARIANT ,VARIANT[3:0] bits (Variant number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 16.--19. " CONSTANT ,CONSTANT[3:0] bits (Reads as 0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,PARTNO[11:0] bits (Part number of the processor core)"
rbitfld.long 0x00 0.--3. " REVISION ,REVISION[3:0] bits (Revision number)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "ICSR,Interrupt control and state register"
bitfld.long 0x00 31. " NMIPENDSET ,NMI set-pending bit" "0,1"
bitfld.long 0x00 28. " PENDSVSET ,PendSV set-pending bit" "0,1"
bitfld.long 0x00 27. " PENDSVCLR ,PendSV clear-pending bit" "0,1"
newline
bitfld.long 0x00 26. " PENDSTSET ,SysTick exception set-pending bit" "0,1"
bitfld.long 0x00 25. " PENDSTCLR ,SysTick exception clear-pending bit" "0,1"
bitfld.long 0x00 22. " ISRPENDING ,Interrupt pending flag. excluding NMI and Faults" "0,1"
newline
bitfld.long 0x00 12.--17. " VECTPENDING ,VECTPENDING[5:0] bits (Pending vector)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. " VECTACTIVE ,VECTACTIVE[5:0] bits (Active vector)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x0C++0x03
line.long 0x00 "AIRCR,Application interrupt and reset control register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,VECTKEY[15:0] bits (Register key)"
bitfld.long 0x00 15. " ENDIANESS ,Data endianness bit" "0,1"
bitfld.long 0x00 2. " SYSRESETREQ ,System reset request" "0,1"
newline
bitfld.long 0x00 1. " VECTCLRACTIVE ,Reserved for Debug use" "0,1"
bitfld.long 0x00 0. " VECTRESET ,Reserved for Debug use" "0,1"
group.long 0x10++0x03
line.long 0x00 "SCR,System control register"
bitfld.long 0x00 4. " SEVEONPEND ,Send event on pending bit" "0,1"
bitfld.long 0x00 2. " SLEEPDEEP ,Controls whether the processor uses sleep or deep sleep" "0,1"
bitfld.long 0x00 1. " SLEEPONEXIT ,Configures sleep-on-exit when returning from Handler mode to Thread mode" "0,1"
group.long 0x14++0x03
line.long 0x00 "CCR,Configuration and control register"
bitfld.long 0x00 9. " STKALIGN ,Configures stack alignment on exception entry" "0,1"
bitfld.long 0x00 3. " UNALIGN_TRP ,Enables unaligned access traps" "0,1"
group.long 0x1C++0x03
line.long 0x00 "SHPR2,System handler priority register 2"
hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,PRI_11[7:0] bits (Priority of system handler 11. SVCall)"
group.long 0x20++0x03
line.long 0x00 "SHPR3,System handler priority register 3"
hexmask.long.byte 0x00 24.--31. 1. " PRI_15 ,PRI_15[7:0] bits (Priority of system handler 15. SysTick exception)"
hexmask.long.byte 0x00 16.--23. 1. " PRI_14 ,PRI_14[7:0] bits (Priority of system handler 14. PendSV)"
width 0x0B
tree.end
tree "SYSTICK (Cortex M0 SysTick registers)"
base ad:0xE000E010
width 7.
group.long 0x00++0x03
line.long 0x00 "CTRL,SysTick Control and Status register"
bitfld.long 0x00 16. " COUNTFLAG ,Timer counted to 0 since last time this was read" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Clock source selection" "0,1"
bitfld.long 0x00 1. " TICKINT ,SysTick exception request enable" "0,1"
newline
bitfld.long 0x00 0. " ENABLE ,SysTick Counter enable" "0,1"
group.long 0x04++0x03
line.long 0x00 "LOAD,SysTick Reload value register"
hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,RELOAD[23:0] bits (Reload value)"
group.long 0x08++0x03
line.long 0x00 "VAL,SysTick Current value register"
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT ,CURRENT[23:0] bits (Current counter value)"
rgroup.long 0x0C++0x03
line.long 0x00 "CALIB,SysTick Calibration value register"
bitfld.long 0x00 31. " NOREF ,Indicates that a separate reference clock is provided" "0,1"
bitfld.long 0x00 30. " SKEW ,Indicates whether the TENMS value is exact" "0,1"
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,TENMS[23:0] bits (Calibration value)"
width 0x0B
tree.end
tree "ADPLLDIG"
base ad:0x40003000
width 29.
group.long 0x64++0x03
line.long 0x00 "ADPLL_ACC_CTRL_REG,"
bitfld.long 0x00 31. " EN_CMF_AVG ," "0,1"
hexmask.long.word 0x00 16.--28. 1. " CLIP_MOD_TUNE_0_TX ,"
hexmask.long.word 0x00 0.--12. 1. " CLIP_MOD_TUNE_0_RX ,"
group.long 0x60++0x03
line.long 0x00 "ADPLL_ANATST_CTRL_REG,"
hexmask.long.word 0x00 16.--31. 1. " ANATSTSPARE ,"
hexmask.long.word 0x00 0.--15. 1. " ANATSTEN ,"
group.long 0x94++0x03
line.long 0x00 "ADPLL_ANATST_RD_REG,"
hexmask.long.word 0x00 0.--15. 1. " ANATSTSPARE_IN ,"
group.long 0x34++0x03
line.long 0x00 "ADPLL_ANA_CTRL_REG,"
bitfld.long 0x00 27.--28. " DTC_LDO_DMY ," "0,1,2,3"
bitfld.long 0x00 24.--25. " VPASETTLE ," "0,1,2,3"
bitfld.long 0x00 16.--21. " TDC_OFFSET ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 15. " DTC_EN ," "0,1"
hexmask.long.byte 0x00 8.--14. 1. " DTCOFFSET ,"
bitfld.long 0x00 7. " TGLDETEN ," "0,1"
newline
bitfld.long 0x00 6. " EN_CKDCOMOD ," "0,1"
bitfld.long 0x00 5. " INV_CKDCOMOD ," "0,1"
bitfld.long 0x00 4. " INV_CKPHV ," "0,1"
newline
bitfld.long 0x00 3. " INV_CKTDC ," "0,1"
bitfld.long 0x00 2. " TDC_INV ," "0,1"
bitfld.long 0x00 1. " TDC_CKVIN_EN ," "0,1"
newline
bitfld.long 0x00 0. " TDC_DTCIN_EN ," "0,1"
group.long 0x00++0x03
line.long 0x00 "ADPLL_ATTR_CTRL_REG,"
bitfld.long 0x00 1. " PWR_MODE_TX ," "0,1"
bitfld.long 0x00 0. " PWR_MODE_RX ," "0,1"
group.long 0x04++0x03
line.long 0x00 "ADPLL_CN_CTRL_REG,"
hexmask.long.word 0x00 16.--28. 1. " CH0 ,"
bitfld.long 0x00 15. " SGN ," "0,1"
bitfld.long 0x00 8. " CS ," "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. " CN ,"
group.long 0x20++0x03
line.long 0x00 "ADPLL_DCOAMP_CAL_CTRL_REG,"
bitfld.long 0x00 28.--31. " DCOAMPIC_LP_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. " DCOAMPIC_LP_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. " DCOAMPIC_HP_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. " DCOAMPIC_HP_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. " DCOAMPTM ," "0,1"
bitfld.long 0x00 6. " AMPCALEN ," "0,1"
newline
bitfld.long 0x00 3.--5. " KMEDIUM ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. " KCOARSE ," "0,1,2,3,4,5,6,7"
group.long 0x80++0x03
line.long 0x00 "ADPLL_DCO_RD_REG,"
rbitfld.long 0x00 26.--29. " DCOAMP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 13.--25. 1. " DCOMOD ,"
rbitfld.long 0x00 7.--12. " DCOFINE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 4.--6. " DCOMEDIUM ," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 0.--3. " DCOCOARSE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x03
line.long 0x00 "ADPLL_DIV_CTRL_REG,"
hexmask.long.word 0x00 17.--25. 1. " TXDIV_TRIM ,"
hexmask.long.word 0x00 8.--16. 1. " RXDIV_TRIM ,"
bitfld.long 0x00 2. " RXDIV_FB_EN_TX ," "0,1"
newline
bitfld.long 0x00 1. " RXDIV_FB_EN_RX ," "0,1"
bitfld.long 0x00 0. " FBDIV_EN ," "0,1"
group.long 0x08++0x03
line.long 0x00 "ADPLL_FIF_CTRL1_REG,"
hexmask.long.word 0x00 0.--13. 1. " FIFRX_1M ,"
group.long 0x0C++0x03
line.long 0x00 "ADPLL_FIF_CTRL2_REG,"
hexmask.long.word 0x00 16.--29. 1. " FIFTX ,"
hexmask.long.word 0x00 0.--13. 1. " FIFRX_OFFSET ,"
group.long 0x7C++0x03
line.long 0x00 "ADPLL_FREQMEAS_RD_REG,"
rbitfld.long 0x00 29. " MEASDONE_OUT ," "0,1"
rbitfld.long 0x00 26. " QUALMONDET ," "0,1"
rbitfld.long 0x00 25. " TDCBUB ," "0,1"
newline
rbitfld.long 0x00 24. " PHVSA0 ," "0,1"
rbitfld.long 0x00 23. " PHVSA1 ," "0,1"
hexmask.long.tbyte 0x00 0.--22. 1. " FREQDIFF ,"
group.long 0x40++0x03
line.long 0x00 "ADPLL_FSM_CTRL_REG,"
bitfld.long 0x00 24.--29. " TVPASETTLE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20.--23. " TSETTLE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. " TPASETTLE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. " TMOD ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. " TFINE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. " TMEDIUM ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. " TCOARSE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C++0x03
line.long 0x00 "ADPLL_INIT_CTRL_REG,"
hexmask.long.word 0x00 16.--28. 1. " DCOMODIC ,"
bitfld.long 0x00 8.--13. " DCOFINEIC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4.--6. " DCOMEDIUMIC ," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--3. " DCOCOARSEIC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "ADPLL_KDCO_CAL_CTRL1_REG,"
hexmask.long.byte 0x00 8.--15. 1. " KDCOLF_IN_1M ,"
hexmask.long.byte 0x00 0.--7. 1. " KDCOHFIC_1M ,"
group.long 0x14++0x03
line.long 0x00 "ADPLL_KDCO_CAL_CTRL2_REG,"
bitfld.long 0x00 30.--31. " KDCOESTDEV ," "0,1,2,3"
bitfld.long 0x00 29. " KDCOCALTX ," "0,1"
bitfld.long 0x00 28. " KDCOCALRX ," "0,1"
newline
bitfld.long 0x00 27. " KDCOLFCALEN ," "0,1"
bitfld.long 0x00 24.--26. " TKDCOCAL ," "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 16.--22. 1. " KDCOCN_IC ,"
newline
bitfld.long 0x00 0.--4. " KMOD_ALPHA_1M ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x84++0x03
line.long 0x00 "ADPLL_KDCO_RD_REG,"
rbitfld.long 0x00 23. " CAL_KDCOCAL ," "0,1"
hexmask.long.byte 0x00 16.--22. 1. " KDCOCN ,"
hexmask.long.byte 0x00 8.--15. 1. " KDCO_HF_OUT ,"
newline
hexmask.long.byte 0x00 0.--7. 1. " KDCO_HF_INT ,"
group.long 0x18++0x03
line.long 0x00 "ADPLL_KDTCTDC_CAL_CTRL1_REG,"
hexmask.long.word 0x00 23.--31. 1. " KDTCIC ,"
hexmask.long.byte 0x00 16.--22. 1. " KDTCCN_IC ,"
bitfld.long 0x00 15. " KDTC_PIPELINE_BYPASS ," "0,1"
newline
hexmask.long.word 0x00 6.--14. 1. " KTDC_IN ,"
bitfld.long 0x00 0.--5. " KDTC_ALPHA ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1C++0x03
line.long 0x00 "ADPLL_KDTCTDC_CAL_CTRL2_REG,"
bitfld.long 0x00 15. " PHRDLY_EXTRA ," "0,1"
bitfld.long 0x00 11.--14. " TKDTCCAL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9.--10. " PHRDLY ," "0,1,2,3"
newline
bitfld.long 0x00 8. " KTDCCALEN ," "0,1"
bitfld.long 0x00 4.--6. " KDTCCALLG ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. " KDTCCAL_INV ," "0,1"
newline
bitfld.long 0x00 2. " KDTCCALMOD1P ," "0,1"
bitfld.long 0x00 1. " KDTCCALMOD ," "0,1"
bitfld.long 0x00 0. " KDTCCALEN ," "0,1"
group.long 0x88++0x03
line.long 0x00 "ADPLL_KDTC_RD_REG,"
rbitfld.long 0x00 25. " CAL_KDTCCAL ," "0,1"
hexmask.long.word 0x00 16.--24. 1. " KDTC_ALPHA_COMP ,"
hexmask.long.byte 0x00 9.--15. 1. " KDTCCN ,"
newline
hexmask.long.word 0x00 0.--8. 1. " KDTC_OUT ,"
group.long 0x2C++0x03
line.long 0x00 "ADPLL_LF_CTRL1_REG,"
bitfld.long 0x00 10.--15. " FINEKZ ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 5.--9. " FINEK ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " FINETAU ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x30++0x03
line.long 0x00 "ADPLL_LF_CTRL2_REG,"
bitfld.long 0x00 30. " RST_TAU_EN ," "0,1"
bitfld.long 0x00 24.--29. " MODKZ ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. " MODK ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 12.--17. " MODTAU ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--11. " MODK_TUNE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. " MODTAU_TUNE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x48++0x03
line.long 0x00 "ADPLL_MISC_CTRL_REG,"
hexmask.long.word 0x00 8.--23. 1. " PHR_FRAC_PRESET_VAL ,"
bitfld.long 0x00 7. " ENFCWMOD ," "0,1"
bitfld.long 0x00 6. " ENRESIDUE ," "0,1"
newline
bitfld.long 0x00 4.--5. " MODDLY ," "0,1,2,3"
bitfld.long 0x00 2.--3. " RESDLY ," "0,1,2,3"
bitfld.long 0x00 0.--1. " DLYFCWDT ," "0,1,2,3"
group.long 0x44++0x03
line.long 0x00 "ADPLL_MON_CTRL_REG,"
bitfld.long 0x00 30. " QUALMONFRCEN ," "0,1"
bitfld.long 0x00 24.--29. " QUALMONTRHLD ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 18.--23. " QUALMONWND ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16.--17. " QUALMONMOD ," "0,1,2,3"
bitfld.long 0x00 8.--11. " HOLD_STATE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. " RFMEAS_MODE ," "0,1"
newline
bitfld.long 0x00 6. " ENRFMEAS ," "0,1"
bitfld.long 0x00 5. " TMREN ," "0,1"
bitfld.long 0x00 0.--4. " TFREQMEAS ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x50++0x03
line.long 0x00 "ADPLL_OVERRULE_CTRL1_REG,"
hexmask.long.byte 0x00 25.--31. 1. " OVR_DTC_OH_WR ,"
bitfld.long 0x00 24. " OVR_DTC_OH_SEL ," "0,1"
bitfld.long 0x00 17.--20. " OVR_DCOAMP_WR ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16. " OVR_DCOAMP_SEL ," "0,1"
bitfld.long 0x00 13. " OVR_DCOAMPHOLD_WR ," "0,1"
bitfld.long 0x00 12. " OVR_DCOAMPHOLD_SEL ," "0,1"
newline
bitfld.long 0x00 11. " OVR_RDYFORDIV_WR ," "0,1"
bitfld.long 0x00 10. " OVR_RDYFORDIV_SEL ," "0,1"
bitfld.long 0x00 9. " OVR_VPAEN_WR ," "0,1"
newline
bitfld.long 0x00 8. " OVR_VPAEN_SEL ," "0,1"
bitfld.long 0x00 7. " OVR_SRESETN_WR ," "0,1"
bitfld.long 0x00 6. " OVR_SRESETN_SEL ," "0,1"
newline
bitfld.long 0x00 5. " OVR_ENPAIN_WR ," "0,1"
bitfld.long 0x00 4. " OVR_ENPAIN_SEL ," "0,1"
bitfld.long 0x00 3. " OVR_RXBIT_WR ," "0,1"
newline
bitfld.long 0x00 2. " OVR_RXBIT_SEL ," "0,1"
bitfld.long 0x00 1. " OVR_ACTIVE_WR ," "0,1"
bitfld.long 0x00 0. " OVR_ACTIVE_SEL ," "0,1"
group.long 0x54++0x03
line.long 0x00 "ADPLL_OVERRULE_CTRL2_REG,"
hexmask.long.byte 0x00 24.--31. 1. " OVR_DCOMOD_WR ,"
bitfld.long 0x00 23. " OVR_DCOMOD_SEL ," "0,1"
bitfld.long 0x00 17.--22. " OVR_DCOFINE_WR ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16. " OVR_DCOFINE_SEL ," "0,1"
bitfld.long 0x00 9.--11. " OVR_DCOMEDIUM_WR ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. " OVR_DCOMEDIUM_SEL ," "0,1"
newline
bitfld.long 0x00 1.--4. " OVR_DCOCOARSE_WR ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. " OVR_DCOCOARSE_SEL ," "0,1"
group.long 0x58++0x03
line.long 0x00 "ADPLL_OVERRULE_CTRL3_REG,"
bitfld.long 0x00 7. " OVR_RXDIV_FB_EN_WR ," "0,1"
bitfld.long 0x00 6. " OVR_RXDIV_FB_EN_SEL ," "0,1"
bitfld.long 0x00 5. " OVR_FBDIV_EN_WR ," "0,1"
newline
bitfld.long 0x00 4. " OVR_FBDIV_EN_SEL ," "0,1"
bitfld.long 0x00 3. " OVR_TXDIV_EN_WR ," "0,1"
bitfld.long 0x00 2. " OVR_TXDIV_EN_SEL ," "0,1"
newline
bitfld.long 0x00 1. " OVR_RXDIV_EN_WR ," "0,1"
bitfld.long 0x00 0. " OVR_RXDIV_EN_SEL ," "0,1"
group.long 0x90++0x03
line.long 0x00 "ADPLL_PLLFCWDT_RD_REG,"
hexmask.long.tbyte 0x00 0.--22. 1. " PLLFCWDT ,"
group.long 0x5C++0x03
line.long 0x00 "ADPLL_RFPT_CTRL_REG,"
bitfld.long 0x00 5. " RFPT_RATE ," "0,1"
bitfld.long 0x00 4. " INV_CKRFPT ," "0,1"
bitfld.long 0x00 0.--3. " RFPT_MUX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x03
line.long 0x00 "ADPLL_SDMOD_CTRL_REG,"
bitfld.long 0x00 3.--5. " SDMMODETX ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. " SDMMODERX ," "0,1,2,3,4,5,6,7"
group.long 0x8C++0x03
line.long 0x00 "ADPLL_TUNESTATE_RD_REG,"
hexmask.long.word 0x00 4.--13. 1. " TMRVAL ,"
rbitfld.long 0x00 0.--3. " TUNE_STATE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "ADPLL_TXMOD_CTRL_REG,"
bitfld.long 0x00 8. " INV_CKMODEXT ," "0,1"
bitfld.long 0x00 6.--7. " TX_MODE ," "0,1,2,3"
bitfld.long 0x00 4. " EO_PACKET_DIS ," "0,1"
newline
bitfld.long 0x00 2.--3. " MOD_INDEX ," "0,1,2,3"
bitfld.long 0x00 1. " TX_DATA_INV ," "0,1"
bitfld.long 0x00 0. " BT_SEL ," "0,1"
width 0x0B
tree.end
tree "ANAMISC"
base ad:0x50001600
width 19.
group.word 0x02++0x01
line.word 0x00 "CLK_REF_CNT_REG,Count value for oscillator calibration"
hexmask.word 0x00 0.--15. 1. " REF_CNT_VAL ,Indicates the calibration time. with a decrement counter to 1"
group.word 0x00++0x01
line.word 0x00 "CLK_REF_SEL_REG,Select clock for oscillator calibration"
bitfld.word 0x00 3. " EXT_CNT_EN_SEL ,0 : Enable XTAL_CNT counter by the REF_CLK selected by REF_CLK_SEL" "0,1"
bitfld.word 0x00 2. " REF_CAL_START ,Writing a '1' starts a calibration of the clock selected by CLK_REF_SEL_REG[REF_CLK_SEL]" "0,1"
bitfld.word 0x00 0.--1. " REF_CLK_SEL ,Select clock input for calibration:_0x0 : RC32K_0x1 : RC32M_0x2 : XTAL32K_0x3 : RCX" "0,1,2,3"
group.word 0x06++0x01
line.word 0x00 "CLK_REF_VAL_H_REG,XTAL32M reference cycles. higher 16 bits"
hexmask.word 0x00 0.--15. 1. " XTAL_CNT_VAL ,Returns the number of DIVN clock cycles counted during the calibration time. defined with REF_CNT_VA.."
group.word 0x04++0x01
line.word 0x00 "CLK_REF_VAL_L_REG,XTAL32M reference cycles. lower 16 bits"
hexmask.word 0x00 0.--15. 1. " XTAL_CNT_VAL ,Returns the number of DIVN clock cycles counted during the calibration time. defined with REF_CNT_VA.."
width 0x0B
tree.end
tree "BLE"
base ad:0x40000000
width 26.
group.long 0xA4++0x03
line.long 0x00 "BLE_ACTSCANSTAT_REG,Active scan register"
hexmask.long.word 0x00 16.--24. 1. " BACKOFF ,Active scan mode back-off counter initialization value"
hexmask.long.word 0x00 0.--8. 1. " UPPERLIMIT ,Active scan mode upper limit counter value"
group.long 0x90++0x03
line.long 0x00 "BLE_ADVCHMAP_REG,Advertising Channel Map"
bitfld.long 0x00 0.--2. " ADVCHMAP ,Advertising Channel Map. defined as per the advertising connection settings" "0,1,2,3,4,5,6,7"
group.long 0xA0++0x03
line.long 0x00 "BLE_ADVTIM_REG,Advertising Packet Interval"
hexmask.long.word 0x00 0.--13. 1. " ADVINT ,Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent"
group.long 0xC0++0x03
line.long 0x00 "BLE_AESCNTL_REG,Start AES register"
bitfld.long 0x00 1. " AES_MODE ,0: Cipher mode_1: Decipher mode" "0,1"
bitfld.long 0x00 0. " AES_START ,Writing a 1 starts AES-128 ciphering/deciphering process" "0,1"
group.long 0xD0++0x03
line.long 0x00 "BLE_AESKEY127_96_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. " AESKEY127_96 ,AES encryption 128-bit key"
group.long 0xC4++0x03
line.long 0x00 "BLE_AESKEY31_0_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. " AESKEY31_0 ,AES encryption 128-bit key"
group.long 0xC8++0x03
line.long 0x00 "BLE_AESKEY63_32_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. " AESKEY63_32 ,AES encryption 128-bit key"
group.long 0xCC++0x03
line.long 0x00 "BLE_AESKEY95_64_REG,AES encryption key"
hexmask.long 0x00 0.--31. 1. " AESKEY95_64 ,AES encryption 128-bit key"
group.long 0xD4++0x03
line.long 0x00 "BLE_AESPTR_REG,Pointer to the block to encrypt/decrypt"
hexmask.long.word 0x00 0.--15. 1. " AESPTR ,Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored"
group.long 0x44++0x03
line.long 0x00 "BLE_BASETIMECNTCORR_REG,Base Time Counter"
hexmask.long 0x00 0.--26. 1. " BASETIMECNTCORR ,Base Time Counter correction value"
group.long 0x1C++0x03
line.long 0x00 "BLE_BASETIMECNT_REG,Base time reference counter"
hexmask.long 0x00 0.--26. 1. " BASETIMECNT ,Value of the 625us base time reference counter"
group.long 0x24++0x03
line.long 0x00 "BLE_BDADDRL_REG,BLE device address LSB register"
hexmask.long 0x00 0.--31. 1. " BDADDRL ,Bluetooth Low Energy Device Address"
group.long 0x28++0x03
line.long 0x00 "BLE_BDADDRU_REG,BLE device address MSB register"
bitfld.long 0x00 16. " PRIV_NPUB ,Bluetooth Low Energy Device Address privacy indicator_0: Public Bluetooth Device Address_1: Private .." "0,1"
hexmask.long.word 0x00 0.--15. 1. " BDADDRU ,Bluetooth Low Energy Device Address"
group.long 0x108++0x03
line.long 0x00 "BLE_BLEMPRIO0_REG,Coexistence interface Priority 0 Register"
bitfld.long 0x00 28.--31. " BLEM7 ,Set Priority value for Passive Scanning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. " BLEM6 ,Set Priority value for Non-Connectable Advertising" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. " BLEM5 ,Set Priority value for Connectable Advertising BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. " BLEM4 ,Set Priority value for Active Scanning BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. " BLEM3 ,Set Priority value for Initiating (Scanning) BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. " BLEM2 ,Set Priority value for Data Channel transmission BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. " BLEM1 ,Set Priority value for LLCP BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " BLEM0 ,Set Priority value for Initiating (Connection Request Response) BLE message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10C++0x03
line.long 0x00 "BLE_BLEMPRIO1_REG,Coexistence interface Priority 1 Register"
bitfld.long 0x00 28.--31. " BLEMDEFAULT ,Set default priority value for other BLE message than those defined above" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x200++0x03
line.long 0x00 "BLE_CNTL2_REG,BLE Control Register 2"
bitfld.long 0x00 24. " BLE_PHY_ERR_MSK_N ," "0,1"
bitfld.long 0x00 23. " BLE_ARP_ERR_MSK_N ,When cleared to _0_ then it masks the BLE_ARP_ERR_STAT in order to not trigger a BLE_ERROR_IRQ" "0,1"
bitfld.long 0x00 22. " BLE_ARP_PHY_ERR_STAT ,When set to _1_ then an error occured in BLE ARP sub-block and the BLE_GEN_IRQ will be aserted" "0,1"
newline
bitfld.long 0x00 21. " BLE_RSSI_SEL ,0: (default) Select Peak-hold RSSI value during the SYNC_FOUND event:_CS->RXRSSI[7:0] = RF_RSSI_RESU.." "0,1"
rbitfld.long 0x00 20. " WAKEUPLPSTAT ,The status of the BLE_WAKEUP_LP_IRQ" "0,1"
bitfld.long 0x00 19. " SW_RPL_SPI ,Keep to 0" "0,1"
newline
bitfld.long 0x00 18. " BB_ONLY ,Keep to 0" "0,1"
bitfld.long 0x00 17. " BLE_PTI_SOURCE_SEL ,0: Provide to COEX block the PTI value indicated by the Control Structure" "0,1"
bitfld.long 0x00 9.--14. " BLE_CLK_SEL ,BLE Clock Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 8. " RADIO_PWRDN_ALLOW ,This active high signal indicates when it is allowed for the BLE core (embedded in the Radio sub-Sys.." "0,1"
rbitfld.long 0x00 7. " MON_LP_CLK ,The SW can only write a _0_ to this bit" "0,1"
rbitfld.long 0x00 6. " BLE_CLK_STAT ,0: BLE uses low power clock_1: BLE uses master clock" "0,1"
newline
bitfld.long 0x00 3. " BLE_DIAG_OVR ,1: Overrule BLE_DIAG" "0,1"
bitfld.long 0x00 2. " EMACCERRMSK ,Exchange Memory Access Error Mask:_When cleared to _0_ the EM_ACC_ERR will not cause an BLE_ERROR_IR.." "0,1"
bitfld.long 0x00 1. " EMACCERRACK ,Exchange Memory Access Error Acknowledge" "0,1"
newline
rbitfld.long 0x00 0. " EMACCERRSTAT ,Exchange Memory Access Error Status:_The bit is read-only and can be cleared only by writing a _1_ a.." "0,1"
group.long 0x100++0x03
line.long 0x00 "BLE_COEXIFCNTL0_REG,Coexistence interface Control 0 Register"
bitfld.long 0x00 20.--21. " WLCRXPRIOMODE ,Defines Bluetooth Low Energy packet ble_rx mode behavior" "0,1,2,3"
bitfld.long 0x00 16.--17. " WLCTXPRIOMODE ,Defines Bluetooth Low Energy packet ble_tx mode behavior_00: Tx indication excluding Tx Power up del.." "0,1,2,3"
bitfld.long 0x00 6.--7. " WLANTXMSK ,Determines how wlan_tx impact BLE Tx and Rx_00: wlan_tx has no impact (default mode)_01: wlan_tx can.." "0,1,2,3"
newline
bitfld.long 0x00 4.--5. " WLANRXMSK ,Determines how wlan_rx impact BLE Tx and Rx_00: wlan_rx has no impact_01: wlan_rx can stop BLE Tx. n.." "0,1,2,3"
bitfld.long 0x00 1. " SYNCGEN_EN ,Determines whether ble_sync is generated or not" "0,1"
bitfld.long 0x00 0. " COEX_EN ,Enable / Disable control of the MWS/WLAN Coexistence control_0: Coexistence interface disabled_1: Co.." "0,1"
group.long 0x104++0x03
line.long 0x00 "BLE_COEXIFCNTL1_REG,Coexistence interface Control 1 Register"
bitfld.long 0x00 24.--28. " WLCPRXTHR ,Applies on ble_rx if WLCRXPRIOMODE equals 10_Determines the threshold for Rx priority setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. " WLCPTXTHR ,Applies on ble_tx if WLCTXPRIOMODE equals 10_Determines the threshold for priority setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 8.--14. 1. " WLCPDURATION ,Applies on ble_tx if WLCTXPRIOMODE equals 10_Applies on ble_rx if WLCRXPRIOMODE equals 10_Determines.."
newline
hexmask.long.byte 0x00 0.--6. 1. " WLCPDELAY ,Applies on ble_tx if WLCTXPRIOMODE equals 10"
group.long 0x2C++0x03
line.long 0x00 "BLE_CURRENTRXDESCPTR_REG,Rx Descriptor Pointer for the Receive Buffer Chained List"
hexmask.long.word 0x00 16.--31. 1. " ETPTR ,Exchange Table Pointer that determines the starting point of the Exchange Table"
hexmask.long.word 0x00 0.--14. 1. " CURRENTRXDESCPTR ,Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List"
group.long 0x58++0x03
line.long 0x00 "BLE_DEBUGADDMAX_REG,Upper limit for the memory zone"
hexmask.long.word 0x00 16.--31. 1. " REG_ADDMAX ,Upper limit for the Register zone indicated by the reg_inzone flag"
hexmask.long.word 0x00 0.--15. 1. " EM_ADDMAX ,Upper limit for the Exchange Memory zone indicated by the em_inzone flag"
group.long 0x5C++0x03
line.long 0x00 "BLE_DEBUGADDMIN_REG,Lower limit for the memory zone"
hexmask.long.word 0x00 16.--31. 1. " REG_ADDMIN ,Lower limit for the Register zone indicated by the reg_inzone flag"
hexmask.long.word 0x00 0.--15. 1. " EM_ADDMIN ,Lower limit for the Exchange Memory zone indicated by the em_inzone flag"
group.long 0x30++0x03
line.long 0x00 "BLE_DEEPSLCNTL_REG,Deep-Sleep control register"
bitfld.long 0x00 31. " EXTWKUPDSB ,External Wake-Up disable_0: RW-BLE Core can be woken by external wake-up_1: RW-BLE Core cannot be wo.." "0,1"
rbitfld.long 0x00 15. " DEEP_SLEEP_STAT ,Indicator of current Deep Sleep clock mux status:_0: RW-BLE Core is not yet in Deep Sleep Mode_1: RW.." "0,1"
bitfld.long 0x00 4. " SOFT_WAKEUP_REQ ,Wake Up Request from BLE Software" "0,1"
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bitfld.long 0x00 3. " DEEP_SLEEP_CORR_EN ,625us base time reference integer and fractional part correction" "0,1"
bitfld.long 0x00 2. " DEEP_SLEEP_ON ,0: BLE Core in normal active mode_1: Request RW-BLE Core to switch in deep sleep mode" "0,1"
bitfld.long 0x00 0.--1. " DEEP_SLEEP_IRQ_EN ,Always set to _3_ when DEEP_SLEEP_ON is set to _1_" "0,1,2,3"
group.long 0x38++0x03
line.long 0x00 "BLE_DEEPSLSTAT_REG,Duration of the last deep sleep phase register"
hexmask.long 0x00 0.--31. 1. " DEEPSLDUR ,Actual duration of the last deep sleep phase measured in low_power_clk clock cycle"
group.long 0x34++0x03
line.long 0x00 "BLE_DEEPSLWKUP_REG,Time (measured in Low Power clock cycles) in Deep Sleep Mode before waking-up the device"
hexmask.long 0x00 0.--31. 1. " DEEPSLTIME ,Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the d.."
group.long 0x20C++0x03
line.long 0x00 "BLE_DIAGCNTL2_REG,Debug use only"
bitfld.long 0x00 31. " DIAG7_EN ,0: Disable diagnostic port 0 output" "0,1"
bitfld.long 0x00 24.--29. " DIAG7 ,Only relevant when DIAG7_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. " DIAG6_EN ,0: Disable diagnostic port 0 output" "0,1"
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bitfld.long 0x00 16.--21. " DIAG6 ,Only relevant when DIAG6_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. " DIAG5_EN ,0: Disable diagnostic port 0 output" "0,1"
bitfld.long 0x00 8.--13. " DIAG5 ,Only relevant when DIAG5_EN= 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. " DIAG4_EN ,0: Disable diagnostic port 0 output" "0,1"
bitfld.long 0x00 0.--5. " DIAG4 ,Only relevant when DIAG4_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x210++0x03
line.long 0x00 "BLE_DIAGCNTL3_REG,Debug use only"
bitfld.long 0x00 31. " DIAG7_INV ,If set. then the specific diagnostic bit will be inverted" "0,1"
bitfld.long 0x00 28.--30. " DIAG7_BIT ,Selects which bit from the DIAG7 word will be forwarded to bit 7 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 27. " DIAG6_INV ,If set. then the specific diagnostic bit will be inverted" "0,1"
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bitfld.long 0x00 24.--26. " DIAG6_BIT ,Selects which bit from the DIAG6 word will be forwarded to bit 6 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23. " DIAG5_INV ,If set. then the specific diagnostic bit will be inverted" "0,1"
bitfld.long 0x00 20.--22. " DIAG5_BIT ,Selects which bit from the DIAG5 word will be forwarded to bit 5 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. " DIAG4_INV ,If set. then the specific diagnostic bit will be inverted" "0,1"
bitfld.long 0x00 16.--18. " DIAG4_BIT ,Selects which bit from the DIAG4 word will be forwarded to bit 4 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. " DIAG3_INV ,If set. then the specific diagnostic bit will be inverted" "0,1"
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bitfld.long 0x00 12.--14. " DIAG3_BIT ,Selects which bit from the DIAG3 word will be forwarded to bit 3 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11. " DIAG2_INV ,If set. then the specific diagnostic bit will be inverted" "0,1"
bitfld.long 0x00 8.--10. " DIAG2_BIT ,Selects which bit from the DIAG2 word will be forwarded to bit 2 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 7. " DIAG1_INV ,If set. then the specific diagnostic bit will be inverted" "0,1"
bitfld.long 0x00 4.--6. " DIAG1_BIT ,Selects which bit from the DIAG1 word will be forwarded to bit 1 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. " DIAG0_INV ,If set. then the specific diagnostic bit will be inverted" "0,1"
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bitfld.long 0x00 0.--2. " DIAG0_BIT ,Selects which bit from the DIAG0 word will be forwarded to bit 0 of the BLE DIagnostic Port" "0,1,2,3,4,5,6,7"
group.long 0x50++0x03
line.long 0x00 "BLE_DIAGCNTL_REG,Diagnostics Register"
bitfld.long 0x00 31. " DIAG3_EN ,0: Disable diagnostic port 0 output" "0,1"
bitfld.long 0x00 24.--29. " DIAG3 ,Only relevant when DIAG3_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 23. " DIAG2_EN ,0: Disable diagnostic port 0 output" "0,1"
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bitfld.long 0x00 16.--21. " DIAG2 ,Only relevant when DIAG2_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15. " DIAG1_EN ,0: Disable diagnostic port 0 output" "0,1"
bitfld.long 0x00 8.--13. " DIAG1 ,Only relevant when DIAG1_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. " DIAG0_EN ,0: Disable diagnostic port 0 output" "0,1"
bitfld.long 0x00 0.--5. " DIAG0 ,Only relevant when DIAG0_EN = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x54++0x03
line.long 0x00 "BLE_DIAGSTAT_REG,Debug use only"
hexmask.long.byte 0x00 24.--31. 1. " DIAG3STAT ,Directly connected to ble_dbg3[7:0] output"
hexmask.long.byte 0x00 16.--23. 1. " DIAG2STAT ,Directly connected to ble_dbg2[7:0] output"
hexmask.long.byte 0x00 8.--15. 1. " DIAG1STAT ,Directly connected to ble_dbg1[7:0] output"
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hexmask.long.byte 0x00 0.--7. 1. " DIAG0STAT ,Directly connected to ble_dbg0[7:0] output"
group.long 0x208++0x03
line.long 0x00 "BLE_EM_BASE_REG,Exchange Memory Base Register"
hexmask.long.byte 0x00 10.--16. 1. " BLE_EM_BASE_16_10 ,The physical address on the system memory map of the base of the Exchange Memory"
group.long 0x3C++0x03
line.long 0x00 "BLE_ENBPRESET_REG,Time in low power oscillator cycles register"
hexmask.long.word 0x00 21.--31. 1. " TWEXT ,Minimum and recommended value is _TWIRQ_RESET + 1_"
hexmask.long.word 0x00 10.--20. 1. " TWIRQ_SET ,Minimum value is _TWIRQ_RESET + 1_"
hexmask.long.word 0x00 0.--9. 1. " TWIRQ_RESET ,Recommended value is 1"
group.long 0x60++0x03
line.long 0x00 "BLE_ERRORTYPESTAT_REG,Error Type Status registers"
rbitfld.long 0x00 17. " CONCEVTIRQ_ERROR ,Indicates whether two consecutive and concurrent ble_event_irq have been generated. and not acknowle.." "0,1"
rbitfld.long 0x00 16. " RXDATA_PTR_ERROR ,Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failu.." "0,1"
rbitfld.long 0x00 15. " TXDATA_PTR_ERROR ,Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning / In.." "0,1"
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rbitfld.long 0x00 14. " RXDESC_EMPTY_ERROR ,Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major progra.." "0,1"
rbitfld.long 0x00 13. " TXDESC_EMPTY_ERROR ,Indicates whether Tx Descriptor pointer value programmed in Control Structure is null during Adverti.." "0,1"
rbitfld.long 0x00 12. " CSFORMAT_ERROR ,Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software prog.." "0,1"
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rbitfld.long 0x00 11. " LLCHMAP_ERROR ,Indicates Link Layer Channel Map error. happens when actual number of CS-LLCHMAP bit set to one is d.." "0,1"
rbitfld.long 0x00 10. " ADV_UNDERRUN ,Indicates Advertising Interval Under run. occurs if time between two consecutive Advertising packet .." "0,1"
rbitfld.long 0x00 9. " IFS_UNDERRUN ,Indicates Inter Frame Space Under run. occurs if IFS time is not enough to update and read Control S.." "0,1"
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rbitfld.long 0x00 8. " WHITELIST_ERROR ,Indicates White List Timeout error. occurs if White List parsing is not finished on time_0: No error.." "0,1"
rbitfld.long 0x00 7. " EVT_CNTL_APFM_ERROR ,Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed. a.." "0,1"
rbitfld.long 0x00 6. " EVT_SCHDL_APFM_ERROR ,Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed. a.." "0,1"
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rbitfld.long 0x00 5. " EVT_SCHDL_ENTRY_ERROR ,Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e" "0,1"
rbitfld.long 0x00 4. " EVT_SCHDL_EMACC_ERROR ,Indicates Event Scheduler Exchange Memory access error. happens when Exchange Memory accesses are no.." "0,1"
rbitfld.long 0x00 3. " RADIO_EMACC_ERROR ,Indicates Radio Controller Exchange Memory access error. happens when Exchange Memory accesses are n.." "0,1"
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rbitfld.long 0x00 2. " PKTCNTL_EMACC_ERROR ,Indicates Packet Controller Exchange Memory access error. happens when Exchange Memory accesses are .." "0,1"
rbitfld.long 0x00 1. " RXCRYPT_ERROR ,Indicates real time decryption error. happens when AES-CCM decryption is too slow compared to Packet.." "0,1"
rbitfld.long 0x00 0. " TXCRYPT_ERROR ,Indicates Real Time encryption error. happens when AES-CCM encryption is too slow compared to Packet.." "0,1"
group.long 0x40++0x03
line.long 0x00 "BLE_FINECNTCORR_REG,Phase correction value register"
hexmask.long.word 0x00 0.--9. 1. " FINECNTCORR ,Phase correction value for the 625us reference counter (i"
group.long 0x20++0x03
line.long 0x00 "BLE_FINETIMECNT_REG,Fine time reference counter"
hexmask.long.word 0x00 0.--9. 1. " FINECNT ,Value of the current s fine time reference counter"
group.long 0xF8++0x03
line.long 0x00 "BLE_FINETIMTGT_REG,Fine Timer Target value"
hexmask.long 0x00 0.--26. 1. " FINETARGET ,Fine Timer Target value on which a ble_finetgtim_irq must be generated"
group.long 0xF4++0x03
line.long 0x00 "BLE_GROSSTIMTGT_REG,Gross Timer Target value"
hexmask.long.tbyte 0x00 0.--22. 1. " GROSSTARGET ,Gross Timer Target value on which a ble_grosstgtim_irq must be generated"
group.long 0x18++0x03
line.long 0x00 "BLE_INTACK_REG,Interrupt acknowledge register"
bitfld.long 0x00 9. " SWINTACK ,SW triggered interrupt acknowledgement bit_Software writing 1 acknowledges the SW triggered interrup.." "0,1"
bitfld.long 0x00 8. " EVENTAPFAINTACK ,End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit_Software writing 1 acknowle.." "0,1"
bitfld.long 0x00 7. " FINETGTIMINTACK ,Fine Target Timer interrupt acknowledgement bit_Software writing 1 acknowledges the Fine Timer inter.." "0,1"
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bitfld.long 0x00 6. " GROSSTGTIMINTACK ,Gross Target Timer interrupt acknowledgement bit_Software writing 1 acknowledges the Gross Timer int.." "0,1"
bitfld.long 0x00 5. " ERRORINTACK ,Error interrupt acknowledgement bit_Software writing 1 acknowledges the Error interrupt" "0,1"
bitfld.long 0x00 4. " CRYPTINTACK ,Encryption engine interrupt acknowledgement bit Software writing 1 acknowledges the Encryption engin.." "0,1"
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bitfld.long 0x00 3. " EVENTINTACK ,End of Event interrupt acknowledgment bit_Software writing 1 acknowledges the End of Advertising / S.." "0,1"
bitfld.long 0x00 2. " SLPINTACK ,End of Deep Sleep interrupt acknowledgment bit_Software writing 1 acknowledges the End of Sleep Mode.." "0,1"
bitfld.long 0x00 1. " RXINTACK ,Packet Reception interrupt acknowledgment bit_Software writing 1 acknowledges the Rx interrupt" "0,1"
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bitfld.long 0x00 0. " CSCNTINTACK ,625us base time reference interrupt acknowledgment bit_Software writing 1 acknowledges the CLKN inte.." "0,1"
group.long 0x0C++0x03
line.long 0x00 "BLE_INTCNTL_REG,Interrupt controller register"
bitfld.long 0x00 15. " CSCNTDEVMSK ,CSCNT interrupt mask during event" "0,1"
bitfld.long 0x00 9. " SWINTMSK ,SW triggered interrupt Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
bitfld.long 0x00 8. " EVENTAPFAINTMSK ,End of event / anticipated pre-fetch abort interrupt Mask_0: Interrupt not generated_1: Interrupt ge.." "0,1"
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bitfld.long 0x00 7. " FINETGTIMINTMSK ,Fine Target Timer Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
bitfld.long 0x00 6. " GROSSTGTIMINTMSK ,Gross Target Timer Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
bitfld.long 0x00 5. " ERRORINTMSK ,Error Interrupt Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
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bitfld.long 0x00 4. " CRYPTINTMSK ,Encryption engine Interrupt Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
bitfld.long 0x00 3. " EVENTINTMSK ,End of event Interrupt Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
bitfld.long 0x00 2. " SLPINTMSK ,Sleep Mode Interrupt Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
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bitfld.long 0x00 1. " RXINTMSK ,Rx Interrupt Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
bitfld.long 0x00 0. " CSCNTINTMSK ,625us Base Time Interrupt Mask_0: Interrupt not generated_1: Interrupt generated" "0,1"
group.long 0x14++0x03
line.long 0x00 "BLE_INTRAWSTAT_REG,Interrupt raw status register"
rbitfld.long 0x00 9. " SWINTRAWSTAT ,SW triggered interrupt raw status_0: No SW triggered interrupt" "0,1"
rbitfld.long 0x00 8. " EVENTAPFAINTRAWSTAT ,End of event / Anticipated Pre-Fetch Abort interrupt raw status_0: No End of Event interrupt" "0,1"
rbitfld.long 0x00 7. " FINETGTIMINTRAWSTAT ,Fine Target Timer Error interrupt raw status_0: No Fine Target Timer interrupt" "0,1"
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rbitfld.long 0x00 6. " GROSSTGTIMINTRAWSTAT ,Gross Target Timer interrupt raw status_0: No Gross Target Timer interrupt" "0,1"
rbitfld.long 0x00 5. " ERRORINTRAWSTAT ,Error interrupt raw status_0: No Error interrupt" "0,1"
rbitfld.long 0x00 4. " CRYPTINTRAWSTAT ,Encryption engine interrupt raw status_0: No Encryption / Decryption interrupt" "0,1"
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rbitfld.long 0x00 3. " EVENTINTRAWSTAT ,End of Event interrupt raw status_0: No End of Advertising / Scanning / Connection interrupt" "0,1"
rbitfld.long 0x00 2. " SLPINTRAWSTAT ,Sleep interrupt raw status_0: No End of Sleep Mode interrupt" "0,1"
rbitfld.long 0x00 1. " RXINTRAWSTAT ,Packet Reception interrupt raw status_0: No Rx interrupt" "0,1"
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rbitfld.long 0x00 0. " CSCNTINTRAWSTAT ,625us base time reference interrupt raw status_0: No 625us Base Time interrupt" "0,1"
group.long 0x10++0x03
line.long 0x00 "BLE_INTSTAT_REG,Interrupt status register"
rbitfld.long 0x00 9. " SWINTSTAT ,SW triggered interrupt status_0: No SW triggered interrupt" "0,1"
rbitfld.long 0x00 8. " EVENTAPFAINTSTAT ,End of event / Anticipated Pre-Fetch Abort interrupt status_0: No End of Event interrupt" "0,1"
rbitfld.long 0x00 7. " FINETGTIMINTSTAT ,Masked Fine Target Timer Error interrupt status_0: No Fine Target Timer interrupt" "0,1"
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rbitfld.long 0x00 6. " GROSSTGTIMINTSTAT ,Masked Gross Target Timer interrupt status_0: No Gross Target Timer interrupt" "0,1"
rbitfld.long 0x00 5. " ERRORINTSTAT ,Masked Error interrupt status_0: No Error interrupt" "0,1"
rbitfld.long 0x00 4. " CRYPTINTSTAT ,Masked Encryption engine interrupt status_0: No Encryption / Decryption interrupt" "0,1"
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rbitfld.long 0x00 3. " EVENTINTSTAT ,Masked End of Event interrupt status_0: No End of Advertising / Scanning / Connection interrupt" "0,1"
rbitfld.long 0x00 2. " SLPINTSTAT ,Masked Sleep interrupt status_0: No End of Sleep Mode interrupt" "0,1"
rbitfld.long 0x00 1. " RXINTSTAT ,Masked Packet Reception interrupt status_0: No Rx interrupt" "0,1"
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rbitfld.long 0x00 0. " CSCNTINTSTAT ,Masked 625us base time reference interrupt status_0: No 625us Base Time interrupt" "0,1"
group.long 0x70++0x03
line.long 0x00 "BLE_RADIOCNTL0_REG,Radio interface control register"
group.long 0x74++0x03
line.long 0x00 "BLE_RADIOCNTL1_REG,Radio interface control register"
bitfld.long 0x00 16.--20. " XRFSEL ,Extended radio selection field. Must be set to _2_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x78++0x03
line.long 0x00 "BLE_RADIOCNTL2_REG,Radio interface control register"
group.long 0x7C++0x03
line.long 0x00 "BLE_RADIOCNTL3_REG,Radio interface control register"
group.long 0x80++0x03
line.long 0x00 "BLE_RADIOPWRUPDN_REG,RX/TX power up/down phase register"
hexmask.long.byte 0x00 24.--30. 1. " RTRIP_DELAY ,Defines round trip delay value"
hexmask.long.byte 0x00 16.--23. 1. " RXPWRUP ,This register holds the length in s of the RX power up phase for the current radio device"
bitfld.long 0x00 8.--11. " TXPWRDN ,This register extends the length in s of the TX power down phase for the current radio device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. " TXPWRUP ,This register holds the length in s of the TX power up phase for the current radio device"
group.long 0xE0++0x03
line.long 0x00 "BLE_RFTESTCNTL_REG,RF Testing Register"
bitfld.long 0x00 31. " INFINITERX ,Applicable in RF Test Mode only_0: Normal mode of operation_1: Infinite Rx window" "0,1"
bitfld.long 0x00 27. " RXPKTCNTEN ,Applicable in RF Test Mode only_0: Rx packet count disabled_1: Rx packet count enabled. and reported.." "0,1"
bitfld.long 0x00 15. " INFINITETX ,Applicable in RF Test Mode only_0: Normal mode of operation" "0,1"
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bitfld.long 0x00 14. " TXLENGTHSRC ,Applicable only in Tx/Rx RF Test mode_0: Normal mode of operation: TxDESC-TXADVLEN controls the Tx p.." "0,1"
bitfld.long 0x00 13. " PRBSTYPE ,Applicable only in Tx/Rx RF Test mode_0: Tx Packet Payload are PRBS9 type_1: Tx Packet Payload are P.." "0,1"
bitfld.long 0x00 12. " TXPLDSRC ,Applicable only in Tx/Rx RF Test mode_0: Tx Packet Payload source is the Control Structure_1: Tx Pac.." "0,1"
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bitfld.long 0x00 11. " TXPKTCNTEN ,Applicable in RF Test Mode only_0: Tx packet count disabled_1: Tx packet count enabled. and reported.." "0,1"
hexmask.long.word 0x00 0.--8. 1. " TXLENGTH ,Applicable only for Tx/Rx RF Test mode. and valid when BLE_RFTESTCNTL_REG[TXLENGTHSRC] = 1_Tx packet.."
group.long 0xE8++0x03
line.long 0x00 "BLE_RFTESTRXSTAT_REG,RF Testing Register"
hexmask.long 0x00 0.--31. 1. " RXPKTCNT ,Reports number of correctly received packet during Test Modes (no sync error. no CRC error)"
group.long 0xE4++0x03
line.long 0x00 "BLE_RFTESTTXSTAT_REG,RF Testing Register"
hexmask.long 0x00 0.--31. 1. " TXPKTCNT ,Reports number of transmitted packet during Test Modes"
group.long 0x00++0x03
line.long 0x00 "BLE_RWBLECNTL_REG,BLE Control register"
bitfld.long 0x00 31. " MASTER_SOFT_RST ,Reset the complete BLE Core except registers and timing generator. when written with a 1" "0,1"
bitfld.long 0x00 30. " MASTER_TGSOFT_RST ,Reset the timing generator. when written with a 1" "0,1"
bitfld.long 0x00 29. " REG_SOFT_RST ,Reset the complete register block. when written with a 1" "0,1"
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bitfld.long 0x00 28. " SWINT_REQ ,Forces the generation of ble_sw_irq when written with a 1. and proper masking is set" "0,1"
bitfld.long 0x00 26. " RFTEST_ABORT ,Abort the current RF Testing defined as per CS-FORMAT when written with a 1" "0,1"
bitfld.long 0x00 25. " ADVERT_ABORT ,Abort the current Advertising event when written with a 1" "0,1"
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bitfld.long 0x00 24. " SCAN_ABORT ,Abort the current scan window when written with a 1" "0,1"
bitfld.long 0x00 22. " MD_DSB ,0: Normal operation of MD bits management_1: Allow a single Tx/Rx exchange whatever the MD bits are" "0,1"
bitfld.long 0x00 21. " SN_DSB ,0: Normal operation of Sequence number_1: Sequence Number Management disabled:_value forced by SW fr.." "0,1"
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bitfld.long 0x00 20. " NESN_DSB ,0: Normal operation of Acknowledge_1: Acknowledge scheme disabled:_value forced by SW from Tx Descri.." "0,1"
bitfld.long 0x00 19. " CRYPT_DSB ,0: Normal operation" "0,1"
bitfld.long 0x00 18. " WHIT_DSB ,0: Normal operation" "0,1"
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bitfld.long 0x00 17. " CRC_DSB ,0: Normal operation" "0,1"
bitfld.long 0x00 16. " HOP_REMAP_DSB ,0: Normal operation" "0,1"
bitfld.long 0x00 9. " ADVERTFILT_EN ,Advertising Channels Error Filtering Enable control_0: BLE Core reports all errors to RW-BLE Softwar.." "0,1"
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bitfld.long 0x00 8. " RWBLE_EN ,0: Disable BLE Core Exchange Table pre-fetch mechanism" "0,1"
bitfld.long 0x00 4.--7. " RXWINSZDEF ,Default Rx Window size in us" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. " SYNCERR ,Indicates the maximum number of errors allowed to recognize the synchronization word" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "BLE_RWBLECONF_REG,Configuration register"
rbitfld.long 0x00 24.--29. " ADD_WIDTH ,Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 16.--22. 1. " RFIF ,Radio Interface ID"
rbitfld.long 0x00 8.--13. " CLK_SEL ,Operating Frequency (in MHz)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 6. " DECIPHER ,0: AES deciphering not present" "0,1"
rbitfld.long 0x00 5. " DMMODE ,0: BLE Core is used as a standalone BLE device" "0,1"
rbitfld.long 0x00 4. " INTMODE ,1: Interrupts are trigger level generated. i" "0,1"
newline
rbitfld.long 0x00 3. " COEX ,1: WLAN Coexistence mechanism present" "0,1"
rbitfld.long 0x00 2. " USEDBG ,1: Diagnostic port instantiated" "0,1"
rbitfld.long 0x00 1. " USECRYPT ,1: AES-CCM Encryption block present" "0,1"
newline
rbitfld.long 0x00 0. " BUSWIDTH ,Processor bus width:_1: 32 bits" "0,1"
group.long 0xDC++0x03
line.long 0x00 "BLE_RXMICVAL_REG,AES / CCM plain MIC value"
hexmask.long 0x00 0.--31. 1. " RXMICVAL ,AES-CCM plain MIC value"
group.long 0xFC++0x03
line.long 0x00 "BLE_SAMPLECLK_REG,Samples the Base Time Counter"
bitfld.long 0x00 0. " SAMP ,Writing a 1 samples the Base Time Counter value in BASETIMECNT register" "0,1"
group.long 0x64++0x03
line.long 0x00 "BLE_SWPROFILING_REG,Software Profiling register"
hexmask.long 0x00 0.--31. 1. " SWPROFVAL ,Software Profiling register: used by BLE Software for profiling purpose: this value is copied on Dia.."
group.long 0xF0++0x03
line.long 0x00 "BLE_TIMGENCNTL_REG,Timing Generator Register"
bitfld.long 0x00 31. " APFM_EN ,Controls the Anticipated pre-Fetch Abort mechanism_0: Disabled_1: Enabled" "0,1"
hexmask.long.word 0x00 16.--25. 1. " PREFETCHABORT_TIME ,Defines the instant in usec at which immediate abort is required after anticipated pre-fetch abort"
hexmask.long.word 0x00 0.--8. 1. " PREFETCH_TIME ,Defines Exchange Table pre-fetch instant in us"
group.long 0xD8++0x03
line.long 0x00 "BLE_TXMICVAL_REG,AES / CCM plain MIC value"
hexmask.long 0x00 0.--31. 1. " TXMICVAL ,AES-CCM plain MIC value"
group.long 0x04++0x03
line.long 0x00 "BLE_VERSION_REG,Version register"
hexmask.long.byte 0x00 24.--31. 1. " TYP ,BLE Core Type"
hexmask.long.byte 0x00 16.--23. 1. " REL ,BLE Core version Major release number"
hexmask.long.byte 0x00 8.--15. 1. " UPG ,BLE Core upgrade Upgrade number"
newline
hexmask.long.byte 0x00 0.--7. 1. " BUILD ,BLE Core Build Build number"
group.long 0xB8++0x03
line.long 0x00 "BLE_WLNBDEV_REG,Devices in white list"
hexmask.long.byte 0x00 8.--15. 1. " NBPRIVDEV ,Number of private devices in the white list"
hexmask.long.byte 0x00 0.--7. 1. " NBPUBDEV ,Number of public devices in the white list"
group.long 0xB4++0x03
line.long 0x00 "BLE_WLPRIVADDPTR_REG,Start address of private devices list"
hexmask.long.word 0x00 0.--15. 1. " WLPRIVADDPTR ,Start address pointer of the private devices white list"
group.long 0xB0++0x03
line.long 0x00 "BLE_WLPUBADDPTR_REG,Start address of public devices list"
hexmask.long.word 0x00 0.--15. 1. " WLPUBADDPTR ,Start address pointer of the public devices white list"
width 0x0B
tree.end
tree "CHIP_VERSION"
base ad:0x50003200
width 19.
group.word 0x00++0x01
line.word 0x00 "CHIP_ID1_REG,Chip identification register 1"
hexmask.word.byte 0x00 0.--7. 1. " CHIP_ID1 ,First character of device type _2632_ in ASCII"
group.word 0x04++0x01
line.word 0x00 "CHIP_ID2_REG,Chip identification register 2"
hexmask.word.byte 0x00 0.--7. 1. " CHIP_ID2 ,Second character of device type _2632_ in ASCII"
group.word 0x08++0x01
line.word 0x00 "CHIP_ID3_REG,Chip identification register 3"
hexmask.word.byte 0x00 0.--7. 1. " CHIP_ID3 ,Third character of device type _2632_ in ASCII"
group.word 0x0C++0x01
line.word 0x00 "CHIP_ID4_REG,Chip identification register 4"
hexmask.word.byte 0x00 0.--7. 1. " CHIP_ID4 ,Fourth character of device type _2632_ in ASCII"
group.word 0x14++0x01
line.word 0x00 "CHIP_REVISION_REG,"
hexmask.word.byte 0x00 0.--7. 1. " CHIP_REVISION ,"
group.word 0x10++0x01
line.word 0x00 "CHIP_SWC_REG,"
rbitfld.word 0x00 0.--3. " CHIP_SWC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xF8++0x01
line.word 0x00 "CHIP_TEST1_REG,"
hexmask.word.byte 0x00 0.--7. 1. " CHIP_LAYOUT_REVISION ,"
group.word 0xFC++0x01
line.word 0x00 "CHIP_TEST2_REG,"
rbitfld.word 0x00 0.--3. " CHIP_METAL_OPTION ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "CRG_AON"
base ad:0x50000300
width 20.
group.word 0x24++0x01
line.word 0x00 "GP_DATA_REG,"
bitfld.word 0x00 5.--7. " ANA_SPARE ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 4. " DISABLE_CLAMP_OVERRULE ," "0,1"
bitfld.word 0x00 0.--3. " SW_GP_DATA ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x10++0x01
line.word 0x00 "HIBERN_CTRL_REG,Hibernation control register"
bitfld.word 0x00 2.--6. " HIBERN_WKUP_MASK ,Selects which pin to wakeup from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 1. " HIBERN_WKUP_POLARITY ,Selects the polarity of the wakeup source" "0,1"
bitfld.word 0x00 0. " HIBERNATION_ENABLE ,Enables the hibernation mode when sleeping_0: deep sleep mode. PD_SLP remains on_1: hibernation mode.." "0,1"
group.word 0x00++0x01
line.word 0x00 "HWR_CTRL_REG,Hardware Reset control register"
bitfld.word 0x00 0. " DISABLE_HWR ,Disables the RST functionality on P00" "0,1"
group.word 0x0C++0x01
line.word 0x00 "PAD_LATCH_REG,Control the state retention of the GPIO ports"
bitfld.word 0x00 0. " PAD_LATCH_EN ,Controls the state retention of the pads" "0,1"
group.word 0x20++0x01
line.word 0x00 "POWER_AON_CTRL_REG,"
bitfld.word 0x00 14. " FORCE_RUNNING_COMP_DIS ," "0,1"
bitfld.word 0x00 10.--13. " LDO_RET_TRIM ,VDD clamp level setting for hibernation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 9. " CMP_VCONT_SLP_DISABLE ,Disable vcont comparator in SLP" "0,1"
newline
bitfld.word 0x00 7.--8. " BOOST_MODE_FORCE ,0x:automatic selection of boost mode_11: force boost mode_10: force buck mode" "0,1,2,3"
bitfld.word 0x00 6. " CHARGE_VBAT_DISABLE ,Do not charge vbat high in boost mode" "0,1"
bitfld.word 0x00 5. " RC32K_LOW_SPEED_FORCE ," "0,1"
newline
bitfld.word 0x00 4. " RC32K_HIGH_SPEED_FORCE ," "0,1"
bitfld.word 0x00 3. " POR_VBAT_HIGH_RST_MASK ,Mask rst from por_vbat_high" "0,1"
bitfld.word 0x00 2. " POR_VBAT_LOW_RST_MASK ,Mask rst from por_vbat_low" "0,1"
newline
bitfld.word 0x00 0.--1. " VBAT_HL_CONNECT_RES_CTRL ,00: OFF_01: Forced ON_10: Active: automatic control. Sleep: forced ON_11: Automatic control" "0,1,2,3"
group.word 0x08++0x01
line.word 0x00 "RAM_LPMX_REG,"
bitfld.word 0x00 0.--2. " RAMx_LPMX ,RAM[3:1] Transparent Light Sleep (TLS) Core Enable for System RAMs" "0,1,2,3,4,5,6,7"
group.word 0x04++0x01
line.word 0x00 "RESET_STAT_REG,Reset status register"
bitfld.word 0x00 3. " WDOGRESET_STAT ,Indicates that a Watchdog has happened" "0,1"
bitfld.word 0x00 2. " SWRESET_STAT ,Indicates that a SW Reset has been requested" "0,1"
bitfld.word 0x00 1. " HWRESET_STAT ,Indicates that a HW Reset has happened_This bit is also set with a PowerOn Reset" "0,1"
newline
bitfld.word 0x00 0. " PORESET_STAT ,Indicates that a PowerOn Reset has happened" "0,1"
group.word 0xF0++0x01
line.word 0x00 "TEST_VDD_REG,"
bitfld.word 0x00 1. " LDOS_DISABLE ," "0,1"
bitfld.word 0x00 0. " TEST_VDD ," "0,1"
width 0x0B
tree.end
tree "CRG_TIM"
base ad:0x50004200
width 16.
group.long 0x4C++0x03
line.long 0x00 "CLK_RTCDIV_REG,Divisor for RTC 100Hz clock"
bitfld.long 0x00 21. " RTC_RESET_REQ ,Reset request for the RTC module" "0,1"
bitfld.long 0x00 20. " RTC_DIV_ENABLE ,Enable for the 100 Hz generation for the RTC block" "0,1"
bitfld.long 0x00 19. " RTC_DIV_DENOM ,Selects the denominator for the fractional division:_0b0: 1000_0b1: 1024" "0,1"
newline
hexmask.long.word 0x00 10.--18. 1. " RTC_DIV_INT ,Integer divisor part for RTC 100Hz generation"
hexmask.long.word 0x00 0.--9. 1. " RTC_DIV_FRAC ,Fractional divisor part for RTC 100Hz generation"
width 0x0B
tree.end
tree "CRG_TOP"
base ad:0x50000000
width 20.
group.word 0x2A++0x01
line.word 0x00 "ANA_STATUS_REG,Status bit of analog (power management) circuits"
rbitfld.word 0x00 12. " CLKLESS_WAKEUP_STAT ,Indicates the output of the Clockless wakeup XOR tree" "0,1"
rbitfld.word 0x00 11. " FORCE_RUNNING ," "0,1"
rbitfld.word 0x00 10. " LDO_GPADC_OK ,Indicates that LDO_GPADC output is OK" "0,1"
newline
rbitfld.word 0x00 9. " LDO_XTAL_OK ,Indicates that LDO_XTAL output is OK" "0,1"
rbitfld.word 0x00 8. " BOOST_SELECTED ,0: Buck mode detected_1: Boost mode detected" "0,1"
rbitfld.word 0x00 7. " POR_VBAT_HIGH ,Output of VBAT_HIGH supply rail voltage monitoring circuit" "0,1"
newline
rbitfld.word 0x00 6. " POR_VBAT_LOW ,Output of VBAT_LOW supply rail voltage monitoring circuit" "0,1"
rbitfld.word 0x00 5. " BANDGAP_OK ,Indicates that BANDGAP is OK" "0,1"
rbitfld.word 0x00 4. " COMP_VBAT_HIGH_NOK ,Indicates that VBAT_HIGH < VBAT_LOW -50 mV" "0,1"
newline
rbitfld.word 0x00 3. " COMP_VBAT_HIGH_OK ,Indicates that VBAT_HIGH > VBAT_LOW +50 mV" "0,1"
rbitfld.word 0x00 2. " DCDC_OK ,Indicates that VBAT_LOW (buck mode) or VBAT_HIGH (boost mode) is OK" "0,1"
rbitfld.word 0x00 1. " LDO_LOW_OK ,Indicates that LDO_LOW output is OK_(only valid for high current mode)" "0,1"
newline
rbitfld.word 0x00 0. " LDO_CORE_OK ,Indicates that LDO_CORE output is OK" "0,1"
group.word 0x28++0x01
line.word 0x00 "BANDGAP_REG,Bandgap trimming"
bitfld.word 0x00 5.--9. " BGR_ITRIM ,Trim setting for bandgap bias current_10000 -> -25%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--4. " BGR_TRIM ,Trim setting for bandgap voltage_10000 -> -6.4%_...._11111 -> ~0%_00000 -> ~0% (typ)_..._01111 -> +5.8%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x00++0x01
line.word 0x00 "CLK_AMBA_REG,HCLK. PCLK. divider and clock gates"
bitfld.word 0x00 7. " OTP_ENABLE ,Clock enable for OTP controller" "0,1"
bitfld.word 0x00 4.--5. " PCLK_DIV ,APB interface clock (PCLK)" "0,1,2,3"
bitfld.word 0x00 0.--1. " HCLK_DIV ,AHB interface and microprocessor clock (HCLK)" "0,1,2,3"
group.word 0x0A++0x01
line.word 0x00 "CLK_CTRL_REG,Clock control register"
rbitfld.word 0x00 7. " RUNNING_AT_XTAL32M ,Indicates that the XTAL32M clock is used as clock. and may not be switched off" "0,1"
rbitfld.word 0x00 6. " RUNNING_AT_RC32M ,Indicates that the RC32M clock is used as clock" "0,1"
rbitfld.word 0x00 5. " RUNNING_AT_LP_CLK ,Indicates that either the LP_CLK is being used as system clock" "0,1"
newline
bitfld.word 0x00 3.--4. " LP_CLK_SEL ,Sets the clock source of the LowerPower clock_0x0: RC32K_0x1: RCX_0x2: XTAL32K through the oscillato.." "0,1,2,3"
bitfld.word 0x00 2. " XTAL32M_DISABLE ,Setting this bit instantaneously disables the 32 MHz crystal oscillator" "0,1"
bitfld.word 0x00 0.--1. " SYS_CLK_SEL ,Selects the clock source" "0,1,2,3"
group.word 0x02++0x01
line.word 0x00 "CLK_FREQ_TRIM_REG,Xtal frequency trimming register"
hexmask.word.byte 0x00 0.--7. 1. " XTAL32M_TRIM ,Xtal frequency fine trimming register"
group.word 0x04++0x01
line.word 0x00 "CLK_PER_REG,Peripheral divider register"
bitfld.word 0x00 11. " QUAD_ENABLE ,Enable the Quadrature clock" "0,1"
bitfld.word 0x00 10. " SPI_ENABLE ,Enable SPI clock" "0,1"
bitfld.word 0x00 7. " UART1_ENABLE ,Enable UART1 clock" "0,1"
newline
bitfld.word 0x00 6. " UART2_ENABLE ,Enable UART2 clock" "0,1"
bitfld.word 0x00 5. " I2C_ENABLE ,Enable I2C clock" "0,1"
bitfld.word 0x00 4. " WAKEUPCT_ENABLE ,Enable Wakeup CaptureTimer clock" "0,1"
newline
bitfld.word 0x00 3. " TMR_ENABLE ,Enable TIMER0 and TIMER2 clock" "0,1"
bitfld.word 0x00 0.--1. " TMR_DIV ,Division factor for TIMER0_0x0: divide by 1_0x1: divide by 2_0x2: divide by 4_0x3: divide by 8" "0,1,2,3"
group.word 0x08++0x01
line.word 0x00 "CLK_RADIO_REG,Radio PLL control register"
bitfld.word 0x00 7. " BLE_ENABLE ,Enable the BLE core clocks" "0,1"
bitfld.word 0x00 6. " BLE_LP_RESET ,Reset for the BLE LP timer" "0,1"
bitfld.word 0x00 4.--5. " BLE_DIV ,Division factor for BLE core blocks_0x0: divide by 1_0x1: divide by 2_0x2: divide by 4_0x3: divide b.." "0,1,2,3"
newline
bitfld.word 0x00 3. " RFCU_ENABLE ,Enable the RF control Unit clock" "0,1"
group.word 0x20++0x01
line.word 0x00 "CLK_RC32K_REG,32 kHz RC oscillator register"
bitfld.word 0x00 1.--4. " RC32K_TRIM ,0000 = lowest frequency_0111 = default_1111 = highest frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0. " RC32K_DISABLE ,Instantly disables the 32kHz RC oscillator_Sleep cycles cannot happen with this clock disabled" "0,1"
group.word 0x24++0x01
line.word 0x00 "CLK_RC32M_REG,Fast RC control register"
bitfld.word 0x00 7.--10. " RC32M_COSC ,C-adjust of RC-oscillator_A higher value of COSC results in a lower frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 5.--6. " RC32M_RANGE ,Coarse adjust_A higher value of RANGE results in a higher frequency. values 2 and 3 are equal" "0,1,2,3"
bitfld.word 0x00 1.--4. " RC32M_BIAS ,Bias adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 0. " RC32M_DISABLE ,Instantly disables the 32MHz RC oscillator_Disabling of the oscillator during sleep happens automati.." "0,1"
group.word 0x26++0x01
line.word 0x00 "CLK_RCX_REG,RCX-oscillator control register"
bitfld.word 0x00 8.--11. " RCX_BIAS ,LDO bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 7. " RCX_C0 ,Add unit capacitance to RC-time delay" "0,1"
bitfld.word 0x00 2.--6. " RCX_CADJUST ,Adjust capacitance part of RC-time delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 1. " RCX_RADJUST ,Adjust resistance part of RC-time delay" "0,1"
bitfld.word 0x00 0. " RCX_ENABLE ,Enable the RCX oscillator" "0,1"
group.word 0x22++0x01
line.word 0x00 "CLK_XTAL32K_REG,32 kHz XTAL oscillator register"
bitfld.word 0x00 8. " XTAL32K_XTAL1_BIAS_DISABLE ," "0,1"
bitfld.word 0x00 7. " XTAL32K_DISABLE_AMPREG ,Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator" "0,1"
bitfld.word 0x00 3.--6. " XTAL32K_CUR ,Bias current for the 32kHz XTAL oscillator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.word 0x00 1.--2. " XTAL32K_RBIAS ,Setting for the bias resistor" "0,1,2,3"
bitfld.word 0x00 0. " XTAL32K_ENABLE ,Enables the 32kHz XTAL oscillator" "0,1"
group.word 0x10++0x01
line.word 0x00 "PMU_CTRL_REG,Power Management Unit control register"
bitfld.word 0x00 6. " MAP_BANDGAP_EN ,Enable wakeup diagnostics mapping" "0,1"
bitfld.word 0x00 4.--5. " OTP_COPY_DIV ,Sets the HCLK division during OTP mirroring" "0,1,2,3"
bitfld.word 0x00 2. " RADIO_SLEEP ,Put the digital part of the radio in powerdown" "0,1"
newline
bitfld.word 0x00 1. " TIM_SLEEP ,Put PD_TIM in powerdown" "0,1"
bitfld.word 0x00 0. " RESET_ON_WAKEUP ,Perform a Hardware Reset after waking up" "0,1"
group.word 0x50++0x01
line.word 0x00 "PMU_SLEEP_REG,Bandgap refresh interval during sleep"
hexmask.word 0x00 0.--11. 1. " BG_REFRESH_INTERVAL ,Defines the refresh interval of reference voltages (bandgap activation and sampling). in units of 2m.."
group.word 0x40++0x01
line.word 0x00 "POR_PIN_REG,Selects a GPIO pin for POR generation"
bitfld.word 0x00 7. " POR_PIN_POLARITY ,0: Active Low_1: Active High_Note: This applies only for the GPIO pin" "0,1"
bitfld.word 0x00 0.--3. " POR_PIN_SELECT ,Selects the GPIO which is used for POR generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x42++0x01
line.word 0x00 "POR_TIMER_REG,Time for POR to happen"
hexmask.word.byte 0x00 0.--6. 1. " POR_TIME ,Time for the POReset to happen"
group.word 0x52++0x01
line.word 0x00 "POWER_CTRL_REG,Power management control"
bitfld.word 0x00 15. " VBAT_HL_CONNECT_MODE ,Sets the control mode fo the switch between VBAT_HIGH and VBAT_LOW_0: Manual (default)_1: Automatic .." "0,1"
bitfld.word 0x00 14. " POR_VBAT_HIGH_HYST_DIS ," "0,1"
bitfld.word 0x00 13. " POR_VBAT_HIGH_HYST_SEL ," "0,1"
newline
bitfld.word 0x00 12. " POR_VBAT_HIGH_DISABLE ,Disable por_vbat_high circuit" "0,1"
bitfld.word 0x00 11. " POR_VBAT_LOW_HYST_DIS ," "0,1"
bitfld.word 0x00 10. " POR_VBAT_LOW_HYST_SEL ," "0,1"
newline
bitfld.word 0x00 9. " POR_VBAT_LOW_DISABLE ,Disable por_vbat_low circuit" "0,1"
bitfld.word 0x00 8. " CP_DISABLE ,Disables LDO_CORE charge-pump circuit" "0,1"
bitfld.word 0x00 7. " LDO_VREF_HOLD_FORCE ,Forces LDO references in HOLD mode" "0,1"
newline
bitfld.word 0x00 5.--6. " LDO_LOW_CTRL_REG ,00: High-current mode in active. LDO_LOW OFF in sleep_01: LDO_LOW OFF_10: Low-current mode in active.." "0,1,2,3"
bitfld.word 0x00 4. " LDO_CORE_DISABLE ,Disables LDO_CORE" "0,1"
bitfld.word 0x00 3. " LDO_CORE_RET_ENABLE ,LDO_CORE_RETENTION_0: Disabled_1: Enabled" "0,1"
newline
bitfld.word 0x00 2. " VBAT_HL_CONNECT ,Switch between VBAT_HIGH and VBAT_LOW_0: Open_1: Closed" "0,1"
bitfld.word 0x00 1. " CMP_VBAT_HIGH_OK_ENABLE ,Enable cmp_vbat_high_ok" "0,1"
bitfld.word 0x00 0. " CMP_VBAT_HIGH_NOK_ENABLE ,Enable cmp_vbat_high_nok" "0,1"
group.word 0x54++0x01
line.word 0x00 "POWER_LEVEL_REG,Power management level and trim settings"
bitfld.word 0x00 11.--13. " DCDC_TRIM ,Delta from DCDC_LEVEL nominal value_000: -75 mV_001: -50 mV_010: -25 mV_011: 0 (default)_100: +25 mV.." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 9.--10. " DCDC_LEVEL ,00: 1.1 V_01: 1.8 V (default)_10: 2.5 V_11: 3.0 V" "0,1,2,3"
bitfld.word 0x00 7.--8. " LDO_CORE_RET_CUR_TRIM ," "0,1,2,3"
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bitfld.word 0x00 4.--6. " LDO_XTAL_TRIM ,Delta from 0.9 V nominal value_000: -75 mV_001: -50 mV_010: -25 mV_011: 0 (default)_100: +25 mV_101: +50 mV_110: +75 mV_111: +100 mV" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 1.--3. " LDO_LOW_TRIM ,Delta from 1.1 V nominal value_000: -75 mV_001: -50 mV_010: -25 mV_011: 0 (default)_100: +25 mV_101: +50 mV_110: +75 mV_111: +100 mV (coldboot)" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0. " LDO_CORE_LEVEL ," "0,1"
group.word 0x18++0x01
line.word 0x00 "RAM_PWR_CTRL_REG,Control power state of System RAMS"
bitfld.word 0x00 4.--5. " RAM3_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3"
bitfld.word 0x00 2.--3. " RAM2_PWR_CTRL ,See description of RAM1_PWR_CTRL" "0,1,2,3"
bitfld.word 0x00 0.--1. " RAM1_PWR_CTRL ,Power state control of the individual RAMs" "0,1,2,3"
group.word 0x12++0x01
line.word 0x00 "SYS_CTRL_REG,System Control register"
bitfld.word 0x00 15. " SW_RESET ,Writing a '1' to this bit will reset the device. except for:_SYS_CTRL_REG_CLK_FREQ_TRIM_REG" "0,1"
bitfld.word 0x00 10. " TIMEOUT_DISABLE ,Disables timeout in Power statemachine" "0,1"
bitfld.word 0x00 7.--8. " DEBUGGER_ENABLE ,Enable the debugger" "0,1,2,3"
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bitfld.word 0x00 6. " OTPC_RESET_REQ ,Reset request for the OTP controller" "0,1"
bitfld.word 0x00 4. " OTP_COPY ,Enables OTP to SysRAM copy action after waking up PD_SYS" "0,1"
bitfld.word 0x00 2. " DEV_PHASE ,Sets the development phase mode" "0,1"
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bitfld.word 0x00 0.--1. " REMAP_ADR0 ,Controls which memory is located at address 0x0000 for execution" "0,1,2,3"
group.word 0x14++0x01
line.word 0x00 "SYS_STAT_REG,System status register"
rbitfld.word 0x00 7. " XTAL32M_SETTLED ,Indicates that XTAL32M has had its settle time. as defined by TRIM_CTRL_REG[XTAL_SETTLE_N]" "0,1"
rbitfld.word 0x00 6. " XTAL32M_TRIM_READY ,Indicates that XTAL trimming mechanism is ready. i" "0,1"
rbitfld.word 0x00 4. " DBG_IS_UP ,Indicates that the SW debugger is attached and in connection with the ARM" "0,1"
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rbitfld.word 0x00 3. " TIM_IS_UP ,Indicates that PD_TIM is functional" "0,1"
rbitfld.word 0x00 2. " TIM_IS_DOWN ,Indicates that PD_TIM is in power down" "0,1"
rbitfld.word 0x00 1. " RAD_IS_UP ,Indicates that PD_RAD is functional" "0,1"
newline
rbitfld.word 0x00 0. " RAD_IS_DOWN ,Indicates that PD_RAD is in power down" "0,1"
group.word 0x16++0x01
line.word 0x00 "TRIM_CTRL_REG,Control trimming of the XTAL32M"
bitfld.word 0x00 8.--13. " XTAL_SETTLE_N ,Designates that the XTAL can be safely used as the CPU clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 6.--7. " XTAL_TRIM_SELECT ,Select which source controls the XTAL trimming_0b00: xtal counter" "0,1,2,3"
bitfld.word 0x00 0.--5. " XTAL_COUNT_N ,Defines the number of XTAL cycles to be counted. before the xtal trimming is applied. in steps of 64.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x38++0x01
line.word 0x00 "XTAL32M_CTRL0_REG,Control bits for XTAL32M"
bitfld.word 0x00 8.--9. " XTAL32M_SPARE ," "0,1,2,3"
bitfld.word 0x00 5.--7. " CORE_AMPL_TRIM ,Core amplitude trimming" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 2.--4. " CORE_CUR_SET ,Core current trim setting" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 1. " CORE_AMPL_REG_NULLBIAS ,Keep bias in ampl detector alive. even when there is a large drive" "0,1"
bitfld.word 0x00 0. " DCBLOCK_ENABLE ,Enable dcblock/high pass filter circuit" "0,1"
group.word 0x30++0x01
line.word 0x00 "XTAL32M_START_REG,Trim values for XTAL32M"
hexmask.word.byte 0x00 8.--15. 1. " XTAL32M_RAMP ,Xtal frequency trimming register"
hexmask.word.byte 0x00 0.--7. 1. " XTAL32M_START ,Xtal frequency trimming register"
group.word 0x32++0x01
line.word 0x00 "XTAL32M_TRSTAT_REG,Read back value of current XTAL trimming"
hexmask.word.byte 0x00 0.--7. 1. " XTAL32M_TRSTAT ,Reads value of the current XTAL trimming"
group.word 0x34++0x01
line.word 0x00 "XTALRDY_CTRL_REG,Control register for XTALRDY IRQ"
hexmask.word.byte 0x00 0.--7. 1. " XTALRDY_CNT ,Number of 32kHz cycles between the crystal is enabled. and the XTALRDY_IRQ is fired"
group.word 0x36++0x01
line.word 0x00 "XTALRDY_STAT_REG,"
hexmask.word.byte 0x00 0.--7. 1. " XTALRDY_STAT ,"
width 0x0B
tree.end
tree "DCDC"
base ad:0x50000080
width 18.
group.word 0x00++0x01
line.word 0x00 "DCDC_CTRL_REG"
bitfld.word 0x00 12.--15. " DCDC_ILIM_MAX ,Maximum value for automatic inductor peak current limit control" "6 mA,12 mA,18 mA,24 mA,30 mA,36 mA,42 mA,48 mA,54 mA (default),60 mA,66 mA,72 mA,78 mA,84 mA,90 mA,96 mA (batt)"
bitfld.word 0x00 8.--11. " DCDC_ILIM_MIN ,Minimum value for automatic inductor peak current limit control" "6 mA,12 mA,18 mA,24 mA,30 mA (default),36 mA,42 mA,48 mA,54 mA,60 mA,66 mA,72 mA,78 mA,84 mA,90 mA,96 mA"
newline
bitfld.word 0x00 6.--7. " DCDC_OK_CLR_CNT ,Number of subsequent V_NOK events to reset VDCD_OK." "2,4,8 (def),15"
bitfld.word 0x00 3.--5. " DCDC_TIMEOUT ,Switch timeout-go to next state if either switch is active for longer th.." "Disabled,0.25 ms,0.50 ms,0.75 ms,1.00 ms (default),1.25 ms,1.50 ms,1.75 ms"
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bitfld.word 0x00 1.--2. " DCDC_CLK_DIV ,Idle clock divider-sets output monitor rate" "/4,/8,/16,/32"
bitfld.word 0x00 0. " DCDC_ENABLE ,Enables hardware control of the DCDC converter." "Disabled,HW control"
rgroup.word 0x06++0x01
line.word 0x00 "DCDC_STATUS1_REG"
rbitfld.word 0x00 12.--15. " DCDC_FSM_STATE ,State of the analog FSM" "Idle,Buck mode-PSW,Buck mode-NSW,Unused,Boost mode-PSW,Unused,Unused,Unused,Boost mode-NSW,Unused,Unused,Unused,Unused,Unused,Unused,Unused"
rbitfld.word 0x00 10.--11. " DCDC_SW_STATE ,State of the DCDC switches" "Both switches open,P switch closed,N switch closed,Unused"
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rbitfld.word 0x00 9. " DCDC_VOUT_NOK ,NOK signal from output comparator."
rbitfld.word 0x00 8. " DCDC_VOUT_OK ,OK signal from output comparator."
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hexmask.word 0x00 4.--7. " DCDC_ILIM ,Actual inductor peak current limit."
rbitfld.word 0x00 3. " DCDC_BOOST_MODE ,Indicates that the converter is in boost mode."
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rbitfld.word 0x00 2. " DCDC_STARTUP_COMPLETE ,Indicates that DCDC converter is enabled and startup delay of 4 ms has passed."
rbitfld.word 0x00 1. " DCDC_ENABLED ,Value of the analog enable signal-depends on both register setting and external enable input."
rbitfld.word 0x00 0. " DCDC_VDCDC_OK ,Becomes high if the output voltage is OK-resets after a programmable number of subsequent NOK events."
rgroup.word 0x08++0x01
line.word 0x00 "DCDC_STATUS2_REG"
hexmask.word 0x00 8.--13. " DCDC_COMP_TRIM ,Actual comparator trim value."
rbitfld.word 0x00 7. " DCDC_TIMEOUT_PSW ,Timeout signal for P switch."
rbitfld.word 0x00 6. " DCDC_TIMEOUT_NSW ,Timeout signal for N switch."
newline
rbitfld.word 0x00 5. " DCDC_COMP_P_DYN_P ,P Output of P side dynamic comparator."
rbitfld.word 0x00 4. " DCDC_COMP_P_DYN_N ,N Output of P side dynamic comparator."
rbitfld.word 0x00 3. " DCDC_COMP_P_CONT ,Output of P side continuous time comparator."
newline
rbitfld.word 0x00 2. " DCDC_COMP_N_DYN_P ,P Output of N side dynamic comparator."
rbitfld.word 0x00 1. " DCDC_COMP_N_DYN_N ,N Output of N side dynamic comparator."
rbitfld.word 0x00 0. " DCDC_COMP_N_CONT ,Output of N side continuous time comparator."
group.word 0x02++0x01
line.word 0x00 "DCDC_TEST1_REG"
bitfld.word 0x00 12.--14. " DCDC_DIG_TST_SEL ,Controls digital test outputs." "Disabled,Lower byte STAT1,Upper byte STAT1,Lower byte STAT2,Upper byte STAT2,Reserved,Reserved,Reserved"
bitfld.word 0x00 8.--11. " DCDC_ILIM_VAL ,Value of the inductor peak current limit when manually controlled."
bitfld.word 0x00 7. " DCDC_COMP_CLK_VAL ,Value of the output comparator clock when manually controlled."
newline
bitfld.word 0x00 6. " DCDC_FORCE_ILIM ,Enables manual control of the inductor peak current limit."
bitfld.word 0x00 5. " DCDC_FORCE_COMP_TRIM ,Enables manual control of the comparator trim value."
bitfld.word 0x00 4. " DCDC_FORCE_COMP_CLK ,Enables manual control of the output comparator clock."
newline
bitfld.word 0x00 2.--3. " DCDC_SW_TST ,Switch test mode" "Normal mode,Force P,Force N,Unused"
bitfld.word 0x00 1. " DCDC_FORCE_TRIG ,Forces a trigger event in the analog FSM."
bitfld.word 0x00 0. " DCDC_FORCE_IDLE ,Forces the DCDC in idle mode-current conversion is finished first."
group.word 0x04++0x01
line.word 0x00 "DCDC_TEST2_REG"
hexmask.word 0x00 0.--5. " DCDC_COMP_TRIM_VAL ,Value of the comparator trim setting when manually controlled."
width 0x0B
tree.end
tree "DMA"
base ad:0x50003600
width 20.
group.word 0x02++0x01
line.word 0x00 "DMA0_A_STARTH_REG,Start address High A of DMA channel 0"
hexmask.word 0x00 0.--15. " DMA0_A_STARTH ,Source start address upper 16 bits "
group.word 0x00++0x01
line.word 0x00 "DMA0_A_STARTL_REG,Start address Low A of DMA channel 0"
hexmask.word 0x00 0.--15. " DMA0_A_STARTL ,Source start address lower 16 bits "
group.word 0x06++0x01
line.word 0x00 "DMA0_B_STARTH_REG,Start address High B of DMA channel 0"
hexmask.word 0x00 0.--15. " DMA0_B_STARTH ,Destination start address upper 16 bits "
group.word 0x04++0x01
line.word 0x00 "DMA0_B_STARTL_REG,Start address Low B of DMA channel 0"
hexmask.word 0x00 0.--15. " DMA0_B_STARTL ,Destination start address lower 16 bits "
group.word 0x0c++0x01
line.word 0x00 "DMA0_CTRL_REG,Control register for the DMA channel 0"
bitfld.word 0x00 13. " REQ_SENSE " "Level-sensitive requests(default),Pos. edge-sensitive requests"
newline
bitfld.word 0x00 12. " DMA_INIT " "Like memcpy,Like memset"
newline
bitfld.word 0x00 11. " DMA_IDLE " "Blocking mode,Interrupting mode"
newline
bitfld.word 0x00 8.--10. " DMA_PRIO ,Priority level. The greater the value the higher the priority."
newline
bitfld.word 0x00 7. " CIRCULAR ,Normal mode stops after transfer of size DMAx_LEN_REG. Circular mode functions if DREQ_MODE = 1" "Normal mode,Circular mode"
newline
bitfld.word 0x00 6. " AINC ,Enable increment of source address." "no increment,increment by BW"
newline
bitfld.word 0x00 5. " BINC ,Enable increment of destination address." "no increment,increment by BW"
newline
bitfld.word 0x00 4. " DREQ_MODE " "Channel starts immediately,Channel triggered by peripheral DMA request"
newline
bitfld.word 0x00 3. " IRQ_ENABLE " "Disable,Enable"
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bitfld.word 0x00 1.--2. " BW ,Bus transfer width (bytes)" "1 byte (UART/8b SPI),2 bytes (I2C/16b SPI),4 bytes (Mem-to-Mem),Reserved"
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bitfld.word 0x00 0. " DMA_ON ,Auto-clears. In circular mode this bit stays set." "Off,Enabled"
rgroup.word 0x0e++0x01
line.word 0x00 "DMA0_IDX_REG,Index value of DMA channel 0"
decmask.word 0x00 0.--15. " DMA0_IDX ,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer. When the transfer is completed the register is automatically reset to 0."
group.word 0x08++0x01
line.word 0x00 "DMA0_INT_REG,DMA receive interrupt register channel 0"
decmask.word 0x00 0.--15. " DMA0_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented."
group.word 0x0a++0x01
line.word 0x00 "DMA0_LEN_REG,DMA receive length register channel 0"
decmask.word 0x00 0.--15. 1. 1. " DMA0_LEN ,DMA channel transfer length. DMAx_LEN 0, 1, 2... results in an actual transfer length 1, 2, 3..."
group.word 0x12++0x01
line.word 0x00 "DMA1_A_STARTH_REG,Start address High A of DMA channel 1"
hexmask.word 0x00 0.--15. " DMA1_A_STARTH ,Source start address upper 16 bits "
group.word 0x10++0x01
line.word 0x00 "DMA1_A_STARTL_REG,Start address Low A of DMA channel 1"
hexmask.word 0x00 0.--15. " DMA1_A_STARTL ,Source start address lower 16 bits "
group.word 0x16++0x01
line.word 0x00 "DMA1_B_STARTH_REG,Start address High B of DMA channel 1"
hexmask.word 0x00 0.--15. " DMA1_B_STARTH ,Destination start address upper 16 bits "
group.word 0x14++0x01
line.word 0x00 "DMA1_B_STARTL_REG,Start address Low B of DMA channel 1"
hexmask.word 0x00 0.--15. " DMA1_B_STARTL ,Destination start address lower 16 bits "
group.word 0x1c++0x01
line.word 0x00 "DMA1_CTRL_REG,Control register for the DMA channel 1"
bitfld.word 0x00 13. " REQ_SENSE " "Level-sensitive requests(default),Pos. edge-sensitive requests"
newline
bitfld.word 0x00 12. " DMA_INIT " "Like memcpy,Like memset"
newline
bitfld.word 0x00 11. " DMA_IDLE " "Blocking mode,Interrupting mode"
newline
bitfld.word 0x00 8.--10. " DMA_PRIO ,Priority level. The greater the value the higher the priority."
newline
bitfld.word 0x00 7. " CIRCULAR ,Normal mode stops after transfer of size DMAx_LEN_REG. Circular mode functions if DREQ_MODE = 1" "Normal mode,Circular mode"
newline
bitfld.word 0x00 6. " AINC ,Enable increment of source address." "no increment,increment by BW"
newline
bitfld.word 0x00 5. " BINC ,Enable increment of destination address." "no increment,increment by BW"
newline
bitfld.word 0x00 4. " DREQ_MODE " "Channel starts immediately,Channel triggered by peripheral DMA request"
newline
bitfld.word 0x00 3. " IRQ_ENABLE " "Disable,Enable"
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bitfld.word 0x00 1.--2. " BW ,Bus transfer width (bytes)" "1 byte (UART/8b SPI),2 bytes (I2C/16b SPI),4 bytes (Mem-to-Mem),Reserved"
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bitfld.word 0x00 0. " DMA_ON ,Auto-clears. In circular mode this bit stays set." "Off,Enabled"
rgroup.word 0x1e++0x01
line.word 0x00 "DMA1_IDX_REG,Index value of DMA channel 1"
decmask.word 0x00 0.--15. " DMA1_IDX ,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer. When the transfer is completed the register is automatically reset to 0."
group.word 0x18++0x01
line.word 0x00 "DMA1_INT_REG,DMA receive interrupt register channel 1"
decmask.word 0x00 0.--15. " DMA1_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented."
group.word 0x1a++0x01
line.word 0x00 "DMA1_LEN_REG,DMA receive length register channel 1"
decmask.word 0x00 0.--15. 1. 1. " DMA1_LEN ,DMA channel transfer length. DMAx_LEN 0, 1, 2... results in an actual transfer length 1, 2, 3..."
group.word 0x22++0x01
line.word 0x00 "DMA2_A_STARTH_REG,Start address High A of DMA channel 2"
hexmask.word 0x00 0.--15. " DMA2_A_STARTH ,Source start address upper 16 bits "
group.word 0x20++0x01
line.word 0x00 "DMA2_A_STARTL_REG,Start address Low A of DMA channel 2"
hexmask.word 0x00 0.--15. " DMA2_A_STARTL ,Source start address lower 16 bits "
group.word 0x26++0x01
line.word 0x00 "DMA2_B_STARTH_REG,Start address High B of DMA channel 2"
hexmask.word 0x00 0.--15. " DMA2_B_STARTH ,Destination start address upper 16 bits "
group.word 0x24++0x01
line.word 0x00 "DMA2_B_STARTL_REG,Start address Low B of DMA channel 2"
hexmask.word 0x00 0.--15. " DMA2_B_STARTL ,Destination start address lower 16 bits "
group.word 0x2c++0x01
line.word 0x00 "DMA2_CTRL_REG,Control register for the DMA channel 2"
bitfld.word 0x00 13. " REQ_SENSE " "Level-sensitive requests(default),Pos. edge-sensitive requests"
newline
bitfld.word 0x00 12. " DMA_INIT " "Like memcpy,Like memset"
newline
bitfld.word 0x00 11. " DMA_IDLE " "Blocking mode,Interrupting mode"
newline
bitfld.word 0x00 8.--10. " DMA_PRIO ,Priority level. The greater the value the higher the priority."
newline
bitfld.word 0x00 7. " CIRCULAR ,Normal mode stops after transfer of size DMAx_LEN_REG. Circular mode functions if DREQ_MODE = 1" "Normal mode,Circular mode"
newline
bitfld.word 0x00 6. " AINC ,Enable increment of source address." "no increment,increment by BW"
newline
bitfld.word 0x00 5. " BINC ,Enable increment of destination address." "no increment,increment by BW"
newline
bitfld.word 0x00 4. " DREQ_MODE " "Channel starts immediately,Channel triggered by peripheral DMA request"
newline
bitfld.word 0x00 3. " IRQ_ENABLE " "Disable,Enable"
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bitfld.word 0x00 1.--2. " BW ,Bus transfer width (bytes)" "1 byte (UART/8b SPI),2 bytes (I2C/16b SPI),4 bytes (Mem-to-Mem),Reserved"
newline
bitfld.word 0x00 0. " DMA_ON ,Auto-clears. In circular mode this bit stays set." "Off,Enabled"
rgroup.word 0x2e++0x01
line.word 0x00 "DMA2_IDX_REG,Index value of DMA channel 2"
decmask.word 0x00 0.--15. " DMA2_IDX ,This (read-only) register determines the data items currently fetched by the DMA channel during an on-going transfer. When the transfer is completed the register is automatically reset to 0."
group.word 0x28++0x01
line.word 0x00 "DMA2_INT_REG,DMA receive interrupt register channel 2"
decmask.word 0x00 0.--15. " DMA2_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented."
group.word 0x2a++0x01
line.word 0x00 "DMA2_LEN_REG,DMA receive length register channel 2"
decmask.word 0x00 0.--15. 1. 1. " DMA2_LEN ,DMA channel transfer length. DMAx_LEN 0, 1, 2... results in an actual transfer length 1, 2, 3..."
group.word 0x32++0x01
line.word 0x00 "DMA3_A_STARTH_REG,Start address High A of DMA channel 3"
hexmask.word 0x00 0.--15. " DMA3_A_STARTH ,Source start address upper 16 bits "
group.word 0x30++0x01
line.word 0x00 "DMA3_A_STARTL_REG,Start address Low A of DMA channel 3"
hexmask.word 0x00 0.--15. " DMA3_A_STARTL ,Source start address lower 16 bits "
group.word 0x36++0x01
line.word 0x00 "DMA3_B_STARTH_REG,Start address High B of DMA channel 3"
hexmask.word 0x00 0.--15. " DMA3_B_STARTH ,Destination start address upper 16 bits "
group.word 0x34++0x01
line.word 0x00 "DMA3_B_STARTL_REG,Start address Low B of DMA channel 3"
hexmask.word 0x00 0.--15. " DMA3_B_STARTL ,Destination start address lower 16 bits "
group.word 0x3c++0x01
line.word 0x00 "DMA3_CTRL_REG,Control register for the DMA channel 3"
bitfld.word 0x00 13. " REQ_SENSE " "Level-sensitive requests(default),Pos. edge-sensitive requests"
newline
bitfld.word 0x00 12. " DMA_INIT " "Like memcpy,Like memset"
newline
bitfld.word 0x00 11. " DMA_IDLE " "Blocking mode,Interrupting mode"
newline
bitfld.word 0x00 8.--10. " DMA_PRIO ,Priority level. The greater the value the higher the priority."
newline
bitfld.word 0x00 7. " CIRCULAR ,Normal mode stops after transfer of size DMAx_LEN_REG. Circular mode functions if DREQ_MODE = 1" "Normal mode,Circular mode"
newline
bitfld.word 0x00 6. " AINC ,Enable increment of source address." "no increment,increment by BW"
newline
bitfld.word 0x00 5. " BINC ,Enable increment of destination address." "no increment,increment by BW"
newline
bitfld.word 0x00 4. " DREQ_MODE " "Channel starts immediately,Channel triggered by peripheral DMA request"
newline
bitfld.word 0x00 3. " IRQ_ENABLE " "Disable,Enable"
newline
bitfld.word 0x00 1.--2. " BW ,Bus transfer width (bytes)" "1 byte (UART/8b SPI),2 bytes (I2C/16b SPI),4 bytes (Mem-to-Mem),Reserved"
newline
bitfld.word 0x00 0. " DMA_ON ,Auto-clears. In circular mode this bit stays set." "Off,Enabled"
rgroup.word 0x3e++0x01
line.word 0x00 "DMA3_IDX_REG,Index value of DMA channel 3"
decmask.word 0x00 0.--15. " DMA3_IDX ,This (read-only) register determines the data items currently fetched by the DMA channel"
group.word 0x38++0x01
line.word 0x00 "DMA3_INT_REG,DMA receive interrupt register channel 3"
decmask.word 0x00 0.--15. " DMA3_INT ,Number of transfers until an interrupt is generated. The interrupt is generated after a transfer if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented."
group.word 0x3a++0x01
line.word 0x00 "DMA3_LEN_REG,DMA receive length register channel 3"
decmask.word 0x00 0.--15. 1. 1. " DMA3_LEN ,DMA channel transfer length. DMAx_LEN 0, 1, 2... results in an actual transfer length 1, 2, 3..."
wgroup.word 0x84++0x01
line.word 0x00 "DMA_CLEAR_INT_REG,DMA clear interrupt register"
bitfld.word 0x00 3. " DMA_RST_IRQ_CH3,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 3" "0,1"
newline
bitfld.word 0x00 2. " DMA_RST_IRQ_CH2,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 2" "0,1"
newline
bitfld.word 0x00 1. " DMA_RST_IRQ_CH1,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 1" "0,1"
newline
bitfld.word 0x00 0. " DMA_RST_IRQ_CH0,Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 0" "0,1"
rgroup.word 0x82++0x01
line.word 0x00 "DMA_INT_STATUS_REG,DMA interrupt status register"
rbitfld.word 0x00 3. " DMA_IRQ_CH3 " "IRQ on channel 3 is not set,IRQ on channel 3 is set"
newline
rbitfld.word 0x00 2. " DMA_IRQ_CH2 " "IRQ on channel 2 is not set,IRQ on channel 2 is set"
newline
rbitfld.word 0x00 1. " DMA_IRQ_CH1 " "IRQ on channel 1 is not set,IRQ on channel 1 is set"
newline
rbitfld.word 0x00 0. " DMA_IRQ_CH0 " "IRQ on channel 0 is not set,IRQ on channel 0 is set"
group.word 0x80++0x01
line.word 0x00 "DMA_REQ_MUX_REG,DMA channel assignments"
hexmask.word 0x00 4.--7. " DMA23_SEL ,Select which combination of peripherals are mapped"
newline
hexmask.word 0x00 0.--3. " DMA01_SEL ,Select which combination of peripherals are mapped"
width 0x0B
tree.end
tree "GPADC"
base ad:0x50001500
width 22.
group.word 0x0E++0x01
line.word 0x00 "GP_ADC_CLEAR_INT_REG,General Purpose ADC Clear Interrupt Register"
hexmask.word 0x00 0.--15. 1. " GP_ADC_CLR_INT ,Writing any value to this register will clear the ADC_INT interrupt"
group.word 0x02++0x01
line.word 0x00 "GP_ADC_CTRL2_REG,General Purpose ADC Second Control Register"
bitfld.word 0x00 13.--15. " GP_ADC_STORE_DEL ,0: Data is stored after handshake synchronisation_1: Data is stored 2 ADC_CLK cycles after internal .." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 9.--12. " GP_ADC_SMPL_TIME ,0: The sample time (switch is closed) is two ADC_CLK cycles_1: The sample time is 1*8 ADC_CLK cycles.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 6.--8. " GP_ADC_CONV_NRS ,0: 1 sample is taken or 2 in case ADC_CHOP is active" "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 4.--5. " GP_ADC_OFFS_SH_CM ,Common mode adjust for offset shifter" "0,1,2,3"
bitfld.word 0x00 3. " GP_ADC_OFFS_SH_EN ,0: Disable input shifter_1: Enable input shifter (900mV - 1800mV shifted to 0mV - 900mV)" "0,1"
bitfld.word 0x00 2. " GP_ADC_I20U ,1: Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the.." "0,1"
newline
bitfld.word 0x00 0.--1. " GP_ADC_ATTN ,0: No attenuator (input voltages up to 0.9V)_1: Enabling 2x attenuator (input voltages up to 1.8V)_2: Enabling 3x attenuator (input voltages up to 2.7V)_3: Enabling 4x attenuator (input voltages up to 3.6V)" "0,1,2,3"
group.word 0x04++0x01
line.word 0x00 "GP_ADC_CTRL3_REG,General Purpose ADC Third Control Register"
hexmask.word.byte 0x00 8.--15. 1. " GP_ADC_INTERVAL ,Defines the interval between two ADC conversions in case GP_ADC_CONT is set"
hexmask.word.byte 0x00 0.--7. 1. " GP_ADC_EN_DEL ,Defines the delay for enabling the ADC after enabling the LDO"
group.word 0x00++0x01
line.word 0x00 "GP_ADC_CTRL_REG,General Purpose ADC Control Register"
bitfld.word 0x00 12. " DIE_TEMP_EN ,Enables the die-temperature sensor" "0,1"
bitfld.word 0x00 11. " GP_ADC_OFFS_SH_GAIN_SEL ," "0,1"
bitfld.word 0x00 10. " GP_ADC_LDO_HOLD ,0: GPADC LDO tracking bandgap reference_1: GPADC LDO hold sampled bandgap reference" "0,1"
newline
bitfld.word 0x00 9. " GP_ADC_CHOP ,0: Chopper mode off_1: Chopper mode enabled" "0,1"
bitfld.word 0x00 8. " GP_ADC_SIGN ,0: Default_1: Conversion with opposite sign at input and output to cancel out the internal offset of.." "0,1"
bitfld.word 0x00 7. " GP_ADC_MUTE ,0: Normal operation_1: Mute ADC input" "0,1"
newline
bitfld.word 0x00 6. " GP_ADC_SE ,0: Differential mode_1: Single ended mode" "0,1"
bitfld.word 0x00 5. " GP_ADC_MINT ,0: Disable (mask) GP_ADC_INT" "0,1"
rbitfld.word 0x00 4. " GP_ADC_INT ,1: AD conversion ready and has generated an interrupt" "0,1"
newline
bitfld.word 0x00 3. " GP_ADC_DMA_EN ,0: DMA functionality disabled_1: DMA functionality enabled" "0,1"
bitfld.word 0x00 2. " GP_ADC_CONT ,0: Manual ADC mode. a single result will be generated after setting the GP_ADC_START bit" "0,1"
bitfld.word 0x00 1. " GP_ADC_START ,0: ADC conversion ready" "0,1"
newline
bitfld.word 0x00 0. " GP_ADC_EN ,0: LDO is off and ADC is disabled" "0,1"
group.word 0x0A++0x01
line.word 0x00 "GP_ADC_OFFN_REG,General Purpose ADC Negative Offset Register"
hexmask.word 0x00 0.--9. 1. " GP_ADC_OFFN ,Offset adjust of 'negative' array of ADC-network (effective if _GP_ADC_SE=0_. or _GP_ADC_SE=1 AND GP.."
group.word 0x08++0x01
line.word 0x00 "GP_ADC_OFFP_REG,General Purpose ADC Positive Offset Register"
hexmask.word 0x00 0.--9. 1. " GP_ADC_OFFP ,Offset adjust of 'positive' array of ADC-network (effective if _GP_ADC_SE=0_. or _GP_ADC_SE=1 AND GP.."
group.word 0x1C++0x01
line.word 0x00 "GP_ADC_PARAM_DIF_REG,"
group.word 0x1E++0x01
line.word 0x00 "GP_ADC_PARAM_SE_REG,"
group.word 0x10++0x01
line.word 0x00 "GP_ADC_RESULT_REG,General Purpose ADC Result Register"
hexmask.word 0x00 0.--15. 1. " GP_ADC_VAL ,Returns the 10 up to 16 bits linear value of the last AD conversion"
group.word 0x0C++0x01
line.word 0x00 "GP_ADC_TRIM_REG,General Purpose ADC Trim Register"
bitfld.word 0x00 4.--6. " GP_ADC_LDO_LEVEL ,GPADC LDO level_0: 825mV_1: 850mV_2: 875mV_3: 900mV (reset)_4: 925mV (default)_5: 950mV_6: 975mV_7:1.." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--3. " GP_ADC_OFFS_SH_VREF ,Offset Shifter common-mode reference fine trimming: 2mV/LSB_Default = mid-scale at 1000" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "GPIO"
base ad:0x50003000
width 23.
group.word 0x3C++0x01
line.word 0x00 "BIST_CTRL_REG,"
bitfld.word 0x00 14. " SYSRAM3_BIST_ENABLE ," "0,1"
bitfld.word 0x00 12.--13. " RAM_BIST_PATTERN ," "0,1,2,3"
rbitfld.word 0x00 11. " SYSRAM12_BIST_BUSY ," "0,1"
newline
rbitfld.word 0x00 10. " SYSRAM12_BIST_FAIL ," "0,1"
rbitfld.word 0x00 8. " SYSRAM3_BIST_BUSY ," "0,1"
rbitfld.word 0x00 7. " SYSRAM3_BIST_FAIL ," "0,1"
newline
rbitfld.word 0x00 5. " ROM_BIST_BUSY ," "0,1"
bitfld.word 0x00 3. " SYSRAM12_BIST_ENABLE ," "0,1"
bitfld.word 0x00 2. " ROMBIST_ENABLE ," "0,1"
newline
bitfld.word 0x00 0.--1. " RAM_BIST_CONFIG ," "0,1,2,3"
group.word 0x06++0x01
line.word 0x00 "P00_MODE_REG,P00 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,Function of port_0 = GPIO (pin direction determined by _PUPD_ field)_1 = UART1_RX_2 = UART1_TX.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1A++0x01
line.word 0x00 "P010_MODE_REG,P010 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x1C++0x01
line.word 0x00 "P011_MODE_REG,P011 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x08++0x01
line.word 0x00 "P01_MODE_REG,P01 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x0A++0x01
line.word 0x00 "P02_MODE_REG,P02 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x0C++0x01
line.word 0x00 "P03_MODE_REG,P03 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x0E++0x01
line.word 0x00 "P04_MODE_REG,P04 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x10++0x01
line.word 0x00 "P05_MODE_REG,P05 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x12++0x01
line.word 0x00 "P06_MODE_REG,P06 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x14++0x01
line.word 0x00 "P07_MODE_REG,P07 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x16++0x01
line.word 0x00 "P08_MODE_REG,P08 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x18++0x01
line.word 0x00 "P09_MODE_REG,P09 Mode Register"
bitfld.word 0x00 8.--9. " PUPD ,00 = Input. no resistors selected_01 = Input. pull-up selected_10 = Input. pull-down selected_11 = O.." "0,1,2,3"
bitfld.word 0x00 0.--4. " PID ,See P00_MODE_REG[PID]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x00++0x01
line.word 0x00 "P0_DATA_REG,P0 Data input/output Register"
hexmask.word 0x00 0.--11. 1. " P0_DATA ,Sets P0 output register when written . Returns the value of P0 port when read"
group.word 0x04++0x01
line.word 0x00 "P0_RESET_DATA_REG,P0 Reset port pins Register"
hexmask.word 0x00 0.--11. 1. " P0_RESET ,Writing a 1 to P0[x] sets P0[x] to 0"
group.word 0x02++0x01
line.word 0x00 "P0_SET_DATA_REG,P0 Set port pins Register"
hexmask.word 0x00 0.--11. 1. " P0_SET ,Writing a 1 to P0[x] sets P0[x] to 1"
group.word 0x1E++0x01
line.word 0x00 "PAD_WEAK_CTRL_REG,Pad driving strength control Register"
hexmask.word 0x00 0.--11. 1. " PAD_LOW_DRV ,0 = Normal operation_1 = Reduces the driving strength of P0_x pad"
group.word 0x40++0x01
line.word 0x00 "ROMBIST_RESULTH_REG,"
hexmask.word 0x00 0.--15. 1. " ROMBIST_RESULTH ,"
group.word 0x3E++0x01
line.word 0x00 "ROMBIST_RESULTL_REG,"
hexmask.word 0x00 0.--15. 1. " ROMBIST_RESULTL ,"
group.word 0x20++0x01
line.word 0x00 "SCAN_OBSERVE_REG,"
hexmask.word 0x00 0.--15. 1. " SCAN_FEEDBACK_MUX ,"
group.word 0x32++0x01
line.word 0x00 "TEST_CTRL2_REG,"
bitfld.word 0x00 12.--15. " ANA_TEST_OUT_PARAM ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 11. " ANA_TEST_OUT_TO_PIN ," "0,1"
hexmask.word 0x00 0.--9. 1. " ANA_TEST_OUT_SEL ,"
group.word 0x34++0x01
line.word 0x00 "TEST_CTRL3_REG,"
bitfld.word 0x00 13. " RF_TEST_OUT_TO_PIN ," "0,1"
bitfld.word 0x00 7.--12. " RF_TEST_OUT_PARAM ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.word 0x00 6. " ENABLE_RFPT ," "0,1"
newline
bitfld.word 0x00 0.--5. " RF_TEST_OUT_SEL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x36++0x01
line.word 0x00 "TEST_CTRL4_REG,"
bitfld.word 0x00 13. " RF_TEST_IN_TO_PIN ," "0,1"
bitfld.word 0x00 8.--12. " RF_TEST_IN_PARAM ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--3. " RF_TEST_IN_SEL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x30++0x01
line.word 0x00 "TEST_CTRL_REG,"
bitfld.word 0x00 12. " ADPLL_SCAN_COMP_EN ," "0,1"
bitfld.word 0x00 11. " ADPLL_SCAN_TEST_EN ," "0,1"
bitfld.word 0x00 9.--10. " CP_CAP_BIAS_TRIM ," "0,1,2,3"
newline
bitfld.word 0x00 6. " LDO_CORE_DUMMY_LOAD_ENABLE ," "0,1"
bitfld.word 0x00 5. " LDO_CORE_CAP_BYPASS ," "0,1"
bitfld.word 0x00 4. " XTAL32M_CAP_TEST_EN ," "0,1"
newline
bitfld.word 0x00 2. " SHOW_DCDC ," "0,1"
bitfld.word 0x00 1. " SHOW_POWER ," "0,1"
bitfld.word 0x00 0. " SHOW_CLOCKS ," "0,1"
group.word 0x38++0x01
line.word 0x00 "XTAL32M_TESTCTRL0_REG,"
bitfld.word 0x00 14.--15. " BIAS_SAH_HOLD_OVERRIDE ," "0,1,2,3"
bitfld.word 0x00 11.--13. " CORE_FREQ_TRIM_SW2_AMP ," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 10. " CORE_GM_CURRENT ," "0,1"
newline
bitfld.word 0x00 8.--9. " CORE_HOLD_AMP_REG_OVERRIDE ," "0,1,2,3"
bitfld.word 0x00 7. " CORE_I2V_TO_TESTBUS ," "0,1"
bitfld.word 0x00 6. " CORE_I2V_TO_TESTBUS_10X ," "0,1"
newline
bitfld.word 0x00 5. " CORE_MAX_CURRENT ," "0,1"
bitfld.word 0x00 4. " CORE_XTAL_DISCHARGE ," "0,1"
bitfld.word 0x00 3. " DCBLOCK_LV_MODE ," "0,1"
newline
bitfld.word 0x00 2. " DIFFBUF_BYPASS ," "0,1"
bitfld.word 0x00 1. " OSC_TRIM_OPEN_DISABLE ," "0,1"
bitfld.word 0x00 0. " SPIKE_FLT_DISABLE ," "0,1"
group.word 0x3A++0x01
line.word 0x00 "XTAL32M_TESTCTRL1_REG,"
bitfld.word 0x00 8. " OSC_TRIM_CAP_BIAS ," "0,1"
bitfld.word 0x00 7. " RFCLK_SEL_ADPLL_ADC_TO_GPIO ," "0,1"
bitfld.word 0x00 6. " RFCLK_ADC_TO_GPIO ," "0,1"
newline
bitfld.word 0x00 5. " RFCLK_ADPLL_TO_GPIO ," "0,1"
bitfld.word 0x00 4. " PROG_VREF_SEL ," "0,1"
bitfld.word 0x00 3. " VARICAP_TEST_SEL_XTAL ," "0,1"
newline
bitfld.word 0x00 2. " VARICAP_TEST_ENABLE ," "0,1"
bitfld.word 0x00 1. " LDO_VREF_HOLD_OVERRIDE ," "0,1"
bitfld.word 0x00 0. " DISABLE_TM_CLK ," "0,1"
width 0x0B
tree.end
tree "GPREG"
base ad:0x50003300
width 18.
group.word 0x0A++0x01
line.word 0x00 "BLE_TIMER_REG,BLE FINECNT sampled value while in deep sleep state"
hexmask.word 0x00 0.--9. 1. " BLE_TIMER_DATA ,Operation depends on GP_CONTROL_REG->BLE_TIMER_DATA_CTRL"
group.word 0x04++0x01
line.word 0x00 "DEBUG_REG,Various debug information register"
bitfld.word 0x00 0. " DEBUGS_FREEZE_EN ,Default '1'. freezing of the on-chip timers is enabled when the Cortex-M0Plus is halted in DEBUG Sta.." "0,1"
group.word 0x08++0x01
line.word 0x00 "GP_CONTROL_REG,General purpose system control register"
bitfld.word 0x00 5.--6. " BLE_TIMER_DATA_CTRL ,Refer to BLE_TIMER_REG" "0,1,2,3"
bitfld.word 0x00 4. " CPU_DMA_BUS_PRIO ,Controls the CPU DMA system bus priority:_If '0'. the CPU has highest priority" "0,1"
rbitfld.word 0x00 2. " BLE_WAKEUP_LP_IRQ ,The current value of the BLE_WAKEUP_LP_IRQ interrupt request" "0,1"
newline
bitfld.word 0x00 0. " BLE_WAKEUP_REQ ,If '1'. the BLE wakes up" "0,1"
group.word 0x06++0x01
line.word 0x00 "GP_STATUS_REG,General purpose system status register"
bitfld.word 0x00 0. " CAL_PHASE ,If '1'. it designates that the chip is in Calibration Phase i" "0,1"
group.word 0x0C++0x01
line.word 0x00 "MEM_CTRL_REG,"
rbitfld.word 0x00 11. " ARB2_AHB2_WR_BUFF ," "0,1"
rbitfld.word 0x00 10. " ARB2_AHB_WR_BUFF ," "0,1"
rbitfld.word 0x00 9. " ARB1_AHB2_WR_BUFF ," "0,1"
newline
rbitfld.word 0x00 8. " ARB1_AHB_WR_BUFF ," "0,1"
bitfld.word 0x00 6.--7. " RAM_MARGIN ," "0,1,2,3"
bitfld.word 0x00 5. " RAM_DST ," "0,1"
newline
bitfld.word 0x00 4. " ROM_MARGIN_EN ," "0,1"
bitfld.word 0x00 0.--3. " ROM_MARGIN_CTRL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x02++0x01
line.word 0x00 "RESET_FREEZE_REG,Controls unfreezing of various timers/counters"
bitfld.word 0x00 4. " FRZ_DMA ,If '1'. the DMA continues. '0' is discarded" "0,1"
bitfld.word 0x00 3. " FRZ_WDOG ,If '1'. the watchdog timer continues. '0' is discarded" "0,1"
bitfld.word 0x00 2. " FRZ_BLETIM ,If '1'. the the BLE master clock continues. '0' is discarded" "0,1"
newline
bitfld.word 0x00 1. " FRZ_SWTIM ,If '1'. the SW Timer (TIMER0) continues. '0' is discarded" "0,1"
bitfld.word 0x00 0. " FRZ_WKUPTIM ,If '1'. the Wake Up Timer continues. '0' is discarded" "0,1"
group.word 0x00++0x01
line.word 0x00 "SET_FREEZE_REG,Controls freezing of various timers/counters"
bitfld.word 0x00 4. " FRZ_DMA ,If '1'. the DMA is frozen. '0' is discarded" "0,1"
bitfld.word 0x00 3. " FRZ_WDOG ,If '1'. the watchdog timer is frozen. '0' is discarded" "0,1"
bitfld.word 0x00 2. " FRZ_BLETIM ,If '1'. the BLE master clock is frozen. '0' is discarded" "0,1"
newline
bitfld.word 0x00 1. " FRZ_SWTIM ,If '1'. the SW Timer (TIMER0) is frozen. '0' is discarded" "0,1"
bitfld.word 0x00 0. " FRZ_WKUPTIM ,If '1'. the Wake Up Timer is frozen. '0' is discarded" "0,1"
width 0x0B
tree.end
tree "I2C"
base ad:0x50001300
width 26.
group.word 0x98++0x01
line.word 0x00 "I2C_ACK_GENERAL_CALL_REG,I2C ACK General Call Register"
bitfld.word 0x00 0. " ACK_GEN_CALL ,ACK General Call" "0,1"
group.word 0x5C++0x01
line.word 0x00 "I2C_CLR_ACTIVITY_REG,Clear ACTIVITY Interrupt Register"
rbitfld.word 0x00 0. " CLR_ACTIVITY ,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1"
group.word 0x68++0x01
line.word 0x00 "I2C_CLR_GEN_CALL_REG,Clear GEN_CALL Interrupt Register"
rbitfld.word 0x00 0. " CLR_GEN_CALL ,Read this register to clear the GEN_CALL interrupt (bit 11) of_I2C_RAW_INTR_STAT register" "0,1"
group.word 0x40++0x01
line.word 0x00 "I2C_CLR_INTR_REG,Clear Combined and Individual Interrupt Register"
rbitfld.word 0x00 0. " CLR_INTR ,Read this register to clear the combined interrupt. all individual interrupts. and the I2C_TX_ABRT_S.." "0,1"
group.word 0x50++0x01
line.word 0x00 "I2C_CLR_RD_REQ_REG,Clear RD_REQ Interrupt Register"
rbitfld.word 0x00 0. " CLR_RD_REQ ,Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0x58++0x01
line.word 0x00 "I2C_CLR_RX_DONE_REG,Clear RX_DONE Interrupt Register"
rbitfld.word 0x00 0. " CLR_RX_DONE ,Read this register to clear the RX_DONE interrupt (bit 7) of the_I2C_RAW_INTR_STAT register" "0,1"
group.word 0x48++0x01
line.word 0x00 "I2C_CLR_RX_OVER_REG,Clear RX_OVER Interrupt Register"
rbitfld.word 0x00 0. " CLR_RX_OVER ,Read this register to clear the RX_OVER interrupt (bit 1) of the_I2C_RAW_INTR_STAT register" "0,1"
group.word 0x44++0x01
line.word 0x00 "I2C_CLR_RX_UNDER_REG,Clear RX_UNDER Interrupt Register"
rbitfld.word 0x00 0. " CLR_RX_UNDER ,Read this register to clear the RX_UNDER interrupt (bit 0) of the_I2C_RAW_INTR_STAT register" "0,1"
group.word 0x64++0x01
line.word 0x00 "I2C_CLR_START_DET_REG,Clear START_DET Interrupt Register"
rbitfld.word 0x00 0. " CLR_START_DET ,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register" "0,1"
group.word 0x60++0x01
line.word 0x00 "I2C_CLR_STOP_DET_REG,Clear STOP_DET Interrupt Register"
rbitfld.word 0x00 0. " CLR_STOP_DET ,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register" "0,1"
group.word 0x54++0x01
line.word 0x00 "I2C_CLR_TX_ABRT_REG,Clear TX_ABRT Interrupt Register"
rbitfld.word 0x00 0. " CLR_TX_ABRT ,Read this register to clear the TX_ABRT interrupt (bit 6) of the_IC_RAW_INTR_STAT register. and the .." "0,1"
group.word 0x4C++0x01
line.word 0x00 "I2C_CLR_TX_OVER_REG,Clear TX_OVER Interrupt Register"
rbitfld.word 0x00 0. " CLR_TX_OVER ,Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register" "0,1"
group.word 0xFA++0x01
line.word 0x00 "I2C_COMP2_VERSION,"
hexmask.word 0x00 0.--15. 1. " IC_COMP2_VERSION ,"
group.word 0xF4++0x01
line.word 0x00 "I2C_COMP_PARAM1_REG,"
hexmask.word 0x00 0.--15. 1. " IC_COMP_PARAM1 ,"
group.word 0xF6++0x01
line.word 0x00 "I2C_COMP_PARAM2_REG,"
hexmask.word 0x00 0.--15. 1. " IC_COMP_PARAM2 ,"
group.word 0xFE++0x01
line.word 0x00 "I2C_COMP_TYPE2_REG,"
hexmask.word 0x00 0.--15. 1. " IC_COMP2_TYPE ,"
group.word 0xFC++0x01
line.word 0x00 "I2C_COMP_TYPE_REG,"
hexmask.word 0x00 0.--15. 1. " IC_COMP_TYPE ,"
group.word 0xF8++0x01
line.word 0x00 "I2C_COMP_VERSION_REG,"
hexmask.word 0x00 0.--15. 1. " IC_COMP_VERSION ,"
group.word 0x00++0x01
line.word 0x00 "I2C_CON_REG,I2C Control Register"
bitfld.word 0x00 6. " I2C_SLAVE_DISABLE ,Slave enabled or disabled after reset is applied. which means software does not have to configure th.." "0,1"
bitfld.word 0x00 5. " I2C_RESTART_EN ,Determines whether RESTART conditions may be sent when acting as a master_0= disable_1=enable" "0,1"
bitfld.word 0x00 4. " I2C_10BITADDR_MASTER ,Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as .." "0,1"
newline
bitfld.word 0x00 3. " I2C_10BITADDR_SLAVE ,When acting as a slave. this bit controls whether the controller responds to 7- or 10-bit addresses" "0,1"
bitfld.word 0x00 1.--2. " I2C_SPEED ,These bits control at which speed the controller operates" "0,1,2,3"
bitfld.word 0x00 0. " I2C_MASTER_MODE ,This bit controls whether the controller master is enabled" "0,1"
group.word 0x10++0x01
line.word 0x00 "I2C_DATA_CMD_REG,I2C Rx/Tx Data Buffer and Command Register"
bitfld.word 0x00 10. " I2C_RESTART ,This bit controls whether a RESTART is issued before the byte is sent or received" "0,1"
bitfld.word 0x00 9. " I2C_STOP ,This bit controls whether a STOP is issued after the byte is sent or received" "0,1"
bitfld.word 0x00 8. " I2C_CMD ,This bit controls whether a read or a write is performed" "0,1"
newline
hexmask.word.byte 0x00 0.--7. 1. " DAT ,This register contains the data to be transmitted or received on the I2C bus"
group.word 0x88++0x01
line.word 0x00 "I2C_DMA_CR_REG,DMA Control Register"
bitfld.word 0x00 1. " TDMAE ,Transmit DMA Enable" "0,1"
bitfld.word 0x00 0. " RDMAE ,Receive DMA Enable" "0,1"
group.word 0x90++0x01
line.word 0x00 "I2C_DMA_RDLR_REG,I2C Receive Data Level Register"
bitfld.word 0x00 0.--4. " DMARDL ,Receive Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x8C++0x01
line.word 0x00 "I2C_DMA_TDLR_REG,DMA Transmit Data Level Register"
bitfld.word 0x00 0.--4. " DMATDL ,Transmit Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x6C++0x01
line.word 0x00 "I2C_ENABLE_REG,I2C Enable Register"
bitfld.word 0x00 1. " I2C_ABORT ,0= ABORT not initiated or ABORT done_1= ABORT operation in progress_The software can abort the I2C t.." "0,1"
bitfld.word 0x00 0. " CTRL_ENABLE ,Controls whether the controller is enabled" "0,1"
group.word 0x9C++0x01
line.word 0x00 "I2C_ENABLE_STATUS_REG,I2C Enable Status Register"
rbitfld.word 0x00 2. " SLV_RX_DATA_LOST ,Slave Received Data Lost" "0,1"
rbitfld.word 0x00 1. " SLV_DISABLED_WHILE_BUSY ,Slave Disabled While Busy (Transmit. Receive)" "0,1"
rbitfld.word 0x00 0. " IC_EN ,ic_en Status" "0,1"
group.word 0x1C++0x01
line.word 0x00 "I2C_FS_SCL_HCNT_REG,Fast Speed I2C Clock SCL High Count Register"
hexmask.word 0x00 0.--15. 1. " IC_FS_SCL_HCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x20++0x01
line.word 0x00 "I2C_FS_SCL_LCNT_REG,Fast Speed I2C Clock SCL Low Count Register"
hexmask.word 0x00 0.--15. 1. " IC_FS_SCL_LCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0xA0++0x01
line.word 0x00 "I2C_IC_FS_SPKLEN_REG,I2C SS and FS spike suppression limit Size"
hexmask.word.byte 0x00 0.--7. 1. " IC_FS_SPKLEN ,This register must be set before any I2C bus transaction can take place to ensure stable operation"
group.word 0x30++0x01
line.word 0x00 "I2C_INTR_MASK_REG,I2C Interrupt Mask Register"
bitfld.word 0x00 11. " M_GEN_CALL ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
bitfld.word 0x00 10. " M_START_DET ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
bitfld.word 0x00 9. " M_STOP_DET ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 8. " M_ACTIVITY ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
bitfld.word 0x00 7. " M_RX_DONE ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
bitfld.word 0x00 6. " M_TX_ABRT ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 5. " M_RD_REQ ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
bitfld.word 0x00 4. " M_TX_EMPTY ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
bitfld.word 0x00 3. " M_TX_OVER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
newline
bitfld.word 0x00 2. " M_RX_FULL ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
bitfld.word 0x00 1. " M_RX_OVER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
bitfld.word 0x00 0. " M_RX_UNDER ,These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register" "0,1"
group.word 0x2C++0x01
line.word 0x00 "I2C_INTR_STAT_REG,I2C Interrupt Status Register"
rbitfld.word 0x00 11. " R_GEN_CALL ,Set only when a General Call address is received and it is acknowledged" "0,1"
rbitfld.word 0x00 10. " R_START_DET ,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of wheth.." "0,1"
rbitfld.word 0x00 9. " R_STOP_DET ,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controlle.." "0,1"
newline
rbitfld.word 0x00 8. " R_ACTIVITY ,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
rbitfld.word 0x00 7. " R_RX_DONE ,When the controller is acting as a slave-transmitter. this bit is set to 1 if the master does not ac.." "0,1"
rbitfld.word 0x00 6. " R_TX_ABRT ,This bit indicates if the controller. as an I2C transmitter. is unable to complete the intended acti.." "0,1"
newline
rbitfld.word 0x00 5. " R_RD_REQ ,This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting t.." "0,1"
rbitfld.word 0x00 4. " R_TX_EMPTY ,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_T.." "0,1"
rbitfld.word 0x00 3. " R_TX_OVER ,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue anoth.." "0,1"
newline
rbitfld.word 0x00 2. " R_RX_FULL ,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
rbitfld.word 0x00 1. " R_RX_OVER ,Set if the receive buffer is completely filled to 32 and an additional byte is received from an exte.." "0,1"
rbitfld.word 0x00 0. " R_RX_UNDER ,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DAT.." "0,1"
group.word 0x34++0x01
line.word 0x00 "I2C_RAW_INTR_STAT_REG,I2C Raw Interrupt Status Register"
rbitfld.word 0x00 11. " GEN_CALL ,Set only when a General Call address is received and it is acknowledged" "0,1"
rbitfld.word 0x00 10. " START_DET ,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of wheth.." "0,1"
rbitfld.word 0x00 9. " STOP_DET ,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controlle.." "0,1"
newline
rbitfld.word 0x00 8. " ACTIVITY ,This bit captures I2C Ctrl activity and stays set until it is cleared" "0,1"
rbitfld.word 0x00 7. " RX_DONE ,When the controller is acting as a slave-transmitter. this bit is set to 1 if the master does not ac.." "0,1"
rbitfld.word 0x00 6. " TX_ABRT ,This bit indicates if the controller. as an I2C transmitter. is unable to complete the intended acti.." "0,1"
newline
rbitfld.word 0x00 5. " RD_REQ ,This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read.." "0,1"
rbitfld.word 0x00 4. " TX_EMPTY ,This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_T.." "0,1"
rbitfld.word 0x00 3. " TX_OVER ,Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue anoth.." "0,1"
newline
rbitfld.word 0x00 2. " RX_FULL ,Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register" "0,1"
rbitfld.word 0x00 1. " RX_OVER ,Set if the receive buffer is completely filled to 32 and an additional byte is received from an exte.." "0,1"
rbitfld.word 0x00 0. " RX_UNDER ,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DAT.." "0,1"
group.word 0x78++0x01
line.word 0x00 "I2C_RXFLR_REG,I2C Receive FIFO Level Register"
rbitfld.word 0x00 0.--5. " RXFLR ,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x38++0x01
line.word 0x00 "I2C_RX_TL_REG,I2C Receive FIFO Threshold Register"
bitfld.word 0x00 0.--4. " RX_TL ,Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL inte.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x08++0x01
line.word 0x00 "I2C_SAR_REG,I2C Slave Address Register"
hexmask.word 0x00 0.--9. 1. " IC_SAR ,The IC_SAR holds the slave address when the I2C is operating as a slave"
group.word 0x7C++0x01
line.word 0x00 "I2C_SDA_HOLD_REG,I2C SDA Hold Time Length Register"
hexmask.word 0x00 0.--15. 1. " IC_SDA_HOLD ,SDA Hold time"
group.word 0x94++0x01
line.word 0x00 "I2C_SDA_SETUP_REG,I2C SDA Setup Register"
hexmask.word.byte 0x00 0.--7. 1. " SDA_SETUP ,SDA Setup"
group.word 0x14++0x01
line.word 0x00 "I2C_SS_SCL_HCNT_REG,Standard Speed I2C Clock SCL High Count Register"
hexmask.word 0x00 0.--15. 1. " IC_SS_SCL_HCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x18++0x01
line.word 0x00 "I2C_SS_SCL_LCNT_REG,Standard Speed I2C Clock SCL Low Count Register"
hexmask.word 0x00 0.--15. 1. " IC_SS_SCL_LCNT ,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing"
group.word 0x70++0x01
line.word 0x00 "I2C_STATUS_REG,I2C Status Register"
rbitfld.word 0x00 6. " SLV_ACTIVITY ,Slave FSM Activity Status" "0,1"
rbitfld.word 0x00 5. " MST_ACTIVITY ,Master FSM Activity Status" "0,1"
rbitfld.word 0x00 4. " RFF ,Receive FIFO Completely Full" "0,1"
newline
rbitfld.word 0x00 3. " RFNE ,Receive FIFO Not Empty" "0,1"
rbitfld.word 0x00 2. " TFE ,Transmit FIFO Completely Empty" "0,1"
rbitfld.word 0x00 1. " TFNF ,Transmit FIFO Not Full" "0,1"
newline
rbitfld.word 0x00 0. " I2C_ACTIVITY ,I2C Activity Status" "0,1"
group.word 0x04++0x01
line.word 0x00 "I2C_TAR_REG,I2C Target Address Register"
bitfld.word 0x00 11. " SPECIAL ,This bit indicates whether software performs a General Call or_START BYTE command" "0,1"
bitfld.word 0x00 10. " GC_OR_START ,If bit 11 (SPECIAL) is set to 1. then this bit indicates whether a General Call or START byte comman.." "0,1"
hexmask.word 0x00 0.--9. 1. " IC_TAR ,This is the target address for any master transaction"
group.word 0x74++0x01
line.word 0x00 "I2C_TXFLR_REG,I2C Transmit FIFO Level Register"
rbitfld.word 0x00 0.--5. " TXFLR ,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x80++0x01
line.word 0x00 "I2C_TX_ABRT_SOURCE_REG,I2C Transmit Abort Source Register"
rbitfld.word 0x00 15. " ABRT_SLVRD_INTX ,1: When the processor side responds to a slave mode request for data to be transmitted to a remote m.." "0,1"
rbitfld.word 0x00 14. " ABRT_SLV_ARBLOST ,1: Slave lost the bus while transmitting data to a remote master" "0,1"
rbitfld.word 0x00 13. " ABRT_SLVFLUSH_TXFIFO ,1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_AB.." "0,1"
newline
rbitfld.word 0x00 12. " ARB_LOST ,1: Master has lost arbitration. or if I2C_TX_ABRT_SOURCE[14] is also set. then the slave transmitter.." "0,1"
rbitfld.word 0x00 11. " ABRT_MASTER_DIS ,1: User tries to initiate a Master operation with the Master mode disabled" "0,1"
rbitfld.word 0x00 10. " ABRT_10B_RD_NORSTRT ,1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command .." "0,1"
newline
rbitfld.word 0x00 9. " ABRT_SBYTE_NORSTRT ,To clear Bit 9. the source of the ABRT_SBYTE_NORSTRT must be fixed first. restart must be enabled (I.." "0,1"
rbitfld.word 0x00 8. " ABRT_HS_NORSTRT ,1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the ma.." "0,1"
rbitfld.word 0x00 7. " ABRT_SBYTE_ACKDET ,1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)" "0,1"
newline
rbitfld.word 0x00 6. " ABRT_HS_ACKDET ,1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior)" "0,1"
rbitfld.word 0x00 5. " ABRT_GCALL_READ ,1: the controller in master mode sent a General Call but the user programmed the byte following the .." "0,1"
rbitfld.word 0x00 4. " ABRT_GCALL_NOACK ,1: the controller in master mode sent a General Call and no slave on the bus acknowledged the Genera.." "0,1"
newline
rbitfld.word 0x00 3. " ABRT_TXDATA_NOACK ,1: This is a master-mode only bit" "0,1"
rbitfld.word 0x00 2. " ABRT_10ADDR2_NOACK ,1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknow.." "0,1"
rbitfld.word 0x00 1. " ABRT_10ADDR1_NOACK ,1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any sl.." "0,1"
newline
rbitfld.word 0x00 0. " ABRT_7B_ADDR_NOACK ,1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave" "0,1"
group.word 0x3C++0x01
line.word 0x00 "I2C_TX_TL_REG,I2C Transmit FIFO Threshold Register"
bitfld.word 0x00 0.--4. " RX_TL ,Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY int.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "KBRD"
base ad:0x50001400
width 25.
group.word 0x0C++0x01
line.word 0x00 "GPIO_DEBOUNCE_REG,debounce counter value for GPIO inputs"
bitfld.word 0x00 11. " DEB_ENABLE_KBRD ,enables the debounce counter for the KBRD interface" "0,1"
bitfld.word 0x00 10. " DEB_ENABLE4 ,enables the debounce counter for GPIO IRQ4" "0,1"
bitfld.word 0x00 9. " DEB_ENABLE3 ,enables the debounce counter for GPIO IRQ3" "0,1"
newline
bitfld.word 0x00 8. " DEB_ENABLE2 ,enables the debounce counter for GPIO IRQ2" "0,1"
bitfld.word 0x00 7. " DEB_ENABLE1 ,enables the debounce counter for GPIO IRQ1" "0,1"
bitfld.word 0x00 6. " DEB_ENABLE0 ,enables the debounce counter for GPIO IRQ0" "0,1"
newline
bitfld.word 0x00 0.--5. " DEB_VALUE ,Keyboard debounce time if enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x10++0x01
line.word 0x00 "GPIO_INT_LEVEL_CTRL_REG,high or low level select for GPIO interrupts"
bitfld.word 0x00 9. " EDGE_LEVELn4 ,see EDGE_LEVELn0. but for GPIO IRQ4" "0,1"
bitfld.word 0x00 8. " EDGE_LEVELn3 ,see EDGE_LEVELn0. but for GPIO IRQ3" "0,1"
bitfld.word 0x00 7. " EDGE_LEVELn2 ,see EDGE_LEVELn0. but for GPIO IRQ2" "0,1"
newline
bitfld.word 0x00 6. " EDGE_LEVELn1 ,see EDGE_LEVELn0. but for GPIO IRQ1" "0,1"
bitfld.word 0x00 5. " EDGE_LEVELn0 ,0: do not wait for key release after interrupt was reset for GPIO IRQ0. so a new interrupt can be in.." "0,1"
bitfld.word 0x00 4. " INPUT_LEVEL4 ,see INPUT_LEVEL0. but for GPIO IRQ4" "0,1"
newline
bitfld.word 0x00 3. " INPUT_LEVEL3 ,see INPUT_LEVEL0. but for GPIO IRQ3" "0,1"
bitfld.word 0x00 2. " INPUT_LEVEL2 ,see INPUT_LEVEL0. but for GPIO IRQ2" "0,1"
bitfld.word 0x00 1. " INPUT_LEVEL1 ,see INPUT_LEVEL0. but for GPIO IRQ1" "0,1"
newline
bitfld.word 0x00 0. " INPUT_LEVEL0 ,0 = selected input will generate GPIO IRQ0 if that input is high" "0,1"
group.word 0x00++0x01
line.word 0x00 "GPIO_IRQ0_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ0"
bitfld.word 0x00 0.--3. " KBRD_IRQ0_SEL ,input selection that can generate a GPIO interrupt_1: P0[0] is selected_2: P0[1] is selected_3: P0[2.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x02++0x01
line.word 0x00 "GPIO_IRQ1_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ1"
bitfld.word 0x00 0.--3. " KBRD_IRQ1_SEL ,see KBRD_IRQ0_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x04++0x01
line.word 0x00 "GPIO_IRQ2_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ2"
bitfld.word 0x00 0.--3. " KBRD_IRQ2_SEL ,see KBRD_IRQ0_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x06++0x01
line.word 0x00 "GPIO_IRQ3_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ3"
bitfld.word 0x00 0.--3. " KBRD_IRQ3_SEL ,see KBRD_IRQ0_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x08++0x01
line.word 0x00 "GPIO_IRQ4_IN_SEL_REG,GPIO interrupt selection for GPIO_IRQ4"
bitfld.word 0x00 0.--3. " KBRD_IRQ4_SEL ,see KBRD_IRQ0_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x0E++0x01
line.word 0x00 "GPIO_RESET_IRQ_REG,GPIO interrupt reset register"
bitfld.word 0x00 5. " RESET_KBRD_IRQ ,writing a 1 to this bit will reset the KBRD IRQ" "0,1"
bitfld.word 0x00 4. " RESET_GPIO4_IRQ ,writing a 1 to this bit will reset the GPIO4 IRQ" "0,1"
bitfld.word 0x00 3. " RESET_GPIO3_IRQ ,writing a 1 to this bit will reset the GPIO3 IRQ" "0,1"
newline
bitfld.word 0x00 2. " RESET_GPIO2_IRQ ,writing a 1 to this bit will reset the GPIO2 IRQ" "0,1"
bitfld.word 0x00 1. " RESET_GPIO1_IRQ ,writing a 1 to this bit will reset the GPIO1 IRQ" "0,1"
bitfld.word 0x00 0. " RESET_GPIO0_IRQ ,writing a 1 to this bit will reset the GPIO0 IRQ" "0,1"
group.word 0x14++0x01
line.word 0x00 "KBRD_CTRL_REG,GPIO Kbrd control register"
bitfld.word 0x00 7. " KBRD_REL ,0 = No interrupt on key release_1 = Interrupt also on key release (also debouncing if enabled)" "0,1"
bitfld.word 0x00 6. " KBRD_LEVEL ,0 = enabled input will generate KBRD IRQ if that input is high" "0,1"
bitfld.word 0x00 0.--5. " KEY_REPEAT ,While key is pressed. automatically generate repeating_KEYB_INT after specified time unequal to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x12++0x01
line.word 0x00 "KBRD_IRQ_IN_SEL0_REG,GPIO interrupt selection for KBRD_IRQ for P0"
bitfld.word 0x00 11. " KBRD_P11_EN ,enable P0[11] for the keyboard interrupt" "0,1"
bitfld.word 0x00 10. " KBRD_P10_EN ,enable P0[10] for the keyboard interrupt" "0,1"
bitfld.word 0x00 9. " KBRD_P09_EN ,enable P0[9] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 8. " KBRD_P08_EN ,enable P0[8] for the keyboard interrupt" "0,1"
bitfld.word 0x00 7. " KBRD_P07_EN ,enable P0[7] for the keyboard interrupt" "0,1"
bitfld.word 0x00 6. " KBRD_P06_EN ,enable P0[6] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 5. " KBRD_P05_EN ,enable P0[5] for the keyboard interrupt" "0,1"
bitfld.word 0x00 4. " KBRD_P04_EN ,enable P0[4] for the keyboard interrupt" "0,1"
bitfld.word 0x00 3. " KBRD_P03_EN ,enable P0[3] for the keyboard interrupt" "0,1"
newline
bitfld.word 0x00 2. " KBRD_P02_EN ,enable P0[2] for the keyboard interrupt" "0,1"
bitfld.word 0x00 1. " KBRD_P01_EN ,enable P0[1] for the keyboard interrupt" "0,1"
bitfld.word 0x00 0. " KBRD_P00_EN ,enable P0[0] for the keyboard interrupt" "0,1"
width 0x0B
tree.end
tree "MBIST_SRAM3"
base ad:0x50003800
width 24.
group.word 0x00++0x01
line.word 0x00 "MBIST_SRAM3_ADDR_REG,"
rbitfld.word 0x00 0. " MBIST_ADDR ,Returns the current address register in case of a mismatch" "0,1"
group.word 0x06++0x01
line.word 0x00 "MBIST_SRAM3_RD_LSB_REG,"
rbitfld.word 0x00 0. " MBIST_LSB_DATA ,Returns the actual LSB read data in case of a mismatch" "0,1"
group.word 0x04++0x01
line.word 0x00 "MBIST_SRAM3_RD_MSB_REG,"
rbitfld.word 0x00 0. " MBIST_MSB_DATA ,Returns the actual MSB read data in case of a mismatch" "0,1"
group.word 0x02++0x01
line.word 0x00 "MBIST_SRAM3_STATE_REG,"
rbitfld.word 0x00 0. " MBIST_STATE ,Returns the current state in case of a mismatch" "0,1"
width 0x0B
tree.end
tree "MBIST_SRAM12"
base ad:0x50003700
width 25.
group.word 0x00++0x01
line.word 0x00 "MBIST_SRAM12_ADDR_REG,"
rbitfld.word 0x00 0. " MBIST_ADDR ,Returns the current address register in case of a mismatch" "0,1"
group.word 0x06++0x01
line.word 0x00 "MBIST_SRAM12_RD_LSB_REG,"
rbitfld.word 0x00 0. " MBIST_LSB_DATA ,Returns the actual LSB read data in case of a mismatch" "0,1"
group.word 0x04++0x01
line.word 0x00 "MBIST_SRAM12_RD_MSB_REG,"
rbitfld.word 0x00 0. " MBIST_MSB_DATA ,Returns the actual MSB read data in case of a mismatch" "0,1"
group.word 0x02++0x01
line.word 0x00 "MBIST_SRAM12_STATE_REG,"
rbitfld.word 0x00 0. " MBIST_STATE ,Returns the current state in case of a mismatch" "0,1"
width 0x0B
tree.end
tree "OTPC"
base ad:0x7F40000
width 17.
group.long 0x18++0x03
line.long 0x00 "OTPC_AHBADR_REG,AHB master start address"
hexmask.long.word 0x00 2.--15. 1. " OTPC_AHBADR ,It is the AHB address used by the AHB master interface of the controller (the bits [15:2])"
group.long 0x1C++0x03
line.long 0x00 "OTPC_CELADR_REG,OTP cell start address"
hexmask.long.word 0x00 0.--12. 1. " OTPC_CELADR ,Defines a word address inside the OTP cell that will be used during the AREAD mode and the OTP mirro.."
group.long 0x00++0x03
line.long 0x00 "OTPC_MODE_REG,Mode register"
bitfld.long 0x00 6.--7. " OTPC_MODE_PRG_SEL ,Defines the part of the OTP cell that is programmed by the controller during the PROG mode. for each.." "0,1,2,3"
bitfld.long 0x00 5. " OTPC_MODE_HT_MARG_EN ,Defines the temperature condition under which is performed a margin read" "0,1"
bitfld.long 0x00 4. " OTPC_MODE_USE_TST_ROW ,Selects the memory area of the OTP cell that will be used" "0,1"
newline
bitfld.long 0x00 0.--2. " OTPC_MODE_MODE ,Defines the mode of operation of the OTPC controller" "0,1,2,3,4,5,6,7"
group.long 0x20++0x03
line.long 0x00 "OTPC_NWORDS_REG,Number of words"
hexmask.long.word 0x00 0.--12. 1. " OTPC_NWORDS ,The number of words (minus one) that will be copied by the AREAD mode"
group.long 0x08++0x03
line.long 0x00 "OTPC_PADDR_REG,The address of the word that will be programmed. when the PROG mode is used"
hexmask.long.word 0x00 0.--12. 1. " OTPC_PADDR ,The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that wi.."
group.long 0x0C++0x03
line.long 0x00 "OTPC_PWORD_REG,The 32-bit word that will be programmed. when the PROG mode is used"
hexmask.long 0x00 0.--31. 1. " OTPC_PWORD ,The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that wi.."
group.long 0x04++0x03
line.long 0x00 "OTPC_STAT_REG,Status register"
rbitfld.long 0x00 2. " OTPC_STAT_MRDY ,Indicates the progress of the transition from a mode of operation to a new mode of operation" "0,1"
rbitfld.long 0x00 1. " OTPC_STAT_PBUF_EMPTY ,Indicates the status of the programming buffer (PBUF)" "0,1"
rbitfld.long 0x00 0. " OTPC_STAT_PRDY ,Indicates the state of the programming process" "0,1"
group.long 0x10++0x03
line.long 0x00 "OTPC_TIM1_REG,Various timing parameters of the OTP cell"
hexmask.long.byte 0x00 24.--30. 1. " OTPC_TIM1_US_T_CSP ,The number of microseconds (minus one) that are required after the selection of the OTP memory. unti.."
bitfld.long 0x00 20.--23. " OTPC_TIM1_US_T_CS ,The number of microseconds (minus one) that are required after the selection of the OTP memory. unti.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. " OTPC_TIM1_US_T_PL ,The number of microseconds (minus one) that are required until to be enabled the LDO of the OTP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--14. " OTPC_TIM1_CC_T_RD ,The number of hclk_c clock periods (minus one) that give a time interval at least higher than 60ns" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--9. " OTPC_TIM1_CC_T_20NS ,The number of hclk_c clock periods (minus one) that give a time interval that is at least higher tha.." "0,1,2,3"
hexmask.long.byte 0x00 0.--6. 1. " OTPC_TIM1_CC_T_1US ,The number of hclk_c clock periods (minus one) that give a time interval equal to 1us"
group.long 0x14++0x03
line.long 0x00 "OTPC_TIM2_REG,Various timing parameters of the OTP cell"
bitfld.long 0x00 31. " OTPC_TIM2_US_ADD_CC_EN ,Adds an additional hclk_c clock cycle at all the time intervals that count in microseconds" "0,1"
bitfld.long 0x00 29.--30. " OTPC_TIM2_US_T_SAS ,The number of microseconds (minus one) that are required after the exit from the deep sleep standby .." "0,1,2,3"
bitfld.long 0x00 24.--28. " OTPC_TIM2_US_T_PPH ,The number of microseconds (minus one) that are required after the last programming pulse and before.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 21.--23. " OTPC_TIM2_US_T_VDS ,The number of microseconds (minus one) that are required after the enabling of the power supply of t.." "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. " OTPC_TIM2_US_T_PPS ,The number of microseconds (minus one) that are required after the enabling of the programming in th.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 8.--14. 1. " OTPC_TIM2_US_T_PPR ,The number of microseconds (minus one) for recovery after a programming sequence"
newline
bitfld.long 0x00 5.--7. " OTPC_TIM2_US_T_PWI ,The number of microseconds (minus one) between two consecutive programming pulses" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. " OTPC_TIM2_US_T_PW ,The number of microseconds (minus one) that lasts the programming of each bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "PATCH"
base ad:0x40080000
width 18.
group.long 0x20++0x03
line.long 0x00 "PATCH_ADDR0_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x70++0x03
line.long 0x00 "PATCH_ADDR10_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x78++0x03
line.long 0x00 "PATCH_ADDR11_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x80++0x03
line.long 0x00 "PATCH_ADDR12_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x88++0x03
line.long 0x00 "PATCH_ADDR13_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x90++0x03
line.long 0x00 "PATCH_ADDR14_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x98++0x03
line.long 0x00 "PATCH_ADDR15_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0xA0++0x03
line.long 0x00 "PATCH_ADDR16_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0xA8++0x03
line.long 0x00 "PATCH_ADDR17_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0xB0++0x03
line.long 0x00 "PATCH_ADDR18_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0xB8++0x03
line.long 0x00 "PATCH_ADDR19_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x28++0x03
line.long 0x00 "PATCH_ADDR1_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0xC0++0x03
line.long 0x00 "PATCH_ADDR20_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.word 0x00 2.--17. 1. " PATCH_ADDR_D ,"
group.long 0xC8++0x03
line.long 0x00 "PATCH_ADDR21_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.word 0x00 2.--17. 1. " PATCH_ADDR_D ,"
group.long 0x30++0x03
line.long 0x00 "PATCH_ADDR2_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x38++0x03
line.long 0x00 "PATCH_ADDR3_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x40++0x03
line.long 0x00 "PATCH_ADDR4_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x48++0x03
line.long 0x00 "PATCH_ADDR5_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x50++0x03
line.long 0x00 "PATCH_ADDR6_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x58++0x03
line.long 0x00 "PATCH_ADDR7_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x60++0x03
line.long 0x00 "PATCH_ADDR8_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0x68++0x03
line.long 0x00 "PATCH_ADDR9_REG,"
bitfld.long 0x00 19. " PATCH_ADDR_19 ," "0,1"
hexmask.long.tbyte 0x00 1.--17. 1. " PATCH_ADDR_C ,"
group.long 0xC4++0x03
line.long 0x00 "PATCH_DATA20_REG,"
hexmask.long 0x00 0.--31. 1. " PATCH_DATA ,"
group.long 0xCC++0x03
line.long 0x00 "PATCH_DATA21_REG,"
hexmask.long 0x00 0.--31. 1. " PATCH_DATA ,"
group.long 0x00++0x03
line.long 0x00 "PATCH_VALID_REG,"
hexmask.long.tbyte 0x00 0.--21. 1. " PATCH_VALID ,"
width 0x0B
tree.end
tree "QUADEC"
base ad:0x50000200
width 20.
group.word 0x06++0x01
line.word 0x00 "QDEC_CLOCKDIV_REG,Clock divider register"
bitfld.word 0x00 10. " QDEC_PRESCALER_EN ,0 = no prescaler enabled_1 = in sleep and active mode. quadrature clock is divided by 2" "0,1"
hexmask.word 0x00 0.--9. 1. " QDEC_CLOCKDIV ,Contains the number of the input clock cycles minus one. that are required to generate one logic clo.."
group.word 0x08++0x01
line.word 0x00 "QDEC_CTRL2_REG,Quad Decoder port selection register"
bitfld.word 0x00 11. " QDEC_CHZ_EVENT_MODE ,0 = Normal quadrature counting_1 = Counts rising and falling edge of both ports (if both ports chang.." "0,1"
bitfld.word 0x00 10. " QDEC_CHY_EVENT_MODE ,0 = Normal quadrature counting_1 = Counts rising and falling edge of both ports (if both ports chang.." "0,1"
bitfld.word 0x00 9. " QDEC_CHX_EVENT_MODE ,0 = Normal quadrature counting_1 = Counts rising and falling edge of both ports (if both ports chang.." "0,1"
newline
bitfld.word 0x00 6.--8. " QDEC_CHZ_PORT_SEL ,Defines which GPIOs are mapped on Channel Z_0: none_1: P0[2] -> CHZ_A. P0[5] -> CHZ_B_2: P0[1] -> CH.." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 3.--5. " QDEC_CHY_PORT_SEL ,Defines which GPIOs are mapped on Channel Y_0: none_1: P0[2] -> CHY_A. P0[5] -> CHY_B_2: P0[1] -> CH.." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 0.--2. " QDEC_CHX_PORT_SEL ,Defines which GPIOs are mapped on Channel X_0: none_1: P0[2] -> CHX_A. P0[5] -> CHX_B_2: P0[1] -> CH.." "0,1,2,3,4,5,6,7"
group.word 0x00++0x01
line.word 0x00 "QDEC_CTRL_REG,Quad Decoder control register"
hexmask.word.byte 0x00 3.--10. 1. " QDEC_IRQ_THRES ,Defines the number of events on either counter (X or Y or Z) that need to be reached before an inter.."
bitfld.word 0x00 2. " QDEC_IRQ_STATUS ,1 = Interrupt is occured" "0,1"
bitfld.word 0x00 1. " QDEC_EVENT_CNT_CLR ,Writing 1 QDEC_EVENT_CNT_REG is cleared" "0,1"
newline
bitfld.word 0x00 0. " QDEC_IRQ_ENABLE ,0 = interrupt is masked_1 = interrupt is enabled" "0,1"
group.word 0x0C++0x01
line.word 0x00 "QDEC_EVENT_CNT_REG,Event counter register"
hexmask.word.byte 0x00 0.--7. 1. " QDEC_EVENT_CNT ,Gives the number of events at all channels"
group.word 0x02++0x01
line.word 0x00 "QDEC_XCNT_REG,Counter value of the X Axis"
hexmask.word 0x00 0.--15. 1. " QDEC_X_CNT ,Contains a signed value of the events"
group.word 0x04++0x01
line.word 0x00 "QDEC_YCNT_REG,Counter value of the Y Axis"
hexmask.word 0x00 0.--15. 1. " QDEC_Y_CNT ,Contains a signed value of the events"
group.word 0x0A++0x01
line.word 0x00 "QDEC_ZCNT_REG,Counter value of the Z Axis"
hexmask.word 0x00 0.--15. 1. " QDEC_Z_CNT ,Contains a signed value of the events"
width 0x0B
tree.end
tree "RFCU"
base ad:0x40001000
width 28.
group.long 0x28++0x03
line.long 0x00 "RF_ADCI_DC_OFFSET_REG,"
hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_I_RD ,"
hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_I_RD ,"
group.long 0x2C++0x03
line.long 0x00 "RF_ADCQ_DC_OFFSET_REG,"
hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_Q_RD ,"
hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_Q_RD ,"
group.long 0x40++0x03
line.long 0x00 "RF_ADC_CTRL1_REG,"
bitfld.long 0x00 14. " ADC_SIGN ," "0,1"
bitfld.long 0x00 13. " ADC_MUTE ," "0,1"
bitfld.long 0x00 0. " ADC_DC_OFFSET_SEL ," "0,1"
group.long 0x44++0x03
line.long 0x00 "RF_ADC_CTRL2_REG,"
hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_I_WR ,"
hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_I_WR ,"
group.long 0x48++0x03
line.long 0x00 "RF_ADC_CTRL3_REG,"
hexmask.long.word 0x00 9.--17. 1. " ADC_OFFN_Q_WR ,"
hexmask.long.word 0x00 0.--8. 1. " ADC_OFFP_Q_WR ,"
group.long 0x0C++0x03
line.long 0x00 "RF_ADPLLDIG_CTRL_REG,"
bitfld.long 0x00 4.--6. " PWR_SW_TIM_CTRL ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. " OPENLOOP_RDY_WR ," "0,1"
bitfld.long 0x00 0. " OPENLOOP_RDY_SEL ," "0,1"
group.long 0xA0++0x03
line.long 0x00 "RF_ADPLLDIG_RFMON_CTRL_REG,"
bitfld.long 0x00 4.--7. " ADPLLDIG_RFMON_SPARE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--3. " ADPLLDIG_RFMON_MUX_SEL ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " ADPLLDIG_SYNC_CLK_INV ," "0,1"
group.long 0x10++0x03
line.long 0x00 "RF_AGC_EXT_LUT_REG,"
hexmask.long.word 0x00 0.--9. 1. " AGC_EXT_LUT ,"
group.long 0x00++0x03
line.long 0x00 "RF_ATTR_REG,"
bitfld.long 0x00 24.--27. " PA_POWER_SETTING ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. " TIA_BIAS ," "0,1"
bitfld.long 0x00 8.--11. " RF_BIAS ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. " IFF_POLARITY ," "0,1"
group.long 0x14++0x03
line.long 0x00 "RF_CALSTATE_REG,"
rbitfld.long 0x00 0.--3. " CALSTATE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "RF_CAL_CTRL_REG,"
bitfld.long 0x00 4. " DC_OFFSET_CAL_DIS ," "0,1"
bitfld.long 0x00 2. " RF_CAL_CTRL_SPARE ," "0,1"
rbitfld.long 0x00 1. " EO_CAL ," "0,1"
newline
bitfld.long 0x00 0. " SO_CAL ," "0,1"
group.long 0xB0++0x03
line.long 0x00 "RF_DIAGIRQ_CTRL_REG,"
bitfld.long 0x00 30. " DIAG_BUS3_EDGE_SEL ," "0,1"
bitfld.long 0x00 27.--29. " DIAG_BUS3_BIT_SEL ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25.--26. " DIAG_BUS3_SEL ," "0,1,2,3"
newline
bitfld.long 0x00 24. " DIAG_BUS3_IRQ_MASK ," "0,1"
bitfld.long 0x00 22. " DIAG_BUS2_EDGE_SEL ," "0,1"
bitfld.long 0x00 19.--21. " DIAG_BUS2_BIT_SEL ," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--18. " DIAG_BUS2_SEL ," "0,1,2,3"
bitfld.long 0x00 16. " DIAG_BUS2_IRQ_MASK ," "0,1"
bitfld.long 0x00 14. " DIAG_BUS1_EDGE_SEL ," "0,1"
newline
bitfld.long 0x00 11.--13. " DIAG_BUS1_BIT_SEL ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9.--10. " DIAG_BUS1_SEL ," "0,1,2,3"
bitfld.long 0x00 8. " DIAG_BUS1_IRQ_MASK ," "0,1"
newline
bitfld.long 0x00 6. " DIAG_BUS0_EDGE_SEL ," "0,1"
bitfld.long 0x00 3.--5. " DIAG_BUS0_BIT_SEL ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1.--2. " DIAG_BUS0_SEL ," "0,1,2,3"
newline
bitfld.long 0x00 0. " DIAG_BUS0_IRQ_MASK ," "0,1"
group.long 0xB4++0x03
line.long 0x00 "RF_DIAGIRQ_STAT_REG,"
rbitfld.long 0x00 0.--3. " DIAGIRQ_STAT ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C++0x03
line.long 0x00 "RF_IFF_CTRL_REG,"
bitfld.long 0x00 13.--14. " IFF_DCOC_DAC_REFCUR_CTRL ," "0,1,2,3"
bitfld.long 0x00 12. " IFF_COMPLEX_DIS ," "0,1"
bitfld.long 0x00 6.--11. " RF_IFF_CTRL_SPARE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 5. " IFF_DCOC_DAC_DIS ," "0,1"
bitfld.long 0x00 4. " IF_MUTE ," "0,1"
bitfld.long 0x00 0.--1. " IF_CAL_TRIM ," "0,1,2,3"
group.long 0x74++0x03
line.long 0x00 "RF_IO_CTRL_REG,"
bitfld.long 0x00 8.--11. " RFIO_TUNE_CAP_TRIM_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " RFIO_TUNE_CAP_TRIM_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "RF_IRQ_CTRL_REG,"
bitfld.long 0x00 0. " EO_CAL_CLEAR ," "0,1"
group.long 0xB8++0x03
line.long 0x00 "RF_LDO_CTRL_REG,"
bitfld.long 0x00 29. " LDO_DCO_HOLD_OVR_EN ," "0,1"
bitfld.long 0x00 28. " LDO_DCO_HOLD_OVR_VAL ," "0,1"
bitfld.long 0x00 27. " LDO_DTC_HOLD_OVR_EN ," "0,1"
newline
bitfld.long 0x00 26. " LDO_DTC_HOLD_OVR_VAL ," "0,1"
bitfld.long 0x00 25. " LDO_RADIO_HOLD_OVR_EN ," "0,1"
bitfld.long 0x00 24. " LDO_RADIO_HOLD_OVR_VAL ," "0,1"
newline
bitfld.long 0x00 16.--20. " LDO_VREF_SMPL_TIME ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 11. " LDO_DCO_CONT_ENABLE ," "0,1"
bitfld.long 0x00 8.--10. " LDO_DCO_LEVEL ," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. " LDO_DTC_CONT_ENABLE ," "0,1"
bitfld.long 0x00 4.--6. " LDO_DTC_LEVEL ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. " LDO_RADIO_CONT_ENABLE ," "0,1"
newline
bitfld.long 0x00 0.--2. " LDO_RADIO_LEVEL ," "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "RF_LDO_STATUS_REG,"
rbitfld.long 0x00 8. " ldo_dtc_vref_hold_rd ," "0,1"
rbitfld.long 0x00 7. " ldo_dco_vref_hold_rd ," "0,1"
rbitfld.long 0x00 6. " ldo_radio_vref_hold_rd ," "0,1"
newline
rbitfld.long 0x00 5. " ldo_dtc_en_rd ," "0,1"
rbitfld.long 0x00 4. " ldo_dco_en_rd ," "0,1"
rbitfld.long 0x00 3. " ADPLLDIG_LDO_ZERO_EN_RD ," "0,1"
newline
rbitfld.long 0x00 2. " ADPLLDIG_LDO_EN_RD ," "0,1"
rbitfld.long 0x00 1. " RADIO_LDO_ZERO_EN_RD ," "0,1"
rbitfld.long 0x00 0. " RADIO_LDO_EN_RD ," "0,1"
group.long 0x58++0x03
line.long 0x00 "RF_LDO_VREF_SEL_REG,"
bitfld.long 0x00 2. " RF_LDO_DCO_VREF_SEL ," "0,1"
bitfld.long 0x00 1. " RF_LDO_DTC_VREF_SEL ," "0,1"
bitfld.long 0x00 0. " RF_LDO_RADIO_VREF_SEL ," "0,1"
group.long 0x78++0x03
line.long 0x00 "RF_LNA_CTRL1_REG,"
bitfld.long 0x00 20.--24. " LNA_TRIM_GAIN4_HP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15.--19. " LNA_TRIM_GAIN3_HP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. " LNA_TRIM_GAIN2_HP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. " LNA_TRIM_GAIN1_HP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " LNA_TRIM_GAIN0_HP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C++0x03
line.long 0x00 "RF_LNA_CTRL2_REG,"
bitfld.long 0x00 20.--24. " LNA_TRIM_GAIN4_LP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15.--19. " LNA_TRIM_GAIN3_LP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. " LNA_TRIM_GAIN2_LP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. " LNA_TRIM_GAIN1_LP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " LNA_TRIM_GAIN0_LP ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80++0x03
line.long 0x00 "RF_LNA_CTRL3_REG,"
bitfld.long 0x00 24.--25. " LNA_SPARE ," "0,1,2,3"
bitfld.long 0x00 20.--21. " LNA_MODE_GAIN4_LP ," "0,1,2,3"
bitfld.long 0x00 16.--17. " LNA_MODE_GAIN3_LP ," "0,1,2,3"
newline
bitfld.long 0x00 12.--13. " LNA_MODE_GAIN2_LP ," "0,1,2,3"
bitfld.long 0x00 8.--9. " LNA_MODE_GAIN1_LP ," "0,1,2,3"
bitfld.long 0x00 4.--5. " LNA_MODE_GAIN0_LP ," "0,1,2,3"
newline
bitfld.long 0x00 0.--2. " LNA_TRIM_CASC ," "0,1,2,3,4,5,6,7"
group.long 0x64++0x03
line.long 0x00 "RF_MIXER_CTRL1_REG,"
hexmask.long.word 0x00 16.--24. 1. " MIXER_IP2_DAC_Q_TRIM ,"
hexmask.long.word 0x00 0.--8. 1. " MIXER_IP2_DAC_I_TRIM ,"
group.long 0x68++0x03
line.long 0x00 "RF_MIXER_CTRL2_REG,"
bitfld.long 0x00 16. " MIX_CAL_SELECT ," "0,1"
bitfld.long 0x00 8.--11. " MIX_CAL_CAP_WR_2M ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " MIX_CAL_CAP_WR_1M ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xAC++0x03
line.long 0x00 "RF_OVERRULE_REG,"
bitfld.long 0x00 2.--3. " RX_EN_OVR ," "0,1,2,3"
bitfld.long 0x00 0.--1. " TX_EN_OVR ," "0,1,2,3"
group.long 0x4C++0x03
line.long 0x00 "RF_PA_CTRL_REG,"
bitfld.long 0x00 8.--9. " PA_RAMP_STEP_SPEED ," "0,1,2,3"
bitfld.long 0x00 3.--5. " TRIM_DUTY_NEG ," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. " TRIM_DUTY_POS ," "0,1,2,3,4,5,6,7"
group.long 0x04++0x03
line.long 0x00 "RF_RADIO_INIT_REG,"
bitfld.long 0x00 24. " RADIO_INIT_AUTOCLEAR ," "0,1"
bitfld.long 0x00 17. " ADPLLDIG_HCLK_DIS ," "0,1"
bitfld.long 0x00 16. " RADIO_REGS_RDY ," "0,1"
newline
bitfld.long 0x00 9. " ADPLLDIG_HCLK_EN ," "0,1"
bitfld.long 0x00 8. " ADPLLDIG_HRESET_N ," "0,1"
bitfld.long 0x00 5. " ADPLLDIG_LDO_EN_WR ," "0,1"
newline
bitfld.long 0x00 4. " ADPLLDIG_LDO_EN_SEL ," "0,1"
bitfld.long 0x00 3. " ADPLLDIG_PWR_SW1_EN ," "0,1"
bitfld.long 0x00 2. " RADIO_LDO_EN_WR ," "0,1"
newline
bitfld.long 0x00 1. " RADIO_LDO_EN_SEL ," "0,1"
bitfld.long 0x00 0. " RADIO_LDO_EN ," "0,1"
group.long 0xA8++0x03
line.long 0x00 "RF_RFCU_CTRL_REG,"
bitfld.long 0x00 0. " RF_RFCU_CLK_DIV ," "0,1"
group.long 0x18++0x03
line.long 0x00 "RF_SCAN_FEEDBACK_REG,"
group.long 0x30++0x03
line.long 0x00 "RF_SPARE_REG,"
bitfld.long 0x00 28. " RF_SPARE_IN_EN ," "0,1"
rbitfld.long 0x00 24.--27. " RF_SPARE_IN ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. " RF_SPARE_BITS_HV ,"
newline
hexmask.long.word 0x00 0.--15. 1. " RF_SPARE_BITS ,"
width 0x0B
tree.end
tree "RFCU_POWER"
base ad:0x40001200
width 24.
group.long 0x180++0x03
line.long 0x00 "RF_ALWAYS_EN1_REG,"
bitfld.long 0x00 31. " ALW_EN_ADPLLDIG_EN ," "0,1"
bitfld.long 0x00 30. " ALW_EN_ADPLLDIG_RST ," "0,1"
bitfld.long 0x00 29. " ALW_EN_ADPLL_CLK_EN ," "0,1"
newline
bitfld.long 0x00 28. " ALW_EN_ADPLL_DCO_EN ," "0,1"
bitfld.long 0x00 27. " ALW_EN_ADC_EN ," "0,1"
bitfld.long 0x00 26. " ALW_EN_ADC_CLK_EN ," "0,1"
newline
bitfld.long 0x00 25. " ALW_EN_IFF_BIAS_SH_OPEN ," "0,1"
bitfld.long 0x00 24. " ALW_EN_IFF_EN ," "0,1"
bitfld.long 0x00 23. " ALW_EN_MIX_BIAS_SH_OPEN ," "0,1"
newline
bitfld.long 0x00 22. " ALW_EN_MIX_EN ," "0,1"
bitfld.long 0x00 21. " ALW_EN_LNA_CGM_EN ," "0,1"
bitfld.long 0x00 20. " ALW_EN_LNA_CORE_EN ," "0,1"
newline
bitfld.long 0x00 19. " ALW_EN_PA_EN ," "0,1"
bitfld.long 0x00 18. " ALW_EN_PA_RAMP_EN ," "0,1"
bitfld.long 0x00 17. " ALW_EN_RFIO_BIAS_SH_OPEN ," "0,1"
newline
bitfld.long 0x00 16. " ALW_EN_RFIO_BIAS_EN ," "0,1"
bitfld.long 0x00 15. " ALW_EN_RFIO_TX_HARM_EN ," "0,1"
bitfld.long 0x00 14. " ALW_EN_RFIO_TX_EN ," "0,1"
newline
bitfld.long 0x00 13. " ALW_EN_RFIO_RX_EN ," "0,1"
bitfld.long 0x00 12. " ALW_EN_ADPLLDIG_LDO_LP ," "0,1"
bitfld.long 0x00 11. " ALW_EN_ADPLLDIG_LDO_ACTIVERDY ," "0,1"
newline
bitfld.long 0x00 10. " ALW_EN_LNA_LDO_ZERO ," "0,1"
bitfld.long 0x00 9. " ALW_EN_LDO_ZERO_EN ," "0,1"
bitfld.long 0x00 8. " ALW_EN_ADPLL_DCO_LDO_EN ," "0,1"
newline
bitfld.long 0x00 7. " ALW_EN_ADPLL_DTC_LDO_EN ," "0,1"
bitfld.long 0x00 6. " ALW_EN_ADPLL_TDC_LDO_EN ," "0,1"
bitfld.long 0x00 5. " ALW_EN_IFFADC_LDO_EN ," "0,1"
newline
bitfld.long 0x00 4. " ALW_EN_IFF_LDO_EN ," "0,1"
bitfld.long 0x00 3. " ALW_EN_MIX_LDO_EN ," "0,1"
bitfld.long 0x00 2. " ALW_EN_LNA_LDO_EN ," "0,1"
newline
bitfld.long 0x00 1. " ALW_EN_PA_LDO_EN ," "0,1"
bitfld.long 0x00 0. " ALW_EN_RFIO_LDO_EN ," "0,1"
group.long 0x184++0x03
line.long 0x00 "RF_ALWAYS_EN2_REG,"
bitfld.long 0x00 14. " ALW_EN_SPARE5 ," "0,1"
bitfld.long 0x00 13. " ALW_EN_SPARE4 ," "0,1"
bitfld.long 0x00 12. " ALW_EN_SPARE3 ," "0,1"
newline
bitfld.long 0x00 11. " ALW_EN_SPARE2 ," "0,1"
bitfld.long 0x00 10. " ALW_EN_SPARE1 ," "0,1"
bitfld.long 0x00 9. " ALW_EN_ADPLL_RDY_FOR_DIV ," "0,1"
newline
bitfld.long 0x00 8. " ALW_EN_PHY_RDY4BS ," "0,1"
bitfld.long 0x00 7. " ALW_EN_DEM_SIGDETECT_EN ," "0,1"
bitfld.long 0x00 6. " ALW_EN_DEM_AGC_UNFREEZE_EN ," "0,1"
newline
bitfld.long 0x00 5. " ALW_EN_DEM_DC_PARCAL_EN ," "0,1"
bitfld.long 0x00 4. " ALW_EN_DEM_EN ," "0,1"
bitfld.long 0x00 3. " ALW_EN_CAL_EN ," "0,1"
newline
bitfld.long 0x00 2. " ALW_EN_ADPLL_LOBUF_PA_EN ," "0,1"
bitfld.long 0x00 1. " ALW_EN_ADPLL_PAIN_EN ," "0,1"
bitfld.long 0x00 0. " ALW_EN_ADPLLDIG_RX_EN ," "0,1"
group.long 0x124++0x03
line.long 0x00 "RF_CNTRL_TIMER_10_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x128++0x03
line.long 0x00 "RF_CNTRL_TIMER_11_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x12C++0x03
line.long 0x00 "RF_CNTRL_TIMER_12_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x130++0x03
line.long 0x00 "RF_CNTRL_TIMER_13_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x134++0x03
line.long 0x00 "RF_CNTRL_TIMER_14_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x138++0x03
line.long 0x00 "RF_CNTRL_TIMER_15_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x13C++0x03
line.long 0x00 "RF_CNTRL_TIMER_16_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x140++0x03
line.long 0x00 "RF_CNTRL_TIMER_17_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x144++0x03
line.long 0x00 "RF_CNTRL_TIMER_18_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x148++0x03
line.long 0x00 "RF_CNTRL_TIMER_19_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x100++0x03
line.long 0x00 "RF_CNTRL_TIMER_1_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x14C++0x03
line.long 0x00 "RF_CNTRL_TIMER_20_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x150++0x03
line.long 0x00 "RF_CNTRL_TIMER_21_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x154++0x03
line.long 0x00 "RF_CNTRL_TIMER_22_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x158++0x03
line.long 0x00 "RF_CNTRL_TIMER_23_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x15C++0x03
line.long 0x00 "RF_CNTRL_TIMER_24_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x160++0x03
line.long 0x00 "RF_CNTRL_TIMER_25_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x164++0x03
line.long 0x00 "RF_CNTRL_TIMER_26_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x168++0x03
line.long 0x00 "RF_CNTRL_TIMER_27_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x16C++0x03
line.long 0x00 "RF_CNTRL_TIMER_28_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x170++0x03
line.long 0x00 "RF_CNTRL_TIMER_29_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x104++0x03
line.long 0x00 "RF_CNTRL_TIMER_2_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x174++0x03
line.long 0x00 "RF_CNTRL_TIMER_30_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x178++0x03
line.long 0x00 "RF_CNTRL_TIMER_31_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x108++0x03
line.long 0x00 "RF_CNTRL_TIMER_3_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x10C++0x03
line.long 0x00 "RF_CNTRL_TIMER_4_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x110++0x03
line.long 0x00 "RF_CNTRL_TIMER_5_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x114++0x03
line.long 0x00 "RF_CNTRL_TIMER_6_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x118++0x03
line.long 0x00 "RF_CNTRL_TIMER_7_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x11C++0x03
line.long 0x00 "RF_CNTRL_TIMER_8_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x120++0x03
line.long 0x00 "RF_CNTRL_TIMER_9_REG,"
hexmask.long.byte 0x00 8.--15. 1. " RESET_OFFSET ,"
hexmask.long.byte 0x00 0.--7. 1. " SET_OFFSET ,"
group.long 0x00++0x03
line.long 0x00 "RF_ENABLE_CONFIG0_REG,"
bitfld.long 0x00 5.--9. " RFIO_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " RFIO_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x28++0x03
line.long 0x00 "RF_ENABLE_CONFIG10_REG,"
bitfld.long 0x00 5.--9. " LNA_LDO_ZERO_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " LNA_LDO_ZERO_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2C++0x03
line.long 0x00 "RF_ENABLE_CONFIG11_REG,"
bitfld.long 0x00 5.--9. " ADPLLDIG_LDO_ACTIVERDY_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLLDIG_LDO_ACTIVERDY_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x30++0x03
line.long 0x00 "RF_ENABLE_CONFIG12_REG,"
bitfld.long 0x00 5.--9. " ADPLLDIG_LDO_LP_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLLDIG_LDO_LP_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x03
line.long 0x00 "RF_ENABLE_CONFIG13_REG,"
bitfld.long 0x00 5.--9. " RFIO_RX_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " RFIO_RX_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x03
line.long 0x00 "RF_ENABLE_CONFIG14_REG,"
bitfld.long 0x00 5.--9. " RFIO_TX_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " RFIO_TX_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C++0x03
line.long 0x00 "RF_ENABLE_CONFIG15_REG,"
bitfld.long 0x00 5.--9. " RFIO_TX_HARM_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " RFIO_TX_HARM_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40++0x03
line.long 0x00 "RF_ENABLE_CONFIG16_REG,"
bitfld.long 0x00 5.--9. " RFIO_BIAS_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " RFIO_BIAS_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x44++0x03
line.long 0x00 "RF_ENABLE_CONFIG17_REG,"
bitfld.long 0x00 5.--9. " RFIO_BIAS_SH_OPEN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " RFIO_BIAS_SH_OPEN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x48++0x03
line.long 0x00 "RF_ENABLE_CONFIG18_REG,"
bitfld.long 0x00 5.--9. " PA_RAMP_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " PA_RAMP_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4C++0x03
line.long 0x00 "RF_ENABLE_CONFIG19_REG,"
bitfld.long 0x00 5.--9. " PA_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " PA_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x04++0x03
line.long 0x00 "RF_ENABLE_CONFIG1_REG,"
bitfld.long 0x00 5.--9. " PA_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " PA_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x50++0x03
line.long 0x00 "RF_ENABLE_CONFIG20_REG,"
bitfld.long 0x00 5.--9. " LNA_CORE_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " LNA_CORE_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x54++0x03
line.long 0x00 "RF_ENABLE_CONFIG21_REG,"
bitfld.long 0x00 5.--9. " LNA_CGM_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " LNA_CGM_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x58++0x03
line.long 0x00 "RF_ENABLE_CONFIG22_REG,"
bitfld.long 0x00 5.--9. " MIX_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " MIX_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5C++0x03
line.long 0x00 "RF_ENABLE_CONFIG23_REG,"
bitfld.long 0x00 5.--9. " MIX_BIAS_SH_OPEN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " MIX_BIAS_SH_OPEN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x60++0x03
line.long 0x00 "RF_ENABLE_CONFIG24_REG,"
bitfld.long 0x00 5.--9. " IFF_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " IFF_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x64++0x03
line.long 0x00 "RF_ENABLE_CONFIG25_REG,"
bitfld.long 0x00 5.--9. " IFF_BIAS_SH_OPEN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " IFF_BIAS_SH_OPEN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x68++0x03
line.long 0x00 "RF_ENABLE_CONFIG26_REG,"
bitfld.long 0x00 5.--9. " ADC_CLK_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADC_CLK_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C++0x03
line.long 0x00 "RF_ENABLE_CONFIG27_REG,"
bitfld.long 0x00 5.--9. " ADC_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADC_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x70++0x03
line.long 0x00 "RF_ENABLE_CONFIG28_REG,"
bitfld.long 0x00 5.--9. " ADPLL_DCO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLL_DCO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x74++0x03
line.long 0x00 "RF_ENABLE_CONFIG29_REG,"
bitfld.long 0x00 5.--9. " ADPLL_CLK_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLL_CLK_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "RF_ENABLE_CONFIG2_REG,"
bitfld.long 0x00 5.--9. " LNA_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " LNA_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x78++0x03
line.long 0x00 "RF_ENABLE_CONFIG30_REG,"
bitfld.long 0x00 5.--9. " ADPLLDIG_RST_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLLDIG_RST_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7C++0x03
line.long 0x00 "RF_ENABLE_CONFIG31_REG,"
bitfld.long 0x00 5.--9. " ADPLLDIG_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLLDIG_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80++0x03
line.long 0x00 "RF_ENABLE_CONFIG32_REG,"
bitfld.long 0x00 5.--9. " ADPLLDIG_RX_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLLDIG_RX_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x84++0x03
line.long 0x00 "RF_ENABLE_CONFIG33_REG,"
bitfld.long 0x00 5.--9. " ADPLLDIG_PAIN_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLLDIG_PAIN_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x88++0x03
line.long 0x00 "RF_ENABLE_CONFIG34_REG,"
bitfld.long 0x00 5.--9. " ADPLL_LOBUF_PA_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLL_LOBUF_PA_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8C++0x03
line.long 0x00 "RF_ENABLE_CONFIG35_REG,"
bitfld.long 0x00 5.--9. " CAL_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " CAL_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x90++0x03
line.long 0x00 "RF_ENABLE_CONFIG36_REG,"
bitfld.long 0x00 5.--9. " DEM_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " DEM_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x94++0x03
line.long 0x00 "RF_ENABLE_CONFIG37_REG,"
bitfld.long 0x00 5.--9. " SPARE_DEM_DC_PARCAL_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " DEM_DC_PARCAL_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x98++0x03
line.long 0x00 "RF_ENABLE_CONFIG38_REG,"
bitfld.long 0x00 5.--9. " SPARE_DEM_AGC_UNFREEZE_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " DEM_AGC_UNFREEZE_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x9C++0x03
line.long 0x00 "RF_ENABLE_CONFIG39_REG,"
bitfld.long 0x00 5.--9. " SPARE_DEM_SIGDETECT_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " DEM_SIGDETECT_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x0C++0x03
line.long 0x00 "RF_ENABLE_CONFIG3_REG,"
bitfld.long 0x00 5.--9. " MIX_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " MIX_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA0++0x03
line.long 0x00 "RF_ENABLE_CONFIG40_REG,"
bitfld.long 0x00 5.--9. " PHY_RDY4BS_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " PHY_RDY4BS_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA4++0x03
line.long 0x00 "RF_ENABLE_CONFIG41_REG,"
bitfld.long 0x00 5.--9. " ADPLL_RDY_FOR_DIV_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLL_RDY_FOR_DIV_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xA8++0x03
line.long 0x00 "RF_ENABLE_CONFIG42_REG,"
bitfld.long 0x00 5.--9. " SPARE1_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " SPARE1_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAC++0x03
line.long 0x00 "RF_ENABLE_CONFIG43_REG,"
bitfld.long 0x00 5.--9. " SPARE2_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " SPARE2_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB0++0x03
line.long 0x00 "RF_ENABLE_CONFIG44_REG,"
bitfld.long 0x00 5.--9. " SPARE3_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " SPARE3_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB4++0x03
line.long 0x00 "RF_ENABLE_CONFIG45_REG,"
bitfld.long 0x00 5.--9. " SPARE4_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " SPARE4_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xB8++0x03
line.long 0x00 "RF_ENABLE_CONFIG46_REG,"
bitfld.long 0x00 5.--9. " SPARE5_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " SPARE5_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10++0x03
line.long 0x00 "RF_ENABLE_CONFIG4_REG,"
bitfld.long 0x00 5.--9. " IFF_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " IFF_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "RF_ENABLE_CONFIG5_REG,"
bitfld.long 0x00 5.--9. " IFFADC_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " IFFADC_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x03
line.long 0x00 "RF_ENABLE_CONFIG6_REG,"
bitfld.long 0x00 5.--9. " ADPLL_TDC_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLL_TDC_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x03
line.long 0x00 "RF_ENABLE_CONFIG7_REG,"
bitfld.long 0x00 5.--9. " ADPLL_DTC_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLL_DTC_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20++0x03
line.long 0x00 "RF_ENABLE_CONFIG8_REG,"
bitfld.long 0x00 5.--9. " ADPLL_DCO_LDO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " ADPLL_DCO_LDO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x24++0x03
line.long 0x00 "RF_ENABLE_CONFIG9_REG,"
bitfld.long 0x00 5.--9. " LDO_ZERO_EN_DCF_TX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " LDO_ZERO_EN_DCF_RX ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x188++0x03
line.long 0x00 "RF_PORT_EN_REG,"
bitfld.long 0x00 9. " RF_PORT4_TX ," "0,1"
bitfld.long 0x00 8. " RF_PORT4_RX ," "0,1"
bitfld.long 0x00 7. " RF_PORT3_TX ," "0,1"
newline
bitfld.long 0x00 6. " RF_PORT3_RX ," "0,1"
bitfld.long 0x00 5. " RF_PORT2_TX ," "0,1"
bitfld.long 0x00 4. " RF_PORT2_RX ," "0,1"
newline
bitfld.long 0x00 3. " RF_PORT1_TX ," "0,1"
bitfld.long 0x00 2. " RF_PORT1_RX ," "0,1"
bitfld.long 0x00 1. " RF_PORT0_TX ," "0,1"
newline
bitfld.long 0x00 0. " RF_PORT0_RX ," "0,1"
group.long 0x18C++0x03
line.long 0x00 "RF_PORT_POL_REG,"
bitfld.long 0x00 4. " RF_PORT4_POL ," "0,1"
bitfld.long 0x00 3. " RF_PORT3_POL ," "0,1"
bitfld.long 0x00 2. " RF_PORT2_POL ," "0,1"
newline
bitfld.long 0x00 1. " RF_PORT1_POL ," "0,1"
bitfld.long 0x00 0. " RF_PORT0_POL ," "0,1"
width 0x0B
tree.end
tree "RFMON"
base ad:0x50003500
width 20.
group.word 0x04++0x01
line.word 0x00 "RFMON_ADDR_REG,"
hexmask.word 0x00 2.--15. 1. " RFMON_ADDR ,"
group.word 0x10++0x01
line.word 0x00 "RFMON_CRV_ADDR_REG,"
hexmask.word 0x00 2.--15. 1. " RFMON_CRV_ADDR ,"
group.word 0x14++0x01
line.word 0x00 "RFMON_CRV_LEN_REG,"
hexmask.word 0x00 0.--13. 1. " RFMON_CRV_LEN ,"
group.word 0x00++0x01
line.word 0x00 "RFMON_CTRL_REG,"
bitfld.word 0x00 1. " RFMON_CIRC_EN ," "0,1"
bitfld.word 0x00 0. " RFMON_PACK_EN ," "0,1"
group.word 0x08++0x01
line.word 0x00 "RFMON_LEN_REG,"
hexmask.word 0x00 0.--13. 1. " RFMON_LEN ,"
group.word 0x0C++0x01
line.word 0x00 "RFMON_STAT_REG,"
bitfld.word 0x00 1. " RFMON_OFLOW_STK ," "0,1"
rbitfld.word 0x00 0. " RFMON_ACTIVE ," "0,1"
width 0x0B
tree.end
tree "RTC"
base ad:0x50004100
width 27.
group.long 0x18++0x03
line.long 0x00 "RTC_ALARM_ENABLE_REG,RTC Alarm Enable Register"
bitfld.long 0x00 5. " RTC_ALARM_MNTH_EN ,Alarm on month enable" "0,1"
bitfld.long 0x00 4. " RTC_ALARM_DATE_EN ,Alarm on date enable" "0,1"
bitfld.long 0x00 3. " RTC_ALARM_HOUR_EN ,Alarm on hour enable" "0,1"
newline
bitfld.long 0x00 2. " RTC_ALARM_MIN_EN ,Alarm on minute enable" "0,1"
bitfld.long 0x00 1. " RTC_ALARM_SEC_EN ,Alarm on second enable" "0,1"
bitfld.long 0x00 0. " RTC_ALARM_HOS_EN ,Alarm on hundredths of a second enable" "0,1"
group.long 0x14++0x03
line.long 0x00 "RTC_CALENDAR_ALARM_REG,RTC Calendar Alram Register"
bitfld.long 0x00 12.--13. " RTC_CAL_D_T ,Date tens" "0,1,2,3"
bitfld.long 0x00 8.--11. " RTC_CAL_D_U ,Date units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. " RTC_CAL_M_T ,Month tens" "0,1"
newline
bitfld.long 0x00 3.--6. " RTC_CAL_M_U ,Month units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "RTC_CALENDAR_REG,RTC Calendar Register"
bitfld.long 0x00 31. " RTC_CAL_CH ,The value in this register has altered since last read" "0,1"
bitfld.long 0x00 28.--29. " RTC_CAL_C_T ,Century tens" "0,1,2,3"
bitfld.long 0x00 24.--27. " RTC_CAL_C_U ,Century units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. " RTC_CAL_Y_T ,Year tens" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. " RTC_CAL_Y_U ,Year units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--13. " RTC_CAL_D_T ,Date tens" "0,1,2,3"
newline
bitfld.long 0x00 8.--11. " RTC_CAL_D_U ,Date units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. " RTC_CAL_M_T ,Month tens" "0,1"
bitfld.long 0x00 3.--6. " RTC_CAL_M_U ,Month units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--2. " RTC_DAY ,Day of the week (arbitrary) units" "0,1,2,3,4,5,6,7"
group.long 0x00++0x03
line.long 0x00 "RTC_CONTROL_REG,RTC Control Register"
bitfld.long 0x00 1. " RTC_CAL_DISABLE ,When this field is set high the RTC stops incrementing the calendar value" "0,1"
bitfld.long 0x00 0. " RTC_TIME_DISABLE ,When this field is set high the RTC stops incrementing the time value" "0,1"
group.long 0x1C++0x03
line.long 0x00 "RTC_EVENT_FLAGS_REG,RTC Event Flags Register"
rbitfld.long 0x00 6. " RTC_EVENT_ALRM ,Alarm event flag" "0,1"
rbitfld.long 0x00 5. " RTC_EVENT_MNTH ,Month rolls over event flag" "0,1"
rbitfld.long 0x00 4. " RTC_EVENT_DATE ,Date rolls over event flag" "0,1"
newline
rbitfld.long 0x00 3. " RTC_EVENT_HOUR ,Hour rolls over event flag" "0,1"
rbitfld.long 0x00 2. " RTC_EVENT_MIN ,Minute rolls over event flag" "0,1"
rbitfld.long 0x00 1. " RTC_EVENT_SEC ,Second rolls over event flag" "0,1"
newline
rbitfld.long 0x00 0. " RTC_EVENT_HOS ,Hundredths of a second event flag" "0,1"
group.long 0x04++0x03
line.long 0x00 "RTC_HOUR_MODE_REG,RTC Hour Mode Register"
bitfld.long 0x00 0. " RTC_HMS ,When this field is set high the RTC operates in 12 hour clock mode. otherwise. times are in 24 hour .." "0,1"
group.long 0x24++0x03
line.long 0x00 "RTC_INTERRUPT_DISABLE_REG,RTC Interrupt Disable Register"
bitfld.long 0x00 6. " RTC_ALRM_INT_DIS ,Interrupt on alarm disable" "0,1"
bitfld.long 0x00 5. " RTC_MNTH_INT_DIS ,Interrupt on month disable" "0,1"
bitfld.long 0x00 4. " RTC_DATE_INT_DIS ,Interrupt on date disable" "0,1"
newline
bitfld.long 0x00 3. " RTC_HOUR_INT_DIS ,IInterrupt on hour disable" "0,1"
bitfld.long 0x00 2. " RTC_MIN_INT_DIS ,Interrupt on minute disable" "0,1"
bitfld.long 0x00 1. " RTC_SEC_INT_DIS ,Interrupt on second disable" "0,1"
newline
bitfld.long 0x00 0. " RTC_HOS_INT_DIS ,Interrupt on hundredths of a second disable" "0,1"
group.long 0x20++0x03
line.long 0x00 "RTC_INTERRUPT_ENABLE_REG,RTC Interrupt Enable Register"
bitfld.long 0x00 6. " RTC_ALRM_INT_EN ,Interrupt on alarm enable" "0,1"
bitfld.long 0x00 5. " RTC_MNTH_INT_EN ,Interrupt on month enable" "0,1"
bitfld.long 0x00 4. " RTC_DATE_INT_EN ,Interrupt on date enable" "0,1"
newline
bitfld.long 0x00 3. " RTC_HOUR_INT_EN ,Interrupt on hour enable" "0,1"
bitfld.long 0x00 2. " RTC_MIN_INT_EN ,Interrupt on minute enable" "0,1"
bitfld.long 0x00 1. " RTC_SEC_INT_EN ,Interrupt on second enable" "0,1"
newline
bitfld.long 0x00 0. " RTC_HOS_INT_EN ,Interrupt on hundredths of a second enable" "0,1"
group.long 0x28++0x03
line.long 0x00 "RTC_INTERRUPT_MASK_REG,RTC Interrupt Mask Register"
rbitfld.long 0x00 6. " RTC_ALRM_INT_MSK ,Mask alarm interrupt" "0,1"
rbitfld.long 0x00 5. " RTC_MNTH_INT_MSK ,Mask month interrupt" "0,1"
rbitfld.long 0x00 4. " RTC_DATE_INT_MSK ,Mask date interrupt" "0,1"
newline
rbitfld.long 0x00 3. " RTC_HOUR_INT_MSK ,Mask hour interrupt" "0,1"
rbitfld.long 0x00 2. " RTC_MIN_INT_MSK ,Mask minute interrupt" "0,1"
rbitfld.long 0x00 1. " RTC_SEC_INT_MSK ,Mask second interrupt" "0,1"
newline
rbitfld.long 0x00 0. " RTC_HOS_INT_MSK ,Mask hundredths of a second interrupt" "0,1"
group.long 0x30++0x03
line.long 0x00 "RTC_KEEP_RTC_REG,RTC Keep RTC Register"
bitfld.long 0x00 0. " RTC_KEEP ,Keep RTC" "0,1"
group.long 0x2C++0x03
line.long 0x00 "RTC_STATUS_REG,RTC Status Register"
rbitfld.long 0x00 3. " RTC_VALID_CAL_ALM ,Valid Calendar Alarm" "0,1"
rbitfld.long 0x00 2. " RTC_VALID_TIME_ALM ,Valid Time Alarm" "0,1"
rbitfld.long 0x00 1. " RTC_VALID_CAL ,Valid Calendar" "0,1"
newline
rbitfld.long 0x00 0. " RTC_VALID_TIME ,Valid Time" "0,1"
group.long 0x10++0x03
line.long 0x00 "RTC_TIME_ALARM_REG,RTC Time Alarm Register"
bitfld.long 0x00 30. " RTC_TIME_PM ,In 12 hour clock mode. indicates PM when set" "0,1"
bitfld.long 0x00 28.--29. " RTC_TIME_HR_T ,Hours tens" "0,1,2,3"
bitfld.long 0x00 24.--27. " RTC_TIME_HR_U ,Hours units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--22. " RTC_TIME_M_T ,Minutes tens" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. " RTC_TIME_M_U ,Minutes units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--14. " RTC_TIME_S_T ,Seconds tens" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--11. " RTC_TIME_S_U ,Seconds units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. " RTC_TIME_H_T ,Hundredths of a second tens" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " RTC_TIME_H_U ,Hundredths of a second units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "RTC_TIME_REG,RTC Time Register"
bitfld.long 0x00 31. " RTC_TIME_CH ,The value in this register has altered since last read" "0,1"
bitfld.long 0x00 30. " RTC_TIME_PM ,In 12 hour clock mode. indicates PM when set" "0,1"
bitfld.long 0x00 28.--29. " RTC_TIME_HR_T ,Hours tens" "0,1,2,3"
newline
bitfld.long 0x00 24.--27. " RTC_TIME_HR_U ,Hours units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--22. " RTC_TIME_M_T ,Minutes tens" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. " RTC_TIME_M_U ,Minutes units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--14. " RTC_TIME_S_T ,Seconds tens" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. " RTC_TIME_S_U ,Seconds units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. " RTC_TIME_H_T ,Hundredths of a second tens" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. " RTC_TIME_H_U ,Hundredths of a second units" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
width 0x0B
tree.end
tree "SPI"
base ad:0x50001200
width 26.
group.word 0x08++0x01
line.word 0x00 "SPI_CLOCK_REG,Spi clock register"
bitfld.word 0x00 7. " SPI_MASTER_CLK_MODE ,Should be always 1" "0,1"
hexmask.word.byte 0x00 0.--6. 1. " SPI_CLK_DIV ,Applicable only in master mode_Defines the spi clock frequency in master only mode_SPI_CLK = module_.."
group.word 0x04++0x01
line.word 0x00 "SPI_CONFIG_REG,Spi control register"
bitfld.word 0x00 7. " SPI_SLAVE_EN ,0 = SPI module master mode_1 = SPI module slave mode" "0,1"
bitfld.word 0x00 2.--6. " SPI_WORD_LENGTH ,Define the spi word length = 1+ SPI_WORD_LENGTH (range 4 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--1. " SPI_MODE ,Define the spi mode (CPOL. CPHA)_0 = new data on falling. capture on rising. clk low in idle state_1.." "0,1,2,3"
group.word 0x24++0x01
line.word 0x00 "SPI_CS_CONFIG_REG,Spi cs configuration register"
bitfld.word 0x00 0.--2. " SPI_CS_SELECT ,Control the cs output in master mode_0 = none slave device selected_1 = selected slave device connec.." "0,1,2,3,4,5,6,7"
group.word 0x00++0x01
line.word 0x00 "SPI_CTRL_REG,Spi control register"
bitfld.word 0x00 7. " SPI_SWAP_BYTES ,0 = normal operation_1 = LSB and MSB are swaped in APB interface_In case of 8bit spi interface. DMA/.." "0,1"
bitfld.word 0x00 6. " SPI_CAPTURE_AT_NEXT_EDGE ,0 = SPI captures data at correct clock edge_1 = SPI captures data at next clock edge" "0,1"
bitfld.word 0x00 5. " SPI_FIFO_RESET ,0 = Fifo normal operation_1 = Fifo in reset state" "0,1"
newline
bitfld.word 0x00 4. " SPI_DMA_RX_EN ,applicable only when SPI_RX_EN=1_0 = No DMA request for RX_1 = DMA request when SPI_STATUS_RX_FULL='.." "0,1"
bitfld.word 0x00 3. " SPI_DMA_TX_EN ,applicable only when SPI_TX_EN=1_0 = No DMA request for TX_1 = DMA request when SPI_STATUS_TX_EMPTY=.." "0,1"
bitfld.word 0x00 2. " SPI_RX_EN ,0 = RX path is disabled_1 = RX path is enabled_Note: if master clk async or spi mode=1 or spi mode=3.." "0,1"
newline
bitfld.word 0x00 1. " SPI_TX_EN ,0 = TX path is disabled_1 = TX path is enabled" "0,1"
bitfld.word 0x00 0. " SPI_EN ,0 = SPI module is disable_1 = SPI module is enable" "0,1"
group.word 0x0C++0x01
line.word 0x00 "SPI_FIFO_CONFIG_REG,Spi fifo configuration register"
bitfld.word 0x00 4.--7. " SPI_RX_TL ,Receive FIFO threshold level in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. " SPI_TX_TL ,Transmit FIFO threshold level in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.word 0x28++0x01
hide.word 0x00 "SPI_FIFO_HIGH ,RX/TX fifo data"
in
hgroup.word 0x1C++0x01
hide.word 0x00 "SPI_FIFO_READ ,Read from RX fifo"
in
group.word 0x18++0x01
line.word 0x00 "SPI_FIFO_STATUS_REG,SPI RX/TX fifo status register"
rbitfld.word 0x00 15. " SPI_TRANSACTION_ACTIVE ,In master mode_0 = spi transaction is inactive_1 = spi transaction is active" "0,1"
rbitfld.word 0x00 14. " SPI_RX_FIFO_OVFL ,When 1. receive data is not written to fifo because fifo was full and interrupt is generated" "0,1"
rbitfld.word 0x00 13. " SPI_STATUS_TX_FULL ,0 = TX fifo is not full_1 = TX fifo is full" "0,1"
newline
rbitfld.word 0x00 12. " SPI_STATUS_RX_EMPTY ,0 = RX fifo is not empty_1 = RX fifo is empty" "0,1"
rbitfld.word 0x00 6.--11. " SPI_TX_FIFO_LEVEL ,Gives the number of bytes in TX fifo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.word 0x00 0.--5. " SPI_RX_FIFO_LEVEL ,Gives the number of bytes in RX fifo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x20++0x01
line.word 0x00 "SPI_FIFO_WRITE_REG,Spi TX fifo wtite register"
hexmask.word 0x00 0.--15. 1. " SPI_FIFO_WRITE ,Write to TX fifo"
group.word 0x10++0x01
line.word 0x00 "SPI_IRQ_MASK_REG,Spi interrupt mask register"
bitfld.word 0x00 1. " SPI_IRQ_MASK_RX_FULL ,0 = FIFO RX full irq is masked_1 = FIFO RX full irq is enabled" "0,1"
bitfld.word 0x00 0. " SPI_IRQ_MASK_TX_EMPTY ,0 = FIFO TX empty irq is masked_1 = FIFO TX empy irq is enabled" "0,1"
group.word 0x14++0x01
line.word 0x00 "SPI_STATUS_REG,Spi status register"
rbitfld.word 0x00 1. " SPI_STATUS_RX_FULL ,Auto clear_0 = RX fifo level is less than SPI_RX_TL+1_1 = RX fifo level is more or equal to SPI_RX_T.." "0,1"
rbitfld.word 0x00 0. " SPI_STATUS_TX_EMPTY ,Auto clear_0 = TX fifo level is larger than SPI_TX_TL_1 = TX fifo level is less or equal to SPI_TX_T.." "0,1"
group.word 0x30++0x01
line.word 0x00 "SPI_TXBUFFER_FORCE_H_REG,SPI TX buffer force high value"
hexmask.word 0x00 0.--15. 1. " SPI_TXBUFFER_FORCE_H ,Write directly the tx buffer (2 MSB)"
group.word 0x2C++0x01
line.word 0x00 "SPI_TXBUFFER_FORCE_L_REG,SPI TX buffer force low value"
hexmask.word 0x00 0.--15. 1. " SPI_TXBUFFER_FORCE_L ,Write directly the tx buffer (2 LSB)"
width 0x0B
tree.end
tree "SYS_WDOG"
base ad:0x50003100
width 19.
group.word 0x02++0x01
line.word 0x00 "WATCHDOG_CTRL_REG,Watchdog control register"
bitfld.word 0x00 0. " NMI_RST ,0 = Watchdog timer generates NMI at value 0. and WDOG (SYS) reset at <=-16" "0,1"
group.word 0x00++0x01
line.word 0x00 "WATCHDOG_REG,Watchdog timer register"
hexmask.word.byte 0x00 9.--15. 1. " WDOG_WEN ,0000.000 = Write enable for Watchdog timer_else Write disable. This filter prevents unintentional presetting the watchdog with a SW run-away."
bitfld.word 0x00 8. " WDOG_VAL_NEG ,0 = Watchdog timer value is positive" "0,1"
hexmask.word.byte 0x00 0.--7. 1. " WDOG_VAL ,Write: Watchdog timer reload value"
width 0x0B
tree.end
tree "TIMER0"
base ad:0x50003400
width 22.
group.word 0x16++0x01
line.word 0x00 "PWM2_END_CYCLE,Defines end Cycle for PWM2"
hexmask.word 0x00 0.--13. 1. " END_CYCLE ,Defines the cycle in which the PWM becomes low"
group.word 0x0A++0x01
line.word 0x00 "PWM2_START_CYCLE,Defines start Cycle for PWM2"
hexmask.word 0x00 0.--13. 1. " START_CYCLE ,Defines the cycle in which the PWM becomes high"
group.word 0x18++0x01
line.word 0x00 "PWM3_END_CYCLE,Defines end Cycle for PWM3"
hexmask.word 0x00 0.--13. 1. " END_CYCLE ,Defines the cycle in which the PWM becomes low"
group.word 0x0C++0x01
line.word 0x00 "PWM3_START_CYCLE,Defines start Cycle for PWM3"
hexmask.word 0x00 0.--13. 1. " START_CYCLE ,Defines the cycle in which the PWM becomes high"
group.word 0x1A++0x01
line.word 0x00 "PWM4_END_CYCLE,Defines end Cycle for PWM4"
hexmask.word 0x00 0.--13. 1. " END_CYCLE ,Defines the cycle in which the PWM becomes low"
group.word 0x0E++0x01
line.word 0x00 "PWM4_START_CYCLE,Defines start Cycle for PWM4"
hexmask.word 0x00 0.--13. 1. " START_CYCLE ,Defines the cycle in which the PWM becomes high"
group.word 0x1C++0x01
line.word 0x00 "PWM5_END_CYCLE,Defines end Cycle for PWM5"
hexmask.word 0x00 0.--13. 1. " END_CYCLE ,Defines the cycle in which the PWM becomes low"
group.word 0x10++0x01
line.word 0x00 "PWM5_START_CYCLE,Defines start Cycle for PWM5"
hexmask.word 0x00 0.--13. 1. " START_CYCLE ,Defines the cycle in which the PWM becomes high"
group.word 0x1E++0x01
line.word 0x00 "PWM6_END_CYCLE,Defines end Cycle for PWM6"
hexmask.word 0x00 0.--13. 1. " END_CYCLE ,Defines the cycle in which the PWM becomes low"
group.word 0x12++0x01
line.word 0x00 "PWM6_START_CYCLE,Defines start Cycle for PWM6"
hexmask.word 0x00 0.--13. 1. " START_CYCLE ,Defines the cycle in which the PWM becomes high"
group.word 0x20++0x01
line.word 0x00 "PWM7_END_CYCLE,Defines end Cycle for PWM7"
hexmask.word 0x00 0.--13. 1. " END_CYCLE ,Defines the cycle in which the PWM becomes low"
group.word 0x14++0x01
line.word 0x00 "PWM7_START_CYCLE,Defines start Cycle for PWM7"
hexmask.word 0x00 0.--13. 1. " START_CYCLE ,Defines the cycle in which the PWM becomes high"
group.word 0x00++0x01
line.word 0x00 "TIMER0_CTRL_REG,Timer0 control register"
bitfld.word 0x00 3. " PWM_MODE ,0 = PWM signals are '1' during high time" "0,1"
bitfld.word 0x00 2. " TIM0_CLK_DIV ,1 = Timer0 uses selected clock frequency as is" "0,1"
bitfld.word 0x00 1. " TIM0_CLK_SEL ,1 = Timer0 uses 16. 8. 4 or 2 MHz (fast) clock frequency" "0,1"
newline
bitfld.word 0x00 0. " TIM0_CTRL ,0 = Timer0 is off and in reset state" "0,1"
group.word 0x02++0x01
line.word 0x00 "TIMER0_ON_REG,Timer0 on control register"
hexmask.word 0x00 0.--15. 1. " TIM0_ON ,Timer0 On reload value:_If read the actual ON-counter value is returned"
group.word 0x04++0x01
line.word 0x00 "TIMER0_RELOAD_M_REG,16 bits reload value for Timer0"
hexmask.word 0x00 0.--15. 1. " TIM0_M ,Timer0 'high' reload value_If read the actual T0-counter value is returned"
group.word 0x06++0x01
line.word 0x00 "TIMER0_RELOAD_N_REG,16 bits reload value for Timer0"
hexmask.word 0x00 0.--15. 1. " TIM0_N ,Timer0 'low' reload value:_If read the actual T0-counter value is returned"
group.word 0x22++0x01
line.word 0x00 "TRIPLE_PWM_CTRL_REG,PWM 2.3.4.5.6.7 Control"
bitfld.word 0x00 3. " TRIPLE_PWM_CLK_SEL ,1 = Timer2 uses 16. 8. 4 or 2 MHz (fast) clock frequency" "0,1"
bitfld.word 0x00 2. " HW_PAUSE_EN ,'1' = HW can pause PWM 2.3.4.5.6.7" "0,1"
bitfld.word 0x00 1. " SW_PAUSE_EN ,'1' = PWM 2 3 4 5 6 7 are paused" "0,1"
newline
bitfld.word 0x00 0. " TRIPLE_PWM_ENABLE ,'1' = enable PWM 2 3 4 5 6 7" "0,1"
group.word 0x08++0x01
line.word 0x00 "TRIPLE_PWM_FREQUENCY,Frequency for PWM 2.3.4.5.6 and 7"
hexmask.word 0x00 0.--13. 1. " PWM_FREQ ,Defines the frequeancy of PWM 2.3.4.5..6 and 7"
width 0x0B
tree.end
tree "TIMER1"
base ad:0x50004000
width 26.
group.long 0x0C++0x03
line.long 0x00 "TIMER1_CAPCNT1_VALUE_REG,Timer1 value for event on GPIO1"
hexmask.long.word 0x00 11.--21. 1. " TIMER1_CAPCNT1_RTC_HIGH ,In Counter mode : Not used_In Capture mode: Gives the RTC time stamp (high part) when an IN1 event w.."
hexmask.long.word 0x00 0.--10. 1. " TIMER1_CAPCNT1_VALUE ,In Counter mode : Gives the number of timer clock cycles minus 1 which was measured during TIMER1_IN.."
group.long 0x10++0x03
line.long 0x00 "TIMER1_CAPCNT2_VALUE_REG,Timer1 value for event on GPIO2"
hexmask.long.word 0x00 11.--21. 1. " TIMER1_CAPCNT2_RTC_HIGH ,In Counter mode : Not used_In Capture mode: Gives the RTC time stamp (high part) when an IN2 event w.."
hexmask.long.word 0x00 0.--10. 1. " TIMER1_CAPCNT2_VALUE ,In Counter mode : Gives the number of timer clock cycles minus 1 which was measured during TIMER1_IN.."
group.long 0x04++0x03
line.long 0x00 "TIMER1_CAPTURE_REG,Timer1 Capture control register"
bitfld.long 0x00 27. " TIMER1_IN2_STAMP_TYPE ,0 = On each event store the counter value_1 = On each event store the RTC time stamp" "0,1"
bitfld.long 0x00 21.--26. " TIMER1_IN2_PERIOD_MAX ,Gives the number of periods +1 of IN2. in which module counts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. " TIMER1_IN2_IRQ_EN ,1 = Interrupt is generated when capture is occurred or was counted TIMER1_IN2_PERIOD_MAX_0 = Interru.." "0,1"
newline
bitfld.long 0x00 19. " TIMER1_IN2_COUNT_EN ,0 = Capture mode_1 = Count mode" "0,1"
bitfld.long 0x00 18. " TIMER1_IN2_EVENT_FALL_EN ,0 = Rising edge event_1 = Falling edge event_it should be written when TIMER1_GPIO2_CONF=0 to preven.." "0,1"
bitfld.long 0x00 14.--17. " TIMER1_GPIO2_CONF ,0.13.14.15 = IN2 is not used_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. " TIMER1_IN1_STAMP_TYPE ,0 = On each event store the counter value_1 = On each event store the RTC time stamp" "0,1"
bitfld.long 0x00 7.--12. " TIMER1_IN1_PERIOD_MAX ,Gives the number of periods +1 of IN1. in which module counts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6. " TIMER1_IN1_IRQ_EN ,1 = Interrupt is generated when capture is occurred or was counted TIMER1_IN1_PERIOD_MAX_0 = Interru.." "0,1"
newline
bitfld.long 0x00 5. " TIMER1_IN1_COUNT_EN ,0 = Capture mode_1 = Count mode" "0,1"
bitfld.long 0x00 4. " TIMER1_IN1_EVENT_FALL_EN ,0 = Rising edge event_1 = Falling edge event_it should be written when TIMER1_GPIO1_CONF=0 to preven.." "0,1"
bitfld.long 0x00 0.--3. " TIMER1_GPIO1_CONF ,0.13.14.15 = IN1 is not used_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "TIMER1_CLR_EVENT_REG,Clear event register"
bitfld.long 0x00 2. " TIMER1_CLR_IN2_EVENT ,Write 1 to clear the TIMER1_IN2_EVENT and TIMER1_IN2_OVRFLW" "0,1"
bitfld.long 0x00 1. " TIMER1_CLR_IN1_EVENT ,Write 1 to clear the TIMER1_IN1_EVENT and TIMER1_IN1_OVRFLW" "0,1"
bitfld.long 0x00 0. " TIMER1_CLR_TIMER_EVENT ,Write 1 to clear the TIMER1_TIMER_EVENT" "0,1"
group.long 0x00++0x03
line.long 0x00 "TIMER1_CTRL_REG,Timer1 control register"
bitfld.long 0x00 16. " TIMER1_CLK_EN ,0 = timer1 clock is disabled_1 = timer1 clock is enabled" "0,1"
bitfld.long 0x00 15. " TIMER1_USE_SYS_CLK ,0 = Timer1 use the clock LP clock_1 = Timer1 use the system clock" "0,1"
bitfld.long 0x00 14. " TIMER1_FREE_RUN_MODE_EN ,Applicable when timer counts up_1 = timer1 goes to zero when it reaches the max value" "0,1"
newline
bitfld.long 0x00 13. " TIMER1_IRQ_EN ,0 = timer1 IRQ masked_1 = timer1 IRQ unmasked" "0,1"
bitfld.long 0x00 12. " TIMER1_COUNT_DOWN_EN ,0 = timer1 counts up_1 = timer1 counts down" "0,1"
bitfld.long 0x00 11. " TIMER1_ENABLE ,0 = Timer1 disabled_1 = Timer1 enabled" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. " TIMER1_RELOAD ,Reload or max value in timer mode"
group.long 0x08++0x03
line.long 0x00 "TIMER1_STATUS_REG,Timer1 counter value"
rbitfld.long 0x00 15. " TIMER1_IN2_OVRFLW ,1 = New IN2 event occurred while Interrupt was pending" "0,1"
rbitfld.long 0x00 14. " TIMER1_IN1_OVRFLW ,1 = New IN1 event occurred while Interrupt was pending" "0,1"
rbitfld.long 0x00 13. " TIMER1_IN2_EVENT ,1 = Pending Capture 2 interrupt" "0,1"
newline
rbitfld.long 0x00 12. " TIMER1_IN1_EVENT ,1 = Pending Capture 1 interrupt" "0,1"
rbitfld.long 0x00 11. " TIMER1_TIMER_EVENT ,1 = Pending Timer interrupt" "0,1"
hexmask.long.word 0x00 0.--10. 1. " TIMER1_TIMER_VALUE ,Gives the current timer value"
width 0x0B
tree.end
tree "UART"
base ad:0x50001000
width 22.
group.word 0xFE++0x01
line.word 0x00 "UART_CTR_HIGH_REG,Component Type Register"
hexmask.word 0x00 0.--15. 1. " CTR ,Component Type Register"
group.word 0xFC++0x01
line.word 0x00 "UART_CTR_REG,Component Type Register"
hexmask.word 0x00 0.--15. 1. " CTR ,Component Type Register"
group.word 0xC0++0x01
line.word 0x00 "UART_DLF_REG,Divisor Latch Fraction Register"
bitfld.word 0x00 0.--3. " UART_DLF ,The fractional value is added to integer value set by DLH. DLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x01
line.word 0x00 "UART_DMASA_REG,DMA Software Acknowledge"
bitfld.word 0x00 0. " DMASA ,This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to.." "0,1"
group.word 0x70++0x01
line.word 0x00 "UART_FAR_REG,FIFO Access Register"
rbitfld.word 0x00 0. " UART_FAR ,Description: Writes will have no effect when FIFO_ACCESS == No. always readable" "0,1"
group.word 0xA4++0x01
line.word 0x00 "UART_HTX_REG,Halt TX"
bitfld.word 0x00 0. " UART_HALT_TX ,This register is use to halt transmissions for testing. so that the transmit FIFO can be filled by t.." "0,1"
group.word 0x04++0x01
line.word 0x00 "UART_IER_DLH_REG,Interrupt Enable Register/Divisor Latch High"
bitfld.word 0x00 7. " PTIME_dlh7 ,Interrupt Enable Register: PTIME. Programmable THRE Interrupt Mode Enable" "0,1"
bitfld.word 0x00 4.--6. " dlh6_4 ,Divisor Latch (High): DLH6 to DLH4. Bits 6 to 4 of the upper part of a 16-bit. read/write. Divisor L.." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 3. " EDSSI_dlh3 ,Interrupt Enable Register: EDSSI. Enable Modem Status Interrupt" "0,1"
newline
bitfld.word 0x00 2. " ELSI_dhl2 ,Interrupt Enable Register: ELSI. Enable Receiver Line Status Interrupt" "0,1"
bitfld.word 0x00 1. " ETBEI_dlh1 ,Interrupt Enable Register: ETBEI. Enable Transmit Holding Register Empty Interrupt" "0,1"
bitfld.word 0x00 0. " ERBFI_dlh0 ,Interrupt Enable Register: ERBFI. Enable Received Data Available Interrupt" "0,1"
group.word 0x08++0x01
line.word 0x00 "UART_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register"
bitfld.word 0x00 6.--7. " UART_FIFOSE_RT ,On read_FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disab.." "0,1,2,3"
bitfld.word 0x00 4.--5. " UART_TET ,On read_reserved_On Write_TX Empty Trigger (or TET): This is used to select the empty threshold leve.." "0,1,2,3"
bitfld.word 0x00 3. " UART_IID3_DMAM ,On Read (Bit3)_Interrupt ID (or IID): This indicates the highest priority pending interrupt which ca.." "0,1"
newline
bitfld.word 0x00 2. " UART_IID2_XFIFOR ,On Read (Bit2)_Interrupt ID (or IID): This indicates the highest priority pending interrupt which ca.." "0,1"
bitfld.word 0x00 1. " UART_IID1_RFIFOE ,On Read (Bit1)_Interrupt ID (or IID): This indicates the highest priority pending interrupt which ca.." "0,1"
bitfld.word 0x00 0. " UART_IID0_FIFOE ,On Read (Bit0)_Interrupt ID (or IID): This indicates the highest priority pending interrupt which ca.." "0,1"
group.word 0x0C++0x01
line.word 0x00 "UART_LCR_REG,Line Control Register"
bitfld.word 0x00 7. " UART_DLAB ,Divisor Latch Access Bit" "0,1"
bitfld.word 0x00 6. " UART_BC ,Break Control Bit" "0,1"
bitfld.word 0x00 4. " UART_EPS ,Even Parity Select" "0,1"
newline
bitfld.word 0x00 3. " UART_PEN ,Parity Enable" "0,1"
bitfld.word 0x00 2. " UART_STOP ,Number of stop bits" "0,1"
bitfld.word 0x00 0.--1. " UART_DLS ,Data Length Select" "0,1,2,3"
group.word 0x14++0x01
line.word 0x00 "UART_LSR_REG,Line Status Register"
rbitfld.word 0x00 7. " UART_RFE ,Receiver FIFO Error bit" "0,1"
rbitfld.word 0x00 6. " UART_TEMT ,Transmitter Empty bit" "0,1"
rbitfld.word 0x00 5. " UART_THRE ,Transmit Holding Register Empty bit" "0,1"
newline
rbitfld.word 0x00 4. " UART_BI ,Break Interrupt bit" "0,1"
rbitfld.word 0x00 3. " UART_FE ,Framing Error bit" "0,1"
rbitfld.word 0x00 2. " UART_PE ,Parity Error bit" "0,1"
newline
rbitfld.word 0x00 1. " UART_OE ,Overrun error bit" "0,1"
rbitfld.word 0x00 0. " UART_DR ,Data Ready bit" "0,1"
group.word 0x10++0x01
line.word 0x00 "UART_MCR_REG,Modem Control Register"
bitfld.word 0x00 5. " UART_AFCE ,Auto Flow Control Enable" "0,1"
bitfld.word 0x00 4. " UART_LB ,LoopBack Bit" "0,1"
bitfld.word 0x00 1. " UART_RTS ,Request to Send" "0,1"
group.word 0x18++0x01
line.word 0x00 "UART_MSR_REG,Modem Status Register"
rbitfld.word 0x00 4. " UART_CTS ,Clear to Send" "0,1"
group.word 0x00++0x01
line.word 0x00 "UART_RBR_THR_DLL_REG,Receive Buffer Register/Transmit Holding Register/Divisor Latch Low"
hexmask.word.byte 0x00 0.--7. 1. " RBR_THR_DLL ,Receive Buffer Register: (RBR)"
group.word 0x84++0x01
line.word 0x00 "UART_RFL_REG,Receive FIFO Level"
rbitfld.word 0x00 0.--4. " UART_RECEIVE_FIFO_LEVEL ,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x90++0x01
line.word 0x00 "UART_SBCR_REG,Shadow Break Control Register"
bitfld.word 0x00 0. " UART_SHADOW_BREAK_CONTROL ,Shadow Break Control Bit" "0,1"
group.word 0x1C++0x01
line.word 0x00 "UART_SCR_REG,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. " UART_SCRATCH_PAD ,This register is for programmers to use as a temporary storage space"
group.word 0x94++0x01
line.word 0x00 "UART_SDMAM_REG,Shadow DMA Mode"
bitfld.word 0x00 0. " UART_SHADOW_DMA_MODE ,Shadow DMA Mode" "0,1"
group.word 0x98++0x01
line.word 0x00 "UART_SFE_REG,Shadow FIFO Enable"
bitfld.word 0x00 0. " UART_SHADOW_FIFO_ENABLE ,Shadow FIFO Enable" "0,1"
group.word 0x30++0x01
line.word 0x00 "UART_SRBR_STHR0_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x58++0x01
line.word 0x00 "UART_SRBR_STHR10_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x5C++0x01
line.word 0x00 "UART_SRBR_STHR11_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x60++0x01
line.word 0x00 "UART_SRBR_STHR12_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x64++0x01
line.word 0x00 "UART_SRBR_STHR13_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x68++0x01
line.word 0x00 "UART_SRBR_STHR14_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x6C++0x01
line.word 0x00 "UART_SRBR_STHR15_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x34++0x01
line.word 0x00 "UART_SRBR_STHR1_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x38++0x01
line.word 0x00 "UART_SRBR_STHR2_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x3C++0x01
line.word 0x00 "UART_SRBR_STHR3_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x40++0x01
line.word 0x00 "UART_SRBR_STHR4_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x44++0x01
line.word 0x00 "UART_SRBR_STHR5_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x48++0x01
line.word 0x00 "UART_SRBR_STHR6_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x4C++0x01
line.word 0x00 "UART_SRBR_STHR7_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x50++0x01
line.word 0x00 "UART_SRBR_STHR8_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x54++0x01
line.word 0x00 "UART_SRBR_STHR9_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x88++0x01
line.word 0x00 "UART_SRR_REG,Software Reset Register"
bitfld.word 0x00 2. " UART_XFR ,XMIT FIFO Reset" "0,1"
bitfld.word 0x00 1. " UART_RFR ,RCVR FIFO Reset" "0,1"
bitfld.word 0x00 0. " UART_UR ,UART Reset" "0,1"
group.word 0x8C++0x01
line.word 0x00 "UART_SRTS_REG,Shadow Request to Send"
bitfld.word 0x00 0. " UART_SHADOW_REQUEST_TO_SEND ,Shadow Request to Send" "0,1"
group.word 0x9C++0x01
line.word 0x00 "UART_SRT_REG,Shadow RCVR Trigger"
bitfld.word 0x00 0.--1. " UART_SHADOW_RCVR_TRIGGER ,Shadow RCVR Trigger" "0,1,2,3"
group.word 0xA0++0x01
line.word 0x00 "UART_STET_REG,Shadow TX Empty Trigger"
bitfld.word 0x00 0.--1. " UART_SHADOW_TX_EMPTY_TRIGGER ,Shadow TX Empty Trigger" "0,1,2,3"
group.word 0x80++0x01
line.word 0x00 "UART_TFL_REG,Transmit FIFO Level"
rbitfld.word 0x00 0.--4. " UART_TRANSMIT_FIFO_LEVEL ,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0xFA++0x01
line.word 0x00 "UART_UCV_HIGH_REG,Component Version"
hexmask.word 0x00 0.--15. 1. " UCV ,Component Version"
group.word 0xF8++0x01
line.word 0x00 "UART_UCV_REG,Component Version"
hexmask.word 0x00 0.--15. 1. " UCV ,Component Version"
group.word 0x7C++0x01
line.word 0x00 "UART_USR_REG,UART Status Register"
rbitfld.word 0x00 4. " UART_RFF ,Receive FIFO Full" "0,1"
rbitfld.word 0x00 3. " UART_RFNE ,Receive FIFO Not Empty" "0,1"
rbitfld.word 0x00 2. " UART_TFE ,Transmit FIFO Empty" "0,1"
newline
rbitfld.word 0x00 1. " UART_TFNF ,Transmit FIFO Not Full" "0,1"
rbitfld.word 0x00 0. " UART_BUSY ,UART Busy" "0,1"
width 0x0B
tree.end
tree "UART2"
base ad:0x50001100
width 23.
group.word 0xFE++0x01
line.word 0x00 "UART2_CTR_HIGH_REG,Component Type Register"
hexmask.word 0x00 0.--15. 1. " CTR ,Component Type Register"
group.word 0xFC++0x01
line.word 0x00 "UART2_CTR_REG,Component Type Register"
hexmask.word 0x00 0.--15. 1. " CTR ,Component Type Register"
group.word 0xC0++0x01
line.word 0x00 "UART2_DLF_REG,Divisor Latch Fraction Register"
bitfld.word 0x00 0.--3. " UART_DLF ,The fractional value is added to integer value set by DLH. DLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0xA8++0x01
line.word 0x00 "UART2_DMASA_REG,DMA Software Acknowledge"
bitfld.word 0x00 0. " DMASA ,This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to.." "0,1"
group.word 0x70++0x01
line.word 0x00 "UART2_FAR_REG,FIFO Access Register"
rbitfld.word 0x00 0. " UART_FAR ,Description: Writes will have no effect when FIFO_ACCESS == No. always readable" "0,1"
group.word 0xA4++0x01
line.word 0x00 "UART2_HTX_REG,Halt TX"
bitfld.word 0x00 0. " UART_HALT_TX ,This register is use to halt transmissions for testing. so that the transmit FIFO can be filled by t.." "0,1"
group.word 0x04++0x01
line.word 0x00 "UART2_IER_DLH_REG,Interrupt Enable Register/Divisor Latch High"
bitfld.word 0x00 7. " PTIME_dlh7 ,Interrupt Enable Register: PTIME. Programmable THRE Interrupt Mode Enable" "0,1"
bitfld.word 0x00 4.--6. " dlh6_4 ,Divisor Latch (High): DLH6 to DLH4. Bits 6 to 4 of the upper part of a 16-bit. read/write. Divisor L.." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 3. " EDSSI_dlh3 ,Interrupt Enable Register: EDSSI. Enable Modem Status Interrupt" "0,1"
newline
bitfld.word 0x00 2. " ELSI_dhl2 ,Interrupt Enable Register: ELSI. Enable Receiver Line Status Interrupt" "0,1"
bitfld.word 0x00 1. " ETBEI_dlh1 ,Interrupt Enable Register: ETBEI. Enable Transmit Holding Register Empty Interrupt" "0,1"
bitfld.word 0x00 0. " ERBFI_dlh0 ,Interrupt Enable Register: ERBFI. Enable Received Data Available Interrupt" "0,1"
group.word 0x08++0x01
line.word 0x00 "UART2_IIR_FCR_REG,Interrupt Identification Register/FIFO Control Register"
bitfld.word 0x00 6.--7. " UART_FIFOSE_RT ,On read_FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disab.." "0,1,2,3"
bitfld.word 0x00 4.--5. " UART_TET ,On read_reserved_On Write_TX Empty Trigger (or TET): This is used to select the empty threshold leve.." "0,1,2,3"
bitfld.word 0x00 3. " UART_IID3_DMAM ,On Read (Bit3)_Interrupt ID (or IID): This indicates the highest priority pending interrupt which ca.." "0,1"
newline
bitfld.word 0x00 2. " UART_IID2_XFIFOR ,On Read (Bit2)_Interrupt ID (or IID): This indicates the highest priority pending interrupt which ca.." "0,1"
bitfld.word 0x00 1. " UART_IID1_RFIFOE ,On Read (Bit1)_Interrupt ID (or IID): This indicates the highest priority pending interrupt which ca.." "0,1"
bitfld.word 0x00 0. " UART_IID0_FIFOE ,On Read (Bit0)_Interrupt ID (or IID): This indicates the highest priority pending interrupt which ca.." "0,1"
group.word 0x0C++0x01
line.word 0x00 "UART2_LCR_REG,Line Control Register"
bitfld.word 0x00 7. " UART_DLAB ,Divisor Latch Access Bit" "0,1"
bitfld.word 0x00 6. " UART_BC ,Break Control Bit" "0,1"
bitfld.word 0x00 4. " UART_EPS ,Even Parity Select" "0,1"
newline
bitfld.word 0x00 3. " UART_PEN ,Parity Enable" "0,1"
bitfld.word 0x00 2. " UART_STOP ,Number of stop bits" "0,1"
bitfld.word 0x00 0.--1. " UART_DLS ,Data Length Select" "0,1,2,3"
group.word 0x14++0x01
line.word 0x00 "UART2_LSR_REG,Line Status Register"
rbitfld.word 0x00 7. " UART_RFE ,Receiver FIFO Error bit" "0,1"
rbitfld.word 0x00 6. " UART_TEMT ,Transmitter Empty bit" "0,1"
rbitfld.word 0x00 5. " UART_THRE ,Transmit Holding Register Empty bit" "0,1"
newline
rbitfld.word 0x00 4. " UART_BI ,Break Interrupt bit" "0,1"
rbitfld.word 0x00 3. " UART_FE ,Framing Error bit" "0,1"
rbitfld.word 0x00 2. " UART_PE ,Parity Error bit" "0,1"
newline
rbitfld.word 0x00 1. " UART_OE ,Overrun error bit" "0,1"
rbitfld.word 0x00 0. " UART_DR ,Data Ready bit" "0,1"
group.word 0x10++0x01
line.word 0x00 "UART2_MCR_REG,Modem Control Register"
bitfld.word 0x00 4. " UART_LB ,LoopBack Bit" "0,1"
group.word 0x00++0x01
line.word 0x00 "UART2_RBR_THR_DLL_REG,Receive Buffer Register/Transmit Holding Register/Divisor Latch Low"
hexmask.word.byte 0x00 0.--7. 1. " RBR_THR_DLL ,Receive Buffer Register: (RBR)"
group.word 0x84++0x01
line.word 0x00 "UART2_RFL_REG,Receive FIFO Level"
rbitfld.word 0x00 0.--4. " UART_RECEIVE_FIFO_LEVEL ,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0x90++0x01
line.word 0x00 "UART2_SBCR_REG,Shadow Break Control Register"
bitfld.word 0x00 0. " UART_SHADOW_BREAK_CONTROL ,Shadow Break Control Bit" "0,1"
group.word 0x1C++0x01
line.word 0x00 "UART2_SCR_REG,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. " UART_SCRATCH_PAD ,This register is for programmers to use as a temporary storage space"
group.word 0x94++0x01
line.word 0x00 "UART2_SDMAM_REG,Shadow DMA Mode"
bitfld.word 0x00 0. " UART_SHADOW_DMA_MODE ,Shadow DMA Mode" "0,1"
group.word 0x98++0x01
line.word 0x00 "UART2_SFE_REG,Shadow FIFO Enable"
bitfld.word 0x00 0. " UART_SHADOW_FIFO_ENABLE ,Shadow FIFO Enable" "0,1"
group.word 0x30++0x01
line.word 0x00 "UART2_SRBR_STHR0_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x58++0x01
line.word 0x00 "UART2_SRBR_STHR10_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x5C++0x01
line.word 0x00 "UART2_SRBR_STHR11_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x60++0x01
line.word 0x00 "UART2_SRBR_STHR12_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x64++0x01
line.word 0x00 "UART2_SRBR_STHR13_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x68++0x01
line.word 0x00 "UART2_SRBR_STHR14_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x6C++0x01
line.word 0x00 "UART2_SRBR_STHR15_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x34++0x01
line.word 0x00 "UART2_SRBR_STHR1_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x38++0x01
line.word 0x00 "UART2_SRBR_STHR2_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x3C++0x01
line.word 0x00 "UART2_SRBR_STHR3_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x40++0x01
line.word 0x00 "UART2_SRBR_STHR4_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x44++0x01
line.word 0x00 "UART2_SRBR_STHR5_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x48++0x01
line.word 0x00 "UART2_SRBR_STHR6_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x4C++0x01
line.word 0x00 "UART2_SRBR_STHR7_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x50++0x01
line.word 0x00 "UART2_SRBR_STHR8_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x54++0x01
line.word 0x00 "UART2_SRBR_STHR9_REG,Shadow Receive/Transmit Buffer Register"
hexmask.word.byte 0x00 0.--7. 1. " SRBR_STHRx ,Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixte.."
group.word 0x88++0x01
line.word 0x00 "UART2_SRR_REG,Software Reset Register"
bitfld.word 0x00 2. " UART_XFR ,XMIT FIFO Reset" "0,1"
bitfld.word 0x00 1. " UART_RFR ,RCVR FIFO Reset" "0,1"
bitfld.word 0x00 0. " UART_UR ,UART Reset" "0,1"
group.word 0x9C++0x01
line.word 0x00 "UART2_SRT_REG,Shadow RCVR Trigger"
bitfld.word 0x00 0.--1. " UART_SHADOW_RCVR_TRIGGER ,Shadow RCVR Trigger" "0,1,2,3"
group.word 0xA0++0x01
line.word 0x00 "UART2_STET_REG,Shadow TX Empty Trigger"
bitfld.word 0x00 0.--1. " UART_SHADOW_TX_EMPTY_TRIGGER ,Shadow TX Empty Trigger" "0,1,2,3"
group.word 0x80++0x01
line.word 0x00 "UART2_TFL_REG,Transmit FIFO Level"
rbitfld.word 0x00 0.--4. " UART_TRANSMIT_FIFO_LEVEL ,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.word 0xFA++0x01
line.word 0x00 "UART2_UCV_HIGH_REG,Component Version"
hexmask.word 0x00 0.--15. 1. " UCV ,Component Version"
group.word 0xF8++0x01
line.word 0x00 "UART2_UCV_REG,Component Version"
hexmask.word 0x00 0.--15. 1. " UCV ,Component Version"
group.word 0x7C++0x01
line.word 0x00 "UART2_USR_REG,UART Status Register"
rbitfld.word 0x00 4. " UART_RFF ,Receive FIFO Full" "0,1"
rbitfld.word 0x00 3. " UART_RFNE ,Receive FIFO Not Empty" "0,1"
rbitfld.word 0x00 2. " UART_TFE ,Transmit FIFO Empty" "0,1"
newline
rbitfld.word 0x00 1. " UART_TFNF ,Transmit FIFO Not Full" "0,1"
rbitfld.word 0x00 0. " UART_BUSY ,UART Busy" "0,1"
width 0x0B
tree.end
tree "WKUP"
base ad:0x50000100
width 23.
group.word 0x0E++0x01
line.word 0x00 "WKUP2_POL_GPIO_REG,Select the sensitivity polarity for each P1 input"
hexmask.word 0x00 0.--11. 1. " WKUP2_POL_GPIO ,0 = the enabled input P0x increments the event2 counter if that input goes high_1 = the enabled inpu.."
group.word 0x0A++0x01
line.word 0x00 "WKUP2_SELECT_GPIO_REG,Select which inputs from P1 port can trigger wkup counter"
hexmask.word 0x00 0.--11. 1. " WKUP2_SELECT_GPIO ,0 = input P0x is not enabled for wakeup event counter_1 = input P0x is enabled for wakeup event coun.."
group.word 0x02++0x01
line.word 0x00 "WKUP_COMPARE_REG,Number of events before wakeup interrupt"
hexmask.word.byte 0x00 0.--7. 1. " WKUP_COMPARE ,Defines the number of events -1 that have to be counted before the wakeup interrupt will be given"
group.word 0x06++0x01
line.word 0x00 "WKUP_COUNTER_REG,Actual number of events of the wakeup counter"
hexmask.word.byte 0x00 8.--15. 1. " EVENT2_VALUE ,This value represents the number of events that have been counted so far"
hexmask.word.byte 0x00 0.--7. 1. " EVENT_VALUE ,This value represents the number of events that have been counted so far"
group.word 0x00++0x01
line.word 0x00 "WKUP_CTRL_REG,Control register for the wakeup counter"
bitfld.word 0x00 8. " WKUP2_ENABLE_IRQ ,0 = no interrupt will be generated_1 = if the event counter2 reaches the value set by WKUP_COMPARE_R.." "0,1"
bitfld.word 0x00 7. " WKUP_ENABLE_IRQ ,0 = no interrupt will be generated_1 = if the event counter reaches the value set by WKUP_COMPARE_RE.." "0,1"
bitfld.word 0x00 6. " WKUP_SFT_KEYHIT ,0 = no effect_1 = emulate key hit" "0,1"
newline
bitfld.word 0x00 0.--5. " WKUP_DEB_VALUE ,Keyboard debounce time (N*1 ms with N = 1 to 63)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.word 0x04++0x01
line.word 0x00 "WKUP_IRQ_STATUS_REG,Reset wakeup interrupt"
bitfld.word 0x00 3. " WKUP2_CNTR_RST ,writing 1 will reset the event2 counter" "0,1"
bitfld.word 0x00 2. " WKUP_CNTR_RST ,writing 1 will reset the event counter" "0,1"
bitfld.word 0x00 1. " WKUP2_IRQ_STATUS ,Gives 1 when there is a wkup2 pending IRQ" "0,1"
newline
bitfld.word 0x00 0. " WKUP_IRQ_STATUS ,Gives 1 when there is a wkup pending IRQ" "0,1"
group.word 0x0C++0x01
line.word 0x00 "WKUP_POL_GPIO_REG,Select the sensitivity polarity for each P0 input"
hexmask.word 0x00 0.--11. 1. " WKUP_POL_GPIO ,0 = the enabled input P0x increments the event counter if that input goes high_1 = the enabled input.."
group.word 0x08++0x01
line.word 0x00 "WKUP_SELECT_GPIO_REG,Select which inputs from P0 port can trigger wkup counter"
hexmask.word 0x00 0.--11. 1. " WKUP_SELECT_GPIO ,0 = input P0x is not enabled for wakeup event counter_1 = input P0x is enabled for wakeup event coun.."
width 0x0B
tree.end
newline
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