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Gen4_R-Car_Trace32/2_Trunk/percortexa8.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: CORTEXA8 On-Chip Peripherals
; @Props: Released
; @Author: KOT, (GAC)
; @Changelog: 2005-08-09 KOT
; @Manufacturer: ARM - ARM Ltd.
; @Doc: DDI0344A3a_cortex-a8_r1p0_trm.pdf (Rev. r1p0 Draft Beta)
; @Core: Cortex-A8
; @Chip: CORTEX-A8
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: percortexa8.per 7176 2016-08-29 15:17:06Z amerkle $
;many registers taken directly from arm11.
config 16. 8.
width 0x0b
ASSERT VERSION.BUILD.BASE()>=80109.
sif PER.isNOTIFICATION()
base AVM:0x00000000
wgroup AVM:0x00++0
textline " Peripheral File Notification - "
button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files:""+CONV.CHAR(0xa)+PER.NOTIFICATION.MISSINGFILES()"
textline " ---------------------------------------------------------------"
textline " The peripheral file for this SoC cannot be displayed. "
textline " Possible reasons are: "
textline " - it is missing in the local installation or under development "
textline " - it is confidential "
textline " "
textline " As fallback only the core registers are shown. "
textline " Please check www.lauterbach.com/scripts.html "
textline " or contact support@lauterbach.com . "
textline " "
endif
width 0x8
; --------------------------------------------------------------------------------
; Identification registers
; --------------------------------------------------------------------------------
tree "ID Registers"
rgroup c15:0x0--0x0
line.long 0x0 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
textline " "
hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup c15:0x100--0x100
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
textline " "
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
rgroup c15:0x200--0x200
line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
bitfld.long 0x0 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,ARMv7,ARMv6,ARMv6,ARMv6"
bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup c15:0x300--0x300
line.long 0x0 "TLBTR,TLB Type Register"
hexmask.long.byte 0x0 16.--23. 0x1 " ITLBLOCK ,Specifies the number of instruction TLB lockable entries"
hexmask.long.byte 0x0 8.--15. 0x1 " DTLBLOCK ,Specifies the number of unified or data TLB lockable entries"
bitfld.long 0x0 0. " S ,Unified or Separate TLBs" "Unified,Separate"
rgroup c15:0x400--0x400
line.long 0x0 "MPUTR,MPU type register"
rgroup c15:0x500--0x500
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitniy Level 2"
hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitniy Level 1"
hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitniy Level 0"
textline " "
rgroup c15:0x0410++0x00
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup c15:0x0510++0x00
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup c15:0x0610++0x00
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup c15:0x0710++0x00
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup c15:0x0020++0x00
line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup c15:0x0120++0x00
line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup c15:0x0220++0x00
line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup c15:0x0320++0x00
line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup c15:0x0420++0x00
line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup c15:0x0520++0x00
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
rgroup c15:0x0620++0x00
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
rgroup c15:0x0720++0x00
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
rgroup c15:0x0010++0x00
line.long 0x00 "PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup c15:0x0110++0x00
line.long 0x00 "PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
textline " "
rgroup c15:0x0210++0x00
line.long 0x00 "DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
textline " "
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup c15:0x0310++0x00
line.long 0x00 "AFR0,Auxiliary Feature Register 0"
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
tree.end
width 0x8
tree "System Control and Configuration"
group c15:0x1--0x1
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline " "
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
textline " "
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
textline " "
group c15:0x101--0x101
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 31. " L2RD ,L2 hardware reset disable" "Enable,Disable"
bitfld.long 0x00 30. " L1RD ,L1 hardware reset disable" "Enable,Disable"
textline " "
bitfld.long 0x00 18. " CPISEL ,CP14/CP15 instruction serialization" "No,Yes"
bitfld.long 0x00 17. " CPWAI ,CP14/CP15 wait on idle" "No,Yes"
bitfld.long 0x00 16. " CPFL ,CP14/CP15 pipeline flush" "No,Yes"
textline " "
bitfld.long 0x00 15. " FETMCLK ,Force ETM clock" "No,Yes"
bitfld.long 0x00 14. " FNCLK ,Force NEON clock" "No,Yes"
bitfld.long 0x00 13. " FMCLK ,Force main clock" "No,Yes"
textline " "
bitfld.long 0x00 12. " FNSI ,Force NEON single issue" "No,Yes"
bitfld.long 0x00 11. " FLSSI ,Force load/store single issue" "No,Yes"
bitfld.long 0x00 10. " FSI ,Force single issue" "No,Yes"
textline " "
bitfld.long 0x00 9. " PLDNOP ,PLD executes as NOP" "Execute,NOP"
bitfld.long 0x00 8. " WFINOP ,WFI executes as NOP" "Execute,NOP"
textline " "
bitfld.long 0x00 7. " DBSM ,Disable branch size mispredicts" "Enable,Disable"
bitfld.long 0x00 6. " IBE ,Invalidate BTB Enable" "Disable,Enable"
textline " "
bitfld.long 0x00 5. " L1NEON ,NEON Data Caching Within the L1 Data Cache Enable" "Disable,Enable"
bitfld.long 0x00 4. " ASA ,Speculative Accesses on AXI Enable" "Disable,Enable"
textline " "
bitfld.long 0x00 3. " L1PE ,L1 Cache Parity Detection Enable" "Disable,Enable"
bitfld.long 0x00 1. " L2EN ,L2 Cache Enable" "Disable,Enable"
bitfld.long 0x00 0. " L1ALIAS ,L1 Data Cache Hardware Alias Checks Enable" "Enable,Disable"
group c15:0x201--0x201
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
group c15:0x11--0x11
line.long 0x0 "SCR,Secure Configuration Register"
bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
textline " "
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
group c15:0x111--0x111
line.long 0x0 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
group c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 18. " PLE ,PLE Registers Access in Nonsecure World" "Denied,Permitted"
bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
textline " "
bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted"
textline " "
bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
group c15:0x000c++0x00
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
group c15:0x10c--0x10c
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
hexmask.long.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
textline " "
rgroup c15:0x1C--0x1C
line.long 0x0 "ISR,Interrupt status Register"
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
tree.end
width 0x0d
tree "Memory Management Unit"
width 8.
group c15:0x1--0x1
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disable,Enable"
textline " "
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline " "
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
textline " "
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
textline " "
group c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
textline " "
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
group c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
textline " "
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
group c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
textline " "
group c15:0x3--0x3
line.long 0x0 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
textline " "
group c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/decode,Reserved,Imprecise/parity/ECC,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/slave,?..."
group c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/parity,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,?..."
group c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
group c15:0x0015++0x00
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
group c15:0x0115++0x00
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
textline " "
group c15:0x002A--0x002A
line.long 0x00 "PMRRR,Primary Memory Region Remap Register"
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
textline " "
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
textline " "
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
textline " "
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
textline " "
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
textline " "
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
group c15:0x012A--0x012A
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
group c15:0x000d++0x00
line.long 0x00 "FCSEPID,FCSE PID Register"
hexmask.long.byte 0x00 25.--31. 1. " FCSEPID ,Process for Fast Context Switch Identification and Specification"
group c15:0x10d--0x10d
line.long 0x0 "CONTEXT,Context ID Register"
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
group c15:0x020d++0x00
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
group c15:0x030d++0x00
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
group c15:0x040d++0x00
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
tree.end
width 0xC
tree "Cache Control and Configuration"
rgroup c15:0x1100--0x1100
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
textline " "
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
textline " "
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
textline " "
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
textline " "
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
rgroup c15:0x1000--0x1000
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
textline " "
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
textline " "
hexmask.long.word 0x00 13.--27. 1. 1. " SETS ,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. " ASSOC ,Associativity"
textline " "
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
group c15:0x2000--0x2000
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/unified,Instruction"
tree.end
width 0x8
tree "L2 Cache Control and Configuration"
group c15:0x1009++0x00
line.long 0x00 "L2CLR,L2 Cache Lockdown Register"
bitfld.long 0x00 7. " LOCK_way_7 ,Way 7 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 6. " LOCK_way_6 ,Way 6 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 5. " LOCK_way_5 ,Way 5 of the L2 Cache Lockdown" "Not locked,Locked"
textline " "
bitfld.long 0x00 4. " LOCK_way_4 ,Way 4 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 3. " LOCK_way_3 ,Way 3 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 2. " LOCK_way_2 ,Way 2 of the L2 Cache Lockdown" "Not locked,Locked"
textline " "
bitfld.long 0x00 1. " LOCK_way_1 ,Way 1 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 0. " LOCK_way_0 ,Way 0 of the L2 Cache Lockdown" "Not locked,Locked"
group c15:0x1209++0x00
line.long 0x00 "L2CACR,L2 Cache Auxiliary Control Register"
bitfld.long 0x00 28. " ECCP ,ECC/Parity Selection" "Parity,ECC"
bitfld.long 0x00 27. " PLDFD ,PLD Forwarding to LS Request Disable" "Enabled,Disabled"
bitfld.long 0x00 26. " PLDD ,PLD Disable" "Enabled,Disabled"
textline " "
bitfld.long 0x00 25. " WCD ,Write Combining Disable" "Enabled,Disabled"
bitfld.long 0x00 24. " WADD ,External Linefill When Storing an Entire Line With Write Allocate Permission Disable" "Enabled,Disabled"
bitfld.long 0x00 23. " WACD ,Combining of Data in the L2 Write Combining Buffers Disable" "Enabled,Disabled"
textline " "
bitfld.long 0x00 22. " WAD ,Allocate on Write Miss in L2 Disable" "Enabled,Disabled"
bitfld.long 0x00 21. " PECCE ,Parity/ECC Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " L2I ,L2 Inner" "Outer,Inner"
textline " "
bitfld.long 0x00 6.--8. " TRAML ,Program Tag RAM Latency" "2 cycles,2 cycles,3 cycles,4 cycles,4 cycles,4 cycles,4 cycles,4 cycles"
bitfld.long 0x00 0.--3. " DRAML ,Program Data RAM Latency" "3 cycles,3 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,13 cycles,13 cycles,13 cycles"
textline " "
rgroup c15:0x000b++0x00
line.long 0x00 "PLEISR0,PLE Identification and Status Register 0"
bitfld.long 0x00 1. " CH1P ,Channel 1 Present" "Not present,Present"
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
rgroup c15:0x010b++0x00
line.long 0x00 "PLEISR1,PLE Identification and Status Register 1"
bitfld.long 0x00 1. " CH1Q ,Channel 1 Queue" "Not queued,Queued"
bitfld.long 0x00 0. " CH0Q ,Channel 0 Queue" "Not queued,Queued"
rgroup c15:0x020b++0x00
line.long 0x00 "PLEISR2,PLE Identification and Status Register 2"
bitfld.long 0x00 1. " CH1R ,Channel 1 Run" "Not running,Running"
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
rgroup c15:0x030b++0x00
line.long 0x00 "PLEISR3,PLE Identification and Status Register 3"
bitfld.long 0x00 1. " CH1I ,Channel 1 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 0. " CH0I ,Channel 0 Interrupt" "No interrupt,Interrupt"
group c15:0x001b++0x00
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
bitfld.long 0x00 1. " U1 ,User Mode Process Access Registers for Channel 1 Permission" "Not permitted,Permitted"
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
group c15:0x002b++0x00
line.long 0x00 "PLECNR,PLE Channel Number Register"
bitfld.long 0x00 0. " CN ,PLE Channel Selection" "Channel 0,Channel 1"
wgroup c15:0x003b++0x00
line.long 0x00 "PLEER0,PLE Enable Register 0"
hexmask.long 0x00 0.--31. 1. " PLEE_STOP ,PLE Enable Stop"
wgroup c15:0x013b++0x00
line.long 0x00 "PLEER1,PLE Enable Register 1"
hexmask.long 0x00 0.--31. 1. " PLEE_START ,PLE Enable Start"
wgroup c15:0x023b++0x00
line.long 0x00 "PLEER2,PLE Enable Register 2"
hexmask.long 0x00 0.--31. 1. " PLEES_CLEAR ,PLE Enable Clear"
group c15:0x004b++0x00
line.long 0x00 "PLECR,PLE Control Register"
bitfld.long 0x00 30. " DT ,Transfer Direction" "Memory->cache,Cache->memory"
bitfld.long 0x00 29. " IC ,Interrupt on Completion of the PLE Transfer" "No interrupt,Interrupt"
bitfld.long 0x00 28. " IE ,Interrupt on an Error" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 26. " UM ,Permission Checks Type" "Privileged,User"
bitfld.long 0x00 0.--2. " Wy ,L2 Cache Way for Filling Data" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7"
textline " "
group c15:0x005b++0x00
line.long 0x00 "PLEISAR,PLE Internal Start Address Register"
hexmask.long 0x00 0.--31. 1. " PLEISA ,PLE Internal Start Address"
group c15:0x007b++0x00
line.long 0x00 "PLEIEAR,PLE Internal End Address Register"
hexmask.long.word 0x00 6.--17. 1. " Lines ,Number of Cache Lines Transferred"
rgroup c15:0x008b++0x00
line.long 0x00 "PLECSR,PLE Channel Status Register"
hexmask.long.byte 0x00 2.--8. 1. " EC ,External Address Error Status"
bitfld.long 0x00 0.--1. " Status ,PLE Channel Status" "Idle,Queued,Running,Complete/error"
group c15:0x00fb++0x00
line.long 0x00 "PLECIDR,PLE Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extension to Form the Process ID and Current Process Identification"
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process and the Current ASID Identification"
tree.end
width 12.
tree "System Performance Monitor"
group c15:0xC9--0xC9
line.long 0x0 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
textline " "
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
textline " "
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
group c15:0x1C9--0x1C9
line.long 0x0 "CNTENS,Count Enable Set Register"
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
group c15:0x2C9--0x2C9
line.long 0x0 "CNTENC,Count Enable Clear Register"
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
group c15:0x3C9--0x3C9
line.long 0x0 "FLAG,Overflow Flag Status Register"
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
group c15:0x4C9--0x4C9
line.long 0x0 "SWINCR,Software Increment Register"
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
group c15:0x5C9--0x5C9
line.long 0x0 "PMSELR,Performance Counter Selection Register"
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,..."
group c15:0xD9--0xD9
line.long 0x0 "PMCCNTR,Cycle Count Register"
group c15:0x01d9++0x00
line.long 0x00 "PMXEVTYPER,Event Selection Register"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group c15:0x02d9++0x00
line.long 0x00 "PMCNT,Performance Monitor Count Register"
group c15:0xE9--0xE9
line.long 0x0 "PMUSERENR,User Enable Register"
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
group c15:0x1E9--0x1E9
line.long 0x0 "INTENS,Interrupt Enable Set Register"
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
group c15:0x2E9--0x2E9
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
tree.end
width 8.
tree "Debug Registers"
width 10.
rgroup c14:0x000--0x000
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. " CONTEXT ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
textline " "
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
textline " "
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
textline " "
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
width 10.
group c14:0x22--0x22
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
textline " "
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
textline " "
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
textline " "
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
textline " "
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
textline " "
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
textline " "
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
textline " "
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
textline " "
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
textline " "
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
textline " "
width 10.
if (((data.long(c14:0x00))&0x01000)==0x00000)
group c14:0x007--0x007
line.long 0x0 "DBGVCR,Vector Catch Register"
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
textline " "
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
textline " "
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
textline " "
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
else
group c14:0x007--0x007
line.long 0x0 "DBGVCR,Vector Catch Register"
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
textline " "
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
endif
width 10.
hgroup c14:0x020--0x020
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
in
group c14:0x023--0x023
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
group c14:0x09++0x00
line.long 0x00 "DBGECR,Event Catch Register"
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
group c14:0x0a++0x00
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
wgroup c14:0x21++0x00
line.long 0x00 "DBGITR,Instruction Transfer Register"
wgroup c14:0x24++0x00
line.long 0x00 "DBGDRCR,Debug Run Control Register"
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
textline " "
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
wgroup c14:0xc0++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup c14:0xc1++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
group c14:0xc2++0x00
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
group c14:0xc4++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
hgroup c14:0xc5++0x00
hide.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
in
width 11.
tree "Processor Identifier Registers"
rgroup c14:0x340--0x340
line.long 0x00 "CPUID,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
textline " "
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
textline " "
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
rgroup c14:0x341--0x341
line.long 0x00 "CACHETYPE,Cache Type Register"
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
rgroup c14:0x343--0x343
line.long 0x00 "TLBTYPE,TLB Type Register"
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
textline " "
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
rgroup c14:0x348--0x348
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup c14:0x349--0x349
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup c14:0x34a--0x34a
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup c14:0x34b--0x34b
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
rgroup c14:0x34c--0x34c
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup c14:0x34d--0x34d
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup c14:0x34e--0x34e
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup c14:0x34f--0x34f
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup c14:0x350--0x350
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup c14:0x351--0x351
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
rgroup c14:0x352--0x352
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup c14:0x353--0x353
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup c14:0x354--0x354
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup c14:0x355--0x355
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
tree.end
width 0xC
tree "Coresight Management Registers"
width 17.
group c14:0x03bd++0x00
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
textline " "
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
textline " "
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
group c14:0x03be++0x00
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
textline " "
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
textline " "
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
textline " "
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
rgroup c14:0x03bf++0x00
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
textline " "
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
textline " "
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
textline " "
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
group c14:0x3c0--0x3c0
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
group c14:0x3e8--0x3e8
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
textline " "
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
textline " "
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
textline " "
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
group c14:0x3e9--0x3e9
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
textline " "
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
textline " "
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
textline " "
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
wgroup c14:0x3ec--0x3ec
line.long 0x0 "DBGLAR,Lock Access Register"
rgroup c14:0x3ed--0x3ed
line.long 0x0 "DBGLSR,Lock Status Register"
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
textline " "
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
width 17.
rgroup c14:0x3ee--0x3ee
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
width 17.
hgroup c14:0x3f2--0x3f2
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
rgroup c14:0x3f3--0x3f3
line.long 0x0 "DBGDEVTYPE,Device Type"
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup c14:0x3f8--0x3f8
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
rgroup c14:0x3f9--0x3f9
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
rgroup c14:0x3fa--0x3fa
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
rgroup c14:0x3fb--0x3fb
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
rgroup c14:0x3f4--0x3f4
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
rgroup c14:0x3fc--0x3fc
line.long 0x00 "DBGCID0,Debug Component ID 0"
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
rgroup c14:0x3fd--0x3fd
line.long 0x00 "DBGCID1,Debug Component ID 1"
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
rgroup c14:0x3fe--0x3fe
line.long 0x00 "DBGCID2,Debug Component ID 2"
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
rgroup c14:0x3ff--0x3ff
line.long 0x00 "DBGCID3,Debug Component ID 3"
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
tree.end
tree.end
width 7.
tree "Breakpoint Registers"
group c14:0x40++0x00
line.long 0x00 "BVR0,Breakpoint Value Register 0"
group c14:0x50++0x00
line.long 0x00 "BCR0,Breakpoint Control Register 0"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x41++0x00
line.long 0x00 "BVR1,Breakpoint Value Register 1"
group c14:0x51++0x00
line.long 0x00 "BCR1,Breakpoint Control Register 1"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x42++0x00
line.long 0x00 "BVR2,Breakpoint Value Register 2"
group c14:0x52++0x00
line.long 0x00 "BCR2,Breakpoint Control Register 2"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x43++0x00
line.long 0x00 "BVR3,Breakpoint Value Register 3"
group c14:0x53++0x00
line.long 0x00 "BCR3,Breakpoint Control Register 3"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x44++0x00
line.long 0x00 "BVR4,Breakpoint Value Register 4"
group c14:0x54++0x00
line.long 0x00 "BCR4,Breakpoint Control Register 4"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x45++0x00
line.long 0x00 "BVR5,Breakpoint Value Register 5"
group c14:0x55++0x00
line.long 0x00 "BCR5,Breakpoint Control Register 5"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
tree.end
width 6.
tree "Watchpoint Control Registers"
group c14:0x60++0x00
line.long 0x00 "WVR0,Watchpoint Value Register 0"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group c14:0x70--0x70
line.long 0x0 "WCR0,Watchpoint Control Register 0"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group c14:0x61++0x00
line.long 0x00 "WVR1,Watchpoint Value Register 1"
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
group c14:0x71--0x71
line.long 0x0 "WCR1,Watchpoint Control Register 1"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group c14:0x006--0x006
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
tree.end
textline ""
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