52112 lines
4.0 MiB
52112 lines
4.0 MiB
; --------------------------------------------------------------------------------
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; @Title: CC26XXR On-Chip Peripherals
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; @Props: Released
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; @Author: ADR, PIW, KRZ
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; @Changelog: 2022-01-19 ADR
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; 2022-04-29 PIW
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; 2022-11-26 KRZ
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; @Manufacturer: TI - Texas Instruments
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; @Doc: XML generated (TIXML2PER 2.1.6), based on:
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; cc2620f128.xml, cc2630f128.xml, cc2640f128.xml, cc2640r2f.xml,
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; cc2640r2l.xml, cc2642r1f.xml, cc2650f128.xml, cc2651p3.xml, cc2651r3.xml,
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; cc2652p1f.xml, cc2652p7.xml, cc2652r1f.xml, cc2652r7.xml, cc2652rb1f.xml,
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; cc2653p10.xml, cc2662r1f.xml, cc2672p3.xml, cc2672r3.xml, cc2674p10.xml,
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; cc2674r10.xml
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; @Core: Cortex-M3, Cortex-M4F, Cortex-M33
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; @Chip: CC2620F128, CC2630F128, CC2640F128, CC2640R, CC2642R, CC2650F128,
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; CC2651P3, CC2651R3, CC2652P, CC2652R, CC2652R7, CC2652RB, CC2653P10,
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; CC2662R, CC2672P3, CC2672R3, CC2674P10, CC2674R10
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: percc26xxr.per 15479 2022-11-26 16:50:58Z kwisniewski $
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sif (CORENAME()=="CORTEXM3")
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
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bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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textline " "
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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tree "CoreSight Identification Registers"
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width 6.
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
elif (CORENAME()=="CORTEXM4F")
|
|
tree.close "Core Registers (Cortex-M4F)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
|
|
bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
|
|
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x23
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
|
|
bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
|
|
rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
|
|
bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
|
|
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
|
|
bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
|
|
bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
|
|
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
|
|
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x00 "MMFSR,MemManage Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
|
|
line.byte 0x01 "BFSR,Bus Fault Status Register"
|
|
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x00 "USAFAULT,Usage Fault Status Register"
|
|
bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
|
|
bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
|
|
bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
|
|
bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
|
|
bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
|
|
group.long 0xD2C++0x07
|
|
line.long 0x00 "HFSR,Hard Fault Status Register"
|
|
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
|
|
line.long 0x04 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
|
|
bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
|
|
bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
|
|
group.long 0xD34++0x0B
|
|
line.long 0x00 "MMFAR,MemManage Fault Address Register"
|
|
line.long 0x04 "BFAR,BusFault Address Register"
|
|
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
|
|
width 10.
|
|
tree "Feature Registers"
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
elif (CORENAME()=="CORTEXM33")
|
|
tree.close "Core Registers (Cortex-M33)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
|
|
bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
|
|
bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
|
|
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
|
|
bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
|
|
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
|
|
group.long 0xD04++0x23
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
|
|
rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
|
|
textline " "
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
|
|
rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
|
|
rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
|
|
bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
|
|
line.long 0x14 "SHPR1,System Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
|
|
bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
|
|
bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
|
|
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
|
|
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
|
|
bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
|
|
bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
|
|
bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
|
|
bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
|
|
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
|
|
bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
|
|
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x00 "MMFSR,MemManage Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
|
|
line.byte 0x01 "BFSR,Bus Fault Status Register"
|
|
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x00 "UFSR,Usage Fault Status Register"
|
|
eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
|
|
eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
|
|
eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
|
|
eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
|
|
eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
|
|
group.long 0xD2C++0x03
|
|
line.long 0x00 "HFSR,HardFault Status Register"
|
|
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
|
|
group.long 0xD34++0x0B
|
|
line.long 0x00 "MMFAR,MemManage Fault Address Register"
|
|
line.long 0x04 "BFAR,BusFault Address Register"
|
|
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
|
|
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
|
|
group.long 0xD8C++0x03
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD8C++0x03
|
|
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
|
|
endif
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Triggered Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
|
|
tree "Memory System"
|
|
width 10.
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
|
|
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
|
|
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
|
|
endif
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
|
|
group.long 0xD84++0x03
|
|
line.long 0x00 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
|
|
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
|
|
wgroup.long 0xF50++0x03
|
|
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
|
|
wgroup.long 0xF58++0x23
|
|
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
|
|
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
|
|
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
|
|
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
|
|
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
|
|
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
|
|
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
|
|
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
|
|
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
|
|
rgroup.long 0xD4C++0x03
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
|
|
rgroup.long 0xD54++0x03
|
|
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD5C++0x03
|
|
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
rgroup.long 0xD64++0x03
|
|
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
|
|
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
|
|
rgroup.long 0xD6C++0x03
|
|
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
|
|
rgroup.long 0xD70++0x03
|
|
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
|
|
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
|
|
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 11.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DPIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DPIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DPIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DPIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DCIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DCIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DCIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
tree.end
|
|
group.long 0xDE4++0x03
|
|
line.long 0x00 "SFSR,Secure Fault Status Register"
|
|
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
|
|
group.long 0xDE8++0x03
|
|
line.long 0x00 "SFAR,Secure Fault Address Register"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
|
|
width 24.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x124++0x03
|
|
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x134++0x03
|
|
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x138++0x03
|
|
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x13C++0x03
|
|
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
width 11.
|
|
tree "Interrupt Active Bit Registers"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
rgroup.long 0x328++0x03
|
|
line.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
rgroup.long 0x32C++0x03
|
|
line.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
rgroup.long 0x338++0x03
|
|
line.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
rgroup.long 0x33C++0x03
|
|
line.long 0x00 "ACTIVE15,Active Bit Register 15"
|
|
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
|
|
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x1F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
line.long 0x10 "IPR60,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
|
|
line.long 0x14 "IPR61,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
|
|
line.long 0x18 "IPR62,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
|
|
line.long 0x1C "IPR63,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x1F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR60,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR61,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR62,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR63,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x500++0x1F
|
|
line.long 0x0 "IPR64,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
|
|
line.long 0x4 "IPR65,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
|
|
line.long 0x8 "IPR66,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
|
|
line.long 0xC "IPR67,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
|
|
line.long 0x10 "IPR68,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
|
|
line.long 0x14 "IPR69,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
|
|
line.long 0x18 "IPR70,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
|
|
line.long 0x1C "IPR71,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
|
|
else
|
|
hgroup.long 0x500++0x1F
|
|
hide.long 0x0 "IPR64,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR65,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR66,Interrupt Priority Register"
|
|
hide.long 0xC "IPR67,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR68,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR69,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR70,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR71,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x520++0x1F
|
|
line.long 0x0 "IPR72,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
|
|
line.long 0x4 "IPR73,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
|
|
line.long 0x8 "IPR74,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
|
|
line.long 0xC "IPR75,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
|
|
line.long 0x10 "IPR76,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
|
|
line.long 0x14 "IPR77,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
|
|
line.long 0x18 "IPR78,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
|
|
line.long 0x1C "IPR79,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
|
|
else
|
|
hgroup.long 0x520++0x1F
|
|
hide.long 0x0 "IPR72,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR73,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR74,Interrupt Priority Register"
|
|
hide.long 0xC "IPR75,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR76,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR77,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR78,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR79,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x540++0x1F
|
|
line.long 0x0 "IPR80,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
|
|
line.long 0x4 "IPR81,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
|
|
line.long 0x8 "IPR82,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
|
|
line.long 0xC "IPR83,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
|
|
line.long 0x10 "IPR84,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
|
|
line.long 0x14 "IPR85,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
|
|
line.long 0x18 "IPR86,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
|
|
line.long 0x1C "IPR87,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
|
|
else
|
|
hgroup.long 0x540++0x1F
|
|
hide.long 0x0 "IPR80,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR81,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR82,Interrupt Priority Register"
|
|
hide.long 0xC "IPR83,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR84,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR85,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR86,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR87,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x560++0x1F
|
|
line.long 0x0 "IPR88,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
|
|
line.long 0x4 "IPR89,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
|
|
line.long 0x8 "IPR90,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
|
|
line.long 0xC "IPR91,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
|
|
line.long 0x10 "IPR92,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
|
|
line.long 0x14 "IPR93,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
|
|
line.long 0x18 "IPR94,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
|
|
line.long 0x1C "IPR95,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
|
|
else
|
|
hgroup.long 0x560++0x1F
|
|
hide.long 0x0 "IPR88,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR89,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR90,Interrupt Priority Register"
|
|
hide.long 0xC "IPR91,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR92,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR93,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR94,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR95,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x580++0x1F
|
|
line.long 0x0 "IPR96,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
|
|
line.long 0x4 "IPR97,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
|
|
line.long 0x8 "IPR98,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
|
|
line.long 0xC "IPR99,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
|
|
line.long 0x10 "IPR100,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
|
|
line.long 0x14 "IPR101,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
|
|
line.long 0x18 "IPR102,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
|
|
line.long 0x1C "IPR103,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
|
|
else
|
|
hgroup.long 0x580++0x1F
|
|
hide.long 0x0 "IPR96,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR97,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR98,Interrupt Priority Register"
|
|
hide.long 0xC "IPR99,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR100,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR101,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR102,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR103,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x5A0++0x1F
|
|
line.long 0x0 "IPR104,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
|
|
line.long 0x4 "IPR105,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
|
|
line.long 0x8 "IPR106,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
|
|
line.long 0xC "IPR107,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
|
|
line.long 0x10 "IPR108,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
|
|
line.long 0x14 "IPR109,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
|
|
line.long 0x18 "IPR110,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
|
|
line.long 0x1C "IPR111,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
|
|
else
|
|
hgroup.long 0x5A0++0x1F
|
|
hide.long 0x0 "IPR104,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR105,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR106,Interrupt Priority Register"
|
|
hide.long 0xC "IPR107,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR108,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR109,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR110,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR111,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x5C0++0x1F
|
|
line.long 0x0 "IPR112,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
|
|
line.long 0x4 "IPR113,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
|
|
line.long 0x8 "IPR114,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
|
|
line.long 0xC "IPR115,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
|
|
line.long 0x10 "IPR116,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
|
|
line.long 0x14 "IPR117,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
|
|
line.long 0x18 "IPR118,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
|
|
line.long 0x1C "IPR119,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
|
|
else
|
|
hgroup.long 0x5C0++0x1F
|
|
hide.long 0x0 "IPR112,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR113,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR114,Interrupt Priority Register"
|
|
hide.long 0xC "IPR115,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR116,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR117,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR118,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR119,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif (CORENAME()=="CORTEXM33F")
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
|
|
newline
|
|
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
|
|
newline
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 13.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
|
|
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
AUTOINDENT.ON center tree
|
|
sif (cpuis("CC2620F128")||cpuis("CC2630F128")||cpuis("CC2640F128")||cpuis("CC2640R")||cpuis("CC2650F128"))
|
|
tree "AON"
|
|
tree "AON_BATMON"
|
|
base ad:0x40095000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTL,Internal"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Internal"
|
|
bitfld.long 0x00 1. "CALC_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MEAS_EN,Internal" "0,1"
|
|
line.long 0x04 "MEASCFG,Internal"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Internal"
|
|
bitfld.long 0x04 0.--1. "PER,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
group.long 0x0C++0x2B
|
|
line.long 0x00 "TEMPP0,Internal"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Internal"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CFG,Internal"
|
|
line.long 0x04 "TEMPP1,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x04 0.--5. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "TEMPP2,Internal"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED5,Internal"
|
|
bitfld.long 0x08 0.--4. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "BATMONP0,Internal"
|
|
hexmask.long 0x0C 7.--31. 1. "RESERVED6,Internal"
|
|
hexmask.long.byte 0x0C 0.--6. 1. "CFG,Internal"
|
|
line.long 0x10 "BATMONP1,Internal"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x10 0.--5. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "IOSTRP0,Internal"
|
|
hexmask.long 0x14 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x14 4.--5. "CFG2,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--3. "CFG1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "FLASHPUMPP0,Internal"
|
|
hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x18 9. "DIS_NOISE_FILTER,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "FALLB,Internal" "0,1"
|
|
bitfld.long 0x18 6.--7. "HIGHLIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 5. "LOWLIM,Internal" "0,1"
|
|
bitfld.long 0x18 4. "OVR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "BAT,Last Measured Battery VoltageThis register may be read while BATUPD.STAT = 1"
|
|
hexmask.long.tbyte 0x1C 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x1C 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x20 "BATUPD,Battery UpdateIndicates BAT Updates"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT," "No update since last clear,New battery voltage is present.Write 1 to clear.."
|
|
line.long 0x24 "TEMP,TemperatureLast Measured Temperature in Degrees CelsiusThis register may be read while TEMPUPD.STAT = 1."
|
|
hexmask.long.word 0x24 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x24 8.--16. "INT,Integer part (signed) of temperature value" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x28 "TEMPUPD,Temperature UpdateIndicates TEMP Updates"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "STAT," "No update since last clear,New temperature is present.Write 1 to clear the.."
|
|
group.long 0x48++0x17
|
|
line.long 0x00 "EVENTMASK,Event Mask"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 5. "TEMP_UPDATE_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "BATT_UPDATE_MASK," "0,1"
|
|
bitfld.long 0x00 3. "TEMP_BELOW_LL_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TEMP_OVER_UL_MASK," "0,1"
|
|
bitfld.long 0x00 1. "BATT_BELOW_LL_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BATT_OVER_UL_MASK," "0,1"
|
|
line.long 0x04 "EVENT,Event"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5. "TEMP_UPDATE,Alias to TEMPUPD.STAT" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "BATT_UPDATE,Alias to BATUPD.STAT" "0,1"
|
|
bitfld.long 0x04 3. "TEMP_BELOW_LL,Read:1: Temperature level is below the lower limit set by TEMPLL.0: Temperature level is not below the lower limit set by TEMPLL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
newline
|
|
bitfld.long 0x04 2. "TEMP_OVER_UL,Read:1: Temperature level is above the upper limit set by TEMPUL.0: Temperature level is not above the upper limit set by TEMPUL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
bitfld.long 0x04 1. "BATT_BELOW_LL,Read:1: Battery level is below the lower limit set by BATTLL.0: Battery level is not below the lower limit set by BATTLL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
newline
|
|
bitfld.long 0x04 0. "BATT_OVER_UL,Read:1: Battery level is above the upper limit set by BATTUL.0: Battery level is not above the upper limit set by BATTUL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
line.long 0x08 "BATTUL,Battery Upper Limit"
|
|
hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x08 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x0C "BATTLL,Battery Lower Limit"
|
|
hexmask.long.tbyte 0x0C 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x0C 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x10 "TEMPUL,Temperature Upper Limit"
|
|
hexmask.long.word 0x10 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x10 8.--16. "INT,Integer part (signed) of temperature upper limit" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "FRAC,Fractional part of temperature upper limit.Total value = INTEGER + FRACTIONALThe encoding is an extension of the 2's complement encoding.00" "0.0C,0.25C,?..."
|
|
rbitfld.long 0x10 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "TEMPLL,Temperature Lower Limit"
|
|
hexmask.long.word 0x14 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x14 8.--16. "INT,Integer part (signed) of temperature lower limit" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
bitfld.long 0x14 6.--7. "FRAC,Fractional part of temperature lower limit.Total value = INTEGER + FRACTIONALThe encoding is an extension of the 2's complement encoding.00" "0.0C,0.25C,?..."
|
|
rbitfld.long 0x14 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "AON_EVENT"
|
|
base ad:0x40093000
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MCUWUSEL,Wake-up Selector For MCUThis register contains pointers to 4 of 8 events (events 0 to 3) which are routed to AON_PMCTRL as wakeup sources for MCU"
|
|
rbitfld.long 0x00 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "WU3_EV,MCU Wakeup Source #3AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "WU2_EV,MCU Wakeup Source #2AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "WU1_EV,MCU Wakeup Source #1AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "WU0_EV,MCU Wakeup Source #0AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
line.long 0x04 "MCUWUSEL1,Wake-up Selector For MCUThis register contains pointers to 4 of 8 events (events 4 to 7) which are routed to AON_PMCTRL as wakeup sources for MCU"
|
|
rbitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 24.--29. "WU7_EV,MCU Wakeup Source #7AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 16.--21. "WU6_EV,MCU Wakeup Source #6AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 8.--13. "WU5_EV,MCU Wakeup Source #5AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x04 0.--5. "WU4_EV,MCU Wakeup Source #4AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
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line.long 0x08 "EVTOMCUSEL,Event Selector For MCU Event Fabric This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT"
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|
hexmask.long.word 0x08 22.--31. 1. "RESERVED22,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 16.--21. "AON_PROG2_EV,Event selector for AON_PROG2 event.AON Event Source id# selecting event routed to EVENT as AON_PROG2 event." "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
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newline
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rbitfld.long 0x08 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
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bitfld.long 0x08 8.--13. "AON_PROG1_EV,Event selector for AON_PROG1 event.AON Event Source id# selecting event routed to EVENT as AON_PROG1 event." "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
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newline
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rbitfld.long 0x08 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x08 0.--5. "AON_PROG0_EV,Event selector for AON_PROG0 event.AON Event Source id# selecting event routed to EVENT as AON_PROG0 event." "Edge detect IO event from the DIO(s) which have..,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,0,?,?,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
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line.long 0x0C "RTCSEL,RTC Capture Event Selector For AON_RTCThis register contains a pointer to select an AON event for RTC capture"
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hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 0.--5. "RTC_CH1_CAPT_EV,AON Event Source id# for RTCSEL event which is fed to AON_RTC" "Edge detect IO event from the DIO(s) which have..,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,0,?,?,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
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tree.end
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tree "AON_IOC"
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base ad:0x40094000
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group.long 0x00++0x0B
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line.long 0x00 "IOSTRMIN,Internal"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
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|
bitfld.long 0x00 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
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line.long 0x04 "IOSTRMED,Internal"
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hexmask.long 0x04 3.--31. 1. "RESERVED3,Internal"
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bitfld.long 0x04 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
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line.long 0x08 "IOSTRMAX,Internal"
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hexmask.long 0x08 3.--31. 1. "RESERVED3,Internal"
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bitfld.long 0x08 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
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|
group.long 0x10++0x07
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line.long 0x00 "CLK32KCTL,SCLK_LF External Output Control"
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|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x00 0. "OE_N," "0,1"
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|
line.long 0x04 "TCKCTL,TCK IO Pin Control"
|
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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|
bitfld.long 0x04 0. "EN," "0,1"
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tree.end
|
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tree "AON_RTC"
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base ad:0x40092000
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group.long 0x00++0x37
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line.long 0x00 "CTL,ControlThis register contains various bitfields for configuration of RTCRTL Name = CONFIG"
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hexmask.long.word 0x00 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
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bitfld.long 0x00 16.--18. "COMB_EV_MASK,Eventmask selecting which delayed events that form the combined event." "No event is selected for combined event.,Use Channel 0 delayed event in combined event,Use Channel 1 delayed event in combined event,?,Use Channel 2 delayed event in combined event,?,?,?"
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newline
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rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EV_DELAY,Number of SCLK_LF clock cycles waited before generating delayed events" "No delay on delayed event,Delay by 1 clock cycles,Delay by 2 clock cycles,Delay by 4 clock cycles,Delay by 8 clock cycles,Delay by 16 clock cycles,Delay by 32 clock cycles,Delay by 48 clock cycles,Delay by 64 clock cycles,Delay by 80 clock cycles,Delay by 96 clock cycles,Delay by 112 clock cycles,Delay by 128 clock cycles,Delay by 144 clock cycles,?,?"
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newline
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bitfld.long 0x00 7. "RESET,RTC Counter reset.Writing 1 to this bit will reset the RTC counter.This bit is cleared when reset takes effect" "0,1"
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rbitfld.long 0x00 3.--6. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 2. "RTC_4KHZ_EN,RTC_4KHZ is a 4 KHz reference output tapped from SUBSEC.VALUE bit 19 which is used by AUX timer" "RTC_4KHZ signal is forced to 0,RTC_4KHZ is enabled ( provied that RTC is.."
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bitfld.long 0x00 1. "RTC_UPD_EN,RTC_UPD is a 16 KHz signal used to sync up the radio timer" "RTC_UPD signal is forced to 0,RTC_UPD signal is toggling @16 kHz"
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newline
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bitfld.long 0x00 0. "EN,Enable RTC counter0: Halted (frozen)1: Running" "Halted (frozen),Running"
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line.long 0x04 "EVFLAGS,Event Flags. RTC StatusThis register contains event flags from the 3 RTC channels"
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hexmask.long.word 0x04 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
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|
bitfld.long 0x04 16. "CH2,Channel 2 event flag set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value.An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any.." "0,1"
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|
newline
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hexmask.long.byte 0x04 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
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|
bitfld.long 0x04 8. "CH1,Channel 1 event flag set when CHCTL.CH1_EN = 1 and one of the following:- CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value.- CHCTL.CH1_CAPT_EN = 1 and capture occurs.An event will be scheduled to occur as soon as possible.." "0,1"
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|
newline
|
|
hexmask.long.byte 0x04 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "CH0,Channel 0 event flag set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value.An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any.." "0,1"
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|
line.long 0x08 "SEC,Second Counter Value. Integer Part"
|
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line.long 0x0C "SUBSEC,Second Counter Value. Fractional Part"
|
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line.long 0x10 "SUBSECINC,Subseconds IncrementValue added to SUBSEC.VALUE on every SCLK_LFclock cycle"
|
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hexmask.long.byte 0x10 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.tbyte 0x10 0.--23. 1. "VALUEINC,This value compensates for a SCLK_LF clock which has an offset from 32768 Hz.The compensation value can be found as 2^38 / freq where freq is SCLK_LF clock frequency in HertzThis value is added to SUBSEC.VALUE on every cycle and carry of this.."
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|
line.long 0x14 "CHCTL,Channel Configuration"
|
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hexmask.long.word 0x14 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 18. "CH2_CONT_EN,Set to enable continuous operation of Channel 2" "0,1"
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newline
|
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rbitfld.long 0x14 17. "RESERVED17,Software should not rely on the value of a reserved" "0,1"
|
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bitfld.long 0x14 16. "CH2_EN,RTC Channel 2 Enable0: Disable RTC Channel 21: Enable RTC Channel 2" "Disable RTC Channel 2,Enable RTC Channel 2"
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|
newline
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rbitfld.long 0x14 10.--15. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 9. "CH1_CAPT_EN,Set Channel 1 mode0: Compare mode (default)1: Capture mode" "Compare mode (default),Capture mode"
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newline
|
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bitfld.long 0x14 8. "CH1_EN,RTC Channel 1 Enable0: Disable RTC Channel 11: Enable RTC Channel 1" "Disable RTC Channel 1,Enable RTC Channel 1"
|
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hexmask.long.byte 0x14 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x14 0. "CH0_EN,RTC Channel 0 Enable0: Disable RTC Channel 01: Enable RTC Channel 0" "Disable RTC Channel 0,Enable RTC Channel 0"
|
|
line.long 0x18 "CH0CMP,Channel 0 Compare Value"
|
|
line.long 0x1C "CH1CMP,Channel 1 Compare Value"
|
|
line.long 0x20 "CH2CMP,Channel 2 Compare Value"
|
|
line.long 0x24 "CH2CMPINC,Channel 2 Compare Value Auto-incrementThis register is primarily used to generate periodical wake-up for the AUX_SCE module. through the [AUX_EVCTL.EVSTAT0.AON_RTC] event."
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|
line.long 0x28 "CH1CAPT,Channel 1 Capture ValueIf CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1. capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL."
|
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hexmask.long.word 0x28 16.--31. 1. "SEC,Value of SEC.VALUE bits 15:0 at capture time"
|
|
hexmask.long.word 0x28 0.--15. 1. "SUBSEC,Value of SUBSEC.VALUE bits 31:16 at capture time"
|
|
line.long 0x2C "SYNC,AON SynchronizationThis register is used for synchronizing between MCU and entire AON domain"
|
|
hexmask.long 0x2C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x2C 0. "WBUSY,This register will always return 0 - however it will not return the value until there are no outstanding write requests between MCU and AONNote: Writing to this register prior to reading will force a wait until next SCLK_MF edge" "0,1"
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|
line.long 0x30 "TIME,Current Counter Value"
|
|
hexmask.long.word 0x30 16.--31. 1. "SEC_L,Returns the lower halfword of SEC register"
|
|
hexmask.long.word 0x30 0.--15. 1. "SUBSEC_H,Returns the upper halfword of SUBSEC register"
|
|
line.long 0x34 "SYNCLF,Synchronization to SCLK_LFThis register is used for synchronizing MCU to positive or negative edge of SCLK_LF"
|
|
hexmask.long 0x34 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x34 0. "PHASE,This bit will always return the SCLK_LF phase" "Falling edge of SCLK_LF,Rising edge of SCLK_LF"
|
|
tree.end
|
|
tree "AON_SYSCTL"
|
|
base ad:0x40090000
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "PWRCTL,Power ManagementThis register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled."
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 2. "DCDC_ACTIVE,Select to use DCDC regulator for VDDR in active mode" "Use GLDO for regulation of VDDRin active mode,Use DCDC for regulation of VDDRin active mode"
|
|
newline
|
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bitfld.long 0x00 1. "EXT_REG_MODE,Status of source for VDDRsupply:0: DCDC/GLDO are generating VDDR1: DCDC/GLDO are bypassed external regulator supplies VDDR" "DCDC/GLDO are generating VDDR,DCDC/GLDO are bypassed external regulator.."
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bitfld.long 0x00 0. "DCDC_EN,Select to use DCDC regulator during recharge of VDDR0: Use GLDO for recharge of VDDR1: Use DCDC for recharge of VDDRNote: This bitfield should be set to the same as DCDC_ACTIVE" "Use GLDO for recharge of VDDR,Use DCDC for recharge of VDDR"
|
|
line.long 0x04 "RESETCTL,Reset ManagementThis register contains bitfields releated to system reset such as reset source and reset request and control of brown out resets"
|
|
bitfld.long 0x04 31. "SYSRESET,Cold reset register" "No effect,Generate system reset"
|
|
rbitfld.long 0x04 26.--30. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x04 25. "BOOT_DET_1_CLR,Internal" "0,1"
|
|
bitfld.long 0x04 24. "BOOT_DET_0_CLR,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 18.--23. "RESERVED18,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 17. "BOOT_DET_1_SET,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "BOOT_DET_0_SET,Internal" "0,1"
|
|
bitfld.long 0x04 15. "WU_FROM_SD,A Wakeup from SHUTDOWN on an IO event has occurred or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached" "Wakeup occurred from cold reset or brown out as..,A wakeup has occurred from SHUTDOWN"
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|
newline
|
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bitfld.long 0x04 14. "GPIO_WU_FROM_SD,A wakeup from SHUTDOWN on an IO event has occurred Please refer to [IOC:IOCFGn .WU_CFG] for configuring the IO's as wakeup sources.0: The wakeup did not occur from SHUTDOWN on an IO event1: A wakeup from SHUTDOWN occurred from an IO.." "The wakeup did not occur from SHUTDOWN on an IO..,A wakeup from SHUTDOWN occurred from an IO.."
|
|
rbitfld.long 0x04 13. "BOOT_DET_1,Internal" "0,1"
|
|
newline
|
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rbitfld.long 0x04 12. "BOOT_DET_0,Internal" "0,1"
|
|
bitfld.long 0x04 11. "VDDS_LOSS_EN_OVR,Override of VDDS_LOSS_EN0: Brown out detect of VDDS is ignored unless VDDS_LOSS_EN=11: Brown out detect of VDDS generates system reset (regardless of VDDS_LOSS_EN)This bit can be locked" "Brown out detect of VDDS is ignored unless..,Brown out detect of VDDS generates system reset.."
|
|
newline
|
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bitfld.long 0x04 10. "VDDR_LOSS_EN_OVR,Override of VDDR_LOSS_EN0: Brown out detect of VDDR is ignored unless VDDR_LOSS_EN=11: Brown out detect of VDDR generates system reset (regardless of VDDR_LOSS_EN)This bit can be locked" "Brown out detect of VDDR is ignored unless..,Brown out detect of VDDR generates system reset.."
|
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bitfld.long 0x04 9. "VDD_LOSS_EN_OVR,Override of VDD_LOSS_EN0: Brown out detect of VDD is ignored unless VDD_LOSS_EN=11: Brown out detect of VDD generates system reset (regardless of VDD_LOSS_EN)This bit can be locked" "Brown out detect of VDD is ignored unless..,Brown out detect of VDD generates system reset.."
|
|
newline
|
|
rbitfld.long 0x04 8. "RESERVED8,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x04 7. "VDDS_LOSS_EN,Controls reset generation in case VDDS is lost0: Brown out detect of VDDS is ignored unless VDDS_LOSS_EN_OVR=11: Brown out detect of VDDS generates system reset " "Brown out detect of VDDS is ignored unless..,Brown out detect of VDDS generates system reset"
|
|
newline
|
|
bitfld.long 0x04 6. "VDDR_LOSS_EN,Controls reset generation in case VDDR is lost" "Brown out detect of VDDR is ignored unless..,Brown out detect of VDDR generates system reset"
|
|
bitfld.long 0x04 5. "VDD_LOSS_EN,Controls reset generation in case VDD is lost0: Brown out detect of VDD is ignored unless VDD_LOSS_EN_OVR=11: Brown out detect of VDD generates system reset" "Brown out detect of VDD is ignored unless..,Brown out detect of VDD generates system reset"
|
|
newline
|
|
bitfld.long 0x04 4. "CLK_LOSS_EN,Controls reset generation in case SCLK_LF is lost" "Clock loss is ignored,Clock loss generates system reset"
|
|
rbitfld.long 0x04 1.--3. "RESET_SRC,Shows the source of the last system reset:Occurrence of one of the reset sources may trigger several other reset sources as essential parts of the system are undergoing reset" "Power on reset,Reset pin,Brown out detect on VDDS,Brown out detect on VDD,Brown out detect on VDDR,Clock loss detect,Software reset via SYSRESET register,Software reset via PRCM warm reset request"
|
|
newline
|
|
rbitfld.long 0x04 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x08 "SLEEPCTL,Sleep ModeThis register is used to unfreeze the IO pad ring after waking up from SHUTDOWN"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "IO_PAD_SLEEP_DIS,Controls the I/O pad sleep mode" "I/O pad sleep mode is enabled ie all pads are..,I/O pad sleep mode is disabledApplication.."
|
|
tree.end
|
|
tree "AON_WUC"
|
|
base ad:0x40091000
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "MCUCLK,MCU Clock ManagementThis register contains bitfields related to the MCU clock"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "RCOSC_HF_CAL_DONE,MCU bootcode will set this bit when RCOSC_HF is calibrated" "RCOSC_HF is not yet calibrated ie FLASH must not..,RCOSC_HF is calibrated to 48 MHz allowing FLASH.."
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|
newline
|
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bitfld.long 0x00 0.--1. "PWR_DWN_SRC,Controls the clock source for the entire MCU domain while MCU is requesting powerdown.When MCU requests powerdown with SCLK_HF as source then WUC will switch over to this clock source during powerdown and automatically switch back to SCLK_HF.." "No clock in Powerdown,Use SCLK_LF in Powerdown,?,?"
|
|
line.long 0x04 "AUXCLK,AUX Clock ManagementThis register contains bitfields that are relevant for setting up the clock to the AUX domain"
|
|
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 11.--12. "PWR_DWN_SRC,When AUX requests powerdown with SCLK_HF as source then WUC will switch over to this clock source during powerdown and automatically switch back to SCLK_HF when AUX system is back in active mode" "No clock in Powerdown,Use SCLK_LF in Powerdown,?,?"
|
|
newline
|
|
bitfld.long 0x04 8.--10. "SCLK_HF_DIV,Select the AUX clock divider for SCLK_HFNB: It is not supported to change the AUX clock divider while SCLK_HF is active source for AUX" "Divide by 2,Divide by 4,Divide by 8,Divide by 16,Divide by 32,Divide by 64,Divide by 128,Divide by 256"
|
|
newline
|
|
rbitfld.long 0x04 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x04 0.--2. "SRC,Selects the clock source for AUX:NB: Switching the clock source is guaranteed to be glitchless" "?,HF Clock (SCLK_HF),?,?,LF Clock (SCLK_LF),?,?,?"
|
|
line.long 0x08 "MCUCFG,MCU ConfigurationThis register contains power management related bitfields for the MCU domain"
|
|
hexmask.long.word 0x08 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 17. "VIRT_OFF,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. "FIXED_WU_EN,Internal" "0,1"
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hexmask.long.word 0x08 4.--15. 1. "RESERVED4,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x08 0.--3. "SRAM_RET_EN,MCU SRAM is partitioned into 4 banks" "Retention is disabled,Retention on for SRAM:BANK0 ,?,Retention on for SRAM:BANK0 and SRAM:BANK1 ,?,?,?,Retention on for SRAM:BANK0 SRAM:BANK1 and..,?,?,?,?,?,?,?,Retention on for all banks (SRAM:BANK0 .."
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|
line.long 0x0C "AUXCFG,AUX ConfigurationThis register contains power management related signals for the AUX domain"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
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newline
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bitfld.long 0x0C 0. "RAM_RET_EN,This bit controls retention mode for the AUX_RAM:BANK0:0: Retention is disabled1: Retention is enabledNB: If retention is disabled the AUX_RAM will be powered off when it would otherwise be put in retention mode" "Retention is disabled,Retention is enabledNB"
|
|
line.long 0x10 "AUXCTL,AUX ControlThis register contains events and control signals for the AUX domain."
|
|
bitfld.long 0x10 31. "RESET_REQ,Reset request for AUX" "AUX reset pin will be deasserted,AUX reset pin will be asserted"
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|
newline
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hexmask.long 0x10 3.--30. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 2. "SCE_RUN_EN,Enables (1) or disables (0) AUX_SCE execution" "AUX_SCE execution will be disabled if AUX_SCE,AUX_SCE execution is enabled"
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newline
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bitfld.long 0x10 1. "SWEV,Writing 1 sets the software event to the AUX domain which can be read through AUX_WUC:WUEVFLAGS.AON_SW.This event is normally cleared by AUX_SCE through the AUX_WUC:WUEVCLR.AON_SW" "0,1"
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newline
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bitfld.long 0x10 0. "AUX_FORCE_ON,Forces the AUX domain into active mode overriding the requests from AUX_WUC:PWROFFREQ AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL" "AUX is allowed to Power Off Power Down or..,AUX Power OFF Power Down or Disconnect requests.."
|
|
line.long 0x14 "PWRSTAT,Power StatusThis register is used to monitor various power management related signals in AON"
|
|
hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 9. "AUX_PWR_DWN,Indicates the AUX powerdown state when AUX domain is powered up.0: Active mode1: AUX Powerdown request has been granted" "Active mode,AUX Powerdown request has been.."
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newline
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rbitfld.long 0x14 7.--8. "RESERVED7,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x14 6. "JTAG_PD_ON,Indicates JTAG power state:0: JTAG is powered off1: JTAG is powered on" "JTAG is powered off,JTAG is powered on"
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newline
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bitfld.long 0x14 5. "AUX_PD_ON,Indicates AUX power state:0: AUX is not ready for use ( may be powered off or in power state transition )1: AUX is powered on connected to bus and ready for use " "AUX is not ready for use ( may be powered off or..,AUX is powered on connected to bus and ready for.."
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newline
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bitfld.long 0x14 4. "MCU_PD_ON,Indicates MCU power state:0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not be reliable1: MCU Power sequencing is finalized and all MCU_AONIF registers are reliable" "MCU Power sequencing is not yet finalized and..,MCU Power sequencing is finalized and all.."
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newline
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rbitfld.long 0x14 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x14 2. "AUX_BUS_CONNECTED,Indicates that AUX Bus is connected:0: AUX bus is not connected1: AUX bus is connected ( idle_ack = 0 )" "AUX bus is not connected,AUX bus is connected ( idle_ack = 0 )"
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newline
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bitfld.long 0x14 1. "AUX_RESET_DONE,Indicates Reset Done from AUX:0: AUX is being reset1: AUX reset is released" "AUX is being reset,AUX reset is released"
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newline
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rbitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x18 "SHUTDOWN,Shutdown ControlThis register contains bitfields required for entering shutdown mode"
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hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 0. "EN,Writing a 1 to this bit forces a shutdown request to be registered and all I/O values to be latched - in the PAD ring possibly enabling I/O wakeup" "0,1"
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group.long 0x20++0x07
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line.long 0x00 "CTL0,Control 0This register contains various chip level control and debug bitfields."
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hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 8. "PWR_DWN_DIS,Controls whether MCU and AUX requesting to be powered off will enable a transition to powerdown:0: Enabled1: Disabled" "Enabled,Disabled"
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newline
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bitfld.long 0x00 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 3. "AUX_SRAM_ERASE,Internal" "0,1"
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newline
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bitfld.long 0x00 2. "MCU_SRAM_ERASE,Internal" "0,1"
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newline
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rbitfld.long 0x00 0.--1. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
line.long 0x04 "CTL1,Control 1This register contains various chip level control and debug bitfields."
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hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 1. "MCU_RESET_SRC,Indicates source of last MCU Voltage Domain warm reset request:0: MCU SW reset1: JTAG resetThis bit can only be cleared by writing a 1 to it" "MCU SW reset,JTAG resetThis bit can only be.."
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newline
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bitfld.long 0x04 0. "MCU_WARM_RESET,Indicates type of last MCU Voltage Domain reset:0: Last MCU reset was not a warm reset1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated in MCU_RESET_SRC)This bit can only be cleared by writing a 1 to it" "Last MCU reset was not a warm reset,Last MCU reset was a warm reset (requested from.."
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group.long 0x30++0x0B
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line.long 0x00 "RECHARGECFG,Recharge Controller ConfigurationThis register sets all relevant patameters for controlling the recharge algorithm"
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bitfld.long 0x00 31. "ADAPTIVE_EN,Enable adaptive rechargeNote: Recharge can be turned completely of by setting MAX_PER_E=7 and MAX_PER_M=31 and this bitfield to 0" "0,1"
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newline
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hexmask.long.byte 0x00 24.--30. 1. "RESERVED24,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x00 20.--23. "C2,Gain factor for adaptive recharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 16.--19. "C1,Gain factor for adaptive recharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 11.--15. "MAX_PER_M,This register defines the maximum period that the recharge algorithm can take i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 8.--10. "MAX_PER_E,This register defines the maximum period that the recharge algorithm can take i.e" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 3.--7. "PER_M,Number of 32 KHz clocks between activation of recharge controllerFor recharge algorithm PERIOD is the initial period when entering powerdown mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 0.--2. "PER_E,Number of 32 KHz clocks between activation of recharge controllerFor recharge algorithm PERIOD is the initial period when entering powerdown mode" "0,1,2,3,4,5,6,7"
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line.long 0x04 "RECHARGESTAT,Recharge Controller StatusThis register controls various status registers which are updated during recharge"
|
|
hexmask.long.word 0x04 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
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newline
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rbitfld.long 0x04 16.--19. "VDDR_SMPLS,The last 4 VDDR samples bit 0 being the newest.The register is being updated in every recharge period with a shift left and bit 0 is updated with the last VDDR sample ie a 1 is shiftet in in case VDDR > VDDR_threshold just before recharge.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.word 0x04 0.--15. 1. "MAX_USED_PER,The maximum value of recharge period seen with VDDR>threshold.The VDDR voltage is compared against the threshold voltage at just before each recharge"
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|
line.long 0x08 "OSCCFG,Oscillator ConfigurationThis register sets the period for Amplitude compensation requests sent to the oscillator control system"
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|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x08 3.--7. "PER_M,Number of 32 KHz clocks between oscillator amplitude calibrations.When this counter expires an oscillator amplitude compensation is triggered immediately in Active mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x08 0.--2. "PER_E,Number of 32 KHz clocks between oscillator amplitude calibrations.When this counter expires an oscillator amplitude compensation is triggered immediately in Active mode" "0,1,2,3,4,5,6,7"
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group.long 0x40++0x07
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line.long 0x00 "JTAGCFG,JTAG ConfigurationThis register contains control for configuration of the JTAG domain.- hereunder access permissions for each TAP"
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|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x00 8. "JTAG_PD_FORCE_ON,Controls JTAG PowerDomain power state:0: Controlled exclusively by debug subsystem" "Controlled exclusively by debug subsystem,JTAG Power Domain is forced on independent of.."
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "JTAGUSERCODE,JTAG USERCODEBoot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem"
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tree.end
|
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tree.end
|
|
tree "AUX"
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|
tree "AUX_ADI4"
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|
base ad:0x400CB000
|
|
group.byte 0x00++0x05
|
|
line.byte 0x00 "MUX0,Internal"
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|
bitfld.byte 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x00 6. "ADCCOMPB_IN,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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|
newline
|
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bitfld.byte 0x00 4.--5. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "COMPA_REF,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
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|
line.byte 0x01 "MUX1,Internal"
|
|
line.byte 0x02 "MUX2,Internal"
|
|
bitfld.byte 0x02 3.--7. "ADCCOMPB_IN,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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|
bitfld.byte 0x02 0.--2. "DAC_VREF_SEL,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?"
|
|
line.byte 0x03 "MUX3,Internal"
|
|
line.byte 0x04 "ISRC,Current SourceStrength and trim control for current source"
|
|
bitfld.byte 0x04 2.--7. "TRIM,Adjust current from current source.Output currents may be combined to get desired total current" "No current connected,0.25 uA,0.5 uA,?,1.0 uA,?,?,?,2.0 uA,?,?,?,?,?,?,?,4.5 uA,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,11.75 uA,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x04 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.byte 0x04 0. "EN,Current source enable" "0,1"
|
|
line.byte 0x05 "COMP,ComparatorControl COMPA and COMPB comparators"
|
|
bitfld.byte 0x05 7. "COMPA_REF_RES_EN,Enables 400kohm resistance from COMPA reference node to ground" "0,1"
|
|
bitfld.byte 0x05 6. "COMPA_REF_CURR_EN,Enables 2uA IPTAT current from ISRC to COMPA reference node" "0,1"
|
|
newline
|
|
bitfld.byte 0x05 3.--5. "LPM_BIAS_WIDTH_TRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x05 2. "COMPB_EN,COMPB enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x05 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x05 0. "COMPA_EN,COMPA enable" "0,1"
|
|
group.byte 0x07++0x04
|
|
line.byte 0x00 "MUX4,Internal"
|
|
line.byte 0x01 "ADC0,ADC Control 0ADC Sample Control"
|
|
bitfld.byte 0x01 7. "SMPL_MODE,ADC Sampling mode:0: Synchronous mode1: Asynchronous modeThe ADC does a sample-and-hold before conversion" "Synchronous mode,Asynchronous modeThe ADC does a.."
|
|
bitfld.byte 0x01 3.--6. "SMPL_CYCLE_EXP,Controls the sampling duration before conversion when the ADC is operated in synchronous mode (SMPL_MODE = 0)" "?,?,?,16x 6 MHz clock periods = 2.7us,32x 6 MHz clock periods = 5.3us,64x 6 MHz clock periods = 10.6us,128x 6 MHz clock periods = 21.3us,256x 6 MHz clock periods = 42.6us,512x 6 MHz clock periods = 85.3us,1024x 6 MHz clock periods = 170us,2048x 6 MHz clock periods = 341us,4096x 6 MHz clock periods = 682us,8192x 6 MHz clock periods = 1.37ms,16384x 6 MHz clock periods = 2.73ms,32768x 6 MHz clock periods = 5.46ms,65536x 6 MHz clock periods = 10.9ms"
|
|
newline
|
|
bitfld.byte 0x01 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x01 1. "RESET_N,Reset ADC digital subchip active low" "Reset,Normal.."
|
|
newline
|
|
bitfld.byte 0x01 0. "EN,ADC Enable0: Disable1: Enable" "Disable,Enable"
|
|
line.byte 0x02 "ADC1,ADC Control 1ADC Comparator Control"
|
|
hexmask.byte 0x02 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.byte 0x02 0. "SCALE_DIS,Internal" "0,1"
|
|
line.byte 0x03 "ADCREF0,ADC Reference 0Control reference used by the ADC"
|
|
bitfld.byte 0x03 7. "SPARE7,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x03 6. "REF_ON_IDLE,Enable ADCREF in IDLE state.0: Disabled in IDLE state1: Enabled in IDLE stateKeep ADCREF enabled when ADC0.SMPL_MODE =" "Disabled in IDLE state,Enabled in IDLE stateKeep ADCREF enabled when.."
|
|
newline
|
|
bitfld.byte 0x03 5. "IOMUX,Internal" "0,1"
|
|
bitfld.byte 0x03 4. "EXT,Internal" "0,1"
|
|
newline
|
|
bitfld.byte 0x03 3. "SRC,ADC reference source:0: Fixed reference =" "Fixed reference = 4.3V,Relative reference = VDDS"
|
|
bitfld.byte 0x03 1.--2. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x03 0. "EN,ADC reference module enable:0: ADC reference module powered down1: ADC reference module enabled" "ADC reference module powered down,ADC reference module enabled"
|
|
line.byte 0x04 "ADCREF1,ADC Reference 1Control reference used by the ADC"
|
|
bitfld.byte 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.byte 0x04 0.--5. "VTRIM,Trim output voltage of ADC fixed reference (64 steps 2's complement)" "nominal voltage 1.43V,nominal + 0.4% 1.435V,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,maximum voltage 1.6V,minimum voltage 1.3V,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,nominal - 0.4% 1.425V"
|
|
group.byte 0x0E++0x01
|
|
line.byte 0x00 "LPMBIAS,Internal"
|
|
bitfld.byte 0x00 6.--7. "SPARE6,Internal" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. "LPM_TRIM_IOUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "STAT,Software should not rely on the value of a reserved"
|
|
tree.end
|
|
repeat 2. (list 0. 1. )(list ad:0x400C1000 ad:0x400C2000 )
|
|
tree "AUX_AIODIO$1"
|
|
base $2
|
|
group.long 0x00++0x47
|
|
line.long 0x00 "IOMODE,Input Output ModeThis register controls pull-up. pull-down. and output mode for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "IO7,Selects mode for AUXIO[8i+7]" "Output Mode:When IOPOE bit 7 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 7 is 0:..,Open-Drain Mode: When IOPOE bit 7 is 0: - If..,Open-Source Mode: When IOPOE bit 7 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "IO6,Selects mode for AUXIO[8i+6]" "Output Mode:When IOPOE bit 6 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 6 is 0:..,Open-Drain Mode: When IOPOE bit 6 is 0: - If..,Open-Source Mode: When IOPOE bit 6 is 0: - If.."
|
|
newline
|
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bitfld.long 0x00 10.--11. "IO5,Selects mode for AUXIO[8i+5]" "Output Mode:When IOPOE bit 5 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 5 is 0:..,Open-Drain Mode: When IOPOE bit 5 is 0: - If..,Open-Source Mode: When IOPOE bit 5 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "IO4,Selects mode for AUXIO[8i+4]" "Output Mode:When IOPOE bit 4 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 4 is 0:..,Open-Drain Mode: When IOPOE bit 4 is 0: - If..,Open-Source Mode: When IOPOE bit 4 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "IO3,Selects mode for AUXIO[8i+3]" "Output Mode:When IOPOE bit 3 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 3 is 0:..,Open-Drain Mode: When IOPOE bit 3 is 0: - If..,Open-Source Mode: When IOPOE bit 3 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "IO2,Select mode for AUXIO[8i+2]" "Output Mode:When IOPOE bit 2 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 2 is 0:..,Open-Drain Mode: When IOPOE bit 2 is 0: - If..,Open-Source Mode: When IOPOE bit 2 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IO1,Select mode for AUXIO[8i+1]" "Output Mode:When IOPOE bit 1 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 1 is 0:..,Open-Drain Mode: When IOPOE bit 1 is 0: - If..,Open-Source Mode: When IOPOE bit 1 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "IO0,Select mode for AUXIO[8i+0]" "Output Mode:When IOPOE bit 0 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 0 is 0:..,Open-Drain Mode: When IOPOE bit 0 is 0: - If..,Open-Source Mode: When IOPOE bit 0 is 0: - If.."
|
|
line.long 0x04 "GPIODIE,General Purpose Input Output Digital Input EnableThis register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]"
|
|
line.long 0x08 "IOPOE,Input Output Peripheral Output EnableThis register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*].Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT"
|
|
line.long 0x0C "GPIODOUT,General Purpose Input Output Data OutThe output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to set AUXIO[8i+n].Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]"
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line.long 0x10 "GPIODIN,General Purpose Input Output Data InThis register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.byte 0x10 0.--7. 1. "IO7_0,Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set"
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|
line.long 0x14 "GPIODOUTSET,General Purpose Input Output Data Out SetSet bits in GPIODOUT in instance i of AUX_AIODIO"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.byte 0x14 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to set GPIODOUT bit n"
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|
line.long 0x18 "GPIODOUTCLR,General Purpose Input Output Data Out ClearClear bits in GPIODOUT instance i of AUX_AIODIO"
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hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x18 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to clear GPIODOUT bit n.Read value is 0"
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line.long 0x1C "GPIODOUTTGL,General Purpose Input Output Data Out ToggleToggle bits in GPIODOUT in instance i of AUX_AIODIO"
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hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x1C 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n"
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line.long 0x20 "IO0PSEL,Input Output 0 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1"
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hexmask.long 0x20 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x24 "IO1PSEL,Input Output 1 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1"
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hexmask.long 0x24 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x28 "IO2PSEL,Input Output 2 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1"
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hexmask.long 0x28 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x28 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x2C "IO3PSEL,Input Output 3 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1"
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hexmask.long 0x2C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x30 "IO4PSEL,Input Output 4 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1"
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hexmask.long 0x30 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x30 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x34 "IO5PSEL,Input Output 5 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1"
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hexmask.long 0x34 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x34 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x38 "IO6PSEL,Input Output 6 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1"
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hexmask.long 0x38 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x38 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x3C "IO7PSEL,Input Output 7 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1"
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hexmask.long 0x3C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x3C 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x40 "IOMODEL,Input Output Mode LowThis is an alias register for IOMODE.IO0 thru IOMODE.IO3"
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hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x40 6.--7. "IO3,See IOMODE.IO3" "0,1,2,3"
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newline
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bitfld.long 0x40 4.--5. "IO2,See IOMODE.IO2" "0,1,2,3"
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newline
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bitfld.long 0x40 2.--3. "IO1,See IOMODE.IO1" "0,1,2,3"
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newline
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bitfld.long 0x40 0.--1. "IO0,See IOMODE.IO0" "0,1,2,3"
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line.long 0x44 "IOMODEH,Input Output Mode HighThis is an alias register for IOMODE.IO4 thru IOMODE.IO7"
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hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x44 6.--7. "IO7,See IOMODE.IO7" "0,1,2,3"
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newline
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bitfld.long 0x44 4.--5. "IO6,See IOMODE.IO6" "0,1,2,3"
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newline
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bitfld.long 0x44 2.--3. "IO5,See IOMODE.IO5" "0,1,2,3"
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newline
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bitfld.long 0x44 0.--1. "IO4,See IOMODE.IO4" "0,1,2,3"
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tree.end
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repeat.end
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tree "AUX_ANAIF"
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base ad:0x400C9000
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group.long 0x10++0x13
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line.long 0x00 "ADCCTL,ADC ControlConfiguration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion"
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hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 14. "START_POL,Select active polarity for START_SRC event" "Set ADC trigger on rising edge of event source.,Set ADC trigger on falling edge of event source."
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newline
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bitfld.long 0x00 8.--13. "START_SRC,Select ADC trigger event source from the asynchronous AUX event bus.Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10,AUX_EVCTL:EVSTAT0.AUXIO11,AUX_EVCTL:EVSTAT0.AUXIO12,AUX_EVCTL:EVSTAT0.AUXIO13,AUX_EVCTL:EVSTAT0.AUXIO14,AUX_EVCTL:EVSTAT0.AUXIO15,AUX_EVCTL:EVSTAT1.AUXIO16,AUX_EVCTL:EVSTAT1.AUXIO17,AUX_EVCTL:EVSTAT1.AUXIO18,AUX_EVCTL:EVSTAT1.AUXIO19,AUX_EVCTL:EVSTAT1.AUXIO20,AUX_EVCTL:EVSTAT1.AUXIO21,AUX_EVCTL:EVSTAT1.AUXIO22,AUX_EVCTL:EVSTAT1.AUXIO23,AUX_EVCTL:EVSTAT1.AUXIO24,AUX_EVCTL:EVSTAT1.AUXIO25,AUX_EVCTL:EVSTAT1.AUXIO26,AUX_EVCTL:EVSTAT1.AUXIO27,AUX_EVCTL:EVSTAT1.AUXIO28,AUX_EVCTL:EVSTAT1.AUXIO29,AUX_EVCTL:EVSTAT1.AUXIO30,AUX_EVCTL:EVSTAT1.AUXIO31,AUX_EVCTL:EVSTAT2.MANUAL_EV ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,?,?,AUX_EVCTL:EVSTAT2.AUX_COMPA,AUX_EVCTL:EVSTAT2.AUX_COMPB,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,?,?,?,?,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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rbitfld.long 0x00 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--1. "CMD,ADC interface command.Non-enumerated values are not supported" "Disable ADC interface.,Enable ADC interface.,?,Flush ADC FIFO.You must set CMD to EN or DIS.."
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line.long 0x04 "ADCFIFOSTAT,ADC FIFO StatusFIFO can hold up to four ADC samples"
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hexmask.long 0x04 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 4. "OVERFLOW,FIFO overflow flag.0: FIFO has not overflowed.1: FIFO has overflowed this flag is sticky until you flush the FIFO.When the flag is set the ADC FIFO write pointer is static" "FIFO has not overflowed,FIFO has overflowed this flag is sticky until.."
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newline
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bitfld.long 0x04 3. "UNDERFLOW,FIFO underflow flag.0: FIFO has not underflowed.1: FIFO has underflowed this flag is sticky until you flush the FIFO.When the flag is set the ADC FIFO read pointer is static" "FIFO has not underflowed,FIFO has underflowed this flag is sticky until.."
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newline
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bitfld.long 0x04 2. "FULL,FIFO full flag.0: FIFO is not full there is less than 4 samples in the FIFO" "FIFO is not full there is less than 4 samples in..,FIFO is full there are 4 samples in the.."
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newline
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bitfld.long 0x04 1. "ALMOST_FULL,FIFO almost full flag.0: There are less than 3 samples in the FIFO or the FIFO is full" "There are less than 3 samples in the FIFO or the..,There are 3 samples in the FIFO there is room.."
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newline
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bitfld.long 0x04 0. "EMPTY,FIFO empty flag.0: FIFO contains one or more samples.1: FIFO is empty.When the flag is set read returns the previous sample that was read and sets the UNDERFLOW flag" "FIFO contains one or more samples,FIFO is empty.When the flag is set read returns.."
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line.long 0x08 "ADCFIFO,ADC FIFO"
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hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x08 0.--11. 1. "DATA,FIFO data.Read:Get oldest ADC sample from FIFO.Write:Write dummy sample to FIFO"
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line.long 0x0C "ADCTRIG,ADC Trigger"
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hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 0. "START,Manual ADC trigger" "0,1"
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line.long 0x10 "ISRCCTL,Current Source Control"
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hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 0. "RESET_N,ISRC reset control.0: ISRC drives 0 uA.1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN" "ISRC drives 0 uA,ISRC drives current ADI_4_AUX"
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group.long 0x30++0x1B
|
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line.long 0x00 "DACCTL,DAC ControlThis register controls the analog part of the DAC."
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hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 5. "DAC_EN,DAC module enable.0: Disable DAC.1: Enable DAC.The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA.The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA in Standby TI-RTOS power mode" "Disable DAC,Enable DAC.The Sensor.."
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newline
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bitfld.long 0x00 4. "DAC_BUFFER_EN,DAC buffer enable.DAC buffer reduces the time required to produce the programmed voltage at the expense of increased current consumption.0: Disable DAC buffer.1: Enable DAC buffer.Enable buffer when DAC_VOUT_SEL equals COMPA_IN.Do not.." "Disable DAC buffer,Enable DAC buffer.Enable buffer when.."
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newline
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bitfld.long 0x00 3. "DAC_PRECHARGE_EN,DAC precharge enable.Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and VDDS is higher than 2.65 V" "0 V to 1.28 V,1.28 V to 2.56 V"
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newline
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bitfld.long 0x00 0.--2. "DAC_VOUT_SEL,DAC output connection.An analog node must only have one driver" "Connect to nothingIt is recommended to use NC..,Connect to COMPB_REF analog node.Required..,Connect to COMPA_REF analog node.It is not..,?,Connect to COMPA_IN analog node.Required..,?,?,?"
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line.long 0x04 "LPMBIASCTL,Low Power Mode Bias ControlThe low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "EN,Module enable.0: Disable low power mode bias module.1: Enable low power mode bias module.Set EN to 1 15 us before you enable the DAC or Comparator A" "Disable low power mode bias module,Enable low power mode bias module.Set EN to 1 15.."
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|
line.long 0x08 "DACSMPLCTL,DAC Sample ControlThe DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor"
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hexmask.long 0x08 1.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x08 0. "EN,DAC sample clock enable.0: Disable sample clock" "Disable sample clock,Enable DAC sample clock"
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line.long 0x0C "DACSMPLCFG0,DAC Sample Configuration 0"
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hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x0C 0.--5. "CLKDIV,Clock division.AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the sample clock base frequency" "Divide by 1,Divide by 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 64"
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|
line.long 0x10 "DACSMPLCFG1,DAC Sample Configuration 1The sample clock period equals (high time + low time) * base period"
|
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x10 14. "H_PER,High time.The sample clock period is high for this many base periods.0: 2 periods1: 4 periods" "2 periods,4 periods"
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|
newline
|
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bitfld.long 0x10 12.--13. "L_PER,Low time.The sample clock period is low for this many base periods.0: 1 period1: 2 periods2: 3 periods3: 4 periods" "1 period,2 periods,3 periods,4 periods"
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newline
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bitfld.long 0x10 8.--11. "SETUP_CNT,Setup count.Number of active sample clock periods during the setup phase.0: 1 sample clock period" "1 sample clock period,2 sample clock periods,?,?,?,?,?,?,?,?,?,?,?,?,?,16 sample clock periods"
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|
newline
|
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hexmask.long.byte 0x10 0.--7. 1. "HOLD_INTERVAL,Hold interval.Number of inactive sample clock periods between each active sample clock period during hold phase"
|
|
line.long 0x14 "DACVALUE,DAC Value"
|
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x14 0.--7. 1. "VALUE,DAC value.Digital data word for the DAC.Only change VALUE when DACCTL.DAC_EN is 0"
|
|
line.long 0x18 "DACSTAT,DAC Status"
|
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hexmask.long 0x18 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x18 1. "SETUP_ACTIVE,DAC setup phase status.0: Sample clock is disabled or setup phase is complete.1: Setup phase in progress" "Sample clock is disabled or setup phase is..,Setup phase in progress"
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newline
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bitfld.long 0x18 0. "HOLD_ACTIVE,DAC hold phase status.0: Sample clock is disabled or DAC is not in hold phase.1: Hold phase in progress" "Sample clock is disabled or DAC is not in hold..,Hold phase in progress"
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tree.end
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tree "AUX_DDI0_OSC"
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|
base ad:0x400CA000
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group.long 0x00++0x37
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|
line.long 0x00 "CTL0,Control 0Controls clock source selects"
|
|
bitfld.long 0x00 31. "XTAL_IS_24M,Set based on the accurate high frequency XTAL" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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|
newline
|
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bitfld.long 0x00 30. "RESERVED30,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
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bitfld.long 0x00 29. "BYPASS_XOSC_LF_CLK_QUAL,Internal" "0,1"
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|
newline
|
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bitfld.long 0x00 28. "BYPASS_RCOSC_LF_CLK_QUAL,Internal" "0,1"
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newline
|
|
bitfld.long 0x00 26.--27. "DOUBLER_START_DURATION,Internal" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x00 25. "DOUBLER_RESET_DURATION,Internal" "0,1"
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|
newline
|
|
bitfld.long 0x00 24. "CLK_DCDC_SRC_SEL,Select DCDC clock source.0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC1: CLK_DCDC is always 48 MHz clock from RCOSC" "CLK_DCDC is 48 MHz clock from RCOSC or XOSC /..,CLK_DCDC is always 48 MHz clock from RCOSC"
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|
newline
|
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hexmask.long.word 0x00 15.--23. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 14. "HPOSC_MODE_EN," "0,1"
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|
newline
|
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bitfld.long 0x00 13. "RESERVED13,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
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bitfld.long 0x00 12. "RCOSC_LF_TRIMMED,Internal" "0,1"
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|
newline
|
|
bitfld.long 0x00 11. "XOSC_HF_POWER_MODE,Internal" "0,1"
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|
newline
|
|
bitfld.long 0x00 10. "XOSC_LF_DIG_BYPASS,Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock.0: Use 32kHz XOSC as xosc_lf clock source1: Use digital input (from AON) as xosc_lf clock source.This bit will only have effect when SCLK_LF_SRC_SEL is.." "Use 32kHz XOSC as xosc_lf clock source,Use digital input (from AON) as xosc_lf clock.."
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|
newline
|
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bitfld.long 0x00 9. "CLK_LOSS_EN,Enable clock loss detection and hence the indicators to the system controller" "Disable,EnableClock loss.."
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|
newline
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bitfld.long 0x00 7.--8. "ACLK_TDC_SRC_SEL,Source select for aclk_tdc.00: RCOSC_HF (48MHz)01: RCOSC_HF (24MHz)10: XOSC_HF (24MHz)11: Not used" "RCOSC_HF (48MHz),RCOSC_HF (24MHz),?..."
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bitfld.long 0x00 4.--6. "ACLK_REF_SRC_SEL,Source select for aclk_ref000: RCOSC_HF derived (31.25kHz)001: XOSC_HF derived (31.25kHz)010: RCOSC_LF (32kHz)011: XOSC_LF (32.768kHz)100: RCOSC_MF (2MHz)101-111: Not used" "RCOSC_HF derived (31.25kHz),XOSC_HF derived (31.25kHz),?..."
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bitfld.long 0x00 2.--3. "SCLK_LF_SRC_SEL,Source select for sclk_lf" "Low frequency clock derived from High Frequency..,Low frequency clock derived from High Frequency..,Low frequency RCOSC,Low frequency XOSC"
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bitfld.long 0x00 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 0. "SCLK_HF_SRC_SEL,Source select for sclk_hf" "High frequency RCOSC clock,High frequency XOSC or HPOSC clk (use HPOSC when.."
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line.long 0x04 "CTL1,Control 1This register contains OSC_DIG configuration"
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hexmask.long.word 0x04 23.--31. 1. "RESERVED23,Software should not rely on the value of a reserved"
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bitfld.long 0x04 18.--22. "RCOSCHFCTRIMFRACT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 17. "RCOSCHFCTRIMFRACT_EN,Internal" "0,1"
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hexmask.long.byte 0x04 10.--16. 1. "SPARE10,Software should not rely on the value of a reserved"
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bitfld.long 0x04 9. "FORCE_RCOSC_LF,Force rcosc_lf to be enabled0: Disabled1: Enabled" "Disabled,Enabled"
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bitfld.long 0x04 8. "CLK_LF_LOSS_EN,Enable LF clock loss detection and hence the indicators to the system controller" "Disable,EnableClock loss.."
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bitfld.long 0x04 2.--7. "SPARE2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 0.--1. "XOSC_HF_FAST_START,Internal" "0,1,2,3"
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line.long 0x08 "RADCEXTCFG,RADC External Configuration"
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hexmask.long.word 0x08 22.--31. 1. "HPM_IBIAS_WAIT_CNT,Internal"
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bitfld.long 0x08 16.--21. "LPM_IBIAS_WAIT_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 12.--15. "IDAC_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 6.--11. "RADC_DAC_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 5. "RADC_MODE_IS_SAR,Internal" "0,1"
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bitfld.long 0x08 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x0C "AMPCOMPCTL,Amplitude Compensation Control"
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bitfld.long 0x0C 31. "SPARE31,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x0C 30. "AMPCOMP_REQ_MODE,Internal" "0,1"
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bitfld.long 0x0C 28.--29. "AMPCOMP_FSM_UPDATE_RATE,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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bitfld.long 0x0C 27. "AMPCOMP_SW_CTRL,Internal" "0,1"
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bitfld.long 0x0C 26. "AMPCOMP_SW_EN,Internal" "0,1"
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bitfld.long 0x0C 24.--25. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x0C 20.--23. "IBIAS_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "IBIAS_INIT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "LPM_IBIAS_WAIT_CNT_FINAL,Internal"
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bitfld.long 0x0C 4.--7. "CAP_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "IBIASCAP_HPTOLP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x10 "AMPCOMPTH1,Amplitude Compensation Threshold 1This register contains threshold values for amplitude compensation algorithm"
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hexmask.long.byte 0x10 24.--31. 1. "SPARE24,Software should not rely on the value of a reserved"
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bitfld.long 0x10 18.--23. "HPMRAMP3_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 16.--17. "SPARE16,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x10 10.--15. "HPMRAMP3_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 6.--9. "IBIASCAP_LPTOHP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0.--5. "HPMRAMP1_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x14 "AMPCOMPTH2,Amplitude Compensation Threshold 2This register contains threshold values for amplitude compensation algorithm."
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bitfld.long 0x14 26.--31. "LPMUPDATE_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 24.--25. "SPARE24,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x14 18.--23. "LPMUPDATE_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 16.--17. "SPARE16,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x14 10.--15. "ADC_COMP_AMPTH_LPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 8.--9. "SPARE8,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x14 2.--7. "ADC_COMP_AMPTH_HPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 0.--1. "SPARE0,Software should not rely on the value of a reserved" "0,1,2,3"
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line.long 0x18 "ANABYPASSVAL1,Analog Bypass Values 1"
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hexmask.long.word 0x18 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
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bitfld.long 0x18 16.--19. "XOSC_HF_ROW_Q12,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x18 0.--15. 1. "XOSC_HF_COLUMN_Q12,Internal"
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line.long 0x1C "ANABYPASSVAL2,Internal"
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hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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hexmask.long.word 0x1C 0.--13. 1. "XOSC_HF_IBIASTHERM,Internal"
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line.long 0x20 "ATESTCTL,Analog Test Control"
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bitfld.long 0x20 31. "SCLK_LF_AUX_EN,Enable 32 kHz clock to AUX_COMPB." "0,1"
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hexmask.long.word 0x20 16.--30. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x20 14.--15. "TEST_RCOSCMF,Test mode control for RCOSC_MF0x0: test modes" "test modes disabled,boosted bias current into self biased inverter,clock qualification disabled,boosted bias current into self biased inverter +.."
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bitfld.long 0x20 12.--13. "ATEST_RCOSCMF,ATEST control for RCOSC_MF0x0: ATEST" "ATEST disabled,ATEST enabled VDD_LOCAL connected ATEST internal..,ATEST disabled,ATEST enabled bias current connected ATEST.."
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hexmask.long.word 0x20 0.--11. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x24 "ADCDOUBLERNANOAMPCTL,ADC Doubler Nanoamp Control"
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hexmask.long.byte 0x24 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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bitfld.long 0x24 24. "NANOAMP_BIAS_ENABLE,Internal" "0,1"
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bitfld.long 0x24 23. "SPARE23,Software should not rely on the value of a reserved" "0,1"
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hexmask.long.tbyte 0x24 6.--22. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x24 5. "ADC_SH_MODE_EN,Internal" "0,1"
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bitfld.long 0x24 4. "ADC_SH_VBUF_EN,Internal" "0,1"
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bitfld.long 0x24 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x24 0.--1. "ADC_IREF_CTRL,Internal" "0,1,2,3"
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line.long 0x28 "XOSCHFCTL,XOSCHF Control"
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hexmask.long.tbyte 0x28 14.--31. 1. "SPARE14,Software should not rely on the value of a reserved"
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bitfld.long 0x28 13. "TCXO_MODE_XOSC_HF_EN,If this register is 1 when TCXO_MODE is 1 then the XOSC_HF is enabled turning on the XOSC_HF bias current allowing a DC bias point to be provided to the clipped-sine wave clock signal on external input" "0,1"
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bitfld.long 0x28 12. "TCXO_MODE,If this register is 1 when BYPASS is 1 this will enable clock qualification on the TCXO clock on external input" "0,1"
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bitfld.long 0x28 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x28 8.--9. "PEAK_DET_ITRIM,Internal" "0,1,2,3"
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bitfld.long 0x28 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x28 6. "BYPASS,Internal" "0,1"
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bitfld.long 0x28 5. "RESERVED5,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x28 2.--4. "HP_BUF_ITRIM,Internal" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 0.--1. "LP_BUF_ITRIM,Internal" "0,1,2,3"
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line.long 0x2C "LFOSCCTL,Low Frequency Oscillator Control"
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hexmask.long.byte 0x2C 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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bitfld.long 0x2C 22.--23. "XOSCLF_REGULATOR_TRIM,Internal" "0,1,2,3"
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bitfld.long 0x2C 18.--21. "XOSCLF_CMIRRWR_RATIO,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 10.--17. 1. "RESERVED10,Software should not rely on the value of a reserved"
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bitfld.long 0x2C 8.--9. "RCOSCLF_RTUNE_TRIM,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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hexmask.long.byte 0x2C 0.--7. 1. "RCOSCLF_CTUNE_TRIM,Internal"
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line.long 0x30 "RCOSCHFCTL,RCOSCHF Control"
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hexmask.long.word 0x30 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x30 8.--15. 1. "RCOSCHF_CTRIM,Internal"
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hexmask.long.byte 0x30 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x34 "RCOSCMFCTL,RCOSC_MF Control"
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hexmask.long.word 0x34 16.--31. 1. "SPARE16,Software should not rely on the value of a reserved"
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abitfld.long 0x34 9.--15. "RCOSC_MF_CAP_ARRAY,Adjust RCOSC_MF capacitor" "0x00=nominal frequency 0.625pF,0x3F=lowest frequency 1.125pF,0x40=highest frequency 0.125pF"
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bitfld.long 0x34 8. "RCOSC_MF_REG_SEL,Choose regulator type.0: default1: alternate" "default,alternate"
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bitfld.long 0x34 6.--7. "RCOSC_MF_RES_COARSE,Select coarse resistor for frequency" "400kohms default,300kohms min,600kohms max,500kohms"
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bitfld.long 0x34 4.--5. "RCOSC_MF_RES_FINE,Select fine resistor for frequency" "11kohms minimum resistance max freq,13kohms,16kohms,20kohms max resistance min freq"
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bitfld.long 0x34 0.--3. "RCOSC_MF_BIAS_ADJ,Adjusts bias current to RCOSC_MF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x3C++0x0B
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line.long 0x00 "STAT0,Status 0This register contains status signals from OSC_DIG"
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bitfld.long 0x00 31. "RCOSC_LF_GOOD,RCOSC_LF_GOOD" "0,1"
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bitfld.long 0x00 29.--30. "SCLK_LF_SRC,Indicates source for the sclk_lf" "Low frequency clock derived from High Frequency..,Low frequency clock derived from High Frequency..,Low frequency RCOSC,Low frequency XOSC"
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bitfld.long 0x00 28. "SCLK_HF_SRC,Indicates source for the sclk_hf" "High frequency RCOSC clock,High frequency XOSC"
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bitfld.long 0x00 23.--27. "RESERVED23,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 22. "RCOSC_HF_EN,RCOSC_HF_EN" "0,1"
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bitfld.long 0x00 21. "RCOSC_LF_EN,RCOSC_LF_EN" "0,1"
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bitfld.long 0x00 20. "XOSC_LF_EN,XOSC_LF_EN" "0,1"
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bitfld.long 0x00 19. "CLK_DCDC_RDY,CLK_DCDC_RDY" "0,1"
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bitfld.long 0x00 18. "CLK_DCDC_RDY_ACK,CLK_DCDC_RDY_ACK" "0,1"
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bitfld.long 0x00 17. "SCLK_HF_LOSS,Indicates sclk_hf is lost" "0,1"
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bitfld.long 0x00 16. "SCLK_LF_LOSS,Indicates sclk_lf is lost" "0,1"
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bitfld.long 0x00 15. "XOSC_HF_EN,Indicates that XOSC_HF is enabled" "0,1"
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bitfld.long 0x00 14. "RESERVED14,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 13. "XB_48M_CLK_EN,Indicates that the 48MHz clock from the DOUBLER is enabled.It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal)" "0,1"
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bitfld.long 0x00 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 11. "XOSC_HF_LP_BUF_EN,XOSC_HF_LP_BUF_EN" "0,1"
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bitfld.long 0x00 10. "XOSC_HF_HP_BUF_EN,XOSC_HF_HP_BUF_EN" "0,1"
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bitfld.long 0x00 9. "RESERVED9,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 8. "ADC_THMET,ADC_THMET" "0,1"
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bitfld.long 0x00 7. "ADC_DATA_READY,indicates when adc_data is ready" "0,1"
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bitfld.long 0x00 1.--6. "ADC_DATA,adc_data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "PENDINGSCLKHFSWITCHING,Indicates when SCLK_HF clock source is ready to be switched" "0,1"
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line.long 0x04 "STAT1,Status 1This register contains status signals from OSC_DIG"
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bitfld.long 0x04 28.--31. "RAMPSTATE,AMPCOMP FSM State" "RESET,INITIALIZATION,HPM_RAMP1,HPM_RAMP2,HPM_RAMP3,HPM_UPDATE,IDAC_INCREMENT,IBIAS_CAP_UPDATE,IBIAS_DECREMENT_WITH_MEASURE,LPM_UPDATE,IBIAS_INCREMENT,IDAC_DECREMENT_WITH_MEASURE,DUMMY_TO_INIT_1,FAST_START,FAST_START_SETTLE,?"
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bitfld.long 0x04 22.--27. "HPM_UPDATE_AMP,XOSC_HF amplitude during HPM_UPDATE state.When amplitude compensation of XOSC_HF is enabled in high performance mode this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC divided by 15 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 16.--21. "LPM_UPDATE_AMP,XOSC_HF amplitude during LPM_UPDATE stateWhen amplitude compensation of XOSC_HF is enabled in low power mode this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC divided by 15 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 15. "FORCE_RCOSC_HF,force_rcosc_hf" "0,1"
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bitfld.long 0x04 14. "SCLK_HF_EN,SCLK_HF_EN" "0,1"
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bitfld.long 0x04 13. "SCLK_MF_EN,SCLK_MF_EN" "0,1"
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bitfld.long 0x04 12. "ACLK_ADC_EN,ACLK_ADC_EN" "0,1"
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bitfld.long 0x04 11. "ACLK_TDC_EN,ACLK_TDC_EN" "0,1"
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bitfld.long 0x04 10. "ACLK_REF_EN,ACLK_REF_EN" "0,1"
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bitfld.long 0x04 9. "CLK_CHP_EN,CLK_CHP_EN" "0,1"
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bitfld.long 0x04 8. "CLK_DCDC_EN,CLK_DCDC_EN" "0,1"
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bitfld.long 0x04 7. "SCLK_HF_GOOD,SCLK_HF_GOOD" "0,1"
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bitfld.long 0x04 6. "SCLK_MF_GOOD,SCLK_MF_GOOD" "0,1"
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bitfld.long 0x04 5. "SCLK_LF_GOOD,SCLK_LF_GOOD" "0,1"
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bitfld.long 0x04 4. "ACLK_ADC_GOOD,ACLK_ADC_GOOD" "0,1"
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bitfld.long 0x04 3. "ACLK_TDC_GOOD,ACLK_TDC_GOOD" "0,1"
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bitfld.long 0x04 2. "ACLK_REF_GOOD,ACLK_REF_GOOD" "0,1"
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bitfld.long 0x04 1. "CLK_CHP_GOOD,CLK_CHP_GOOD" "0,1"
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bitfld.long 0x04 0. "CLK_DCDC_GOOD,CLK_DCDC_GOOD" "0,1"
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line.long 0x08 "STAT2,Status 2This register contains status signals from AMPCOMP FSM"
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bitfld.long 0x08 26.--31. "ADC_DCBIAS,DC Bias read by RADC during SAR modeThe value is an unsigned integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 25. "HPM_RAMP1_THMET,Indication of threshold is met for hpm_ramp1" "0,1"
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bitfld.long 0x08 24. "HPM_RAMP2_THMET,Indication of threshold is met for hpm_ramp2" "0,1"
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bitfld.long 0x08 23. "HPM_RAMP3_THMET,Indication of threshold is met for hpm_ramp3" "0,1"
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hexmask.long.byte 0x08 16.--22. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x08 12.--15. "RAMPSTATE,xosc_hf amplitude compensation FSMThis is identical to STAT1.RAMPSTATE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 4.--11. 1. "RESERVED4,Software should not rely on the value of a reserved"
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bitfld.long 0x08 3. "AMPCOMP_REQ,ampcomp_req" "0,1"
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bitfld.long 0x08 2. "XOSC_HF_AMPGOOD,amplitude of xosc_hf is within the required threshold (set by DDI)" "0,1"
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bitfld.long 0x08 1. "XOSC_HF_FREQGOOD,frequency of xosc_hf is good to use for the digital clocks" "0,1"
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bitfld.long 0x08 0. "XOSC_HF_RF_FREQGOOD,frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations" "0,1"
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tree.end
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tree "AUX_EVCTL"
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base ad:0x400C5000
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rgroup.long 0x00++0x1B
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line.long 0x00 "EVSTAT0,Event Status 0Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x00 15. "AUXIO15,AUXIO15 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 7" "0,1"
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bitfld.long 0x00 14. "AUXIO14,AUXIO14 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 6" "0,1"
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bitfld.long 0x00 13. "AUXIO13,AUXIO13 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 5" "0,1"
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bitfld.long 0x00 12. "AUXIO12,AUXIO12 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 4" "0,1"
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bitfld.long 0x00 11. "AUXIO11,AUXIO11 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 3" "0,1"
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bitfld.long 0x00 10. "AUXIO10,AUXIO10 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 2" "0,1"
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bitfld.long 0x00 9. "AUXIO9,AUXIO9 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 1" "0,1"
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bitfld.long 0x00 8. "AUXIO8,AUXIO8 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 0" "0,1"
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bitfld.long 0x00 7. "AUXIO7,AUXIO7 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 7" "0,1"
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bitfld.long 0x00 6. "AUXIO6,AUXIO6 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 6" "0,1"
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bitfld.long 0x00 5. "AUXIO5,AUXIO5 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 5" "0,1"
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bitfld.long 0x00 4. "AUXIO4,AUXIO4 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 4" "0,1"
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bitfld.long 0x00 3. "AUXIO3,AUXIO3 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 3" "0,1"
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bitfld.long 0x00 2. "AUXIO2,AUXIO2 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 2" "0,1"
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bitfld.long 0x00 1. "AUXIO1,AUXIO1 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 1" "0,1"
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bitfld.long 0x00 0. "AUXIO0,AUXIO0 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 0" "0,1"
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line.long 0x04 "EVSTAT1,Event Status 1Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "AUXIO31,AUXIO31 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 7" "0,1"
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bitfld.long 0x04 14. "AUXIO30,AUXIO30 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 6" "0,1"
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bitfld.long 0x04 13. "AUXIO29,AUXIO29 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 5" "0,1"
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bitfld.long 0x04 12. "AUXIO28,AUXIO28 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 4" "0,1"
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bitfld.long 0x04 11. "AUXIO27,AUXIO27 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 3" "0,1"
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bitfld.long 0x04 10. "AUXIO26,AUXIO26 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 2" "0,1"
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bitfld.long 0x04 9. "AUXIO25,AUXIO25 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 1" "0,1"
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bitfld.long 0x04 8. "AUXIO24,AUXIO24 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 0" "0,1"
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bitfld.long 0x04 7. "AUXIO23,AUXIO23 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 7" "0,1"
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bitfld.long 0x04 6. "AUXIO22,AUXIO22 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 6" "0,1"
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bitfld.long 0x04 5. "AUXIO21,AUXIO21 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 5" "0,1"
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bitfld.long 0x04 4. "AUXIO20,AUXIO20 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 4" "0,1"
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bitfld.long 0x04 3. "AUXIO19,AUXIO19 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 3" "0,1"
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bitfld.long 0x04 2. "AUXIO18,AUXIO18 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 2" "0,1"
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bitfld.long 0x04 1. "AUXIO17,AUXIO17 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 1" "0,1"
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bitfld.long 0x04 0. "AUXIO16,AUXIO16 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 0" "0,1"
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line.long 0x08 "EVSTAT2,Event Status 2Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x08 15. "AUX_COMPB,Comparator B output" "0,1"
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bitfld.long 0x08 14. "AUX_COMPA,Comparator A output" "0,1"
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bitfld.long 0x08 13. "MCU_OBSMUX1,Observation input 1 from IOC" "0,1"
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bitfld.long 0x08 12. "MCU_OBSMUX0,Observation input 0 from IOC" "0,1"
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bitfld.long 0x08 11. "MCU_EV,Event from EVENT configured by EVENT:AUXSEL0" "0,1"
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bitfld.long 0x08 10. "ACLK_REF,TDC reference clock.It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ" "0,1"
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bitfld.long 0x08 9. "VDDR_RECHARGE,Event is high during VDDR recharge" "0,1"
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bitfld.long 0x08 8. "MCU_ACTIVE,Event is high while system(MCU AUX or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state)" "0,1"
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bitfld.long 0x08 7. "PWR_DWN,Event is high while system(MCU AUX or JTAG domains) is in powerdown (uLDO power supply)" "0,1"
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bitfld.long 0x08 6. "SCLK_LF,SCLK_LF clock" "0,1"
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bitfld.long 0x08 5. "AON_BATMON_TEMP_UPD,Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP" "0,1"
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newline
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bitfld.long 0x08 4. "AON_BATMON_BAT_UPD,Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT" "0,1"
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bitfld.long 0x08 3. "AON_RTC_4KHZ,AON_RTC:SUBSEC.VALUE bit" "0,1"
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bitfld.long 0x08 2. "AON_RTC_CH2_DLY,AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration" "0,1"
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bitfld.long 0x08 1. "AON_RTC_CH2,AON_RTC:EVFLAGS.CH2" "0,1"
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bitfld.long 0x08 0. "MANUAL_EV,Programmable event" "0,1"
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line.long 0x0C "EVSTAT3,Event Status 3Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 15. "AUX_TIMER2_CLKSWITCH_RDY,AUX_SYSIF:TIMER2CLKSWITCH.RDY" "0,1"
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bitfld.long 0x0C 14. "AUX_DAC_HOLD_ACTIVE,AUX_ANAIF:DACSTAT.HOLD_ACTIVE" "0,1"
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bitfld.long 0x0C 13. "AUX_SMPH_AUTOTAKE_DONE,See AUX_SMPH:AUTOTAKE.SMPH_ID for description" "0,1"
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bitfld.long 0x0C 12. "AUX_ADC_FIFO_NOT_EMPTY,AUX_ANAIF:ADCFIFOSTAT.EMPTY negated" "0,1"
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bitfld.long 0x0C 11. "AUX_ADC_FIFO_ALMOST_FULL,AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL" "0,1"
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bitfld.long 0x0C 10. "AUX_ADC_IRQ,The logical function for this event is configurable.When DMACTL.EN =" "0,1"
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bitfld.long 0x0C 9. "AUX_ADC_DONE,AUX_ANAIF ADC conversion done event" "0,1"
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bitfld.long 0x0C 8. "AUX_ISRC_RESET_N,AUX_ANAIF:ISRCCTL.RESET_N" "0,1"
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bitfld.long 0x0C 7. "AUX_TDC_DONE,AUX_TDC:STAT.DONE" "0,1"
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bitfld.long 0x0C 6. "AUX_TIMER0_EV,AUX_TIMER0_EV event see AUX_TIMER01:T0TARGET for description" "0,1"
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bitfld.long 0x0C 5. "AUX_TIMER1_EV,AUX_TIMER1_EV event see AUX_TIMER01:T1TARGET for description" "0,1"
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bitfld.long 0x0C 4. "AUX_TIMER2_PULSE,AUX_TIMER2 pulse event" "0,1"
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bitfld.long 0x0C 3. "AUX_TIMER2_EV3,AUX_TIMER2 event output 3" "0,1"
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bitfld.long 0x0C 2. "AUX_TIMER2_EV2,AUX_TIMER2 event output 2" "0,1"
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bitfld.long 0x0C 1. "AUX_TIMER2_EV1,AUX_TIMER2 event output 1" "0,1"
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bitfld.long 0x0C 0. "AUX_TIMER2_EV0,AUX_TIMER2 event output 0" "0,1"
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line.long 0x10 "SCEWEVCFG0,Sensor Controller Engine Wait Event Configuration 0Configuration of this register and SCEWEVCFG1 controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS"
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hexmask.long 0x10 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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bitfld.long 0x10 6. "COMB_EV_EN,Event combination control:0: Disable event combination.1: Enable event combination" "Disable event combination,Enable event combination"
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bitfld.long 0x10 0.--5. "EV0_SEL,Select the event source from the synchronous event bus to be used in event equation" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10 ,EVSTAT0.AUXIO11 ,EVSTAT0.AUXIO12 ,EVSTAT0.AUXIO13 ,EVSTAT0.AUXIO14 ,EVSTAT0.AUXIO15 ,EVSTAT1.AUXIO16 ,EVSTAT1.AUXIO17 ,EVSTAT1.AUXIO18 ,EVSTAT1.AUXIO19 ,EVSTAT1.AUXIO20 ,EVSTAT1.AUXIO21 ,EVSTAT1.AUXIO22 ,EVSTAT1.AUXIO23 ,EVSTAT1.AUXIO24 ,EVSTAT1.AUXIO25 ,EVSTAT1.AUXIO26 ,EVSTAT1.AUXIO27 ,EVSTAT1.AUXIO28 ,EVSTAT1.AUXIO29 ,EVSTAT1.AUXIO30 ,EVSTAT1.AUXIO31 ,Programmable delay event as described in PROGDLY,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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line.long 0x14 "SCEWEVCFG1,Sensor Controller Engine Wait Event Configuration 1See SCEWEVCFG0 for description"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 7. "EV0_POL,Polarity of SCEWEVCFG0.EV0_SEL event.When SCEWEVCFG0.COMB_EV_EN is" "Non-inverted,Inverted"
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newline
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bitfld.long 0x14 6. "EV1_POL,Polarity of EV1_SEL event.When SCEWEVCFG0.COMB_EV_EN is" "Non-inverted,Inverted"
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newline
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bitfld.long 0x14 0.--5. "EV1_SEL,Select the event source from the synchronous event bus to be used in event equation" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10 ,EVSTAT0.AUXIO11 ,EVSTAT0.AUXIO12 ,EVSTAT0.AUXIO13 ,EVSTAT0.AUXIO14 ,EVSTAT0.AUXIO15 ,EVSTAT1.AUXIO16 ,EVSTAT1.AUXIO17 ,EVSTAT1.AUXIO18 ,EVSTAT1.AUXIO19 ,EVSTAT1.AUXIO20 ,EVSTAT1.AUXIO21 ,EVSTAT1.AUXIO22 ,EVSTAT1.AUXIO23 ,EVSTAT1.AUXIO24 ,EVSTAT1.AUXIO25 ,EVSTAT1.AUXIO26 ,EVSTAT1.AUXIO27 ,EVSTAT1.AUXIO28 ,EVSTAT1.AUXIO29 ,EVSTAT1.AUXIO30 ,EVSTAT1.AUXIO31 ,Programmable delay event as described in PROGDLY,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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line.long 0x18 "DMACTL,Direct Memory Access Control"
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hexmask.long 0x18 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 2. "REQ_MODE,UDMA0 Request mode" "Burst requests are generated on UDMA0 channel 7..,Single requests are generated on UDMA0 channel 7.."
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newline
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bitfld.long 0x18 1. "EN,uDMA ADC interface enable.0: Disable UDMA0 interface to ADC.1: Enable UDMA0 interface to ADC" "Disable UDMA0 interface to ADC,Enable UDMA0 interface to ADC"
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newline
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bitfld.long 0x18 0. "SEL,Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data" "UDMA0 trigger event will be generated when there..,UDMA0 trigger event will be generated when the.."
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group.long 0x20++0x4B
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line.long 0x00 "SWEVSET,Software Event SetSet software event flags from AUX domain to AON and MCU domains"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 2. "SWEV2,Software event flag" "No effect,Set software event flag 2"
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newline
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bitfld.long 0x00 1. "SWEV1,Software event flag" "No effect,Set software event flag 1"
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newline
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bitfld.long 0x00 0. "SWEV0,Software event flag" "No effect,Set software event flag 0"
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line.long 0x04 "EVTOAONFLAGS,Events To AON FlagsThis register contains a collection of event flags routed to AON_EVENT"
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hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 8. "AUX_TIMER1_EV,This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV" "0,1"
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newline
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bitfld.long 0x04 7. "AUX_TIMER0_EV,This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV" "0,1"
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newline
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bitfld.long 0x04 6. "AUX_TDC_DONE,This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE" "0,1"
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newline
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bitfld.long 0x04 5. "AUX_ADC_DONE,This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE" "0,1"
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newline
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bitfld.long 0x04 4. "AUX_COMPB,This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB" "0,1"
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newline
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bitfld.long 0x04 3. "AUX_COMPA,This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA" "0,1"
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newline
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bitfld.long 0x04 2. "SWEV2,This event flag is set when software writes a 1 to SWEVSET.SWEV2" "0,1"
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newline
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bitfld.long 0x04 1. "SWEV1,This event flag is set when software writes a 1 to SWEVSET.SWEV1" "0,1"
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newline
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bitfld.long 0x04 0. "SWEV0,This event flag is set when software writes a 1 to SWEVSET.SWEV0" "0,1"
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line.long 0x08 "EVTOAONPOL,Events To AON PolarityEvent source polarity configuration for EVTOAONFLAGS"
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hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 8. "AUX_TIMER1_EV,Select the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV" "High level,Low level"
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newline
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bitfld.long 0x08 7. "AUX_TIMER0_EV,Select the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV" "High level,Low level"
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newline
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bitfld.long 0x08 6. "AUX_TDC_DONE,Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE" "High level,Low level"
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newline
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bitfld.long 0x08 5. "AUX_ADC_DONE,Select the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE" "High level,Low level"
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newline
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bitfld.long 0x08 4. "AUX_COMPB,Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB" "Rising edge,Falling edge"
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newline
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bitfld.long 0x08 3. "AUX_COMPA,Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA" "Rising edge,Falling edge"
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newline
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rbitfld.long 0x08 0.--2. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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line.long 0x0C "EVTOAONFLAGSCLR,Events To AON ClearClear event flags in EVTOAONFLAGS"
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hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 8. "AUX_TIMER1_EV,Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 7. "AUX_TIMER0_EV,Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 6. "AUX_TDC_DONE,Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 5. "AUX_ADC_DONE,Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 4. "AUX_COMPB,Write 1 to clear EVTOAONFLAGS.AUX_COMPB.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 3. "AUX_COMPA,Write 1 to clear EVTOAONFLAGS.AUX_COMPA.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 2. "SWEV2,Write 1 to clear EVTOAONFLAGS.SWEV2.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 1. "SWEV1,Write 1 to clear EVTOAONFLAGS.SWEV1.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 0. "SWEV0,Write 1 to clear EVTOAONFLAGS.SWEV0.Read value is 0" "0,1"
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line.long 0x10 "EVTOMCUFLAGS,Events to MCU FlagsThis register contains a collection of event flags routed to MCU domain"
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hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 15. "AUX_TIMER2_PULSE,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE occurs on EVSTAT3.AUX_TIMER2_PULSE" "0,1"
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newline
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bitfld.long 0x10 14. "AUX_TIMER2_EV3,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 occurs on EVSTAT3.AUX_TIMER2_EV3" "0,1"
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newline
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bitfld.long 0x10 13. "AUX_TIMER2_EV2,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 occurs on EVSTAT3.AUX_TIMER2_EV2" "0,1"
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newline
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bitfld.long 0x10 12. "AUX_TIMER2_EV1,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 occurs on EVSTAT3.AUX_TIMER2_EV1" "0,1"
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newline
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bitfld.long 0x10 11. "AUX_TIMER2_EV0,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 occurs on EVSTAT3.AUX_TIMER2_EV0" "0,1"
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newline
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bitfld.long 0x10 10. "AUX_ADC_IRQ,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ" "0,1"
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newline
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bitfld.long 0x10 9. "MCU_OBSMUX0,This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0" "0,1"
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newline
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bitfld.long 0x10 8. "AUX_ADC_FIFO_ALMOST_FULL,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL" "0,1"
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newline
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bitfld.long 0x10 7. "AUX_ADC_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE" "0,1"
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newline
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bitfld.long 0x10 6. "AUX_SMPH_AUTOTAKE_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE" "0,1"
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newline
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bitfld.long 0x10 5. "AUX_TIMER1_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV" "0,1"
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newline
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bitfld.long 0x10 4. "AUX_TIMER0_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV" "0,1"
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newline
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bitfld.long 0x10 3. "AUX_TDC_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE" "0,1"
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newline
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bitfld.long 0x10 2. "AUX_COMPB,This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB" "0,1"
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newline
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bitfld.long 0x10 1. "AUX_COMPA,This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA" "0,1"
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newline
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bitfld.long 0x10 0. "AUX_WU_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on reduction-OR of the AUX_SYSIF:WUFLAGS register" "0,1"
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line.long 0x14 "EVTOMCUPOL,Event To MCU PolarityEvent source polarity configuration for EVTOMCUFLAGS"
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hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 15. "AUX_TIMER2_PULSE,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE" "High level,Low level"
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newline
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bitfld.long 0x14 14. "AUX_TIMER2_EV3,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3" "High level,Low level"
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newline
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bitfld.long 0x14 13. "AUX_TIMER2_EV2,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2" "High level,Low level"
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newline
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bitfld.long 0x14 12. "AUX_TIMER2_EV1,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1" "High level,Low level"
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newline
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bitfld.long 0x14 11. "AUX_TIMER2_EV0,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0" "High level,Low level"
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newline
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bitfld.long 0x14 10. "AUX_ADC_IRQ,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ" "High level,Low level"
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newline
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bitfld.long 0x14 9. "MCU_OBSMUX0,Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0" "High level,Low level"
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newline
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bitfld.long 0x14 8. "AUX_ADC_FIFO_ALMOST_FULL,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL" "High level,Low level"
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newline
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bitfld.long 0x14 7. "AUX_ADC_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE" "High level,Low level"
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newline
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bitfld.long 0x14 6. "AUX_SMPH_AUTOTAKE_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE" "High level,Low level"
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newline
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bitfld.long 0x14 5. "AUX_TIMER1_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV" "High level,Low level"
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newline
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bitfld.long 0x14 4. "AUX_TIMER0_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV" "High level,Low level"
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newline
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bitfld.long 0x14 3. "AUX_TDC_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE" "High level,Low level"
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newline
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bitfld.long 0x14 2. "AUX_COMPB,Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB" "Rising edge,Falling edge"
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newline
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bitfld.long 0x14 1. "AUX_COMPA,Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA" "Rising edge,Falling edge"
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newline
|
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bitfld.long 0x14 0. "AUX_WU_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV" "High level,Low level"
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line.long 0x18 "EVTOMCUFLAGSCLR,Events To MCU Flags ClearClear event flags in EVTOMCUFLAGS"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x18 15. "AUX_TIMER2_PULSE,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 14. "AUX_TIMER2_EV3,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 13. "AUX_TIMER2_EV2,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 12. "AUX_TIMER2_EV1,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 11. "AUX_TIMER2_EV0,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 10. "AUX_ADC_IRQ,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x18 9. "MCU_OBSMUX0,Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 8. "AUX_ADC_FIFO_ALMOST_FULL,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 7. "AUX_ADC_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x18 6. "AUX_SMPH_AUTOTAKE_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 5. "AUX_TIMER1_EV,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 4. "AUX_TIMER0_EV,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 3. "AUX_TDC_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE.Read value is 0" "0,1"
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newline
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bitfld.long 0x18 2. "AUX_COMPB,Write 1 to clear EVTOMCUFLAGS.AUX_COMPB.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x18 1. "AUX_COMPA,Write 1 to clear EVTOMCUFLAGS.AUX_COMPA.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x18 0. "AUX_WU_EV,Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV.Read value is 0" "0,1"
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line.long 0x1C "COMBEVTOMCUMASK,Combined Event To MCU MaskSelect event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU.The AUX_COMB event is high as long as one or more of the included event flags are set"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x1C 15. "AUX_TIMER2_PULSE,EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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newline
|
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bitfld.long 0x1C 14. "AUX_TIMER2_EV3,EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
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bitfld.long 0x1C 13. "AUX_TIMER2_EV2,EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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newline
|
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bitfld.long 0x1C 12. "AUX_TIMER2_EV1,EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
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bitfld.long 0x1C 11. "AUX_TIMER2_EV0,EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
|
bitfld.long 0x1C 10. "AUX_ADC_IRQ,EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
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bitfld.long 0x1C 9. "MCU_OBSMUX0,EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
|
bitfld.long 0x1C 8. "AUX_ADC_FIFO_ALMOST_FULL,EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
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bitfld.long 0x1C 7. "AUX_ADC_DONE,EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
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bitfld.long 0x1C 6. "AUX_SMPH_AUTOTAKE_DONE,EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
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bitfld.long 0x1C 5. "AUX_TIMER1_EV,EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
|
bitfld.long 0x1C 4. "AUX_TIMER0_EV,EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 3. "AUX_TDC_DONE,EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 2. "AUX_COMPB,EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event.0: Exclude1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 1. "AUX_COMPA,EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 0. "AUX_WU_EV,EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
line.long 0x20 "EVOBSCFG,Event Observation Configuration"
|
|
hexmask.long 0x20 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--5. "EVOBS_SEL,Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIOn" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10,EVSTAT0.AUXIO11,EVSTAT0.AUXIO12,EVSTAT0.AUXIO13,EVSTAT0.AUXIO14,EVSTAT0.AUXIO15,EVSTAT1.AUXIO16,EVSTAT1.AUXIO17,EVSTAT1.AUXIO18,EVSTAT1.AUXIO19,EVSTAT1.AUXIO20,EVSTAT1.AUXIO21,EVSTAT1.AUXIO22,EVSTAT1.AUXIO23,EVSTAT1.AUXIO24,EVSTAT1.AUXIO25,EVSTAT1.AUXIO26,EVSTAT1.AUXIO27,EVSTAT1.AUXIO28,EVSTAT1.AUXIO29,EVSTAT1.AUXIO30,EVSTAT1.AUXIO31,EVSTAT2.MANUAL_EV,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
|
|
line.long 0x24 "PROGDLY,Programmable Delay"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "VALUE,VALUE decrements to 0 at a rate of 1 MHz.The event AUX_PROG_DLY_IDLE is high when VALUE is 0 otherwise it is low"
|
|
line.long 0x28 "MANUAL,ManualProgrammable event"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0. "EV,This bit field sets the value of EVSTAT2.MANUAL_EV" "0,1"
|
|
line.long 0x2C "EVSTAT0L,Event Status 0 Low"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "ALIAS_EV,Alias of EVSTAT0 event 7 down to 0"
|
|
line.long 0x30 "EVSTAT0H,Event Status 0 High"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "ALIAS_EV,Alias of EVSTAT0 event 15 down to 8"
|
|
line.long 0x34 "EVSTAT1L,Event Status 1 Low"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "ALIAS_EV,Alias of EVSTAT1 event 7 down to 0"
|
|
line.long 0x38 "EVSTAT1H,Event Status 1 High"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "ALIAS_EV,Alias of EVSTAT1 event 15 down to 8"
|
|
line.long 0x3C "EVSTAT2L,Event Status 2 Low"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "ALIAS_EV,Alias of EVSTAT2 event 7 down to 0"
|
|
line.long 0x40 "EVSTAT2H,Event Status 2 High"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "ALIAS_EV,Alias of EVSTAT2 event 15 down to 8"
|
|
line.long 0x44 "EVSTAT3L,Event Status 3 Low"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "ALIAS_EV,Alias of EVSTAT3 event 7 down to 0"
|
|
line.long 0x48 "EVSTAT3H,Event Status 3 High"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "ALIAS_EV,Alias of EVSTAT3 event 15 down to 8"
|
|
tree.end
|
|
tree "AUX_SCE"
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|
base ad:0x400E1000
|
|
group.long 0x00++0x27
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|
line.long 0x00 "CTL,Internal"
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|
hexmask.long.byte 0x00 24.--31. 1. "FORCE_EV_LOW,Internal"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FORCE_EV_HIGH,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESET_VECTOR,Internal"
|
|
rbitfld.long 0x00 7. "RESERVED7,Internal" "0,1"
|
|
newline
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|
bitfld.long 0x00 6. "DBG_FREEZE_EN,Internal" "0,1"
|
|
bitfld.long 0x00 5. "FORCE_WU_LOW,Internal" "0,1"
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|
newline
|
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bitfld.long 0x00 4. "FORCE_WU_HIGH,Internal" "0,1"
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|
bitfld.long 0x00 3. "RESTART,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SINGLE_STEP,Internal" "0,1"
|
|
bitfld.long 0x00 1. "SUSPEND,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CLK_EN,Internal" "0,1"
|
|
line.long 0x04 "FETCHSTAT,Internal"
|
|
hexmask.long.word 0x04 16.--31. 1. "OPCODE,Internal"
|
|
hexmask.long.word 0x04 0.--15. 1. "PC,Internal"
|
|
line.long 0x08 "CPUSTAT,Internal"
|
|
hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED12,Internal"
|
|
bitfld.long 0x08 11. "BUS_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. "SLEEP,Internal" "0,1"
|
|
bitfld.long 0x08 9. "WEV,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "HALTED,Internal" "0,1"
|
|
bitfld.long 0x08 4.--7. "RESERVED4,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 3. "V_FLAG,Internal" "0,1"
|
|
bitfld.long 0x08 2. "C_FLAG,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "N_FLAG,Internal" "0,1"
|
|
bitfld.long 0x08 0. "Z_FLAG,Internal" "0,1"
|
|
line.long 0x0C "WUSTAT,Internal"
|
|
hexmask.long.word 0x0C 19.--31. 1. "RESERVED20,Internal"
|
|
bitfld.long 0x0C 16.--18. "EXC_VECTOR,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0C 9.--15. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x0C 8. "WU_SIGNAL,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV_SIGNALS,Internal"
|
|
line.long 0x10 "REG1_0,Internal"
|
|
hexmask.long.word 0x10 16.--31. 1. "REG1,Internal"
|
|
hexmask.long.word 0x10 0.--15. 1. "REG0,Internal"
|
|
line.long 0x14 "REG3_2,Internal"
|
|
hexmask.long.word 0x14 16.--31. 1. "REG3,Internal"
|
|
hexmask.long.word 0x14 0.--15. 1. "REG2,Internal"
|
|
line.long 0x18 "REG5_4,Internal"
|
|
hexmask.long.word 0x18 16.--31. 1. "REG5,Internal"
|
|
hexmask.long.word 0x18 0.--15. 1. "REG4,Internal"
|
|
line.long 0x1C "REG7_6,Internal"
|
|
hexmask.long.word 0x1C 16.--31. 1. "REG7,Internal"
|
|
hexmask.long.word 0x1C 0.--15. 1. "REG6,Internal"
|
|
line.long 0x20 "LOOPADDR,Internal"
|
|
hexmask.long.word 0x20 16.--31. 1. "STOP,Internal"
|
|
hexmask.long.word 0x20 0.--15. 1. "START,Internal"
|
|
line.long 0x24 "LOOPCNT,Internal"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED8,Internal"
|
|
hexmask.long.byte 0x24 0.--7. 1. "ITER_LEFT,Internal"
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "NONSECDDIACC$1,Non-Secure DDI Access 0When system is in secure state. AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED23,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 22. "RD_EN,Read Enable0: AUX_SCE is not allowed to read DDI half-word given by ADDR.1: AUX_SCE is allowed to read DDI half-word given by ADDR." "AUX_SCE is not allowed to read DDI half-word..,AUX_SCE is allowed to read DDI half-word given.."
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|
newline
|
|
bitfld.long 0x00 16.--21. "ADDR,AddressAUX_SCE is allowed to update this DDI half-word using SET or CLR access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
hexmask.long.word 0x00 0.--15. 1. "WR_MASK,MaskAUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask"
|
|
repeat.end
|
|
tree.end
|
|
tree "AUX_SMPH"
|
|
base ad:0x400C8000
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SMPH$1,Semaphore 0"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Request or release of semaphore.Request by read:0: Semaphore not available.1: Semaphore granted.Release by write:0: Do not use.1: Release semaphore" "Do not use,Release semaphore"
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|
repeat.end
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AUTOTAKE,Auto TakeSticky Request for Single Semaphore"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--2. "SMPH_ID,Write the semaphore ID 0x0-0x7 to SMPH_ID to request this semaphore until it is granted" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "AUX_TDCIF"
|
|
base ad:0x400C4000
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CTL,Control"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CMD,TDC commands" "Clear STAT.SAT STAT.DONE and RESULT.VALUE..,Synchronous counter start.The counter looks..,Asynchronous counter start.The counter starts..,Force TDC state machine back to IDLE.."
|
|
line.long 0x04 "STAT,Status"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 7. "SAT,TDC measurement saturation flag.0: Conversion has not saturated.1: Conversion stopped due to saturation.This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD" "Conversion has not saturated,Conversion stopped due to saturation.This field.."
|
|
newline
|
|
bitfld.long 0x04 6. "DONE,TDC measurement complete flag.0: TDC measurement has not yet completed.1: TDC measurement has completed.This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD" "TDC measurement has not yet completed,TDC measurement has completed.This field clears.."
|
|
newline
|
|
bitfld.long 0x04 0.--5. "STATE,TDC state machine status" "Current state is TDC_STATE_WAIT_START. The..,?,?,?,Current state is..,?,Current state is TDC_STATE_IDLE. This is the..,Current state is TDC_STATE_CLRCNT. The..,Current state is TDC_STATE_WAIT_STOP.The state..,?,?,?,Current state is TDC_STATE_WAIT_STOPCNTDOWN.The..,?,Current state is TDC_STATE_GETRESULTS.The state..,Current state is TDC_STATE_POR. This is the..,?,?,?,?,?,?,Current state is TDC_STATE_WAIT_CLRCNT_DONE..,?,?,?,?,?,?,?,Current state is TDC_WAIT_STARTFALL. The..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Current state is TDC_FORCESTOP.You wrote ABORT..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
line.long 0x08 "RESULT,ResultResult of last TDC conversion"
|
|
hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long 0x08 0.--24. 1. "VALUE,TDC conversion result.The result of the TDC conversion is given in number of clock edges of the clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL"
|
|
line.long 0x0C "SATCFG,Saturation Configuration"
|
|
hexmask.long 0x0C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "LIMIT,Saturation limit.The flag STAT.SAT is set when the TDC counter saturates.Values not enumerated are not supported" "?,?,?,Result bit 12: TDC conversion saturates and..,Result bit 13: TDC conversion saturates and..,Result bit 14: TDC conversion saturates and..,Result bit 15: TDC conversion saturates and..,Result bit 16: TDC conversion saturates and..,Result bit 17: TDC conversion saturates and..,Result bit 18: TDC conversion saturates and..,Result bit 19: TDC conversion saturates and..,Result bit 20: TDC conversion saturates and..,Result bit 21: TDC conversion saturates and..,Result bit 22: TDC conversion saturates and..,Result bit 23: TDC conversion saturates and..,Result bit 24: TDC conversion saturates and.."
|
|
line.long 0x10 "TRIGSRC,Trigger SourceSelect source and polarity for TDC start and stop events"
|
|
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 13. "STOP_POL,Polarity of stop source.Change only while STAT.STATE is IDLE" "TDC conversion stops when high level is detected.,TDC conversion stops when low level is detected."
|
|
newline
|
|
bitfld.long 0x10 8.--12. "STOP_SRC,Select stop source from the asynchronous AUX event bus.Change only while STAT.STATE is IDLE" "AUX_EVCTL:EVSTAT0.AON_RTC_CH2,AUX_EVCTL:EVSTAT0.AUX_COMPA,AUX_EVCTL:EVSTAT0.AUX_COMPB,AUX_ANAIF:ISRCCTL.RESET_N,AUX_EVCTL:EVSTAT0.TIMER0_EV,AUX_EVCTL:EVSTAT0.TIMER1_EV,AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE,AUX_EVCTL:EVSTAT0.ADC_DONE,AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL,AUX_EVCTL:EVSTAT0.OBSMUX0,AUX_EVCTL:EVSTAT0.OBSMUX1,AUX_EVCTL:EVSTAT0.AON_SW,AUX_EVCTL:EVSTAT0.AON_PROG_WU,AUX_EVCTL:EVSTAT0.AUXIO0,AUX_EVCTL:EVSTAT0.AUXIO1,AUX_EVCTL:EVSTAT0.AUXIO2,AUX_EVCTL:EVSTAT1.AUXIO3 ,AUX_EVCTL:EVSTAT1.AUXIO4 ,AUX_EVCTL:EVSTAT1.AUXIO5 ,AUX_EVCTL:EVSTAT1.AUXIO6 ,AUX_EVCTL:EVSTAT1.AUXIO7 ,AUX_EVCTL:EVSTAT1.AUXIO8 ,AUX_EVCTL:EVSTAT1.AUXIO9 ,AUX_EVCTL:EVSTAT1.AUXIO10,AUX_EVCTL:EVSTAT1.AUXIO11,AUX_EVCTL:EVSTAT1.AUXIO12 ,AUX_EVCTL:EVSTAT1.AUXIO13 ,AUX_EVCTL:EVSTAT1.AUXIO14 ,AUX_EVCTL:EVSTAT1.AUXIO15,AUX_EVCTL:EVSTAT1.ACLK_REF,AUX_EVCTL:EVSTAT1.MCU_EV,Select TDC Prescaler event which is generated by.."
|
|
newline
|
|
rbitfld.long 0x10 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 5. "START_POL,Polarity of start source.Change only while STAT.STATE is IDLE" "TDC conversion starts when high level is detected.,TDC conversion starts when low level is detected."
|
|
newline
|
|
bitfld.long 0x10 0.--4. "START_SRC,Select start source from the asynchronous AUX event bus.Change only while STAT.STATE is IDLE" "AUX_EVCTL:EVSTAT0.AON_RTC_CH2,AUX_EVCTL:EVSTAT0.AUX_COMPA,AUX_EVCTL:EVSTAT0.AUX_COMPB,AUX_ANAIF:ISRCCTL.RESET_N,AUX_EVCTL:EVSTAT0.TIMER0_EV,AUX_EVCTL:EVSTAT0.TIMER1_EV,AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE,AUX_EVCTL:EVSTAT0.ADC_DONE,AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL,AUX_EVCTL:EVSTAT0.OBSMUX0,AUX_EVCTL:EVSTAT0.OBSMUX1,AUX_EVCTL:EVSTAT0.AON_SW,AUX_EVCTL:EVSTAT0.AON_PROG_WU,AUX_EVCTL:EVSTAT0.AUXIO0,AUX_EVCTL:EVSTAT0.AUXIO1,AUX_EVCTL:EVSTAT0.AUXIO2,AUX_EVCTL:EVSTAT1.AUXIO3 ,AUX_EVCTL:EVSTAT1.AUXIO4 ,AUX_EVCTL:EVSTAT1.AUXIO5 ,AUX_EVCTL:EVSTAT1.AUXIO6 ,AUX_EVCTL:EVSTAT1.AUXIO7 ,AUX_EVCTL:EVSTAT1.AUXIO8 ,AUX_EVCTL:EVSTAT1.AUXIO9 ,AUX_EVCTL:EVSTAT1.AUXIO10,AUX_EVCTL:EVSTAT1.AUXIO11,AUX_EVCTL:EVSTAT1.AUXIO12 ,AUX_EVCTL:EVSTAT1.AUXIO13 ,AUX_EVCTL:EVSTAT1.AUXIO14 ,AUX_EVCTL:EVSTAT1.AUXIO15,AUX_EVCTL:EVSTAT1.ACLK_REF,AUX_EVCTL:EVSTAT1.MCU_EV,Select TDC Prescaler event which is generated by.."
|
|
line.long 0x14 "TRIGCNT,Trigger CounterStop-counter control and status"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.Read CNT to get the remaining number of stop events to ignore during a TDC measurement"
|
|
line.long 0x18 "TRIGCNTLOAD,Trigger Counter LoadStop-counter load"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "CNT,Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.To measure frequency of an event source: - Set start event equal to stop event.- Set CNT to number of periods to measure"
|
|
line.long 0x1C "TRIGCNTCFG,Trigger Counter ConfigurationStop-counter configuration"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0. "EN,Enable stop-counter.0: Disable stop-counter.1: Enable stop-counter.Change only while STAT.STATE is IDLE" "Disable stop-counter,Enable stop-counter.Change only while STAT.STATE.."
|
|
line.long 0x20 "PRECTL,Prescaler ControlThe prescaler can be used to count events that are faster than the AUX clock frequency"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 7. "RESET_N,Prescaler reset.0: Reset prescaler.1: Release reset of prescaler.AUX_TDC_PRE event becomes 0 when you reset the prescaler" "Reset prescaler,Release reset of prescaler.AUX_TDC_PRE.."
|
|
newline
|
|
bitfld.long 0x20 6. "RATIO,Prescaler ratio" "Prescaler divides input by 16. AUX_TDC_PRE..,Prescaler divides input by 64. AUX_TDC_PRE.."
|
|
newline
|
|
rbitfld.long 0x20 5. "RESERVED5,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0.--4. "SRC,Prescaler event source" "AUX_EVCTL:EVSTAT0.AON_RTC_CH2,AUX_EVCTL:EVSTAT0.AUX_COMPA,AUX_EVCTL:EVSTAT0.AUX_COMPB,AUX_ANAIF:ISRCCTL.RESET_N,AUX_EVCTL:EVSTAT0.TIMER0_EV,AUX_EVCTL:EVSTAT0.TIMER1_EV,AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE,AUX_EVCTL:EVSTAT0.ADC_DONE,AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL,AUX_EVCTL:EVSTAT0.OBSMUX0,AUX_EVCTL:EVSTAT0.OBSMUX1,AUX_EVCTL:EVSTAT0.AON_SW,AUX_EVCTL:EVSTAT0.AON_PROG_WU,AUX_EVCTL:EVSTAT0.AUXIO0,AUX_EVCTL:EVSTAT0.AUXIO1,AUX_EVCTL:EVSTAT0.AUXIO2,AUX_EVCTL:EVSTAT1.AUXIO3 ,AUX_EVCTL:EVSTAT1.AUXIO4 ,AUX_EVCTL:EVSTAT1.AUXIO5 ,AUX_EVCTL:EVSTAT1.AUXIO6 ,AUX_EVCTL:EVSTAT1.AUXIO7 ,AUX_EVCTL:EVSTAT1.AUXIO8 ,AUX_EVCTL:EVSTAT1.AUXIO9 ,AUX_EVCTL:EVSTAT1.AUXIO10,AUX_EVCTL:EVSTAT1.AUXIO11,AUX_EVCTL:EVSTAT1.AUXIO12 ,AUX_EVCTL:EVSTAT1.AUXIO13 ,AUX_EVCTL:EVSTAT1.AUXIO14 ,AUX_EVCTL:EVSTAT1.AUXIO15,AUX_EVCTL:EVSTAT1.ACLK_REF,AUX_EVCTL:EVSTAT1.MCU_EV,AUX_EVCTL:EVSTAT1.ADC_IRQ"
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line.long 0x24 "PRECNT,Prescaler Counter"
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x24 0.--15. 1. "CNT,Prescaler counter value.Write a value to CNT to capture the value of the 16-bit prescaler counter into CNT"
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tree.end
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tree "AUX_TIMER"
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base ad:0x400C7000
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group.long 0x00++0x17
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line.long 0x00 "T0CFG,Timer 0 Configuration"
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hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 13. "TICK_SRC_POL,Tick source polarity for Timer 0" "Count on rising edges of TICK_SRC.,Count on falling edges of TICK_SRC."
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newline
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bitfld.long 0x00 8.--12. "TICK_SRC,Select Timer 0 tick source from the synchronous event bus" "AUX_EVCTL:EVSTAT0.AON_RTC_CH2,AUX_EVCTL:EVSTAT0.AUX_COMPA,AUX_EVCTL:EVSTAT0.AUX_COMPB,AUX_EVCTL:EVSTAT0.TDC_DONE,?,AUX_EVCTL:EVSTAT0.TIMER1_EV,AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE,AUX_EVCTL:EVSTAT0.ADC_DONE,AON_RTC:SUBSEC.VALUE bit 19..,AUX_EVCTL:EVSTAT0.OBSMUX0,AUX_EVCTL:EVSTAT0.OBSMUX1,AUX_EVCTL:EVSTAT0.AON_SW,AUX_EVCTL:EVSTAT0.AON_PROG_WU,AUX_EVCTL:EVSTAT0.AUXIO0,AUX_EVCTL:EVSTAT0.AUXIO1,AUX_EVCTL:EVSTAT0.AUXIO2,AUX_EVCTL:EVSTAT1.AUXIO3 ,AUX_EVCTL:EVSTAT1.AUXIO4 ,AUX_EVCTL:EVSTAT1.AUXIO5 ,AUX_EVCTL:EVSTAT1.AUXIO6 ,AUX_EVCTL:EVSTAT1.AUXIO7 ,AUX_EVCTL:EVSTAT1.AUXIO8 ,AUX_EVCTL:EVSTAT1.AUXIO9 ,AUX_EVCTL:EVSTAT1.AUXIO10,AUX_EVCTL:EVSTAT1.AUXIO11,AUX_EVCTL:EVSTAT1.AUXIO12 ,AUX_EVCTL:EVSTAT1.AUXIO13 ,AUX_EVCTL:EVSTAT1.AUXIO14 ,AUX_EVCTL:EVSTAT1.AUXIO15,AUX_EVCTL:EVSTAT1.ACLK_REF,AUX_EVCTL:EVSTAT1.MCU_EV,AUX_EVCTL:EVSTAT1.ADC_IRQ"
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newline
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bitfld.long 0x00 4.--7. "PRE,Prescaler division ratio is" "Divide by 1,Divide by 2,Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 32 768"
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newline
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rbitfld.long 0x00 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 1. "MODE,Timer 0 mode.Configure source for Timer 0 prescaler" "Use AUX clock as source for prescaler.,Use event set by TICK_SRC as source for.."
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newline
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bitfld.long 0x00 0. "RELOAD,Timer 0 reload mode" "Manual mode.Timer 0 stops and T0CTL.EN becomes..,Continuous mode.Timer 0 restarts when the.."
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line.long 0x04 "T1CFG,Timer 1 Configuration"
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hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 13. "TICK_SRC_POL,Tick source polarity for Timer 1" "Count on rising edges of TICK_SRC.,Count on falling edges of TICK_SRC."
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newline
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bitfld.long 0x04 8.--12. "TICK_SRC,Select Timer 1 tick source from the synchronous event bus" "AUX_EVCTL:EVSTAT0.AON_RTC_CH2,AUX_EVCTL:EVSTAT0.AUX_COMPA,AUX_EVCTL:EVSTAT0.AUX_COMPB,AUX_EVCTL:EVSTAT0.TDC_DONE,AUX_EVCTL:EVSTAT0.TIMER0_EV,?,AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE,AUX_EVCTL:EVSTAT0.ADC_DONE,AON_RTC:SUBSEC.VALUE bit 19..,AUX_EVCTL:EVSTAT0.OBSMUX0,AUX_EVCTL:EVSTAT0.OBSMUX1,AUX_EVCTL:EVSTAT0.AON_SW,AUX_EVCTL:EVSTAT0.AON_PROG_WU,AUX_EVCTL:EVSTAT0.AUXIO0,AUX_EVCTL:EVSTAT0.AUXIO1,AUX_EVCTL:EVSTAT0.AUXIO2,AUX_EVCTL:EVSTAT1.AUXIO3 ,AUX_EVCTL:EVSTAT1.AUXIO4 ,AUX_EVCTL:EVSTAT1.AUXIO5 ,AUX_EVCTL:EVSTAT1.AUXIO6 ,AUX_EVCTL:EVSTAT1.AUXIO7 ,AUX_EVCTL:EVSTAT1.AUXIO8 ,AUX_EVCTL:EVSTAT1.AUXIO9 ,AUX_EVCTL:EVSTAT1.AUXIO10,AUX_EVCTL:EVSTAT1.AUXIO11,AUX_EVCTL:EVSTAT1.AUXIO12 ,AUX_EVCTL:EVSTAT1.AUXIO13 ,AUX_EVCTL:EVSTAT1.AUXIO14 ,AUX_EVCTL:EVSTAT1.AUXIO15,AUX_EVCTL:EVSTAT1.ACLK_REF,AUX_EVCTL:EVSTAT1.MCU_EV,AUX_EVCTL:EVSTAT1.ADC_IRQ"
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newline
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bitfld.long 0x04 4.--7. "PRE,Prescaler division ratio is" "Divide by 1,Divide by 2,Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 32 768"
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newline
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rbitfld.long 0x04 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x04 1. "MODE,Timer 1 mode.Configure source for Timer 1 prescaler" "Use AUX clock as source for prescaler.,Use event set by TICK_SRC as source for.."
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newline
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bitfld.long 0x04 0. "RELOAD,Timer 1 reload mode" "Manual mode.Timer 1 stops and T1CTL.EN becomes..,Continuous mode.Timer 1 restarts when the.."
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line.long 0x08 "T0CTL,Timer 0 Control"
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hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 0. "EN,Timer 0 enable.0: Disable Timer" "Disable Timer 0,Enable Timer 0.The counter restarts from 0.."
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line.long 0x0C "T0TARGET,Timer 0 Target"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "VALUE,Timer 0 target value.Manual Reload Mode:- Timer 0 increments until the counter value becomes equal to or greater than VALUE"
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line.long 0x10 "T1TARGET,Timer 1 TargetTimer 1 counter target value"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "VALUE,Timer 1 target value.Manual Reload Mode:- Timer 1 increments until the counter value becomes equal to or greater than VALUE"
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line.long 0x14 "T1CTL,Timer 1 Control"
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hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 0. "EN,Timer 1 enable.0: Disable Timer" "Disable Timer 1,Enable Timer 1.The counter restarts from 0.."
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tree.end
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tree "AUX_WUC"
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base ad:0x400C6000
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group.long 0x00++0x17
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line.long 0x00 "MODCLKEN0,Module Clock EnableClock enable for each module in the AUX domainFor use by the system CPUThe settings in this register are OR'ed with the corresponding settings in MODCLKEN1"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x00 7. "AUX_ADI4,Enables (1) or disables (0) clock for AUX_ADI4." "System CPU has not requested clock for AUX_ADI4,System CPU has requested clock for AUX_ADI4"
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newline
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bitfld.long 0x00 6. "AUX_DDI0_OSC,Enables (1) or disables (0) clock for AUX_DDI0_OSC." "System CPU has not requested clock for..,System CPU has requested clock for AUX_DDI0_OSC"
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bitfld.long 0x00 5. "TDC,Enables (1) or disables (0) clock for AUX_TDCIF" "System CPU has not requested clock for TDC,System CPU has requested clock for TDC"
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newline
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bitfld.long 0x00 4. "ANAIF,Enables (1) or disables (0) clock for AUX_ANAIF.Note that the ADC internal clock must be requested separately using ADCCLKCTL" "System CPU has not requested clock for ANAIF,System CPU has requested clock for ANAIF"
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bitfld.long 0x00 3. "TIMER,Enables (1) or disables (0) clock for AUX_TIMER" "System CPU has not requested clock for TIMER,System CPU has requested clock for TIMER"
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newline
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bitfld.long 0x00 2. "AIODIO1,Enables (1) or disables (0) clock for AUX_AIODIO1" "System CPU has not requested clock for AIODIO1,System CPU has requested clock for AIODIO1"
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bitfld.long 0x00 1. "AIODIO0,Enables (1) or disables (0) clock for AUX_AIODIO0" "System CPU has not requested clock for AIODIO0,System CPU has requested clock for AIODIO0"
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newline
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bitfld.long 0x00 0. "SMPH,Enables (1) or disables (0) clock for AUX_SMPH" "System CPU has not requested clock for SMPH,System CPU has requested clock for SMPH"
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line.long 0x04 "PWROFFREQ,Power Off RequestRequests power off request for the AUX domain"
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hexmask.long 0x04 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x04 0. "REQ,Power off request0: No action1: Request to power down AUX" "No action,Request to power down AUX"
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line.long 0x08 "PWRDWNREQ,Power Down RequestRequest from AUX for system to enter power down"
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hexmask.long 0x08 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x08 0. "REQ,Power down request0: Request for system to be in active mode1: Request for system to be in power down modeWhen REQ is 1 one shall assume that the system is in power down and that current supply is limited" "Request for system to be in active mode,Request for system to be in power down modeWhen.."
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line.long 0x0C "PWRDWNACK,Power Down Acknowledgment"
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hexmask.long 0x0C 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 0. "ACK,Power down acknowledgment" "AUX can assume that the system is in active mode,The request for power down is acknowledged and.."
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line.long 0x10 "CLKLFREQ,Low Frequency Clock Request"
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hexmask.long 0x10 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x10 0. "REQ,Low frequency request" "Request clock frequency to be controlled by..,Request low frequency clock SCLK_LF as the clock.."
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line.long 0x14 "CLKLFACK,Low Frequency Clock Acknowledgment"
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hexmask.long 0x14 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x14 0. "ACK,Acknowledgment of CLKLFREQ.REQ0: Acknowledgement that clock frequency is controlled by AON_WUC:AUXCLK and the system state1: Acknowledgement that the low frequency clock SCLK_LF is the clock source for AUX" "Acknowledgement that clock frequency is..,Acknowledgement that the low frequency clock.."
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rgroup.long 0x28++0x2F
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line.long 0x00 "WUEVFLAGS,Wake-up Event FlagsStatus of wake-up events from the AON domainThe event flags are cleared by setting the corresponding bits in WUEVCLR"
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hexmask.long 0x00 3.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x00 2. "AON_RTC_CH2,Indicates pending event from AON_RTC_CH2 compare" "0,1"
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newline
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bitfld.long 0x00 1. "AON_SW,Indicates pending event triggered by system CPU writing a 1 to AON_WUC:AUXCTL.SWEV." "0,1"
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bitfld.long 0x00 0. "AON_PROG_WU,Indicates pending event triggered by the sources selected in AON_EVENT:AUXWUSEL.WU0_EV AON_EVENT:AUXWUSEL.WU1_EV and AON_EVENT:AUXWUSEL.WU2_EV." "0,1"
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line.long 0x04 "WUEVCLR,Wake-up Event ClearClears wake-up events from the AON domain"
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hexmask.long 0x04 3.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x04 2. "AON_RTC_CH2,Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event" "0,1"
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newline
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bitfld.long 0x04 1. "AON_SW,Set to clear the WUEVFLAGS.AON_SW wake-up event" "0,1"
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bitfld.long 0x04 0. "AON_PROG_WU,Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event" "0,1"
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line.long 0x08 "ADCCLKCTL,ADC Clock ControlControls the ADC internal clockNote that the ADC command and data interface requires MODCLKEN0.ANAIF or MODCLKEN1.ANAIF also to be set"
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hexmask.long 0x08 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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rbitfld.long 0x08 1. "ACK,Acknowledges the last value written to REQ." "0,1"
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newline
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bitfld.long 0x08 0. "REQ,Enables(1) or disables (0) the ADC internal clock.This bit must not be modified unless ACK matches the current value." "0,1"
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line.long 0x0C "TDCCLKCTL,TDC Clock ControlControls the TDC counter clock source. which steps the TDC counter valueThe source of this clock is controlled by OSC_DIG:CTL0.ACLK_TDC_SRC_SEL."
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hexmask.long 0x0C 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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rbitfld.long 0x0C 1. "ACK,Acknowledges the last value written to REQ" "0,1"
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newline
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bitfld.long 0x0C 0. "REQ,Enables(1) or disables (0) the TDC counter clock source.This bit must not be modified unless ACK matches the current value" "0,1"
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line.long 0x10 "REFCLKCTL,Reference Clock ControlControls the TDC reference clock source. which is to be compared against the TDC counter clock"
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hexmask.long 0x10 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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rbitfld.long 0x10 1. "ACK,Acknowledges the last value written to REQ" "0,1"
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newline
|
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bitfld.long 0x10 0. "REQ,Enables(1) or disables (0) the TDC reference clock source.This bit must not be modified unless ACK matches the current value" "0,1"
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line.long 0x14 "RTCSUBSECINC0,Real Time Counter Sub Second Increment 0New value for the real-time counter (AON_RTC) sub-second increment value. part corresponding to AON_RTC:SUBSECINC bits 15:0.After setting INC15_0 and RTCSUBSECINC1.INC23_16. the value is loaded into.."
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hexmask.long.word 0x14 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
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hexmask.long.word 0x14 0.--15. 1. "INC15_0,Bits 15:0 of the RTC sub-second increment value"
|
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line.long 0x18 "RTCSUBSECINC1,Real Time Counter Sub Second Increment 1New value for the real-time counter (AON_RTC) sub-second increment value. part corresponding to AON_RTC:SUBSECINC bits 23:16.After setting RTCSUBSECINC0.INC15_0 and INC23_16. the value is loaded into.."
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hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
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hexmask.long.byte 0x18 0.--7. 1. "INC23_16,Bits 23:16 of the RTC sub-second increment value"
|
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line.long 0x1C "RTCSUBSECINCCTL,Real Time Counter Sub Second Increment Control"
|
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hexmask.long 0x1C 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x1C 1. "UPD_ACK,Acknowledgment of the UPD_REQ." "0,1"
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newline
|
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bitfld.long 0x1C 0. "UPD_REQ,Signal that a new real time counter sub second increment value is available0: New sub second increment is not available1: New sub second increment is availableThis bit must not be modified unless UPD_ACK matches the current value" "New sub second increment is not available,New sub second increment is availableThis bit.."
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|
line.long 0x20 "MCUBUSCTL,MCU Bus ControlControls the connection between the AUX domain bus and the MCU domain bus.The buses must be disconnected to allow power-down or power-off of the AUX domain."
|
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hexmask.long 0x20 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x20 0. "DISCONNECT_REQ,Requests the AUX domain bus to be disconnected from the MCU domain bus" "0,1"
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line.long 0x24 "MCUBUSSTAT,MCU Bus StatusIndicates the connection state of the AUX domain and MCU domain buses.Note that this register cannot be read from the MCU domain while disconnected. and is therefore only useful for the AUX_SCE"
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hexmask.long 0x24 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
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bitfld.long 0x24 1. "DISCONNECTED,Indicates whether the AUX domain and MCU domain buses are currently disconnected (1) or connected (0)" "0,1"
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newline
|
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bitfld.long 0x24 0. "DISCONNECT_ACK,Acknowledges reception of the bus disconnection request by matching the value of MCUBUSCTL.DISCONNECT_REQ" "0,1"
|
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line.long 0x28 "AONCTLSTAT,AON Domain Control StatusStatus of AUX domain control from AON_WUC"
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hexmask.long 0x28 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x28 1. "AUX_FORCE_ON,Status of AON_WUC:AUX_CTL.AUX_FORCE_ON" "0,1"
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newline
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bitfld.long 0x28 0. "SCE_RUN_EN,Status of AON_WUC:AUX_CTL.SCE_RUN_EN" "0,1"
|
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line.long 0x2C "AUXIOLATCH,AUX Input Output LatchControls latching of signals between AUX_AIODIO0/AUX_AIODIO1 and AON_IOC"
|
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hexmask.long 0x2C 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x2C 0. "EN,Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal latching.At startup set EN = TRANSP before configuring AUX_AIODIO0/AUX_AIODIO1 and subsequently selecting AUX mode in the AON_IOC.When powering off the AUX domain (using PWROFFREQ.REQ) set EN.." "Latches are static ( closed ),Latches are transparent ( open )"
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group.long 0x5C++0x03
|
|
line.long 0x00 "MODCLKEN1,Module Clock Enable 1Clock enable for each module in the AUX domain. for use by the AUX_SCE"
|
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
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bitfld.long 0x00 7. "AUX_ADI4,Enables (1) or disables (0) clock for AUX_ADI4" "AUX_SCE has not requested clock for AUX_ADI4,AUX_SCE has requested clock for AUX_ADI4"
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newline
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bitfld.long 0x00 6. "AUX_DDI0_OSC,Enables (1) or disables (0) clock for AUX_DDI0_OSC" "AUX_SCE has not requested clock for AUX_DDI0_OSC,AUX_SCE has requested clock for AUX_DDI0_OSC"
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bitfld.long 0x00 5. "TDC,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
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bitfld.long 0x00 4. "ANAIF,Enables (1) or disables (0) clock for AUX_ANAIF" "AUX_SCE has not requested clock for ANAIF,AUX_SCE has requested clock for ANAIF"
|
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bitfld.long 0x00 3. "TIMER,Enables (1) or disables (0) clock for AUX_TIMER" "AUX_SCE has not requested clock for TIMER,AUX_SCE has requested clock for TIMER"
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newline
|
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bitfld.long 0x00 2. "AIODIO1,Enables (1) or disables (0) clock for AUX_AIODIO1" "AUX_SCE has not requested clock for AIODIO1,AUX_SCE has requested clock for AIODIO1"
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bitfld.long 0x00 1. "AIODIO0,Enables (1) or disables (0) clock for AUX_AIODIO0" "AUX_SCE has not requested clock for AIODIO0,AUX_SCE has requested clock for AIODIO0"
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newline
|
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bitfld.long 0x00 0. "SMPH,Enables (1) or disables (0) clock for AUX_SMPH" "AUX_SCE has not requested clock for SMPH,AUX_SCE has requested clock for SMPH"
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tree.end
|
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tree.end
|
|
tree "CCFG"
|
|
base ad:0x50003000
|
|
rgroup.long 0x00++0x47
|
|
line.long 0x00 "SIZE_AND_DIS_FLAGS,CCFG Size and Disable Flags"
|
|
hexmask.long.word 0x00 16.--31. 1. "SIZE_OF_CCFG,Total size of CCFG in bytes"
|
|
newline
|
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hexmask.long.word 0x00 4.--15. 1. "DISABLE_FLAGS,Reserved for future use"
|
|
newline
|
|
bitfld.long 0x00 3. "DIS_TCXO,Deprecated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DIS_GPRAM,Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).0: GPRAM is enabled and hence CACHE disabled.1: GPRAM is disabled and instead CACHE is enabled (default).Notes:- Disabling CACHE will reduce CPU execution speed (up to 60%).- GPRAM is 8.." "GPRAM is enabled and hence CACHE disabled,GPRAM is disabled and instead CACHE is enabled.."
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newline
|
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bitfld.long 0x00 1. "DIS_ALT_DCDC_SETTING,Disable alternate DC/DC settings" "Enable alternate DC/DC settings,Disable alternate DC/DC settings.See"
|
|
newline
|
|
bitfld.long 0x00 0. "DIS_XOSC_OVR,Disable XOSC override functionality.0: Enable XOSC override functionality.1: Disable XOSC override functionality.See:MODE_CONF_1.DELTA_IBIAS_INITMODE_CONF_1.DELTA_IBIAS_OFFSETMODE_CONF_1.XOSC_MAX_START" "Enable XOSC override functionality,Disable XOSC override functionality.See"
|
|
line.long 0x04 "MODE_CONF,Mode Configuration 0"
|
|
bitfld.long 0x04 28.--31. "VDDR_TRIM_SLEEP_DELTA,Signed delta value to apply to theVDDR_TRIM_SLEEP target minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 27. "DCDC_RECHARGE,DC/DC during recharge in powerdown.0: Use the DC/DC during recharge in powerdown.1: Do not use the DC/DC during recharge in powerdown (default).NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly.." "Use the DC/DC during recharge in powerdown,Do not use the DC/DC during recharge in.."
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bitfld.long 0x04 26. "DCDC_ACTIVE,DC/DC in active mode.0: Use the DC/DC during active mode.1: Do not use the DC/DC during active mode (default).NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled.." "Use the DC/DC during active mode,Do not use the DC/DC during active mode.."
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bitfld.long 0x04 25. "VDDR_EXT_LOAD,Reserved for future use" "0,1"
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newline
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bitfld.long 0x04 24. "VDDS_BOD_LEVEL,VDDS BOD level.0: VDDS BOD level is 2.0V (necessary for external load mode or for maximum PA output power on CC13xx).1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default)." "VDDS BOD level is 2.0V (necessary for external..,VDDS BOD level is 1.8V (or 1.65V for external.."
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bitfld.long 0x04 22.--23. "SCLK_LF_OPTION,Select source for SCLK_LF" "31.25kHz clock derived from 48MHz XOSC or HPOSC..,External low frequency clock on DIO defined by..,32.768kHz low frequency XOSC,Low frequency RCOSC (default)"
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newline
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bitfld.long 0x04 21. "VDDR_TRIM_SLEEP_TC," "0,1"
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newline
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bitfld.long 0x04 20. "RTC_COMP,Reserved for future use" "0,1"
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bitfld.long 0x04 18.--19. "XOSC_FREQ,Selects which high frequency oscillator is used (required for radio usage)" "External 48Mhz TCXO.Refer to..,Internal high precision oscillator.,48 MHz XOSC_HF,24 MHz XOSC_HF. Not supported."
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bitfld.long 0x04 17. "XOSC_CAP_MOD,Enable modification (delta) to XOSC cap-array" "Apply cap-array delta,Do not apply cap-array delta (default)"
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bitfld.long 0x04 16. "HF_COMP,Reserved for future use" "0,1"
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hexmask.long.byte 0x04 8.--15. 1. "XOSC_CAPARRAY_DELTA,Signed 8-bit value directly modifying trimmed XOSC cap-array step value"
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newline
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hexmask.long.byte 0x04 0.--7. 1. "VDDR_CAP,Unsigned 8-bit integer representing the minimum decoupling capacitance (worst case) on VDDR in units of 100nF"
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line.long 0x08 "MODE_CONF_1,Mode Configuration 1"
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bitfld.long 0x08 31. "TCXO_TYPE,Selects the TCXO type.0: CMOS type" "CMOS type,Clipped-sine type"
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hexmask.long.byte 0x08 24.--30. 1. "TCXO_MAX_START,Maximum TCXO startup time in units of 100us.Bit field value is only valid if MODE_CONF.XOSC_FREQ=0"
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bitfld.long 0x08 20.--23. "ALT_DCDC_VMIN,Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).Voltage = (28 + ALT_DCDC_VMIN) /" "1.75V,1.8125V,?,?,?,?,?,?,?,?,?,?,?,?,2.625V,2.6875VNOTE! The.."
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bitfld.long 0x08 19. "ALT_DCDC_DITHER_EN,Enable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).0: Dither disable1: Dither enable" "Dither disable,Dither enable"
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bitfld.long 0x08 16.--18. "ALT_DCDC_IPEAK,Inductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 12.--15. "DELTA_IBIAS_INIT,Signed delta value for IBIAS_INIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. "DELTA_IBIAS_OFFSET,Signed delta value for IBIAS_OFFSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 0.--7. 1. "XOSC_MAX_START,Unsigned value of maximum XOSC startup time (worst case) in units of 100us"
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line.long 0x0C "VOLT_LOAD_0,Voltage Load 0Enabled by MODE_CONF.VDDR_EXT_LOAD"
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hexmask.long.byte 0x0C 24.--31. 1. "VDDR_EXT_TP45,Reserved for future use"
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hexmask.long.byte 0x0C 16.--23. 1. "VDDR_EXT_TP25,Reserved for future use"
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hexmask.long.byte 0x0C 8.--15. 1. "VDDR_EXT_TP5,Reserved for future use"
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hexmask.long.byte 0x0C 0.--7. 1. "VDDR_EXT_TM15,Reserved for future use"
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line.long 0x10 "VOLT_LOAD_1,Voltage Load 1Enabled by MODE_CONF.VDDR_EXT_LOAD"
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hexmask.long.byte 0x10 24.--31. 1. "VDDR_EXT_TP125,Reserved for future use"
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hexmask.long.byte 0x10 16.--23. 1. "VDDR_EXT_TP105,Reserved for future use"
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hexmask.long.byte 0x10 8.--15. 1. "VDDR_EXT_TP85,Reserved for future use"
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hexmask.long.byte 0x10 0.--7. 1. "VDDR_EXT_TP65,Reserved for future use"
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line.long 0x14 "EXT_LF_CLK,Extern LF clock configuration"
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hexmask.long.byte 0x14 24.--31. 1. "DIO,Unsigned integer selecting the DIO to supply external 32kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTC_INCREMENT,Unsigned integer defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC"
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line.long 0x18 "IEEE_MAC_0,IEEE MAC Address 0"
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line.long 0x1C "IEEE_MAC_1,IEEE MAC Address 1"
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line.long 0x20 "IEEE_BLE_0,IEEE BLE Address 0"
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line.long 0x24 "IEEE_BLE_1,IEEE BLE Address 1"
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line.long 0x28 "BL_CONFIG,Bootloader ConfigurationConfigures the functionality of the ROM boot loader.If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the.."
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hexmask.long.byte 0x28 24.--31. 1. "BOOTLOADER_ENABLE,Bootloader enable"
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hexmask.long.byte 0x28 17.--23. 1. "RESERVED,Software should not rely on the value of a reserved"
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bitfld.long 0x28 16. "BL_LEVEL,Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field.0: Active low.1: Active high" "Active low,Active high"
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newline
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hexmask.long.byte 0x28 8.--15. 1. "BL_PIN_NUMBER,DIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field"
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newline
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hexmask.long.byte 0x28 0.--7. 1. "BL_ENABLE,Enables the boot loader"
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line.long 0x2C "ERASE_CONF,Erase Configuration"
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hexmask.long.tbyte 0x2C 9.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 8. "CHIP_ERASE_DIS_N,Chip erase.This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD.A successful chip erase operation will force the content of the flash main bank back to.." "Disable,Enable"
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hexmask.long.byte 0x2C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 0. "BANK_ERASE_DIS_N,Bank erase.This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE).A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration.." "Disable the boot loader bank erase function,Enable the boot loader bank erase function"
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line.long 0x30 "ERASE_CONF_1,Erase Configuration 1"
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hexmask.long 0x30 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x30 0. "WEPROT_CCFG_N,WriteErase protect the CCFG sectorSetting this bit = 0 will set FLASH:WEPROT_AUX_BY1.WEPROT_B0_CCFG_BY1 = 1 during boot and hence WriteErase protect the CCFG" "0,1"
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line.long 0x34 "CCFG_TI_OPTIONS,TI Options"
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hexmask.long.word 0x34 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x34 8.--15. 1. "IDAU_CFG_ENABLE,IDAU"
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newline
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hexmask.long.byte 0x34 0.--7. 1. "TI_FA_ENABLE,TI Failure"
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line.long 0x38 "CCFG_TAP_DAP_0,Test Access Points Enable 0"
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hexmask.long.byte 0x38 24.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x38 16.--23. 1. "CPU_DAP_ENABLE,Enable CPU"
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newline
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hexmask.long.byte 0x38 8.--15. 1. "PWRPROF_TAP_ENABLE,Enable PWRPROF TAP.0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PWRPROF TAP access will remain disabled out of.."
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newline
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hexmask.long.byte 0x38 0.--7. 1. "TEST_TAP_ENABLE,Enable Test TAP.0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: TEST TAP access will remain disabled out of.."
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line.long 0x3C "CCFG_TAP_DAP_1,Test Access Points Enable 1"
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hexmask.long.byte 0x3C 24.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x3C 16.--23. 1. "PBIST2_TAP_ENABLE,Enable PBIST2 TAP.0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PBIST2 TAP access will remain disabled out of.."
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newline
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hexmask.long.byte 0x3C 8.--15. 1. "PBIST1_TAP_ENABLE,Enable PBIST1 TAP.0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PBIST1 TAP access will remain disabled out of.."
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newline
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hexmask.long.byte 0x3C 0.--7. 1. "AON_TAP_ENABLE,Enable AON TAP0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: AON TAP access will remain disabled out of.."
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line.long 0x40 "IMAGE_VALID_CONF,Image Valid"
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line.long 0x44 "CCFG_WEPROT_31_0_BY2K,Protect Sectors 0-31Each bit write protects one 2KB flash sector from being both programmed and erased"
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bitfld.long 0x44 31. "WEPROT_SEC_31_N," "0,1"
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bitfld.long 0x44 30. "WEPROT_SEC_30_N," "0,1"
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bitfld.long 0x44 29. "WEPROT_SEC_29_N," "0,1"
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bitfld.long 0x44 28. "WEPROT_SEC_28_N," "0,1"
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bitfld.long 0x44 27. "WEPROT_SEC_27_N," "0,1"
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bitfld.long 0x44 26. "WEPROT_SEC_26_N," "0,1"
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bitfld.long 0x44 25. "WEPROT_SEC_25_N," "0,1"
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bitfld.long 0x44 24. "WEPROT_SEC_24_N," "0,1"
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bitfld.long 0x44 23. "WEPROT_SEC_23_N," "0,1"
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bitfld.long 0x44 22. "WEPROT_SEC_22_N," "0,1"
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bitfld.long 0x44 21. "WEPROT_SEC_21_N," "0,1"
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bitfld.long 0x44 20. "WEPROT_SEC_20_N," "0,1"
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bitfld.long 0x44 19. "WEPROT_SEC_19_N," "0,1"
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bitfld.long 0x44 18. "WEPROT_SEC_18_N," "0,1"
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bitfld.long 0x44 17. "WEPROT_SEC_17_N," "0,1"
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bitfld.long 0x44 16. "WEPROT_SEC_16_N," "0,1"
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bitfld.long 0x44 15. "WEPROT_SEC_15_N," "0,1"
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bitfld.long 0x44 14. "WEPROT_SEC_14_N," "0,1"
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bitfld.long 0x44 13. "WEPROT_SEC_13_N," "0,1"
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bitfld.long 0x44 12. "WEPROT_SEC_12_N," "0,1"
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bitfld.long 0x44 11. "WEPROT_SEC_11_N," "0,1"
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bitfld.long 0x44 10. "WEPROT_SEC_10_N," "0,1"
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bitfld.long 0x44 9. "WEPROT_SEC_9_N," "0,1"
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newline
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bitfld.long 0x44 8. "WEPROT_SEC_8_N," "0,1"
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newline
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bitfld.long 0x44 7. "WEPROT_SEC_7_N," "0,1"
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bitfld.long 0x44 6. "WEPROT_SEC_6_N," "0,1"
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bitfld.long 0x44 5. "WEPROT_SEC_5_N," "0,1"
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newline
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bitfld.long 0x44 4. "WEPROT_SEC_4_N," "0,1"
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newline
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bitfld.long 0x44 3. "WEPROT_SEC_3_N," "0,1"
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newline
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bitfld.long 0x44 2. "WEPROT_SEC_2_N," "0,1"
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newline
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bitfld.long 0x44 1. "WEPROT_SEC_1_N," "0,1"
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newline
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bitfld.long 0x44 0. "WEPROT_SEC_0_N," "0,1"
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repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
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rgroup.long ($2+0x48)++0x03
|
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line.long 0x00 "CCFG_WEPROT_SPARE_$1,Spare register for WriteErase configuration"
|
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repeat.end
|
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rgroup.long 0x54++0x0B
|
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line.long 0x00 "TRUSTZONE_FLASH_CFG,Trustzone configuration register for flash"
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hexmask.long.word 0x00 17.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x00 10.--16. 1. "NSADDR_BOUNDARY,Value will be written to PRCM:NVMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
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newline
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hexmask.long.word 0x00 0.--9. 1. "NSCADDR_BOUNDARY,Value will be written to PRCM:NVMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
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line.long 0x04 "TRUSTZONE_SRAM_CFG,Trustzone configuration register for MCU SRAM"
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hexmask.long.word 0x04 18.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x04 9.--17. 1. "NSADDR_BOUNDARY,Value will be written to PRCM:SRAMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
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newline
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hexmask.long.word 0x04 0.--8. 1. "NSCADDR_BOUNDARY,Value will be written to PRCM:SRAMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
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line.long 0x08 "SRAM_CFG,Configuration register for MCU SRAM"
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hexmask.long.tbyte 0x08 8.--31. 1. "MEM_SEL,Value will be written to SRAM_MMR:MEM_CTL.MEM_SEL by ROM boot FW"
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newline
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hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 0. "PARITY_DIS,Value will be inverted and then written to PRCM:MCUSRAMCFG.PARITY_EN by ROM boot FW" "0,1"
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rgroup.long 0x64++0x07
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line.long 0x00 "CPU_LOCK_CFG,Configuration register for MCU CPU lock options"
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hexmask.long 0x00 5.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 4. "LOCKNSVTOR_N,Value will be inverted and written to PRCM:CPULOCK.LOCKNSVTOR by ROM boot FW" "0,1"
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newline
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bitfld.long 0x00 3. "LOCKSVTAIRCR_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSVTAIRCR by ROM boot FW" "0,1"
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newline
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bitfld.long 0x00 2. "LOCKSAU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSAU by ROM boot FW" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "LOCKNSMPU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKNSMPU by ROM boot FW" "0,1"
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newline
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bitfld.long 0x00 0. "LOCKSMPU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSMPU by ROM boot FW" "0,1"
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line.long 0x04 "DEB_AUTH_CFG,Configuration register for debug authentication"
|
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hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 3. "INTSPNIDEN,Value will be written to CPU_DCB:DAUTHCTRL.INTSPNIDEN by ROM boot FW" "0,1"
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newline
|
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bitfld.long 0x04 2. "SPNIDENSEL,Value will be written to CPU_DCB:DAUTHCTRL.SPNIDENSEL by ROM boot FW" "0,1"
|
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newline
|
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bitfld.long 0x04 1. "INTSPIDEN,Value will be written to CPU_DCB:DAUTHCTRL.INTSPIDEN by ROM boot FW" "0,1"
|
|
newline
|
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bitfld.long 0x04 0. "SPIDENSEL,Value will be written to CPU_DCB:DAUTHCTRL.SPIDENSEL by ROM boot FW" "0,1"
|
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tree.end
|
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tree "CPU"
|
|
tree "CPU_DWT"
|
|
base ad:0xE0001000
|
|
rgroup.long 0x00++0x1F
|
|
line.long 0x00 "CTRL,Provides configuration and status information for the DWT unit. and used to control features of the unit"
|
|
bitfld.long 0x00 28.--31. "NUMCOMP,Number of DWT comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 27. "NOTRCPKT,Indicates whether the implementation does not support trace" "0,1"
|
|
bitfld.long 0x00 26. "NOEXTTRIG,Reserved RAZ" "0,1"
|
|
bitfld.long 0x00 25. "NOCYCCNT,Indicates whether the implementation does not include a cycle counter" "0,1"
|
|
bitfld.long 0x00 24. "NOPRFCNT,Indicates whether the implementation does not include the profiling counters" "0,1"
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|
bitfld.long 0x00 23. "CYCDISS,Controls whether the cycle counter is disabled in Secure state" "0,1"
|
|
bitfld.long 0x00 22. "CYCEVTENA,Enables Event Counter packet generation on POSTCNT underflow" "0,1"
|
|
bitfld.long 0x00 21. "FOLDEVTENA,Enables DWT_FOLDCNT counter" "0,1"
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|
newline
|
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bitfld.long 0x00 20. "LSUEVTENA,Enables DWT_LSUCNT counter" "0,1"
|
|
bitfld.long 0x00 19. "SLEEPEVTENA,Enable DWT_SLEEPCNT counter" "0,1"
|
|
bitfld.long 0x00 18. "EXCEVTENA,Enables DWT_EXCCNT counter" "0,1"
|
|
bitfld.long 0x00 17. "CPIEVTENA,Enables DWT_CPICNT counter" "0,1"
|
|
bitfld.long 0x00 16. "EXTTRCENA,Enables generation of Exception Trace packets" "0,1"
|
|
bitfld.long 0x00 13.--15. "RESERVED13,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "PCSAMPLENA,Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation" "0,1"
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|
bitfld.long 0x00 10.--11. "SYNCTAP,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x00 9. "CYCTAP,Selects the position of the POSTCNT tap on the CYCCNT counter" "0,1"
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|
bitfld.long 0x00 5.--8. "POSTINIT,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 1.--4. "POSTPRESET,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. "CYCCNTENA,Enables CYCCNT" "0,1"
|
|
line.long 0x04 "CYCCNT,Shows or sets the value of the processor cycle counter. CYCCNT"
|
|
line.long 0x08 "CPICNT,CPI Count Register"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x08 0.--7. 1. "CPICNT,Counts one on each cycle when all of the following are true:- DWT_CTRL.CPIEVTENA == 1 and DEMCR.TRCENA == 1.- No instruction is executed.- No load-store operation is in progress see DWT_LSUCNT.- No exception-entry or exception-exit operation is.."
|
|
line.long 0x0C "EXCCNT,Counts the total cycles spent in exception processing"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EXCCNT,Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x10 "SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SLEEPCNT,Counts one on each cycle when all of the following are true:- DWT_CTRL.SLEEPEVTENA == 1 and DEMCR.TRCENA == 1.- No instruction is executed see DWT_CPICNT.- No load-store operation is in progress see DWT_LSUCNT.- No exception-entry or.."
|
|
line.long 0x14 "LSUCNT,Increments on the additional cycles required to execute all load or store instructions"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x14 0.--7. 1. "LSUCNT,Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x18 "FOLDCNT,Increments on the additional cycles required to execute all load or store instructions"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FOLDCNT,Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x1C "PCSR,Program Counter Sample Register"
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x10 0x20 0x30 )
|
|
hgroup.long ($2+0x20)++0x03
|
|
hide.long 0x00 "COMP$1,Provides a reference value for use by watchpoint comparator 0"
|
|
repeat.end
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x10 0x20 0x30 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "FUNCTION$1,Controls the operation of watchpoint comparator 0"
|
|
rbitfld.long 0x00 27.--31. "ID,Identifies the capabilities for MATCH for comparator *n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 25.--26. "RESERVED25,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 24. "MATCHED,Set to 1 when the comparator matches" "0,1"
|
|
hexmask.long.word 0x00 12.--23. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,Defines the size of the object being watched for by Data Value and Data Address comparators" "0,1,2,3"
|
|
rbitfld.long 0x00 6.--9. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "ACTION,Defines the action on a match" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "MATCH,Controls the type of match generated by this comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the DWT"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_FPB"
|
|
base ad:0xE0002000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Provides FPB implementation information. and the global enable for the FPB unit"
|
|
rbitfld.long 0x00 28.--31. "REV,Flash Patch and Breakpoint Unit architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 15.--27. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 12.--14. "NUM_CODE_14_12_,Indicates the number of implemented instruction address comparators" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--11. "NUM_LIT,Indicates the number of implemented literal address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "NUM_CODE_7_4_,Indicates the number of implemented instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "KEY,Writes to the FP_CTRL are ignored unless KEY is concurrently written to one" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the FPB" "0,1"
|
|
line.long 0x04 "REMAP,Indicates whether the implementation supports Flash Patch remap and. if it does. holds the target address for remap"
|
|
bitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x04 29. "RMPSPT,Indicates whether the FPB unit supports the Flash Patch remap function" "0,1"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. "REMAP,Holds the bits[28:5] of the Flash Patch remap address"
|
|
bitfld.long 0x04 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "COMP$1,Holds an address for comparison"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "BE,Selects between flashpatch and breakpoint functionality" "0,1"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the FPB"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the FPB"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the FP"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_ITM"
|
|
base ad:0xE0000000
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "STIM$1,Provides the interface for generating Instrumentation packets"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "DISABLED,Indicates whether the Stimulus Port is enabled or disabled" "0,1"
|
|
bitfld.long 0x00 0. "FIFOREADY,Indicates whether the Stimulus Port can accept data" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "STIM$1,Provides the interface for generating Instrumentation packets"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "DISABLED,Indicates whether the Stimulus Port is enabled or disabled" "0,1"
|
|
bitfld.long 0x00 0. "FIFOREADY,Indicates whether the Stimulus Port can accept data" "0,1"
|
|
repeat.end
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "TER0,Provide an individual enable bit for each ITM_STIM register"
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "TPR,Controls which stimulus ports can be accessed by unprivileged code"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "TCR,Configures and controls transfers through the ITM interface"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 23. "BUSY,Indicates whether the ITM is currently processing events" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "TraceBusID,Identifier for multi-source trace stream formatting"
|
|
rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "GTSFREQ,Defines how often the ITM generates a global timestamp based on the global timestamp clock frequency or disables generation of global timestamps" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "TSPrescale,Local timestamp prescaler used with the trace packet reference clock" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x00 5. "STALLENA,Stall the PE to guarantee delivery of Data Trace packets" "0,1"
|
|
bitfld.long 0x00 4. "SWOENA,Enables asynchronous clocking of the timestamp counter" "0,1"
|
|
bitfld.long 0x00 3. "TXENA,Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU" "0,1"
|
|
bitfld.long 0x00 2. "SYNCENA,Enables Synchronization packet transmission for a synchronous TPIU" "0,1"
|
|
bitfld.long 0x00 1. "TSENA,Enables Local timestamp generation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ITMENA,Enables the ITM" "0,1"
|
|
rgroup.long 0xEF0++0x03
|
|
line.long 0x00 "INT_ATREADY,Integration Mode: Read ATB Ready"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFVALID,A read of this bit returns the value of AFVALID" "0,1"
|
|
bitfld.long 0x00 0. "ATREADY,A read of this bit returns the value of ATREADY" "0,1"
|
|
group.long 0xEF8++0x03
|
|
line.long 0x00 "INT_ATVALID,Integration Mode: Write ATB Valid"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFREADY,A write to this bit gives the value of AFREADY" "0,1"
|
|
bitfld.long 0x00 0. "ATREADY,A write to this bit gives the value of ATVALID" "0,1"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ITCTRL,Integration Mode Control Register"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "IME,Integration mode enable bit - The possible values are" "The trace unit is not in integration mode,The trace unit is in integration mode"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the ITM"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_SCS"
|
|
base ad:0xE000E000
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "RESERVED000,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "ICTR,Interrupt Control TypeRead this register to see the number of interrupt lines that the NVIC supports"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "INTLINESNUM,Total number of interrupt lines in groups of" "0...32,33...64,65...96,97...128,129...160,161...192,193...224,225...256"
|
|
line.long 0x08 "ACTLR,Auxiliary ControlThis register is used to disable certain aspects of functionality within the processor"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 9. "DISOOFP,Disables floating point instructions completing out of order with respect to integer instructions" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "DISFPCA,Disable automatic update of CONTROL.FPCA" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "DISFOLD,Disables folding of IT instruction" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "DISDEFWBUF,Disables write buffer use during default memory map accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "DISMCYCINT,Disables interruption of multi-cycle instructions" "0,1"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "STCSR,SysTick Control and StatusThis register enables the SysTick features and returns status flags related to SysTick"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 16. "COUNTFLAG,Returns 1 if timer counted to 0 since last time this was" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 3.--15. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "CLKSOURCE,Clock source:0: External reference clock.1: Core clockExternal clock is not available in this device" "External reference clock,Core clockExternal clock is not available in.."
|
|
newline
|
|
bitfld.long 0x00 1. "TICKINT," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,Enable SysTick counter0: Counter disabled1: Counter operates in a multi-shot way" "Counter disabled,Counter operates in a multi-shot way"
|
|
line.long 0x04 "STRVR,SysTick Reload ValueThis register is used to specify the start value to load into the current value register STCVR.CURRENT when the counter reaches 0"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x04 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current ValueRead from this register returns the current value of SysTick counter"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "CURRENT,Current value at the time the register is accessed"
|
|
line.long 0x0C "STCR,SysTick Calibration ValueUsed to enable software to scale to any required speed using divide and multiply"
|
|
bitfld.long 0x0C 31. "NOREF,Reads as one" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 30. "SKEW,Reads as one" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 24.--29. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. "TENMS,An optional Reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "NVIC_ISER0,Irq 0 to 31 Set EnableThis register is used to enable interrupts and determine which interrupts are currently enabled"
|
|
bitfld.long 0x00 31. "SETENA31,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SETENA30,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "SETENA29,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "SETENA28,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "SETENA27,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "SETENA26,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "SETENA25,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "SETENA24,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "SETENA23,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "SETENA22,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SETENA21,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "SETENA20,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "SETENA19,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "SETENA18,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "SETENA17,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "SETENA16,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "SETENA15,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "SETENA14,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "SETENA13,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SETENA12,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SETENA11,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "SETENA10,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SETENA9,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SETENA8,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SETENA7,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SETENA6,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SETENA5,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SETENA4,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SETENA3,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SETENA2,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SETENA1,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SETENA0,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
|
|
line.long 0x04 "NVIC_ISER1,Irq 32 to 63 Set EnableThis register is used to enable interrupts and determine which interrupts are currently enabled"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "SETENA37,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "SETENA36,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "SETENA35,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "SETENA34,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "SETENA33,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "SETENA32,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
|
|
group.long 0x180++0x07
|
|
line.long 0x00 "NVIC_ICER0,Irq 0 to 31 Clear EnableThis register is used to disable interrupts and determine which interrupts are currently enabled"
|
|
bitfld.long 0x00 31. "CLRENA31,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLRENA30,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CLRENA29,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "CLRENA28,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CLRENA27,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "CLRENA26,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "CLRENA25,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "CLRENA24,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CLRENA23,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "CLRENA22,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CLRENA21,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "CLRENA20,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CLRENA19,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CLRENA18,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CLRENA17,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CLRENA16,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CLRENA15,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CLRENA14,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CLRENA13,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CLRENA12,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CLRENA11,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CLRENA10,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CLRENA9,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CLRENA8,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CLRENA7,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "CLRENA6,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "CLRENA5,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "CLRENA4,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "CLRENA3,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "CLRENA2,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "CLRENA1,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "CLRENA0,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
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line.long 0x04 "NVIC_ICER1,Irq 32 to 63 Clear EnableThis register is used to disable interrupts and determine which interrupts are currently enabled"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x04 5. "CLRENA37,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "CLRENA36,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "CLRENA35,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "CLRENA34,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "CLRENA33,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "CLRENA32,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
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group.long 0x200++0x07
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line.long 0x00 "NVIC_ISPR0,Irq 0 to 31 Set PendingThis register is used to force interrupts into the pending state and determine which interrupts are currently pending"
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bitfld.long 0x00 31. "SETPEND31,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
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bitfld.long 0x00 30. "SETPEND30,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
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bitfld.long 0x00 29. "SETPEND29,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
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bitfld.long 0x00 28. "SETPEND28,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
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bitfld.long 0x00 27. "SETPEND27,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
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bitfld.long 0x00 26. "SETPEND26,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
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bitfld.long 0x00 25. "SETPEND25,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
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bitfld.long 0x00 24. "SETPEND24,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
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bitfld.long 0x00 23. "SETPEND23,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
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bitfld.long 0x00 22. "SETPEND22,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
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bitfld.long 0x00 21. "SETPEND21,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
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bitfld.long 0x00 20. "SETPEND20,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
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bitfld.long 0x00 19. "SETPEND19,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
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bitfld.long 0x00 18. "SETPEND18,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
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bitfld.long 0x00 17. "SETPEND17,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
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bitfld.long 0x00 16. "SETPEND16,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
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bitfld.long 0x00 15. "SETPEND15,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
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bitfld.long 0x00 14. "SETPEND14,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
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bitfld.long 0x00 13. "SETPEND13,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
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bitfld.long 0x00 12. "SETPEND12,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
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bitfld.long 0x00 11. "SETPEND11,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
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bitfld.long 0x00 10. "SETPEND10,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
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bitfld.long 0x00 9. "SETPEND9,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
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bitfld.long 0x00 8. "SETPEND8,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
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bitfld.long 0x00 7. "SETPEND7,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "SETPEND6,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "SETPEND5,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "SETPEND4,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "SETPEND3,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "SETPEND2,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "SETPEND1,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "SETPEND0,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
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line.long 0x04 "NVIC_ISPR1,Irq 32 to 63 Set PendingThis register is used to force interrupts into the pending state and determine which interrupts are currently pending"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 5. "SETPEND37,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "SETPEND36,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "SETPEND35,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "SETPEND34,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "SETPEND33,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "SETPEND32,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
|
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group.long 0x280++0x07
|
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line.long 0x00 "NVIC_ICPR0,Irq 0 to 31 Clear PendingThis register is used to clear pending interrupts and determine which interrupts are currently pending"
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bitfld.long 0x00 31. "CLRPEND31,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
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bitfld.long 0x00 30. "CLRPEND30,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
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bitfld.long 0x00 29. "CLRPEND29,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
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bitfld.long 0x00 28. "CLRPEND28,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
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bitfld.long 0x00 27. "CLRPEND27,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
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bitfld.long 0x00 26. "CLRPEND26,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
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bitfld.long 0x00 25. "CLRPEND25,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
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bitfld.long 0x00 24. "CLRPEND24,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
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bitfld.long 0x00 23. "CLRPEND23,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
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bitfld.long 0x00 22. "CLRPEND22,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
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bitfld.long 0x00 21. "CLRPEND21,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
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bitfld.long 0x00 20. "CLRPEND20,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
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bitfld.long 0x00 19. "CLRPEND19,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
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bitfld.long 0x00 18. "CLRPEND18,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
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bitfld.long 0x00 17. "CLRPEND17,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
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bitfld.long 0x00 16. "CLRPEND16,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
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bitfld.long 0x00 15. "CLRPEND15,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
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bitfld.long 0x00 14. "CLRPEND14,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
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bitfld.long 0x00 13. "CLRPEND13,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
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bitfld.long 0x00 12. "CLRPEND12,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
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bitfld.long 0x00 11. "CLRPEND11,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
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bitfld.long 0x00 10. "CLRPEND10,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
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bitfld.long 0x00 9. "CLRPEND9,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
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bitfld.long 0x00 8. "CLRPEND8,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
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bitfld.long 0x00 7. "CLRPEND7,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "CLRPEND6,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "CLRPEND5,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "CLRPEND4,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "CLRPEND3,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "CLRPEND2,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "CLRPEND1,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "CLRPEND0,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
|
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line.long 0x04 "NVIC_ICPR1,Irq 32 to 63 Clear PendingThis register is used to clear pending interrupts and determine which interrupts are currently pending"
|
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 5. "CLRPEND37,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "CLRPEND36,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "CLRPEND35,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "CLRPEND34,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "CLRPEND33,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "CLRPEND32,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
|
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rgroup.long 0x300++0x07
|
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line.long 0x00 "NVIC_IABR0,Irq 0 to 31 Active BitThis register is used to determine which interrupts are active"
|
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bitfld.long 0x00 31. "ACTIVE31,Reading 0 from this bit implies that interrupt line 31 is not active" "0,1"
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bitfld.long 0x00 30. "ACTIVE30,Reading 0 from this bit implies that interrupt line 30 is not active" "0,1"
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bitfld.long 0x00 29. "ACTIVE29,Reading 0 from this bit implies that interrupt line 29 is not active" "0,1"
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newline
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bitfld.long 0x00 28. "ACTIVE28,Reading 0 from this bit implies that interrupt line 28 is not active" "0,1"
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newline
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bitfld.long 0x00 27. "ACTIVE27,Reading 0 from this bit implies that interrupt line 27 is not active" "0,1"
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newline
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bitfld.long 0x00 26. "ACTIVE26,Reading 0 from this bit implies that interrupt line 26 is not active" "0,1"
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bitfld.long 0x00 25. "ACTIVE25,Reading 0 from this bit implies that interrupt line 25 is not active" "0,1"
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bitfld.long 0x00 24. "ACTIVE24,Reading 0 from this bit implies that interrupt line 24 is not active" "0,1"
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newline
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bitfld.long 0x00 23. "ACTIVE23,Reading 0 from this bit implies that interrupt line 23 is not active" "0,1"
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bitfld.long 0x00 22. "ACTIVE22,Reading 0 from this bit implies that interrupt line 22 is not active" "0,1"
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newline
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bitfld.long 0x00 21. "ACTIVE21,Reading 0 from this bit implies that interrupt line 21 is not active" "0,1"
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bitfld.long 0x00 20. "ACTIVE20,Reading 0 from this bit implies that interrupt line 20 is not active" "0,1"
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newline
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bitfld.long 0x00 19. "ACTIVE19,Reading 0 from this bit implies that interrupt line 19 is not active" "0,1"
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newline
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bitfld.long 0x00 18. "ACTIVE18,Reading 0 from this bit implies that interrupt line 18 is not active" "0,1"
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newline
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bitfld.long 0x00 17. "ACTIVE17,Reading 0 from this bit implies that interrupt line 17 is not active" "0,1"
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newline
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bitfld.long 0x00 16. "ACTIVE16,Reading 0 from this bit implies that interrupt line 16 is not active" "0,1"
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newline
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bitfld.long 0x00 15. "ACTIVE15,Reading 0 from this bit implies that interrupt line 15 is not active" "0,1"
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newline
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bitfld.long 0x00 14. "ACTIVE14,Reading 0 from this bit implies that interrupt line 14 is not active" "0,1"
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newline
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bitfld.long 0x00 13. "ACTIVE13,Reading 0 from this bit implies that interrupt line 13 is not active" "0,1"
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bitfld.long 0x00 12. "ACTIVE12,Reading 0 from this bit implies that interrupt line 12 is not active" "0,1"
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newline
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bitfld.long 0x00 11. "ACTIVE11,Reading 0 from this bit implies that interrupt line 11 is not active" "0,1"
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newline
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bitfld.long 0x00 10. "ACTIVE10,Reading 0 from this bit implies that interrupt line 10 is not active" "0,1"
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bitfld.long 0x00 9. "ACTIVE9,Reading 0 from this bit implies that interrupt line 9 is not active" "0,1"
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newline
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bitfld.long 0x00 8. "ACTIVE8,Reading 0 from this bit implies that interrupt line 8 is not active" "0,1"
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bitfld.long 0x00 7. "ACTIVE7,Reading 0 from this bit implies that interrupt line 7 is not active" "0,1"
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bitfld.long 0x00 6. "ACTIVE6,Reading 0 from this bit implies that interrupt line 6 is not active" "0,1"
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bitfld.long 0x00 5. "ACTIVE5,Reading 0 from this bit implies that interrupt line 5 is not active" "0,1"
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bitfld.long 0x00 4. "ACTIVE4,Reading 0 from this bit implies that interrupt line 4 is not active" "0,1"
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bitfld.long 0x00 3. "ACTIVE3,Reading 0 from this bit implies that interrupt line 3 is not active" "0,1"
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bitfld.long 0x00 2. "ACTIVE2,Reading 0 from this bit implies that interrupt line 2 is not active" "0,1"
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bitfld.long 0x00 1. "ACTIVE1,Reading 0 from this bit implies that interrupt line 1 is not active" "0,1"
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bitfld.long 0x00 0. "ACTIVE0,Reading 0 from this bit implies that interrupt line 0 is not active" "0,1"
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line.long 0x04 "NVIC_IABR1,Irq 32 to 63 Active BitThis register is used to determine which interrupts are active"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x04 5. "ACTIVE37,Reading 0 from this bit implies that interrupt line 37 is not active" "0,1"
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bitfld.long 0x04 4. "ACTIVE36,Reading 0 from this bit implies that interrupt line 36 is not active" "0,1"
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bitfld.long 0x04 3. "ACTIVE35,Reading 0 from this bit implies that interrupt line 35 is not active" "0,1"
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bitfld.long 0x04 2. "ACTIVE34,Reading 0 from this bit implies that interrupt line 34 is not active" "0,1"
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bitfld.long 0x04 1. "ACTIVE33,Reading 0 from this bit implies that interrupt line 33 is not active" "0,1"
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bitfld.long 0x04 0. "ACTIVE32,Reading 0 from this bit implies that interrupt line 32 is not active" "0,1"
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group.long 0x400++0x27
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line.long 0x00 "NVIC_IPR0,Irq 0 to 3 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details)"
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hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details)"
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hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details)"
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hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details)"
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line.long 0x04 "NVIC_IPR1,Irq 4 to 7 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x04 24.--31. 1. "PRI_7,Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details)"
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hexmask.long.byte 0x04 16.--23. 1. "PRI_6,Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details)"
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hexmask.long.byte 0x04 8.--15. 1. "PRI_5,Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details)"
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hexmask.long.byte 0x04 0.--7. 1. "PRI_4,Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details)"
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line.long 0x08 "NVIC_IPR2,Irq 8 to 11 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x08 24.--31. 1. "PRI_11,Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details)"
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hexmask.long.byte 0x08 16.--23. 1. "PRI_10,Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details)"
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hexmask.long.byte 0x08 8.--15. 1. "PRI_9,Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details)"
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hexmask.long.byte 0x08 0.--7. 1. "PRI_8,Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details)"
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line.long 0x0C "NVIC_IPR3,Irq 12 to 15 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x0C 24.--31. 1. "PRI_15,Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details)"
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hexmask.long.byte 0x0C 16.--23. 1. "PRI_14,Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details)"
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hexmask.long.byte 0x0C 8.--15. 1. "PRI_13,Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details)"
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hexmask.long.byte 0x0C 0.--7. 1. "PRI_12,Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details)"
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line.long 0x10 "NVIC_IPR4,Irq 16 to 19 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x10 24.--31. 1. "PRI_19,Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details)"
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hexmask.long.byte 0x10 16.--23. 1. "PRI_18,Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details)"
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hexmask.long.byte 0x10 8.--15. 1. "PRI_17,Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details)"
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hexmask.long.byte 0x10 0.--7. 1. "PRI_16,Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details)"
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line.long 0x14 "NVIC_IPR5,Irq 20 to 23 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x14 24.--31. 1. "PRI_23,Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details)"
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hexmask.long.byte 0x14 16.--23. 1. "PRI_22,Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details)"
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hexmask.long.byte 0x14 8.--15. 1. "PRI_21,Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details)"
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hexmask.long.byte 0x14 0.--7. 1. "PRI_20,Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details)"
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line.long 0x18 "NVIC_IPR6,Irq 24 to 27 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x18 24.--31. 1. "PRI_27,Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details)"
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hexmask.long.byte 0x18 16.--23. 1. "PRI_26,Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details)"
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hexmask.long.byte 0x18 8.--15. 1. "PRI_25,Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details)"
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hexmask.long.byte 0x18 0.--7. 1. "PRI_24,Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details)"
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line.long 0x1C "NVIC_IPR7,Irq 28 to 31 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x1C 24.--31. 1. "PRI_31,Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details)"
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hexmask.long.byte 0x1C 16.--23. 1. "PRI_30,Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details)"
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hexmask.long.byte 0x1C 8.--15. 1. "PRI_29,Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details)"
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hexmask.long.byte 0x1C 0.--7. 1. "PRI_28,Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details)"
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line.long 0x20 "NVIC_IPR8,Irq 32 to 35 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x20 24.--31. 1. "PRI_35,Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details)"
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hexmask.long.byte 0x20 16.--23. 1. "PRI_34,Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details)"
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hexmask.long.byte 0x20 8.--15. 1. "PRI_33,Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details)"
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hexmask.long.byte 0x20 0.--7. 1. "PRI_32,Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details)"
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line.long 0x24 "NVIC_IPR9,Irq 32 to 35 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x24 8.--15. 1. "PRI_37,Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details)"
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hexmask.long.byte 0x24 0.--7. 1. "PRI_36,Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details)"
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rgroup.long 0xD00++0x4F
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line.long 0x00 "CPUID,CPUID BaseThis register determines the ID number of the processor core. the version number of the processor core and the implementation details of the processor core"
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hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementor code"
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bitfld.long 0x00 20.--23. "VARIANT,Implementation defined variant number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "CONSTANT,Reads as 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "PARTNO,Number of processor within family"
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bitfld.long 0x00 0.--3. "REVISION,Implementation defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "ICSR,Interrupt Control StateThis register is used to set a pending Non-Maskable Interrupt (NMI). set or clear a pending SVC. set or clear a pending SysTick. check for pending exceptions. check the vector number of the highest priority pended exception.."
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bitfld.long 0x04 31. "NMIPENDSET,Set pending NMI bit" "No action,Set pending NMI"
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bitfld.long 0x04 29.--30. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x04 28. "PENDSVSET,Set pending pendSV bit.0: No action1: Set pending PendSV" "No action,Set pending PendSV"
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bitfld.long 0x04 27. "PENDSVCLR,Clear pending pendSV bit0: No action1: Clear pending pendSV" "No action,Clear pending pendSV"
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bitfld.long 0x04 26. "PENDSTSET,Set a pending SysTick bit.0: No action1: Set pending SysTick" "No action,Set pending SysTick"
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bitfld.long 0x04 25. "PENDSTCLR,Clear pending SysTick bit0: No action1: Clear pending SysTick" "No action,Clear pending SysTick"
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rbitfld.long 0x04 24. "RESERVED24,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x04 23. "ISRPREEMPT,This field can only be used at debug time" "A pending exception is not serviced,A pending exception is serviced on exit from the.."
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bitfld.long 0x04 22. "ISRPENDING,Interrupt pending flag" "Interrupt not pending,Interrupt pending"
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rbitfld.long 0x04 18.--21. "RESERVED18,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x04 12.--17. "VECTPENDING,Pending ISR number field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 11. "RETTOBASE,Indicates whether there are preempted active exceptions:0: There are preempted active exceptions to execute1: There are no active exceptions or the currently-executing exception is the only active exception" "There are preempted active exceptions to execute,There are no active exceptions or the.."
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rbitfld.long 0x04 9.--10. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3"
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hexmask.long.word 0x04 0.--8. 1. "VECTACTIVE,Active ISR number field"
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line.long 0x08 "VTOR,Vector Table OffsetThis register is used to relocated the vector table base address"
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bitfld.long 0x08 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
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hexmask.long.tbyte 0x08 7.--29. 1. "TBLOFF,Bits 29 down to 7 of the vector table base offset"
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hexmask.long.byte 0x08 0.--6. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x0C "AIRCR,Application Interrupt/Reset ControlThis register is used to determine data endianness. clear all active state information for debug or to recover from a hard failure. execute a system reset. alter the priority grouping position (binary point)"
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hexmask.long.word 0x0C 16.--31. 1. "VECTKEY,Register key"
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rbitfld.long 0x0C 15. "ENDIANESS,Data endianness bit" "Little endian,Big endian"
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rbitfld.long 0x0C 11.--14. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--10. "PRIGROUP,Interrupt priority grouping field" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 2. "SYSRESETREQ,Requests a warm reset" "0,1"
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bitfld.long 0x0C 1. "VECTCLRACTIVE,Clears all active state information for active NMI fault and interrupts" "0,1"
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bitfld.long 0x0C 0. "VECTRESET,System Reset bit" "0,1"
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line.long 0x10 "SCR,System ControlThis register is used for power-management functions. i.e.. signaling to the system when the processor can enter a low power state. controlling how the processor enters and exits low power states"
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hexmask.long 0x10 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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bitfld.long 0x10 4. "SEVONPEND,Send Event on Pending bit:0: Only enabled interrupts or events can wakeup the processor disabled interrupts are excluded1: Enabled events and all interrupts including disabled interrupts can wakeup the processor.When an event or interrupt.." "Only enabled interrupts or events can wakeup the..,Enabled events and all interrupts including.."
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bitfld.long 0x10 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x10 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low power mode" "Sleep,Deep sleep"
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bitfld.long 0x10 1. "SLEEPONEXIT,Sleep on exit when returning from Handler mode to Thread mode" "Do not sleep when returning to thread mode,Sleep on ISR exit"
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bitfld.long 0x10 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x14 "CCR,Configuration ControlThis register is used to enable NMI. HardFault and FAULTMASK to ignore bus fault. trap divide by zero and unaligned accesses. enable user access to the Software Trigger Interrupt Register (STIR). control entry to Thread Mode"
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hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
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bitfld.long 0x14 9. "STKALIGN,Stack alignment bit.0: Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.1: On exception entry the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved" "Only 4-byte alignment is guaranteed for the SP..,On exception entry the SP used prior to the.."
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bitfld.long 0x14 8. "BFHFNMIGN,Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions" "Data BusFaults caused by load and store..,Data BusFaults caused by load and store.."
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bitfld.long 0x14 5.--7. "RESERVED5,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4. "DIV_0_TRP,Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of" "Do not trap divide by 0,Trap divide by 0"
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bitfld.long 0x14 3. "UNALIGN_TRP,Enables unaligned access traps:0: Do not trap unaligned halfword and word accesses1: Trap unaligned halfword and word accesses" "Do not trap unaligned halfword and word accesses,Trap unaligned halfword and word accesses"
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bitfld.long 0x14 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x14 1. "USERSETMPEND,Enables unprivileged software access to STIR:0: User code is not allowed to write to the Software Trigger Interrupt register (STIR).1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception.." "User code is not allowed to write to the..,User code can write the Software Trigger.."
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bitfld.long 0x14 0. "NONBASETHREDENA,Indicates how the processor enters Thread mode:0: Processor can enter Thread mode only when no exception is active.1: Processor can enter Thread mode from any level using the appropriate return value (EXC_RETURN).Exception returns occur.." "Processor can enter Thread mode only when no..,Processor can enter Thread mode from any level.."
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line.long 0x18 "SHPR1,System Handlers 4-7 PriorityThis register is used to prioritize the following system handlers: Memory manage. Bus fault. and Usage fault"
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hexmask.long.byte 0x18 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x18 16.--23. 1. "PRI_6,Priority of system handler 6"
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hexmask.long.byte 0x18 8.--15. 1. "PRI_5,Priority of system handler"
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hexmask.long.byte 0x18 0.--7. 1. "PRI_4,Priority of system handler"
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line.long 0x1C "SHPR2,System Handlers 8-11 PriorityThis register is used to prioritize the SVC handler"
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hexmask.long.byte 0x1C 24.--31. 1. "PRI_11,Priority of system handler 11"
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hexmask.long.tbyte 0x1C 0.--23. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
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line.long 0x20 "SHPR3,System Handlers 12-15 PriorityThis register is used to prioritize the following system handlers: SysTick. PendSV and Debug Monitor"
|
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hexmask.long.byte 0x20 24.--31. 1. "PRI_15,Priority of system handler 15"
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hexmask.long.byte 0x20 16.--23. 1. "PRI_14,Priority of system handler 14"
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hexmask.long.byte 0x20 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x20 0.--7. 1. "PRI_12,Priority of system handler 12"
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line.long 0x24 "SHCSR,System Handler Control and StateThis register is used to enable or disable the system handlers. determine the pending status of bus fault. mem manage fault. and SVC. determine the active status of the system handlers"
|
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hexmask.long.word 0x24 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
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bitfld.long 0x24 18. "USGFAULTENA,Usage fault system handler enable" "Exception disabled,Exception enabled"
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bitfld.long 0x24 17. "BUSFAULTENA,Bus fault system handler enable" "Exception disabled,Exception enabled"
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bitfld.long 0x24 16. "MEMFAULTENA,MemManage fault system handler enable" "Exception disabled,Exception enabled"
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rbitfld.long 0x24 15. "SVCALLPENDED,SVCall pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 14. "BUSFAULTPENDED,BusFault pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 13. "MEMFAULTPENDED,MemManage exception pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 12. "USGFAULTPENDED,Usage fault pending" "Exception is not active,Exception is pending."
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bitfld.long 0x24 11. "SYSTICKACT,SysTick active" "Not active,Active"
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bitfld.long 0x24 10. "PENDSVACT,PendSV" "Not active,Active"
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rbitfld.long 0x24 9. "RESERVED9,Software should not rely on the value of a reserved" "0,1"
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rbitfld.long 0x24 8. "MONITORACT,Debug monitor active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 7. "SVCALLACT,SVCall active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 4.--6. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 3. "USGFAULTACT,UsageFault exception active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
|
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rbitfld.long 0x24 1. "BUSFAULTACT,BusFault exception active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 0. "MEMFAULTACT,MemManage exception active" "Exception is not active,Exception is active"
|
|
line.long 0x28 "CFSR,Configurable Fault StatusThis register is used to obtain information about local faults"
|
|
bitfld.long 0x28 26.--31. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 25. "DIVBYZERO,When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0 this fault occurs The instruction is executed and the return PC points to it" "0,1"
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bitfld.long 0x28 24. "UNALIGNED,When CCR.UNALIGN_TRP is enabled and there is an attempt to make an unaligned memory access then this fault occurs" "0,1"
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|
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bitfld.long 0x28 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 19. "NOCP,Attempt to use a coprocessor instruction" "0,1"
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bitfld.long 0x28 18. "INVPC,Attempt to load EXC_RETURN into PC illegally" "0,1"
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bitfld.long 0x28 17. "INVSTATE,Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state)" "0,1"
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bitfld.long 0x28 16. "UNDEFINSTR,This bit is set when the processor attempts to execute an undefined instruction" "0,1"
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bitfld.long 0x28 15. "BFARVALID,This bit is set if the Bus Fault Address Register (BFAR) contains a valid address" "0,1"
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bitfld.long 0x28 13.--14. "RESERVED13,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x28 12. "STKERR,Stacking from exception has caused one or more bus faults" "0,1"
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bitfld.long 0x28 11. "UNSTKERR,Unstack from exception return has caused one or more bus faults" "0,1"
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bitfld.long 0x28 10. "IMPRECISERR,Imprecise data bus error" "0,1"
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bitfld.long 0x28 9. "PRECISERR,Precise data bus error return" "0,1"
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bitfld.long 0x28 8. "IBUSERR,Instruction bus error flag" "0,1"
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bitfld.long 0x28 7. "MMARVALID,Memory Manage Address Register (MMFAR) address valid flag" "0,1"
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bitfld.long 0x28 5.--6. "RESERVED5,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
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bitfld.long 0x28 4. "MSTKERR,Stacking from exception has caused one or more access violations" "0,1"
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bitfld.long 0x28 3. "MUNSTKERR,Unstack from exception return has caused one or more access violations" "0,1"
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bitfld.long 0x28 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x28 1. "DACCVIOL,Data access violation flag" "0,1"
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bitfld.long 0x28 0. "IACCVIOL,Instruction access violation flag" "0,1"
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line.long 0x2C "HFSR,Hard Fault StatusThis register is used to obtain information about events that activate the Hard Fault handler"
|
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bitfld.long 0x2C 31. "DEBUGEVT,This bit is set if there is a fault related to debug" "0,1"
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bitfld.long 0x2C 30. "FORCED,Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled" "0,1"
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hexmask.long 0x2C 2.--29. 1. "RESERVED2,Software should not rely on the value of a reserved"
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|
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bitfld.long 0x2C 1. "VECTTBL,This bit is set if there is a fault because of vector table read on exception processing (Bus Fault)" "0,1"
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bitfld.long 0x2C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x30 "DFSR,Debug Fault StatusThis register is used to monitor external debug requests. vector catches. data watchpoint match. BKPT instruction execution. halt requests"
|
|
hexmask.long 0x30 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
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bitfld.long 0x30 4. "EXTERNAL,External debug request flag" "External debug request signal not asserted,External debug request signal asserted"
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bitfld.long 0x30 3. "VCATCH,Vector catch flag" "No vector catch occurred,Vector catch occurred"
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bitfld.long 0x30 2. "DWTTRAP,Data Watchpoint and Trace (DWT) flag" "No DWT match,DWT match"
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bitfld.long 0x30 1. "BKPT,BKPT flag" "No BKPT instruction execution,BKPT instruction execution"
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bitfld.long 0x30 0. "HALTED,Halt request flag" "No halt request,Halt requested by NVIC including step"
|
|
line.long 0x34 "MMFAR,Mem Manage Fault AddressThis register is used to read the address of the location that caused a Memory Manage Fault"
|
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line.long 0x38 "BFAR,Bus Fault AddressThis register is used to read the address of the location that generated a Bus Fault"
|
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line.long 0x3C "AFSR,Auxiliary Fault StatusThis register is used to determine additional system fault information to software"
|
|
line.long 0x40 "ID_PFR0,Processor Feature 0"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
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bitfld.long 0x40 4.--7. "STATE1,State1 (T-bit ==" "N/A,N/A,Thumb-2 encoding with the 16-bit basic..,Thumb-2 encoding with all Thumb-2 basic..,?..."
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|
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bitfld.long 0x40 0.--3. "STATE0,State0 (T-bit ==" "No ARM..,N/A,?..."
|
|
line.long 0x44 "ID_PFR1,Processor Feature 1"
|
|
hexmask.long.tbyte 0x44 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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|
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bitfld.long 0x44 8.--11. "MICROCONTROLLER_PROGRAMMERS_MODEL,Microcontroller programmer's model0x0: Not supported0x2: Two-stack support" "Not supported,?,Two-stack support,?..."
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|
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hexmask.long.byte 0x44 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x48 "ID_DFR0,Debug Feature 0This register provides a high level view of the debug system"
|
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hexmask.long.byte 0x48 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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bitfld.long 0x48 20.--23. "MICROCONTROLLER_DEBUG_MODEL,Microcontroller Debug Model - memory mapped0x0: Not supported0x1: Microcontroller debug v1 (ITMv1 and DWTv1)" "Not supported,Microcontroller debug v1 (ITMv1 and..,?..."
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|
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hexmask.long.tbyte 0x48 0.--19. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x4C "ID_AFR0,Auxiliary Feature 0This register provides some freedom for implementation defined features to be registered"
|
|
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
|
|
rgroup.long ($2+0xD50)++0x03
|
|
line.long 0x00 "ID_MMFR$1,Memory Model Feature 0General information on the memory model and memory management support"
|
|
repeat.end
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature 2General information on the memory model and memory management support"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED28,Software should not rely on the value of a reserved"
|
|
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bitfld.long 0x00 24. "WAIT_FOR_INTERRUPT_STALLING,wait for interrupt stalling0x0: Not supported0x1: Wait for interrupt supported" "Not supported,Wait for interrupt supported"
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hexmask.long.tbyte 0x00 0.--23. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
repeat 5. (list 0. 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0xD60)++0x03
|
|
line.long 0x00 "ID_ISAR$1,ISA Feature 0Information on the instruction set attributes register"
|
|
repeat.end
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access ControlThis register specifies the access privileges for coprocessors"
|
|
rgroup.long 0xD90++0x2B
|
|
line.long 0x00 "MPU_TYPE,MPU TypeThis register indicates many regions the MPU supports"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Reads 0"
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|
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hexmask.long.byte 0x00 16.--23. 1. "IREGION,The processor core uses only a unified MPU this field always reads 0x0"
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hexmask.long.byte 0x00 8.--15. 1. "DREGION,Number of supported MPU regions field"
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hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Reads 0"
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bitfld.long 0x00 0. "SEPARATE,The processor core uses only a unified MPU thus this field is always 0" "0,1"
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|
line.long 0x04 "MPU_CTRL,MPU ControlThis register is used to enable the MPU. enable the default memory map (background region). and enable the MPU when in Hard Fault. Non-maskable Interrupt (NMI). and FAULTMASK escalated handlers"
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hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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bitfld.long 0x04 2. "PRIVDEFENA,This bit enables the default memory map for privileged access as a background region when the MPU is enabled" "0,1"
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bitfld.long 0x04 1. "HFNMIENA,This bit enables the MPU when in Hard Fault NMI and FAULTMASK escalated handlers" "0,1"
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bitfld.long 0x04 0. "ENABLE,Enable MPU0: MPU disabled1: MPU enabled" "MPU disabled,MPU enabled"
|
|
line.long 0x08 "MPU_RNR,MPU Region NumberThis register is used to select which protection region is accessed"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
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hexmask.long.byte 0x08 0.--7. 1. "REGION,Region select field"
|
|
line.long 0x0C "MPU_RBAR,MPU Region Base AddressThis register writes the base address of a region"
|
|
hexmask.long 0x0C 5.--31. 1. "ADDR,Region base address field"
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newline
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bitfld.long 0x0C 4. "VALID,MPU region number valid:0: MPU_RNR remains unchanged and is interpreted.1: MPU_RNR is overwritten by REGION" "MPU_RNR remains unchanged and is interpreted,MPU_RNR is overwritten by REGION"
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newline
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bitfld.long 0x0C 0.--3. "REGION,MPU region override field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x10 "MPU_RASR,MPU Region Attribute and SizeThis register controls the MPU access permissions"
|
|
bitfld.long 0x10 29.--31. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 28. "XN,Instruction access disable:0: Enable instruction" "Enable instruction fetches,Disable instruction fetches"
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|
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bitfld.long 0x10 27. "RESERVED27,Software should not rely on the value of a reserved" "0,1"
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|
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bitfld.long 0x10 24.--26. "AP,Data access permission:0x0: Priviliged permissions: No access" "Priviliged permissions,Priviliged permissions,Priviliged permissions,Priviliged permissions,Reserved,Priviliged permissions,Priviliged permissions,Priviliged permissions"
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bitfld.long 0x10 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
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|
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bitfld.long 0x10 19.--21. "TEX,Type extension" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 18. "S,Shareable bit:0: Not shareable1: Shareable" "Not shareable,Shareable"
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|
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|
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bitfld.long 0x10 17. "C,Cacheable bit:0: Not" "Not cacheable,Cacheable"
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|
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|
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bitfld.long 0x10 16. "B,Bufferable bit:0: Not bufferable1: Bufferable" "Not bufferable,Bufferable"
|
|
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|
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hexmask.long.byte 0x10 8.--15. 1. "SRD,Sub-Region Disable field:Setting a bit in this field disables the corresponding sub-region"
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bitfld.long 0x10 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
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|
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bitfld.long 0x10 1.--5. "SIZE,MPU Protection Region Size" "?,?,?,?,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
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|
newline
|
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bitfld.long 0x10 0. "ENABLE,Region enable bit:0: Disable region" "Disable region,Enable region"
|
|
line.long 0x14 "MPU_RBAR_A1,MPU Alias 1 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x18 "MPU_RASR_A1,MPU Alias 1 Region Attribute and SizeAlias for MPU_RASR"
|
|
line.long 0x1C "MPU_RBAR_A2,MPU Alias 2 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x20 "MPU_RASR_A2,MPU Alias 2 Region Attribute and SizeAlias for MPU_RASR"
|
|
line.long 0x24 "MPU_RBAR_A3,MPU Alias 3 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x28 "MPU_RASR_A3,MPU Alias 3 Region Attribute and SizeAlias for MPU_RASR"
|
|
group.long 0xDF0++0x0F
|
|
line.long 0x00 "DHCSR,Debug Halting Control and StatusThe purpose of this register is to provide status information about the state of the processor. enable core debug. halt and step the processor"
|
|
bitfld.long 0x00 26.--31. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 25. "S_RESET_ST,Indicates that the core has been reset or is now being reset since the last time this bit was" "0,1"
|
|
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|
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bitfld.long 0x00 24. "S_RETIRE_ST,Indicates that an instruction has completed since last" "0,1"
|
|
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|
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bitfld.long 0x00 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 19. "S_LOCKUP,Reads as one if the core is running (not halted) and a lockup condition is present.When writing to this register 1 must be written this bit-field otherwise the write operation is ignored and no bits are written into the register" "0,1"
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|
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|
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bitfld.long 0x00 18. "S_SLEEP,Indicates that the core is sleeping (WFI WFE or **SLEEP-ON-EXIT**)" "0,1"
|
|
newline
|
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bitfld.long 0x00 17. "S_HALT,The core is in debug state when this bit is set.When writing to this register 1 must be written this bit-field otherwise the write operation is ignored and no bits are written into the register" "0,1"
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|
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|
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bitfld.long 0x00 16. "S_REGRDY,Register Read/Write on the Debug Core Register Selector register is available" "0,1"
|
|
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|
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hexmask.long.word 0x00 6.--15. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
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|
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bitfld.long 0x00 5. "C_SNAPSTALL,If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete" "0,1"
|
|
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|
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bitfld.long 0x00 4. "RESERVED4,Software should not rely on the value of a reserved" "0,1"
|
|
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|
|
bitfld.long 0x00 3. "C_MASKINTS,Mask interrupts when stepping or running in halted debug" "0,1"
|
|
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|
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bitfld.long 0x00 2. "C_STEP,Steps the core in halted debug" "0,1"
|
|
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|
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bitfld.long 0x00 1. "C_HALT,Halts the core" "0,1"
|
|
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|
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bitfld.long 0x00 0. "C_DEBUGEN,Enables debug" "0,1"
|
|
line.long 0x04 "DCRSR,Deubg Core Register SelectorThe purpose of this register is to select the processor register to transfer data to or from"
|
|
hexmask.long.word 0x04 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 16. "REGWNR," "0,1"
|
|
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|
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hexmask.long.word 0x04 5.--15. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "REGSEL,Register select0x00: R00x01: R10x02: R20x03: R30x04: R40x05: R50x06: R60x07: R70x08: R80x09: R90x0A: R100x0B: R110x0C: R120x0D: Current SP0x0E: LR0x0F" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,XPSR/flags..,MSP (Main SP),PSP (Process SP),?,CONTROL<<24 |..,?..."
|
|
line.long 0x08 "DCRDR,Debug Core Register Data"
|
|
line.long 0x0C "DEMCR,Debug Exception and Monitor ControlThe purpose of this register is vector catching and debug monitor control"
|
|
hexmask.long.byte 0x0C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 24. "TRCENA,This bit must be set to 1 to enable use of the trace and debug blocks: DWT ITM ETM and TPIU" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 19. "MON_REQ,This enables the monitor to identify how it wakes up" "Woken up by debug exception,Woken up by MON_PEND"
|
|
newline
|
|
bitfld.long 0x0C 18. "MON_STEP,When MON_EN = 1 this steps the core" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 17. "MON_PEND,Pend the monitor to activate when priority permits" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. "MON_EN,Enable the debug monitor" "0,1"
|
|
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|
|
bitfld.long 0x0C 11.--15. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 10. "VC_HARDERR,Debug trap on Hard Fault" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "VC_INTERR,Debug trap on a fault occurring during an exception entry or return sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "VC_BUSERR,Debug Trap on normal Bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 7. "VC_STATERR,Debug trap on Usage Fault state errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "VC_CHKERR,Debug trap on Usage Fault enabled checking errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "VC_NOCPERR,Debug trap on a UsageFault access to a Coprocessor" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "VC_MMERR,Debug trap on Memory Management faults" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0C 0. "VC_CORERESET,Reset Vector Catch" "0,1"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID field"
|
|
group.long 0xF34++0x13
|
|
line.long 0x00 "FPCCR,Floating Point Context ControlThis register holds control data for the floating-point unit"
|
|
bitfld.long 0x00 31. "ASPEN,Automatic State Preservation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "LSPEN,Lazy State Preservation enable" "Disable automatic lazy state preservation for..,Enable automatic lazy state preservation for.."
|
|
newline
|
|
hexmask.long.tbyte 0x00 9.--29. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "MONRDY,Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending.0: DebugMonitor is disabled or priority did not permit setting DEMCR.MON_PEND when the.." "DebugMonitor is disabled or priority did not..,DebugMonitor is enabled and priority permits.."
|
|
newline
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bitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "BFRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending.0: BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when.." "BusFault is disabled or priority did not permit..,BusFault is enabled and priority permitted.."
|
|
newline
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bitfld.long 0x00 5. "MMRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending.0: MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when.." "MemManage is disabled or priority did not permit..,MemManage is enabled and priority permitted.."
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|
newline
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bitfld.long 0x00 4. "HFRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending.0: Priority did not permit setting the HardFault handler to the pending state when the floating-point stack.." "Priority did not permit setting the HardFault..,Priority permitted setting the HardFault handler.."
|
|
newline
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|
bitfld.long 0x00 3. "THREAD,Indicates the processor mode was Thread when it allocated the FP stack frame.0: Mode was not Thread Mode when the floating-point stack frame was allocated.1: Mode was Thread Mode when the floating-point stack frame was allocated" "Mode was not Thread Mode when the floating-point..,Mode was Thread Mode when the floating-point.."
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "USER,Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame:0: Privilege level was not user when the floating-point stack frame was allocated.1: Privilege level was user when the.." "Privilege level was not user when the..,Privilege level was user when the floating-point.."
|
|
newline
|
|
bitfld.long 0x00 0. "LSPACT,Indicates whether Lazy preservation of the FP state is active:0: Lazy state preservation is not active.1: Lazy state preservation is active" "Lazy state preservation is not active,Lazy state preservation is active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address This register holds the location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
hexmask.long 0x04 2.--31. 1. "ADDRESS,Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
newline
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bitfld.long 0x04 0.--1. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
line.long 0x08 "FPDSCR,Floating Point Default Status ControlThis register holds the default values for the floating-point status control data that the processor assigns to the FPSCR when it creates a new floating-point context"
|
|
bitfld.long 0x08 27.--31. "RESERVED27,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 26. "AHP,Default value for Alternative Half Precision bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. "DN,Default value for Default NaN mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 24. "FZ,Default value for Flush-to-Zero mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22.--23. "RMODE,Default value for Rounding Mode control field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--21. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "MVFR0,Media and FP Feature 0Describes the features provided by the Floating-point extension"
|
|
bitfld.long 0x0C 28.--31. "FP_ROUNDING_MODES,Indicates the rounding modes supported by the FP floating-point hardware" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 24.--27. "SHORT_VECTORS,Indicates the hardware support for FP short vectors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x0C 20.--23. "SQUARE_ROOT,Indicates the hardware support for FP square root operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x0C 16.--19. "DIVIDE,Indicates the hardware support for FP divide operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 12.--15. "FP_EXCEPTION_TRAPPING,Indicates whether the FP hardware implementation supports exception trapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 8.--11. "DOUBLE_PRECISION,Indicates the hardware support for FP double-precision operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 4.--7. "SINGLE_PRECISION,Indicates the hardware support for FP single-precision operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "A_SIMD,Indicates the size of the FP register bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "MVFR1,Media and FP Feature 1Describes the features provided by the Floating-point extension"
|
|
bitfld.long 0x10 28.--31. "FP_FUSED_MAC,Indicates whether the FP supports fused multiply accumulate operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 24.--27. "FP_HPFP,Indicates whether the FP supports half-precision floating-point conversion operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x10 8.--23. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 4.--7. "D_NAN_MODE,Indicates whether the FP hardware implementation supports only the Default NaN mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x10 0.--3. "FTZ_MODE,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_TIPROP"
|
|
base ad:0xE00FE000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RESERVED000,Software should not rely on the value of a reserved"
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "TRACECLKMUX,Internal"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x00 0. "TRACECLK_N_SWV,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
tree.end
|
|
tree "CPU_TPIU"
|
|
base ad:0xE0040000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "SSPSR,Supported Sync Port SizesThis register represents a single port size that is supported on the device. that is. 4. 2 or 1"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "FOUR,4-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 2. "THREE,3-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 1. "TWO,2-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 0. "ONE,1-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
line.long 0x04 "CSPSR,Current Sync Port SizeThis register has the same format as SSPSR but only one bit can be set. and all others must be zero"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 3. "FOUR,4-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "THREE,3-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
bitfld.long 0x04 1. "TWO,2-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "ONE,1-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ACPR,Async Clock PrescalerThis register scales the baud rate of the asynchronous output"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x00 0.--12. 1. "PRESCALER,Divisor for input trace clock is (PRESCALER + 1)"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "SPPR,Selected Pin ProtocolThis register selects the protocol to be used for trace output"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--1. "PROTOCOL,Trace output protocol" "TracePort mode,SerialWire Output (Manchester). This is the..,SerialWire Output (NRZ),?"
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "FFSR,Formatter and Flush Status"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "FTNONSTOP," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RESERVED0,This field always reads as zero" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FFCR,Formatter and Flush ControlWhen one of the two single wire output (SWO) modes is selected. ENFCONT enables the formatter to be bypassed"
|
|
hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "TRIGIN,Indicates that triggers are inserted when a trigger pin is asserted" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 1. "ENFCONT,Enable continuous formatting:0: Continuous formatting disabled1: Continuous formatting enabled" "Continuous formatting disabled,Continuous formatting enabled"
|
|
newline
|
|
bitfld.long 0x04 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x08 "FSCR,Formatter Synchronization Counter"
|
|
rgroup.long 0xFA0++0x03
|
|
line.long 0x00 "CLAIMMASK,Claim Tag Mask"
|
|
wgroup.long 0xFA0++0x07
|
|
line.long 0x00 "CLAIMSET,Claim Tag Set"
|
|
line.long 0x04 "CLAIMTAG,Current Claim Tag"
|
|
wgroup.long 0xFA4++0x03
|
|
line.long 0x00 "CLAIMCLR,Claim Tag Clear"
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVID,Device ID"
|
|
tree.end
|
|
tree.end
|
|
tree "CRYPTO"
|
|
base ad:0x40024000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DMACH0CTL,Channel 0 ControlThis register is used for channel enabling and priority selection"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "PRIO,Channel priority0: Low1: HighIf both channels have the same priority access of the channels to the external port is arbitrated using the round robin scheme" "Low,HighIf.."
|
|
newline
|
|
bitfld.long 0x00 0. "EN,Channel enable0: Disabled1: EnableNote: Disabling an active channel interrupts the DMA operation" "Disabled,Enable"
|
|
line.long 0x04 "DMACH0EXTADDR,Channel 0 External Address"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMACH0LEN,Channel 0 DMA Length"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DMALEN,Channel DMA length in bytesDuring configuration this register contains the DMA transfer length in bytes"
|
|
rgroup.long 0x18++0x0F
|
|
line.long 0x00 "DMASTAT,DMAC StatusThis register provides the actual state of each DMA channel"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 17. "PORT_ERR,Reflects possible transfer errors on the AHB port" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--16. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_ACT,A value of 1 indicates that channel 1 is active (DMA transfer on-going)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CH0_ACT,A value of 1 indicates that channel 0 is active (DMA transfer on-going)" "0,1"
|
|
line.long 0x04 "DMASWRESET,DMAC Software ResetSoftware reset is used to reset the DMAC to stop all transfers and clears the port error status register"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "SWRES,Software reset enable0 : Disabled1 : Enabled (self-cleared to 0)Completion of the software reset must be checked through the DMASTAT" "Disabled,Enabled (self-cleared.."
|
|
line.long 0x08 "DMACH1CTL,Channel 1 ControlThis register is used for channel enabling and priority selection"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "PRIO,Channel priority0: Low1: HighIf both channels have the same priority access of the channels to the external port is arbitrated using the round robin scheme" "Low,HighIf.."
|
|
newline
|
|
bitfld.long 0x08 0. "EN,Channel enable0: Disabled1: EnableNote: Disabling an active channel interrupts the DMA operation" "Disabled,Enable"
|
|
line.long 0x0C "DMACH1EXTADDR,Channel 1 External Address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMACH1LEN,Channel 1 DMA Length"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DMALEN,Channel DMA length in bytes.During configuration this register contains the DMA transfer length in bytes"
|
|
group.long 0x78++0x07
|
|
line.long 0x00 "DMABUSCFG,DMAC Master Run-time ParametersThis register defines all the run-time parameters for the AHB master interface port"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "AHB_MST1_BURST_SIZE,Maximum burst size that can be performed on the AHB bus" "?,?,4 bytes,8 bytes ,16 bytes ,32 bytes ,64 bytes ,?,?,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x00 11. "AHB_MST1_IDLE_EN,Idle insertion between consecutive burst transfers on AHB" "Do not insert idle transfers.,Idle transfer insertion enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "AHB_MST1_INCR_EN,Burst length type of AHB transfer" "Unspecified length burst transfers,Fixed length bursts or single transfers"
|
|
newline
|
|
bitfld.long 0x00 9. "AHB_MST1_LOCK_EN,Locked transform on AHB" "Transfers are not locked,Transfers are locked"
|
|
newline
|
|
bitfld.long 0x00 8. "AHB_MST1_BIGEND,Endianess for the AHB master" "Little Endian,Big Endian"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "DMAPORTERR,DMAC Port Error Raw StatusThis register provides the actual status of individual port errors"
|
|
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 12. "PORT1_AHB_ERROR,A value of 1 indicates that the EIP-101 has detected an AHB bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 9. "PORT1_CHANNEL,Indicates which channel has serviced last (channel 0 or channel 1) by AHB master port" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 0.--8. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "DMAHWVER,DMAC VersionThis register contains an indication (or signature) of the EIP type of this DMAC. as well as the hardware version/patch numbers"
|
|
bitfld.long 0x00 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "HW_MAJOR_VERSION,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "HW_MINOR_VERSION,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HW_PATCH_LEVEL,Patch levelStarts at 0 at first delivery of this version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "EIP_NUMBER_COMPL,Bit-by-bit complement of the EIP_NUMBER field bits"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EIP_NUMBER,Binary encoding of the EIP-number of this DMA controller (209)"
|
|
group.long 0x400++0x0F
|
|
line.long 0x00 "KEYWRITEAREA,Key Store Write AreaThis register defines where the keys should be written in the key store RAM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "RAM_AREA7,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA7 is not selected to be written.1: RAM_AREA7 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA7 is not selected to be written,RAM_AREA7 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 6. "RAM_AREA6,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA6 is not selected to be written.1: RAM_AREA6 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA6 is not selected to be written,RAM_AREA6 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 5. "RAM_AREA5,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA5 is not selected to be written.1: RAM_AREA5 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA5 is not selected to be written,RAM_AREA5 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 4. "RAM_AREA4,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA4 is not selected to be written.1: RAM_AREA4 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA4 is not selected to be written,RAM_AREA4 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 3. "RAM_AREA3,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA3 is not selected to be written.1: RAM_AREA3 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA3 is not selected to be written,RAM_AREA3 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 2. "RAM_AREA2,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA2 is not selected to be written.1: RAM_AREA2 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA2 is not selected to be written,RAM_AREA2 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 1. "RAM_AREA1,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA1 is not selected to be written.1: RAM_AREA1 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA1 is not selected to be written,RAM_AREA1 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 0. "RAM_AREA0,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA0 is not selected to be written.1: RAM_AREA0 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA0 is not selected to be written,RAM_AREA0 is selected to be written.Writing to.."
|
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line.long 0x04 "KEYWRITTENAREA,Key Store Written AreaThis register shows which areas of the key store RAM contain valid written keys.When a new key needs to be written to the key store. on a location that is already occupied by a valid key. this key area must be.."
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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bitfld.long 0x04 7. "RAM_AREA_WRITTEN7,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 6. "RAM_AREA_WRITTEN6,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 5. "RAM_AREA_WRITTEN5,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 4. "RAM_AREA_WRITTEN4,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 3. "RAM_AREA_WRITTEN3,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 2. "RAM_AREA_WRITTEN2,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 1. "RAM_AREA_WRITTEN1,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 0. "RAM_AREA_WRITTEN0,On read this bit returns the key area written status.This bit can be reset by writing a" "0,1"
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line.long 0x08 "KEYSIZE,Key Store SizeThis register defines the size of the keys that are written with DMA"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x08 0.--1. "SIZE,Key size:00: ReservedWhen writing this to this register the KEY_STORE_WRITTEN_AREA register is reset" "?,128 bits,192 bits,256 bits"
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line.long 0x0C "KEYREADAREA,Key Store Read AreaThis register selects the key store RAM area from where the key needs to be read that will be used for an AES operation"
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bitfld.long 0x0C 31. "BUSY,Key store operation busy status flag (read only):0: Operation is complete.1: Operation is not completed and the key store is busy" "Operation is complete,Operation is not completed and the key store is.."
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hexmask.long 0x0C 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 0.--3. "RAM_AREA,Selects the area of the key store RAM from where the key needs to be read that will be writen to the AES engineRAM_AREA:RAM areas RAM_AREA0 RAM_AREA2 RAM_AREA4 and RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes.Only RAM.." "RAM Area 0,RAM Area 1,RAM Area 2,RAM Area 3,RAM Area 4,RAM Area 5,RAM Area 6,RAM Area 7,No RAM,?,?,?,?,?,?,?"
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wgroup.long 0x500++0x03
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line.long 0x00 "AESKEY2,AES_KEY2_0 / AES_GHASH_H_IN_0Second Key / GHASH Key (internal. but clearable)The following registers are not accessible through the host for reading and writing"
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wgroup.long 0x510++0x03
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line.long 0x00 "AESKEY3,AES_KEY3_0 / AES_KEY2_4Third Key / Second Key (internal. but clearable)The following registers are not accessible through the host for reading and writing"
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group.long 0x540++0x03
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line.long 0x00 "AESIV,AES initialization vector registersThese registers are used to provide and read the IV from the AES engine"
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group.long 0x550++0x0F
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line.long 0x00 "AESCTL,AES ControlAES input/output buffer control and mode registerThis register specifies the AES mode of operation for the EIP-120t.Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0"
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rbitfld.long 0x00 31. "CONTEXT_READY,If 1 this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context" "0,1"
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bitfld.long 0x00 30. "SAVED_CONTEXT_RDY,If 1 this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the host to retrieve" "0,1"
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bitfld.long 0x00 29. "SAVE_CONTEXT,This bit indicates that an authentication TAG or result IV needs to be stored as a result context.Typically this bit must be set for authentication modes returning a TAG (CBC-MAC GCM and CCM) or for basic encryption modes that require.." "0,1"
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bitfld.long 0x00 28. "GCM_CCM_CONTINUE,Continue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase.Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation to continue processing from the.." "0,1"
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bitfld.long 0x00 27. "GET_DIGEST,Interrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation.Set this write-only signal to '1b' to interrupt GCM or CCM processing at the next full block (128 bits) boundary" "0,1"
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bitfld.long 0x00 26. "GCM_CCM_CONTINUE_AAD,Continue processing of an interrupted AES-GCM or AES-CCM operation in the AAD phase.Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation to continue processing from the next full.." "0,1"
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bitfld.long 0x00 25. "XCBC_MAC,Set to '1' to select AES-XCBC MAC mode.The direction bit must be set to '1' for this mode.Selecting this mode requires writing the length register" "0,1"
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bitfld.long 0x00 22.--24. "CCM_M,Defines M which indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one).Note: The EIP-120t always returns a 128-bit authentication field of which the M.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--21. "CCM_L,Defines L which indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18. "CCM,If set to 1 AES-CCM is selectedAES-CCM is a combined mode using AES for authentication and encryption.Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers.Note: The CTR mode bit in this register must.." "0,1"
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bitfld.long 0x00 16.--17. "GCM,Set these bits to 11 to select AES-GCM mode.AES-GCM is a combined mode using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption.Note: The CTR mode bit in this register must also be set to 1 to.." "No GCM mode,Reserved do not select,?..."
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bitfld.long 0x00 15. "CBC_MAC,Set to 1 to select AES-CBC MAC mode.The direction bit must be set to 1 for this mode.Selecting this mode requires writing the length register after all other registers" "0,1"
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bitfld.long 0x00 9.--14. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7.--8. "CTR_WIDTH,Specifies the counter width for AES-CTR mode00 = 32-bit counter01 = 64-bit counter10 = 96-bit counter11 = 128-bit counter" "32-bit counter,64-bit counter,?..."
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bitfld.long 0x00 6. "CTR,If set to 1 AES counter mode (CTR) is selected.Note: This bit must also be set for GCM and CCM when encryption/decryption is required" "0,1"
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bitfld.long 0x00 5. "CBC,If set to 1 cipher-block-chaining (CBC) mode is selected" "0,1"
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bitfld.long 0x00 3.--4. "KEY_SIZE,This read-only field specifies the key size.The key size is automatically configured when a new key is loaded through the key store module.00 = N/A - Reserved01 =" "N/A - Reserved,128-bit,?..."
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bitfld.long 0x00 2. "DIR,If set to 1 an encrypt operation is performed.If set to 0 a decrypt operation is performed.This bit must be written with a 1 when CBC-MAC is selected" "0,1"
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bitfld.long 0x00 1. "INPUT_READY,If 1 this status bit indicates that the 16-byte AES input buffer is empty" "0,1"
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bitfld.long 0x00 0. "OUTPUT_READY,If 1 this status bit indicates that an AES output block is available to be retrieved by the host.Writing 0 clears the bit to 0 and indicates that output data is read by the host" "0,1"
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line.long 0x04 "AESDATALEN0,AES Crypto Length 0 (LSW)These registers are used to write the Length values to the EIP-120t"
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line.long 0x08 "AESDATALEN1,AES Crypto Length 1 (MSW)These registers are used to write the Length values to the EIP-120t"
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bitfld.long 0x08 29.--31. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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hexmask.long 0x08 0.--28. 1. "C_LENGTH,C_LENGTH[60:32]Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes"
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line.long 0x0C "AESAUTHLEN,AES Authentication Length"
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repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
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rgroup.long ($2+0x560)++0x03
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line.long 0x00 "AESDATAOUT$1,Data Input/Output"
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repeat.end
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repeat 2. (list 0. 1. )(list 0x00 0x04 )
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wgroup.long ($2+0x560)++0x03
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line.long 0x00 "AESDATAIN$1,AES Data Input_Output 0The data registers are typically accessed through the DMA and not with host writes and/or reads"
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repeat.end
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wgroup.long 0x568++0x0B
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line.long 0x00 "AESDATAIN2,AES Data Input_Output 2The data registers are typically accessed via DMA and not with host writes and/or reads"
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line.long 0x04 "AESDATAIN3,AES Data Input_Output 3The data registers are typically accessed via DMA and not with host writes and/or reads"
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line.long 0x08 "AESTAGOUT,AES Tag Out 0The tag registers can be accessed via DMA or directly with host reads.These registers buffer the TAG from the EIP-120t"
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group.long 0x5D4++0x0B
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line.long 0x00 "AESCCMALNWRD,This register needs to be read and stored when an AES-CCM operation is interrupted"
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line.long 0x04 "AESBLKCNT0,This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations"
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line.long 0x08 "AESBLKCNT1,This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations"
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hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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hexmask.long 0x08 0.--24. 1. "AES_BLK_CNT_56_32,[56:32] of Internal block counter for AES GCM and CCM operations.These bits read the block count value that represents the number of blocks to go"
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repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
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wgroup.long ($2+0x604)++0x03
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line.long 0x00 "HASHDATAIN$1,HASH Data Input 1The data input registers should be used to provide input data to the hash module through the slave interface"
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repeat.end
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repeat 15. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
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wgroup.long ($2+0x644)++0x03
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line.long 0x00 "HASHDATAIN$1,HASH Data Input 17The data input registers should be used to provide input data to the hash module through the slave interface"
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repeat.end
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group.long 0x680++0x0F
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line.long 0x00 "HASHIOBUFCTRL,HASH Input_Output Buffer ControlThis register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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bitfld.long 0x00 7. "PAD_DMA_MESSAGE,Note: This bit must only be used when data is supplied through the DMA" "0,1"
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bitfld.long 0x00 6. "GET_DIGEST,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 5. "PAD_MESSAGE,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 3.--4. "RESERVED3,Write 0s and ignore on reading" "0,1,2,3"
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bitfld.long 0x00 2. "RFD_IN,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 1. "DATA_IN_AV,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 0. "OUTPUT_FULL,Indicates that the output buffer registers (HASHDIGESTn) are available for reading by the host.When this bit reads 0 the output buffer registers are released; the hash engine is allowed to write new data to it" "0,1"
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line.long 0x04 "HASHMODE,HASH Mode"
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hexmask.long 0x04 7.--31. 1. "RESERVED7,Write 0s and ignore on reading"
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bitfld.long 0x04 6. "SHA384_MODE,The host must write this bit with 1 prior to processing a SHA 384 session" "0,1"
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bitfld.long 0x04 5. "SHA512_MODE,The host must write this bit with 1 prior to processing a SHA 512 session" "0,1"
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bitfld.long 0x04 4. "SHA224_MODE,The host must write this bit with 1 prior to processing a SHA 224 session" "0,1"
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bitfld.long 0x04 3. "SHA256_MODE,The host must write this bit with 1 prior to processing a SHA 256 session" "0,1"
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bitfld.long 0x04 1.--2. "RESERVED1,Write 0s and ignore on reading" "0,1,2,3"
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bitfld.long 0x04 0. "NEW_HASH,When set to 1 it indicates that the hash engine must start processing a new hash session" "0,1"
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line.long 0x08 "HASHINLENL,HASH Input Length LSB"
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line.long 0x0C "HASHINLENH,HASH Input Length MSB"
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group.long 0x6C0++0x47
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line.long 0x00 "HASHDIGESTA,HASH Digest AThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x04 "HASHDIGESTB,HASH Digest BThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x08 "HASHDIGESTC,HASH Digest CThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x0C "HASHDIGESTD,HASH Digest DThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x10 "HASHDIGESTE,HASH Digest EThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x14 "HASHDIGESTF,HASH Digest FThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x18 "HASHDIGESTG,HASH Digest GThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x1C "HASHDIGESTH,HASH Digest HThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x20 "HASHDIGESTI,HASH Digest IThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x24 "HASHDIGESTJ,HASH Digest JThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x28 "HASHDIGESTK,HASH Digest KThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x2C "HASHDIGESTL,HASH Digest LThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x30 "HASHDIGESTM,HASH Digest MThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x34 "HASHDIGESTN,HASH Digest NThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x38 "HASHDIGESTO,HASH Digest 0The hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x3C "HASHDIGESTP,HASH Digest PThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x40 "ALGSEL,Algorithm SelectThis algorithm selection register configures the internal destination of the DMA controller"
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bitfld.long 0x40 31. "TAG,If this bit is cleared to 0 the DMA operation involves only data.If this bit is set the DMA operation includes a TAG (Authentication Result / Digest).For SHA-256 operation a DMA must be set up for both input data and TAG" "0,1"
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hexmask.long 0x40 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
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bitfld.long 0x40 3. "HASH_SHA_512,If set to one selects the hash engine in 512B mode as destination for the DMAThe maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out.." "0,1"
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bitfld.long 0x40 2. "HASH_SHA_256,If set to one selects the hash engine in 256B mode as destination for the DMAThe maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out.." "0,1"
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bitfld.long 0x40 1. "AES,If set to one selects the AES engine as source/destination for the DMAThe read and write maximum transfer size to the DMA engine is set to 16 bytes" "0,1"
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bitfld.long 0x40 0. "KEY_STORE,If set to one selects the Key Store as destination for the DMAThe maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16 24 and 32 bytes are allowed)" "0,1"
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line.long 0x44 "DMAPROTCTL,DMA Protection ControlMaster PROT privileged access enableThis register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys.."
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hexmask.long 0x44 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x44 0. "PROT_EN,Select AHB transfer protection control for DMA transfers using the key store area as destination.0 : transfers use 'USER' type access.1 : transfers use 'PRIVILEGED' type access" "transfers use 'USER' type access,transfers use 'PRIVILEGED' type access"
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group.long 0x740++0x03
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line.long 0x00 "SWRESET,Software Reset"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x00 0. "SW_RESET,If this bit is set to 1 the following modules are reset: - Master control internal state is reset" "0,1"
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group.long 0x780++0x13
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line.long 0x00 "IRQTYPE,Control Interrupt Configuration"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x00 0. "LEVEL,If this bit is 0 the interrupt output is a pulse.If this bit is set to 1 the interrupt is a level interrupt that must be cleared by writing the interrupt clear register.This bit is applicable for both interrupt output signals" "0,1"
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line.long 0x04 "IRQEN,Control Interrupt Enable"
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hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 1. "DMA_IN_DONE,If this bit is set to 0 the DMA input done interrupt disabledIf this bit is set to 1 the DMA input done interrupt enabled." "0,1"
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bitfld.long 0x04 0. "RESULT_AVAIL,If this bit is set to 0 the Result Available interrupt is disabledIf this bit is set to 1 the Result Available interrupt is enabled." "0,1"
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line.long 0x08 "IRQCLR,Control Interrupt Clear"
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bitfld.long 0x08 31. "DMA_BUS_ERR,If 1 is written to this bit the DMA bus error status is cleared.Writing 0 has no effect" "0,1"
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bitfld.long 0x08 30. "KEY_ST_WR_ERR,If 1 is written to this bit the key store write error status is cleared.Writing 0 has no effect" "0,1"
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bitfld.long 0x08 29. "KEY_ST_RD_ERR,If 1 is written to this bit the key store read error status is cleared.Writing 0 has no effect" "0,1"
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hexmask.long 0x08 2.--28. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x08 1. "DMA_IN_DONE,If 1 is written to this bit the DMA in done interrupt status is cleared.Writing 0 has no effect.Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE)." "0,1"
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bitfld.long 0x08 0. "RESULT_AVAIL,If 1 is written to this bit the result available interrupt status is cleared.Writing 0 has no effect.Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE)." "0,1"
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line.long 0x0C "IRQSET,Control Interrupt Set"
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hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 1. "DMA_IN_DONE,If 1 is written to this bit the DMA data in done interrupt is set.Writing 0 has no effect.If the interrupt configuration register is programmed to pulse clearing the DMA data in done interrupt is not needed" "0,1"
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|
|
bitfld.long 0x0C 0. "RESULT_AVAIL,If 1 is written to this bit the result available interrupt is setWriting 0 has no effect.If the interrupt configuration register is programmed to pulse clearing the result available interrupt is not needed" "0,1"
|
|
line.long 0x10 "IRQSTAT,Control Interrupt Status"
|
|
bitfld.long 0x10 31. "DMA_BUS_ERR,This bit is set when a DMA bus error is detected during a DMA operation" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "KEY_ST_WR_ERR,This bit is set when a write error is detected during the DMA write operation to the key store memory" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "KEY_ST_RD_ERR,This bit is set when a read error is detected during the read of a key from the key store while copying it to the AES core" "0,1"
|
|
newline
|
|
hexmask.long 0x10 2.--28. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 1. "DMA_IN_DONE,This read only bit returns the actual DMA data in done interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "RESULT_AVAIL,This read only bit returns the actual result available interrupt status" "0,1"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "HWVER,Hardware Version"
|
|
bitfld.long 0x00 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "HW_MAJOR_VER,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "HW_MINOR_VER,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HW_PATCH_LVL,Patch levelStarts at 0 at first delivery of this version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "VER_NUM_COMPL,These bits simply contain the complement of bits [7:0] (0x87) used by a driver to ascertain that the EIP-120t register is indeed"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VER_NUM,These bits encode the EIP number for the EIP-120t this field contains the value 120 (decimal) or 0x78"
|
|
tree.end
|
|
tree "EVENT"
|
|
base ad:0x40083000
|
|
rgroup.long 0x00++0xAB
|
|
line.long 0x00 "CPUIRQSEL0,Output Selection for CPU Interrupt 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x04 "CPUIRQSEL1,Output Selection for CPU Interrupt 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x08 "CPUIRQSEL2,Output Selection for CPU Interrupt 2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "CPUIRQSEL3,Output Selection for CPU Interrupt 3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "CPUIRQSEL4,Output Selection for CPU Interrupt 4"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "CPUIRQSEL5,Output Selection for CPU Interrupt 5"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "CPUIRQSEL6,Output Selection for CPU Interrupt 6"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "CPUIRQSEL7,Output Selection for CPU Interrupt 7"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "CPUIRQSEL8,Output Selection for CPU Interrupt 8"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "CPUIRQSEL9,Output Selection for CPU Interrupt 9"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x28 "CPUIRQSEL10,Output Selection for CPU Interrupt 10"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x2C "CPUIRQSEL11,Output Selection for CPU Interrupt 11"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x30 "CPUIRQSEL12,Output Selection for CPU Interrupt 12"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x34 "CPUIRQSEL13,Output Selection for CPU Interrupt 13"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x38 "CPUIRQSEL14,Output Selection for CPU Interrupt 14"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x3C "CPUIRQSEL15,Output Selection for CPU Interrupt 15"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x40 "CPUIRQSEL16,Output Selection for CPU Interrupt 16"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x44 "CPUIRQSEL17,Output Selection for CPU Interrupt 17"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x48 "CPUIRQSEL18,Output Selection for CPU Interrupt 18"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x4C "CPUIRQSEL19,Output Selection for CPU Interrupt 19"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x50 "CPUIRQSEL20,Output Selection for CPU Interrupt 20"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x54 "CPUIRQSEL21,Output Selection for CPU Interrupt 21"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x58 "CPUIRQSEL22,Output Selection for CPU Interrupt 22"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x5C "CPUIRQSEL23,Output Selection for CPU Interrupt 23"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x60 "CPUIRQSEL24,Output Selection for CPU Interrupt 24"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x64 "CPUIRQSEL25,Output Selection for CPU Interrupt 25"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x68 "CPUIRQSEL26,Output Selection for CPU Interrupt 26"
|
|
hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x68 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x6C "CPUIRQSEL27,Output Selection for CPU Interrupt 27"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x70 "CPUIRQSEL28,Output Selection for CPU Interrupt 28"
|
|
hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x70 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x74 "CPUIRQSEL29,Output Selection for CPU Interrupt 29"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x78 "CPUIRQSEL30,Output Selection for CPU Interrupt 30"
|
|
hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x78 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x7C "CPUIRQSEL31,Output Selection for CPU Interrupt 31"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x80 "CPUIRQSEL32,Output Selection for CPU Interrupt 32"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x84 "CPUIRQSEL33,Output Selection for CPU Interrupt 33"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x88 "CPUIRQSEL34,Output Selection for CPU Interrupt 34"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x8C "CPUIRQSEL35,Output Selection for CPU Interrupt 35"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x90 "CPUIRQSEL36,Output Selection for CPU Interrupt 36"
|
|
hexmask.long.tbyte 0x90 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x90 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x94 "CPUIRQSEL37,Output Selection for CPU Interrupt 37"
|
|
hexmask.long.tbyte 0x94 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x94 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x98 "CPUIRQSEL38,Output Selection for CPU Interrupt 38"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x9C "CPUIRQSEL39,Output Selection for CPU Interrupt 39"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA0 "CPUIRQSEL40,Output Selection for CPU Interrupt 40"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA4 "CPUIRQSEL41,Output Selection for CPU Interrupt 41"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA8 "CPUIRQSEL42,Output Selection for CPU Interrupt 42"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--7. 1. "EV,Read only selection value"
|
|
rgroup.long 0x100++0x27
|
|
line.long 0x00 "RFCSEL0,Output Selection for RFC Event 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x04 "RFCSEL1,Output Selection for RFC Event 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x08 "RFCSEL2,Output Selection for RFC Event 2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "RFCSEL3,Output Selection for RFC Event 3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "RFCSEL4,Output Selection for RFC Event 4"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "RFCSEL5,Output Selection for RFC Event 5"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "RFCSEL6,Output Selection for RFC Event 6"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "RFCSEL7,Output Selection for RFC Event 7"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "RFCSEL8,Output Selection for RFC Event 8"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "RFCSEL9,Output Selection for RFC Event 9"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "GPT0ACAPTSEL,Output Selection for GPT0 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT0BCAPTSEL,Output Selection for GPT0 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "GPT1ACAPTSEL,Output Selection for GPT1 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT1BCAPTSEL,Output Selection for GPT1 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "GPT2ACAPTSEL,Output Selection for GPT2 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT2BCAPTSEL,Output Selection for GPT2 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
rgroup.long 0x500++0x107
|
|
line.long 0x00 "UDMACH0SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "UDMACH0BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x08 "UDMACH1SSEL,Output Selection for DMA Channel 1 SREQ"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "UDMACH1BSEL,Output Selection for DMA Channel 1 REQ"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "UDMACH2SSEL,Output Selection for DMA Channel 2 SREQ"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "UDMACH2BSEL,Output Selection for DMA Channel 2 REQ"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "UDMACH3SSEL,Output Selection for DMA Channel 3 SREQ"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "UDMACH3BSEL,Output Selection for DMA Channel 3 REQ"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "UDMACH4SSEL,Output Selection for DMA Channel 4 SREQ"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "UDMACH4BSEL,Output Selection for DMA Channel 4 REQ"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x28 "UDMACH5SSEL,Output Selection for DMA Channel 5 SREQ"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x2C "UDMACH5BSEL,Output Selection for DMA Channel 5 REQ"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x30 "UDMACH6SSEL,Output Selection for DMA Channel 6 SREQ"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x34 "UDMACH6BSEL,Output Selection for DMA Channel 6 REQ"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x38 "UDMACH7SSEL,Output Selection for DMA Channel 7 SREQ"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x3C "UDMACH7BSEL,Output Selection for DMA Channel 7 REQ"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x40 "UDMACH8SSEL,Output Selection for DMA Channel 8 SREQSingle request is ignored for this channel"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x44 "UDMACH8BSEL,Output Selection for DMA Channel 8 REQ"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x48 "UDMACH9SSEL,Output Selection for DMA Channel 9 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x4C "UDMACH9BSEL,Output Selection for DMA Channel 9 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x50 "UDMACH10SSEL,Output Selection for DMA Channel 10 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x54 "UDMACH10BSEL,Output Selection for DMA Channel 10 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x58 "UDMACH11SSEL,Output Selection for DMA Channel 11 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x5C "UDMACH11BSEL,Output Selection for DMA Channel 11 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x60 "UDMACH12SSEL,Output Selection for DMA Channel 12 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x64 "UDMACH12BSEL,Output Selection for DMA Channel 12 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x68 "UDMACH13SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x6C "UDMACH13BSEL,Output Selection for DMA Channel 13 REQ"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x70 "UDMACH14SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x74 "UDMACH14BSEL,Output Selection for DMA Channel 14 REQ"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x78 "UDMACH15SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x7C "UDMACH15BSEL,Output Selection for DMA Channel 15 REQ"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x80 "UDMACH16SSEL,Output Selection for DMA Channel 16 SREQ"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x84 "UDMACH16BSEL,Output Selection for DMA Channel 16 REQ"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x88 "UDMACH17SSEL,Output Selection for DMA Channel 17 SREQ"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x8C "UDMACH17BSEL,Output Selection for DMA Channel 17 REQ"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x90 "UDMACH18SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x94 "UDMACH18BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x98 "UDMACH19SSEL,Output Selection for DMA Channel 19 SREQ"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x9C "UDMACH19BSEL,Output Selection for DMA Channel 19 REQ"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA0 "UDMACH20SSEL,Output Selection for DMA Channel 20 SREQ"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA4 "UDMACH20BSEL,Output Selection for DMA Channel 20 REQ"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA8 "UDMACH21SSEL,Output Selection for DMA Channel 21 SREQ"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xAC "UDMACH21BSEL,Output Selection for DMA Channel 21 REQ"
|
|
hexmask.long.tbyte 0xAC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xAC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB0 "UDMACH22SSEL,Output Selection for DMA Channel 22 SREQ"
|
|
hexmask.long.tbyte 0xB0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB4 "UDMACH22BSEL,Output Selection for DMA Channel 22 REQ"
|
|
hexmask.long.tbyte 0xB4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB8 "UDMACH23SSEL,Output Selection for DMA Channel 23 SREQ"
|
|
hexmask.long.tbyte 0xB8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xBC "UDMACH23BSEL,Output Selection for DMA Channel 23 REQ"
|
|
hexmask.long.tbyte 0xBC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC0 "UDMACH24SSEL,Output Selection for DMA Channel 24 SREQ"
|
|
hexmask.long.tbyte 0xC0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC4 "UDMACH24BSEL,Output Selection for DMA Channel 24 REQ"
|
|
hexmask.long.tbyte 0xC4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC8 "UDMACH25SSEL,Output Selection for DMA Channel 25 SREQ"
|
|
hexmask.long.tbyte 0xC8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xCC "UDMACH25BSEL,Output Selection for DMA Channel 25 REQ"
|
|
hexmask.long.tbyte 0xCC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD0 "UDMACH26SSEL,Output Selection for DMA Channel 26 SREQ"
|
|
hexmask.long.tbyte 0xD0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xD0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD4 "UDMACH26BSEL,Output Selection for DMA Channel 26 REQ"
|
|
hexmask.long.tbyte 0xD4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xD4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD8 "UDMACH27SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0xDC "UDMACH27BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0xE0 "UDMACH28SSEL,Output Selection for DMA Channel 28 SREQ"
|
|
hexmask.long.tbyte 0xE0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xE4 "UDMACH28BSEL,Output Selection for DMA Channel 28 REQ"
|
|
hexmask.long.tbyte 0xE4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xE8 "UDMACH29SSEL,Output Selection for DMA Channel 29 SREQ"
|
|
hexmask.long.tbyte 0xE8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xEC "UDMACH29BSEL,Output Selection for DMA Channel 29 REQ"
|
|
hexmask.long.tbyte 0xEC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xEC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF0 "UDMACH30SSEL,Output Selection for DMA Channel 30 SREQ"
|
|
hexmask.long.tbyte 0xF0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF4 "UDMACH30BSEL,Output Selection for DMA Channel 30 REQ"
|
|
hexmask.long.tbyte 0xF4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF8 "UDMACH31SSEL,Output Selection for DMA Channel 31 SREQ"
|
|
hexmask.long.tbyte 0xF8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xFC "UDMACH31BSEL,Output Selection for DMA Channel 31 REQ"
|
|
hexmask.long.tbyte 0xFC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xFC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x100 "GPT3ACAPTSEL,Output Selection for GPT3 0"
|
|
hexmask.long.tbyte 0x100 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x100 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x104 "GPT3BCAPTSEL,Output Selection for GPT3 1"
|
|
hexmask.long.tbyte 0x104 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x104 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "AUXSEL0,Output Selection for AUX Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "CM3NMISEL0,Output Selection for NMI Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "I2SSTMPSEL0,Output Selection for I2S Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "FRZSEL0,Output Selection for FRZ SubscriberThe halted debug signal is passed to peripherals such as the General Purpose Timer. Sensor Controller with Digital and Analog Peripherals (AUX). Radio. and RTC"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "SWEV,Set or Clear Software Events"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 24. "SWEV3,Writing '1' to this bit when the value is '0' triggers the Software 3 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "SWEV2,Writing '1' to this bit when the value is '0' triggers the Software 2 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "SWEV1,Writing '1' to this bit when the value is '0' triggers the Software 1 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "SWEV0,Writing '1' to this bit when the value is '0' triggers the Software 0 event" "0,1"
|
|
tree.end
|
|
tree "FCFG1"
|
|
base ad:0x50001000
|
|
repeat 4. (list 0. 4. 140. 324. )(list 0x00 0x04 0x150 0x324 )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "RESERVED_$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "MISC_CONF_1,Misc configurations"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DEVICE_MINOR_REV,HW minor revision number (a value of 0xFF shall be treated equally to 0x00).Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer.Value may change without warning"
|
|
line.long 0x04 "MISC_CONF_2,Internal"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "HPOSC_COMP_P3,Internal"
|
|
repeat 5. (list 5. 4. 3. 2. 1. )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0xB0)++0x03
|
|
line.long 0x00 "HPOSC_MEAS_$1,Internal"
|
|
hexmask.long.word 0x00 16.--31. 1. "HPOSC_D5,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "HPOSC_T5,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "HPOSC_DT5,Internal"
|
|
repeat.end
|
|
rgroup.long 0xC4++0x1B
|
|
line.long 0x00 "CONFIG_CC26_FE,Internal"
|
|
bitfld.long 0x00 28.--31. "IFAMP_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "LNA_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "IFAMP_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--18. "CTL_PA0_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13. "PATRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RSSITRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSSI_OFFSET,Internal"
|
|
line.long 0x04 "CONFIG_CC13_FE,Internal"
|
|
bitfld.long 0x04 28.--31. "IFAMP_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 24.--27. "LNA_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 19.--23. "IFAMP_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 14.--18. "CTL_PA0_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 13. "PATRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12. "RSSITRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8.--11. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "RSSI_OFFSET,Internal"
|
|
line.long 0x08 "CONFIG_RF_COMMON,Internal"
|
|
bitfld.long 0x08 31. "DISABLE_CORNER_CAP,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25.--30. "SLDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 22.--24. "RESERVED,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 21. "PA20DBMTRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16.--20. "CTL_PA_20DBM_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x08 9.--15. 1. "RFLDO_TRIM_OUTPUT,Internal"
|
|
newline
|
|
bitfld.long 0x08 6.--8. "QUANTCTLTHRES,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "DACTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CONFIG_SYNTH_DIV2_CC26_2G4,Internal"
|
|
bitfld.long 0x0C 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x0C 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x0C 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "CONFIG_SYNTH_DIV2_CC13_2G4,Internal"
|
|
bitfld.long 0x10 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x10 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x10 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x10 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "CONFIG_SYNTH_DIV2_CC26_1G,Internal"
|
|
bitfld.long 0x14 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x14 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x14 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x14 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "CONFIG_SYNTH_DIV2_CC13_1G,Internal"
|
|
bitfld.long 0x18 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x18 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x18 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x18 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xE0)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV4_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 4. (list 5. 10. 15. 30. )(list 0x00 0x0C 0x18 0x1C )
|
|
rgroup.long ($2+0xE8)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xEC)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV6_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xF8)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV12_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "IOCONF,IO Configuration"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "GPIO_CNT,Number of available DIOs."
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "USER_ID,User Identification.Reading this register and the FCFG1:ICEPICK_DEVICE_ID register is the only supported way of identifying a device.The value of this register will be written to AON_PMCTL:JTAGUSERCODE by boot FW while in safezone"
|
|
bitfld.long 0x00 28.--31. "PG_REV,Field used to distinguish revisions of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "VER,Version number.0x0: Bits [25:12] of this register has the stated meaning.Any other setting indicate a different encoding of these bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 25. "PA," "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED24,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CC13," "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "SEQUENCE,Sequence.Used to differentiate between marketing/orderable product where other fields of this register are the same (temp range flash size voltage range etc)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PKG,Package type.0x0: 4x4mm QFN (RHB) package0x1: 5x5mm QFN (RSM) package0x2: 7x7mm QFN (RGZ) package0x3: Wafer sale package (naked" "4x4mm QFN (RHB) package,5x5mm QFN (RSM) package,7x7mm QFN (RGZ) package,Wafer sale package (naked die),WCSP (YFV),7x7mm QFN package with Wettable FlanksOther..,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PROTOCOL,Protocols supported.0x1: BLE" "?,BLE,RF4CE,?,Zigbee/6lowpan,?,?,?,ProprietaryMore than..,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
rgroup.long 0x2B0++0x0B
|
|
line.long 0x00 "FLASH_OTP_DATA3,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FLASH_SIZE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "ANA2_TRIM,Internal"
|
|
bitfld.long 0x04 31. "RCOSCHFCTRIMFRACT_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 26.--30. "RCOSCHFCTRIMFRACT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 25. "RESERVED0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 23.--24. "SET_RCOSC_HF_FINE_RESISTOR,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 22. "ATESTLF_UDIGLDO_IBIAS_TRIM,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 15.--21. 1. "NANOAMP_RES_TRIM,Internal"
|
|
newline
|
|
bitfld.long 0x04 12.--14. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 11. "DITHER_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8.--10. "DCDC_IPEAK,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 6.--7. "DEAD_TIME_TRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 3.--5. "DCDC_LOW_EN_SEL,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "DCDC_HIGH_EN_SEL,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "LDO_TRIM,Internal"
|
|
bitfld.long 0x08 29.--31. "RESERVED4,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 24.--28. "VDDR_TRIM_SLEEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 19.--23. "RESERVED3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 16.--18. "GLDO_CURSRC,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 13.--15. "RESERVED2,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 11.--12. "ITRIM_DIGLDO_LOAD,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 8.--10. "ITRIM_UDIGLDO,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 3.--7. "RESERVED1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "VTRIM_DELTA,Internal" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2E8++0x0F
|
|
line.long 0x00 "MAC_BLE_0,MAC BLE Address 0"
|
|
line.long 0x04 "MAC_BLE_1,MAC BLE Address 1"
|
|
line.long 0x08 "MAC_15_4_0,MAC IEEE 802.15.4 Address 0"
|
|
line.long 0x0C "MAC_15_4_1,MAC IEEE 802.15.4 Address 1"
|
|
rgroup.long 0x30C++0x07
|
|
line.long 0x00 "MISC_TRIM,Miscellaneous Trim Parameters"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--16. "TRIM_RECHARGE_COMP_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TRIM_RECHARGE_COMP_REFLEVEL,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEMPVSLOPE,Signed byte value representing the TEMP slope with battery voltage in degrees C / V with four fractional bits"
|
|
line.long 0x04 "RCOSC_HF_TEMPCOMP,Internal"
|
|
hexmask.long.byte 0x04 24.--31. 1. "FINE_RESISTOR,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. "CTRIM,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "CTRIMFRACT_QUAD,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "CTRIMFRACT_SLOPE,Internal"
|
|
rgroup.long 0x318++0x0B
|
|
line.long 0x00 "ICEPICK_DEVICE_ID,IcePick Device IdentificationReading this register and the FCFG1:USER_ID register is the only supported way of identifying a device"
|
|
bitfld.long 0x00 28.--31. "PG_REV,Field used to distinguish revisions of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "WAFER_ID,Field used to identify silicon die"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "MANUFACTURER_ID,Manufacturer"
|
|
line.long 0x04 "FCFG1_REVISION,Factory Configuration (FCFG1) Revision"
|
|
line.long 0x08 "MISC_OTP_DATA,Misc OTP Data"
|
|
bitfld.long 0x08 28.--31. "RCOSC_HF_ITUNE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x08 20.--27. 1. "RCOSC_HF_CRIM,Internal"
|
|
newline
|
|
bitfld.long 0x08 15.--19. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 12.--14. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
rgroup.long 0x34C++0x07
|
|
line.long 0x00 "CONFIG_IF_ADC,Internal"
|
|
bitfld.long 0x00 28.--31. "FF2ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FF3ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "INT3ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "FF1ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "AAFCAP,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--13. "INT2ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "IFDIGLDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 0.--4. "IFANALDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CONFIG_OSC_TOP,Internal"
|
|
bitfld.long 0x04 30.--31. "RESERVED,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 26.--29. "XOSC_HF_ROW_Q12,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x04 10.--25. 1. "XOSC_HF_COLUMN_Q12,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 2.--9. 1. "RCOSCLF_CTUNE_TRIM,Internal"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RCOSCLF_RTUNE_TRIM,Internal" "0,1,2,3"
|
|
rgroup.long 0x35C++0x07
|
|
line.long 0x00 "SOC_ADC_ABS_GAIN,AUX_ADC Gain in Absolute Reference Mode"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "SOC_ADC_ABS_GAIN_TEMP1,SOC_ADC gain in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REL_GAIN,AUX_ADC Gain in Relative Reference Mode"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "SOC_ADC_REL_GAIN_TEMP1,SOC_ADC gain in relative reference mode at temperature 1 (30C)"
|
|
rgroup.long 0x368++0x17
|
|
line.long 0x00 "SOC_ADC_OFFSET_INT,AUX_ADC Temperature Offsets in Absolute Reference Mode"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "SOC_ADC_REL_OFFSET_TEMP1,SOC_ADC offset in relative reference mode at temperature 1 (30C)"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SOC_ADC_ABS_OFFSET_TEMP1,SOC_ADC offset in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REF_TRIM_AND_OFFSET_EXT,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "SOC_ADC_REF_VOLTAGE_TRIM_TEMP1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "AMPCOMP_TH1,Internal"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED1,Internal"
|
|
newline
|
|
bitfld.long 0x08 18.--23. "HPMRAMP3_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 16.--17. "RESERVED0,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 10.--15. "HPMRAMP3_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
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|
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bitfld.long 0x08 6.--9. "IBIASCAP_LPTOHP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x08 0.--5. "HPMRAMP1_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "AMPCOMP_TH2,Internal"
|
|
bitfld.long 0x0C 26.--31. "LPMUPDATE_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 24.--25. "RESERVED3,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 18.--23. "LPMUPDATE_HTM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x0C 16.--17. "RESERVED2,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 10.--15. "ADC_COMP_AMPTH_LPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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newline
|
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bitfld.long 0x0C 8.--9. "RESERVED1,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 2.--7. "ADC_COMP_AMPTH_HPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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newline
|
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bitfld.long 0x0C 0.--1. "RESERVED0,Internal" "0,1,2,3"
|
|
line.long 0x10 "AMPCOMP_CTRL1,Internal"
|
|
bitfld.long 0x10 31. "RESERVED1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "AMPCOMP_REQ_MODE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24.--29. "RESERVED0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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newline
|
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bitfld.long 0x10 20.--23. "IBIAS_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. "IBIAS_INIT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "LPM_IBIAS_WAIT_CNT_FINAL,Internal"
|
|
newline
|
|
bitfld.long 0x10 4.--7. "CAP_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 0.--3. "IBIASCAP_HPTOLP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "ANABYPASS_VALUE2,Internal"
|
|
hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.word 0x14 0.--13. 1. "XOSC_HF_IBIASTHERM,Internal"
|
|
rgroup.long 0x388++0x0B
|
|
line.long 0x00 "VOLT_TRIM,Internal"
|
|
bitfld.long 0x00 29.--31. "RESERVED3,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24.--28. "VDDR_TRIM_HH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 21.--23. "RESERVED2,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "VDDR_TRIM_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "VDDR_TRIM_SLEEP_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED0,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "TRIMBOD_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "OSC_CONF,OSC Configuration"
|
|
bitfld.long 0x04 30.--31. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 29. "ADC_SH_VBUF_EN,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x04 28. "ADC_SH_MODE_EN,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x04 27. "ATESTLF_RCOSCLF_IBIAS_TRIM,Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM" "0,1"
|
|
newline
|
|
bitfld.long 0x04 25.--26. "XOSCLF_REGULATOR_TRIM,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 21.--24. "XOSCLF_CMIRRWR_RATIO,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 19.--20. "XOSC_HF_FAST_START,Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 18. "XOSC_OPTION," "0,1"
|
|
newline
|
|
bitfld.long 0x04 17. "HPOSC_OPTION,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "HPOSC_BIAS_HOLD_MODE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12.--15. "HPOSC_CURRMIRR_RATIO,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. "HPOSC_BIAS_RES_SET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. "HPOSC_FILTER_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5.--6. "HPOSC_BIAS_RECHARGE_DELAY,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 3.--4. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 1.--2. "HPOSC_SERIES_CAP,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0. "HPOSC_DIV3_BYPASS,Internal" "0,1"
|
|
line.long 0x08 "FREQ_OFFSET,Internal"
|
|
hexmask.long.word 0x08 16.--31. 1. "HPOSC_COMP_P0,Internal"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. "HPOSC_COMP_P1,Internal"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "HPOSC_COMP_P2,Internal"
|
|
rgroup.long 0x398++0x03
|
|
line.long 0x00 "MISC_OTP_DATA_1,Internal"
|
|
bitfld.long 0x00 29.--31. "RESERVED,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "PEAK_DET_ITRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "HP_BUF_ITRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "LP_BUF_ITRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DBLR_LOOP_FILTER_RESET_VOLTAGE,Internal" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "HPM_IBIAS_WAIT_CNT,Internal"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "LPM_IBIAS_WAIT_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "IDAC_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x3D0++0x0F
|
|
line.long 0x00 "SHDW_DIE_ID_0,Shadow of DIE_ID_0 register in eFuse"
|
|
line.long 0x04 "SHDW_DIE_ID_1,Shadow of DIE_ID_1 register in eFuse"
|
|
line.long 0x08 "SHDW_DIE_ID_2,Shadow of DIE_ID_2 register in eFuse"
|
|
line.long 0x0C "SHDW_DIE_ID_3,Shadow of DIE_ID_3 register in eFuse"
|
|
rgroup.long 0x3F8++0x07
|
|
line.long 0x00 "SHDW_SCAN_MCU3_SEC,Internal"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SECURITY,Internal"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 11.--22. 1. "ULL_MCU_RAM_0_REP,Internal"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "ULL_MCU_RAM_1_REP_1,Internal"
|
|
line.long 0x04 "SHDW_SCAN_DATA1_CRC,Internal"
|
|
bitfld.long 0x04 31. "FLASH_RDY,Internal" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x04 9.--30. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 1.--8. 1. "CRC,Internal"
|
|
newline
|
|
bitfld.long 0x04 0. "TAP_DAP_LOCK_N,Internal" "0,1"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "DAC_BIAS_CNF,Internal"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "LPM_TRIM_IOUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "LPM_BIAS_WIDTH_TRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "LPM_BIAS_BACKUP_EN,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED1,Internal"
|
|
rgroup.long 0x418++0x17
|
|
line.long 0x00 "TFW_PROBE,Internal"
|
|
line.long 0x04 "TFW_FT,Internal"
|
|
line.long 0x08 "DAC_CAL0,Internal"
|
|
hexmask.long.word 0x08 16.--31. 1. "SOC_DAC_VOUT_CAL_DECOUPLE_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "SOC_DAC_VOUT_CAL_DECOUPLE_C1,Internal"
|
|
line.long 0x0C "DAC_CAL1,Internal"
|
|
hexmask.long.word 0x0C 16.--31. 1. "SOC_DAC_VOUT_CAL_PRECH_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--15. 1. "SOC_DAC_VOUT_CAL_PRECH_C1,Internal"
|
|
line.long 0x10 "DAC_CAL2,Internal"
|
|
hexmask.long.word 0x10 16.--31. 1. "SOC_DAC_VOUT_CAL_ADCREF_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "SOC_DAC_VOUT_CAL_ADCREF_C1,Internal"
|
|
line.long 0x14 "DAC_CAL3,Internal"
|
|
hexmask.long.word 0x14 16.--31. 1. "SOC_DAC_VOUT_CAL_VDDS_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "SOC_DAC_VOUT_CAL_VDDS_C1,Internal"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "RESERVED_N,Software should not rely on the value of a reserved"
|
|
tree.end
|
|
tree "FLASH"
|
|
base ad:0x40030000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "WEPROT_B0_31_0_BY1,Internal"
|
|
line.long 0x04 "WEPROT_AUX_BY1,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x04 5. "WEPROT_B1_ENGR_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "WEPROT_B0_ENGR_BY1,Internal" "0,1"
|
|
bitfld.long 0x04 3. "WEPROT_B1_TRIM_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "WEPROT_B0_TRIM_BY1,Internal" "0,1"
|
|
bitfld.long 0x04 1. "WEPROT_B1_FCFG_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "WEPROT_B0_CCFG_BY1,Internal" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STAT,NW and Efuse Status"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "STALLSTAT,An ocp1 or ocp3 read stall has occurred.0 : No stall or stall acknowledged by writing a" "No stall or stall acknowledged by writing a 1,Stall condition occurred/occurringThis is a.."
|
|
newline
|
|
bitfld.long 0x00 15. "EFUSE_BLANK,Efuse scanning detected if fuse ROM is blank:0 : Not blank1 : Blank" "Not blank,Blank"
|
|
bitfld.long 0x00 14. "EFUSE_TIMEOUT,Efuse scanning resulted in timeout error.0 : No Timeout error1 : Timeout Error" "No Timeout error,Timeout Error"
|
|
newline
|
|
bitfld.long 0x00 13. "SPRS_BYTE_NOT_OK,Efuse scanning resulted in scan chain Sparse byte error.0 : No Sparse error1 : Sparse Error" "No Sparse error,Sparse Error"
|
|
rbitfld.long 0x00 8.--12. "EFUSE_ERRCODE,Same as EFUSEERROR.CODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED7,Software should not rely on the value of a reserved bit" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "BUSY,NW FW_SMSTAT.CMD_IN_PROGRESS bit.This flag is valid immediately after the operation setting it" "Not busy,BusyBit 4 is for the..,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "READY1T,1T access readiness status indicator from NW" "FLASH banks are not ready for 1T accesses,FLASH banks are ready for 1T accesses"
|
|
bitfld.long 0x00 2. "READY2T,2T access readiness status indicator from NW1: FLASH banks are ready for 2T accesses0: FLASH banks are not ready for 2T accesses" "FLASH banks are not ready for 2T accesses,FLASH banks are ready for 2T accesses"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "POWER_MODE,Power state of each of the 2 flash arbiter FSM instances in the flash sub-system" "Active,Ready for Low..,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFG,Internal"
|
|
bitfld.long 0x00 31. "RESERVED31,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x00 30. "DIS_FWTEST,Internal" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 12.--29. 1. "RESERVED12,Internal"
|
|
bitfld.long 0x00 11. "MAIN_STICKY_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CCFG_STICKY_EN,Internal" "0,1"
|
|
bitfld.long 0x00 9. "FCFG_STICKY_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ENGR_TRIM_STICKY_EN,Internal" "0,1"
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "DIS_EFUSECLK,Internal" "0,1"
|
|
bitfld.long 0x00 4. "DIS_READACCESS,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "BP_TRIMCFG_EN,Internal" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FLASH_SIZE,Internal"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED10,Internal"
|
|
bitfld.long 0x00 7.--9. "SECTORS,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "RESERVED0,Internal"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "FWLOCK,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x00 0.--2. "FWLOCK,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FWFLAG,Internal"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x04 0.--2. "FWFLAG,Internal" "0,1,2,3,4,5,6,7"
|
|
repeat 2. (list 3. 2. )(list 0x00 0x04 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "BANK0_TRIM_CFG_$1,Internal"
|
|
repeat.end
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "BANK0_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x00 28.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--27. "REDSWSELW3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "REDSWSELW2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. "REDSWSELW1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "REDSWSELW0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3. "REDSWENW3,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REDSWENW2,Internal" "0,1"
|
|
bitfld.long 0x00 1. "REDSWENW1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "REDSWENW0,Internal" "0,1"
|
|
line.long 0x04 "BANK0_TRIM_CFG_0,Internal"
|
|
repeat 2. (list 3. 2. )(list 0x00 0x04 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "BANK1_TRIM_CFG_$1,Internal"
|
|
repeat.end
|
|
group.long 0x68++0x13
|
|
line.long 0x00 "BANK1_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x00 28.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--27. "REDSWSELW3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "REDSWSELW2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. "REDSWSELW1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "REDSWSELW0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3. "REDSWENW3,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REDSWENW2,Internal" "0,1"
|
|
bitfld.long 0x00 1. "REDSWENW1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "REDSWENW0,Internal" "0,1"
|
|
line.long 0x04 "BANK1_TRIM_CFG_0,Internal"
|
|
line.long 0x08 "PUMP_TRIM_CFG_2,Internal"
|
|
bitfld.long 0x08 26.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--25. "VWLCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 14.--19. "VSLCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 9.--13. "VREADCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 4.--8. "VINLOWCCORCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--3. "VINHICCORCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "PUMP_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x0C 31. "VINHICCORCTLSB,Internal" "0,1"
|
|
bitfld.long 0x0C 25.--30. "VINHCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 20.--24. "VCGCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 15.--19. "IREFVRDCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 10.--14. "IREFTCCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 6.--9. "IREFCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 0.--5. "FOSCCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "PUMP_TRIM_CFG_0,Internal"
|
|
bitfld.long 0x10 30.--31. "RESERVED2,Internal" "0,1,2,3"
|
|
hexmask.long.word 0x10 20.--29. 1. "VHVCT_PV,Internal"
|
|
newline
|
|
hexmask.long.word 0x10 10.--19. 1. "VHVCT_PGM,Internal"
|
|
hexmask.long.word 0x10 0.--9. 1. "VHVCT_ERS,Internal"
|
|
group.long 0x1000++0x4F
|
|
line.long 0x00 "EFUSE,Internal"
|
|
rbitfld.long 0x00 29.--31. "RESERVED29,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "INSTRUCTION,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RESERVED16,Internal"
|
|
hexmask.long.word 0x00 0.--15. 1. "DUMPWORD,Internal"
|
|
line.long 0x04 "EFUSEADDR,Internal"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Internal"
|
|
bitfld.long 0x04 11.--15. "BLOCK,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x04 0.--10. 1. "ROW,Internal"
|
|
line.long 0x08 "DATAUPPER,Internal"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Internal"
|
|
bitfld.long 0x08 3.--7. "SPARE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "P,Internal" "0,1"
|
|
bitfld.long 0x08 1. "R,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "EEN,Internal" "0,1"
|
|
line.long 0x0C "DATALOWER,Internal"
|
|
line.long 0x10 "EFUSECFG,Internal"
|
|
hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x10 8. "IDLEGATING,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 5.--7. "RESERVED5,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 3.--4. "SLAVEPOWER,Internal" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x10 1.--2. "RESERVED1,Internal" "0,1,2,3"
|
|
bitfld.long 0x10 0. "GATING,Internal" "0,1"
|
|
line.long 0x14 "EFUSESTAT,Internal"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x14 0. "RESETDONE,Internal" "0,1"
|
|
line.long 0x18 "ACC,Internal"
|
|
hexmask.long.byte 0x18 24.--31. 1. "RESERVED24,Internal"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "ACCUMULATOR,Internal"
|
|
line.long 0x1C "BOUNDARY,Internal"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "RESERVED24,Internal"
|
|
bitfld.long 0x1C 23. "DISROW0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "SPARE,Internal" "0,1"
|
|
bitfld.long 0x1C 21. "EFC_SELF_TEST_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 20. "EFC_INSTRUCTION_INFO,Internal" "0,1"
|
|
bitfld.long 0x1C 19. "EFC_INSTRUCTION_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 18. "EFC_AUTOLOAD_ERROR,Internal" "0,1"
|
|
bitfld.long 0x1C 14.--17. "OUTPUTENABLE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 13. "SYS_ECC_SELF_TEST_EN,Internal" "0,1"
|
|
bitfld.long 0x1C 12. "SYS_ECC_OVERRIDE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "EFC_FDI,Internal" "0,1"
|
|
bitfld.long 0x1C 10. "SYS_DIEID_AUTOLOAD_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8.--9. "SYS_REPAIR_EN,Internal" "0,1,2,3"
|
|
bitfld.long 0x1C 4.--7. "SYS_WS_READ_STATES,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 0.--3. "INPUTENABLE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "EFUSEFLAG,Internal"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x20 0. "KEY,Internal" "0,1"
|
|
line.long 0x24 "EFUSEKEY,Internal"
|
|
line.long 0x28 "EFUSERELEASE,Internal"
|
|
hexmask.long.byte 0x28 25.--31. 1. "ODPYEAR,Internal"
|
|
bitfld.long 0x28 21.--24. "ODPMONTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x28 16.--20. "ODPDAY,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x28 9.--15. 1. "EFUSEYEAR,Internal"
|
|
newline
|
|
bitfld.long 0x28 5.--8. "EFUSEMONTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 0.--4. "EFUSEDAY,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "EFUSEPINS,Internal"
|
|
hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Internal"
|
|
bitfld.long 0x2C 15. "EFC_SELF_TEST_DONE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 14. "EFC_SELF_TEST_ERROR,Internal" "0,1"
|
|
bitfld.long 0x2C 13. "SYS_ECC_SELF_TEST_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 12. "EFC_INSTRUCTION_INFO,Internal" "0,1"
|
|
bitfld.long 0x2C 11. "EFC_INSTRUCTION_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 10. "EFC_AUTOLOAD_ERROR,Internal" "0,1"
|
|
bitfld.long 0x2C 9. "SYS_ECC_OVERRIDE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "EFC_READY,Internal" "0,1"
|
|
bitfld.long 0x2C 7. "EFC_FCLRZ,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 6. "SYS_DIEID_AUTOLOAD_EN,Internal" "0,1"
|
|
bitfld.long 0x2C 4.--5. "SYS_REPAIR_EN,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 0.--3. "SYS_WS_READ_STATES,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "EFUSECRA,Internal"
|
|
hexmask.long 0x30 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x30 0.--5. "DATA,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x34 "EFUSEREAD,Internal"
|
|
hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED10,Internal"
|
|
bitfld.long 0x34 8.--9. "DATABIT,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x34 4.--7. "READCLOCK,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 3. "DEBUG,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "SPARE,Internal" "0,1"
|
|
bitfld.long 0x34 0.--1. "MARGIN,Internal" "0,1,2,3"
|
|
line.long 0x38 "EFUSEPROGRAM,Internal"
|
|
rbitfld.long 0x38 31. "RESERVED31,Internal" "0,1"
|
|
bitfld.long 0x38 30. "COMPAREDISABLE,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x38 14.--29. 1. "CLOCKSTALL,Internal"
|
|
bitfld.long 0x38 13. "VPPTOVDD,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x38 9.--12. "ITERATIONS,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x38 0.--8. 1. "WRITECLOCK,Internal"
|
|
line.long 0x3C "EFUSEERROR,Internal"
|
|
hexmask.long 0x3C 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x3C 5. "DONE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 0.--4. "CODE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x40 "SINGLEBIT,Internal"
|
|
hexmask.long 0x40 1.--31. 1. "FROMN,Internal"
|
|
bitfld.long 0x40 0. "FROM0,Internal" "0,1"
|
|
line.long 0x44 "TWOBIT,Internal"
|
|
hexmask.long 0x44 1.--31. 1. "FROMN,Internal"
|
|
bitfld.long 0x44 0. "FROM0,Internal" "0,1"
|
|
line.long 0x48 "SELFTESTCYC,Internal"
|
|
line.long 0x4C "SELFTESTSIGN,Internal"
|
|
tree.end
|
|
tree "GPIO"
|
|
base ad:0x40022000
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "DOUT3_0,Data Out 0 to 3Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 24. "DIO3,Sets the state of the pin that is configured as DIO#3 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "DIO2,Sets the state of the pin that is configured as DIO#2 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "DIO1,Sets the state of the pin that is configured as DIO#1 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "DIO0,Sets the state of the pin that is configured as DIO#0 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x04 "DOUT7_4,Data Out 4 to 7Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x04 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 24. "DIO7,Sets the state of the pin that is configured as DIO#7 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 16. "DIO6,Sets the state of the pin that is configured as DIO#6 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "DIO5,Sets the state of the pin that is configured as DIO#5 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "DIO4,Sets the state of the pin that is configured as DIO#4 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x08 "DOUT11_8,Data Out 8 to 11Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 24. "DIO11,Sets the state of the pin that is configured as DIO#11 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 16. "DIO10,Sets the state of the pin that is configured as DIO#10 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 8. "DIO9,Sets the state of the pin that is configured as DIO#9 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "DIO8,Sets the state of the pin that is configured as DIO#8 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x0C "DOUT15_12,Data Out 12 to 15Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x0C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 24. "DIO15,Sets the state of the pin that is configured as DIO#15 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 16. "DIO14,Sets the state of the pin that is configured as DIO#14 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 8. "DIO13,Sets the state of the pin that is configured as DIO#13 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "DIO12,Sets the state of the pin that is configured as DIO#12 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x10 "DOUT19_16,Data Out 16 to 19Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x10 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 24. "DIO19,Sets the state of the pin that is configured as DIO#19 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 16. "DIO18,Sets the state of the pin that is configured as DIO#18 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 8. "DIO17,Sets the state of the pin that is configured as DIO#17 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "DIO16,Sets the state of the pin that is configured as DIO#16 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x14 "DOUT23_20,Data Out 20 to 23Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x14 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 24. "DIO23,Sets the state of the pin that is configured as DIO#23 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 16. "DIO22,Sets the state of the pin that is configured as DIO#22 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 8. "DIO21,Sets the state of the pin that is configured as DIO#21 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "DIO20,Sets the state of the pin that is configured as DIO#20 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x18 "DOUT27_24,Data Out 24 to 27Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x18 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 24. "DIO27,Sets the state of the pin that is configured as DIO#27 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 16. "DIO26,Sets the state of the pin that is configured as DIO#26 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 8. "DIO25,Sets the state of the pin that is configured as DIO#25 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "DIO24,Sets the state of the pin that is configured as DIO#24 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x1C "DOUT31_28,Data Out 28 to 31Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x1C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 24. "DIO31,Sets the state of the pin that is configured as DIO#31 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 16. "DIO30,Sets the state of the pin that is configured as DIO#30 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 8. "DIO29,Sets the state of the pin that is configured as DIO#29 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "DIO28,Sets the state of the pin that is configured as DIO#28 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x20 "DOUT35_32,Data Out 35 to 32Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x20 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 24. "DIO35,Sets the state of the pin that is configured as DIO#35 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 16. "DIO34,Sets the state of the pin that is configured as DIO#34 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 8. "DIO33,Sets the state of the pin that is configured as DIO#33 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "DIO32,Sets the state of the pin that is configured as DIO#32 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x24 "DOUT39_36,Data Out 39 to 36Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x24 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 24. "DIO39,Sets the state of the pin that is configured as DIO#39 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 16. "DIO38,Sets the state of the pin that is configured as DIO#38 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 8. "DIO37,Sets the state of the pin that is configured as DIO#37 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0. "DIO36,Sets the state of the pin that is configured as DIO#36 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x28 "DOUT43_40,Data Out 43 to 40Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x28 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 24. "DIO43,Sets the state of the pin that is configured as DIO#43 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 16. "DIO42,Sets the state of the pin that is configured as DIO#42 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 8. "DIO41,Sets the state of the pin that is configured as DIO#41 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "DIO40,Sets the state of the pin that is configured as DIO#40 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x2C "DOUT47_44,Data Out 47 to 44Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x2C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 24. "DIO47,Sets the state of the pin that is configured as DIO#47 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 16. "DIO46,Sets the state of the pin that is configured as DIO#46 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 8. "DIO45,Sets the state of the pin that is configured as DIO#45 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
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bitfld.long 0x2C 0. "DIO44,Sets the state of the pin that is configured as DIO#44 if the corresponding DOE47_0 bitfield is set." "0,1"
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group.long 0x80++0x07
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line.long 0x00 "DOUT31_0,Data Output for DIO 0 to 31"
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bitfld.long 0x00 31. "DIO31,Data output for DIO 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Data output for DIO 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Data output for DIO 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Data output for DIO 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Data output for DIO 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Data output for DIO 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Data output for DIO 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Data output for DIO 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Data output for DIO 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Data output for DIO 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Data output for DIO 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Data output for DIO 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Data output for DIO 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Data output for DIO 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Data output for DIO 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Data output for DIO 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Data output for DIO 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Data output for DIO 14" "0,1"
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newline
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bitfld.long 0x00 13. "DIO13,Data output for DIO 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Data output for DIO 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Data output for DIO 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Data output for DIO 10" "0,1"
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bitfld.long 0x00 9. "DIO9,Data output for DIO 9" "0,1"
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bitfld.long 0x00 8. "DIO8,Data output for DIO 8" "0,1"
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bitfld.long 0x00 7. "DIO7,Data output for DIO 7" "0,1"
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bitfld.long 0x00 6. "DIO6,Data output for DIO 6" "0,1"
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bitfld.long 0x00 5. "DIO5,Data output for DIO 5" "0,1"
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newline
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bitfld.long 0x00 4. "DIO4,Data output for DIO 4" "0,1"
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bitfld.long 0x00 3. "DIO3,Data output for DIO 3" "0,1"
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bitfld.long 0x00 2. "DIO2,Data output for DIO 2" "0,1"
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bitfld.long 0x00 1. "DIO1,Data output for DIO 1" "0,1"
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bitfld.long 0x00 0. "DIO0,Data output for DIO 0" "0,1"
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line.long 0x04 "DOUT47_32,Data Output for DIO 0 to 31"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "DIO47,Data output for DIO 47" "0,1"
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bitfld.long 0x04 14. "DIO46,Data output for DIO 46" "0,1"
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bitfld.long 0x04 13. "DIO45,Data output for DIO 45" "0,1"
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bitfld.long 0x04 12. "DIO44,Data output for DIO 44" "0,1"
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bitfld.long 0x04 11. "DIO43,Data output for DIO 43" "0,1"
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bitfld.long 0x04 10. "DIO42,Data output for DIO 42" "0,1"
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bitfld.long 0x04 9. "DIO41,Data output for DIO 41" "0,1"
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bitfld.long 0x04 8. "DIO40,Data output for DIO 40" "0,1"
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newline
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bitfld.long 0x04 7. "DIO39,Data output for DIO 39" "0,1"
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bitfld.long 0x04 6. "DIO38,Data output for DIO 38" "0,1"
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bitfld.long 0x04 5. "DIO37,Data output for DIO 37" "0,1"
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bitfld.long 0x04 4. "DIO36,Data output for DIO 36" "0,1"
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bitfld.long 0x04 3. "DIO35,Data output for DIO 35" "0,1"
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bitfld.long 0x04 2. "DIO34,Data output for DIO 34" "0,1"
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bitfld.long 0x04 1. "DIO33,Data output for DIO 33" "0,1"
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bitfld.long 0x04 0. "DIO32,Data output for DIO 32" "0,1"
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group.long 0x90++0x07
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line.long 0x00 "DOUTSET31_0,Data Out SetWriting 1 to a bit position sets the corresponding bit in the DOUT47_0 register"
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bitfld.long 0x00 31. "DIO31,Set bit 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Set bit 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Set bit 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Set bit 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Set bit 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Set bit 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Set bit 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Set bit 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Set bit 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Set bit 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Set bit 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Set bit 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Set bit 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Set bit 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Set bit 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Set bit 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Set bit 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Set bit 14" "0,1"
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newline
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bitfld.long 0x00 13. "DIO13,Set bit 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Set bit 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Set bit 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Set bit 10" "0,1"
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bitfld.long 0x00 9. "DIO9,Set bit 9" "0,1"
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bitfld.long 0x00 8. "DIO8,Set bit 8" "0,1"
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bitfld.long 0x00 7. "DIO7,Set bit 7" "0,1"
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bitfld.long 0x00 6. "DIO6,Set bit 6" "0,1"
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bitfld.long 0x00 5. "DIO5,Set bit 5" "0,1"
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newline
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bitfld.long 0x00 4. "DIO4,Set bit 4" "0,1"
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bitfld.long 0x00 3. "DIO3,Set bit 3" "0,1"
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bitfld.long 0x00 2. "DIO2,Set bit 2" "0,1"
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bitfld.long 0x00 1. "DIO1,Set bit 1" "0,1"
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bitfld.long 0x00 0. "DIO0,Set bit 0" "0,1"
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line.long 0x04 "DOUTSET47_32,Data Out SetWriting 1 to a bit position sets the corresponding bit in the DOUT47_0 register"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "DIO47,Set bit 47" "0,1"
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bitfld.long 0x04 14. "DIO46,Set bit 46" "0,1"
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bitfld.long 0x04 13. "DIO45,Set bit 45" "0,1"
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bitfld.long 0x04 12. "DIO44,Set bit 44" "0,1"
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bitfld.long 0x04 11. "DIO43,Set bit 43" "0,1"
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bitfld.long 0x04 10. "DIO42,Set bit 42" "0,1"
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bitfld.long 0x04 9. "DIO41,Set bit 41" "0,1"
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bitfld.long 0x04 8. "DIO40,Set bit 40" "0,1"
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newline
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bitfld.long 0x04 7. "DIO39,Set bit 39" "0,1"
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bitfld.long 0x04 6. "DIO38,Set bit 38" "0,1"
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bitfld.long 0x04 5. "DIO37,Set bit 37" "0,1"
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bitfld.long 0x04 4. "DIO36,Set bit 36" "0,1"
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bitfld.long 0x04 3. "DIO35,Set bit 35" "0,1"
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bitfld.long 0x04 2. "DIO34,Set bit 34" "0,1"
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bitfld.long 0x04 1. "DIO33,Set bit 33" "0,1"
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bitfld.long 0x04 0. "DIO32,Set bit 32" "0,1"
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group.long 0xA0++0x07
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line.long 0x00 "DOUTCLR31_0,Data Out ClearWriting 1 to a bit position clears the corresponding bit in the DOUT47_0 register"
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bitfld.long 0x00 31. "DIO31,Clears bit 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Clears bit 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Clears bit 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Clears bit 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Clears bit 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Clears bit 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Clears bit 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Clears bit 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Clears bit 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Clears bit 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Clears bit 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Clears bit 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Clears bit 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Clears bit 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Clears bit 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Clears bit 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Clears bit 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Clears bit 14" "0,1"
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newline
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bitfld.long 0x00 13. "DIO13,Clears bit 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Clears bit 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Clears bit 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Clears bit 10" "0,1"
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bitfld.long 0x00 9. "DIO9,Clears bit 9" "0,1"
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bitfld.long 0x00 8. "DIO8,Clears bit 8" "0,1"
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bitfld.long 0x00 7. "DIO7,Clears bit 7" "0,1"
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bitfld.long 0x00 6. "DIO6,Clears bit 6" "0,1"
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bitfld.long 0x00 5. "DIO5,Clears bit 5" "0,1"
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newline
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bitfld.long 0x00 4. "DIO4,Clears bit 4" "0,1"
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bitfld.long 0x00 3. "DIO3,Clears bit 3" "0,1"
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bitfld.long 0x00 2. "DIO2,Clears bit 2" "0,1"
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bitfld.long 0x00 1. "DIO1,Clears bit 1" "0,1"
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bitfld.long 0x00 0. "DIO0,Clears bit 0" "0,1"
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line.long 0x04 "DOUTCLR47_32,Data Out ClearWriting 1 to a bit position clears the corresponding bit in the DOUT47_0 register"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "DIO47,Clears bit 47" "0,1"
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bitfld.long 0x04 14. "DIO46,Clears bit 46" "0,1"
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bitfld.long 0x04 13. "DIO45,Clears bit 45" "0,1"
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bitfld.long 0x04 12. "DIO44,Clears bit 44" "0,1"
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bitfld.long 0x04 11. "DIO43,Clears bit 43" "0,1"
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bitfld.long 0x04 10. "DIO42,Clears bit 42" "0,1"
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bitfld.long 0x04 9. "DIO41,Clears bit 41" "0,1"
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bitfld.long 0x04 8. "DIO40,Clears bit 40" "0,1"
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newline
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bitfld.long 0x04 7. "DIO39,Clears bit 39" "0,1"
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bitfld.long 0x04 6. "DIO38,Clears bit 38" "0,1"
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bitfld.long 0x04 5. "DIO37,Clears bit 37" "0,1"
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bitfld.long 0x04 4. "DIO36,Clears bit 36" "0,1"
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bitfld.long 0x04 3. "DIO35,Clears bit 35" "0,1"
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bitfld.long 0x04 2. "DIO34,Clears bit 34" "0,1"
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bitfld.long 0x04 1. "DIO33,Clears bit 33" "0,1"
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bitfld.long 0x04 0. "DIO32,Clears bit 32" "0,1"
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group.long 0xB0++0x07
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line.long 0x00 "DOUTTGL31_0,Data Out ToggleWriting 1 to a bit position will invert the corresponding DIO output"
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bitfld.long 0x00 31. "DIO31,Toggles bit 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Toggles bit 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Toggles bit 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Toggles bit 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Toggles bit 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Toggles bit 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Toggles bit 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Toggles bit 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Toggles bit 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Toggles bit 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Toggles bit 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Toggles bit 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Toggles bit 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Toggles bit 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Toggles bit 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Toggles bit 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Toggles bit 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Toggles bit 14" "0,1"
|
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newline
|
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bitfld.long 0x00 13. "DIO13,Toggles bit 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Toggles bit 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Toggles bit 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Toggles bit 10" "0,1"
|
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bitfld.long 0x00 9. "DIO9,Toggles bit 9" "0,1"
|
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bitfld.long 0x00 8. "DIO8,Toggles bit 8" "0,1"
|
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bitfld.long 0x00 7. "DIO7,Toggles bit 7" "0,1"
|
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bitfld.long 0x00 6. "DIO6,Toggles bit 6" "0,1"
|
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bitfld.long 0x00 5. "DIO5,Toggles bit 5" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "DIO4,Toggles bit 4" "0,1"
|
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bitfld.long 0x00 3. "DIO3,Toggles bit 3" "0,1"
|
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bitfld.long 0x00 2. "DIO2,Toggles bit 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Toggles bit 1" "0,1"
|
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bitfld.long 0x00 0. "DIO0,Toggles bit 0" "0,1"
|
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line.long 0x04 "DOUTTGL47_32,Data Out ToggleWriting 1 to a bit position will invert the corresponding DIO output"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Toggles bit 47" "0,1"
|
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bitfld.long 0x04 14. "DIO46,Toggles bit 46" "0,1"
|
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bitfld.long 0x04 13. "DIO45,Toggles bit 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Toggles bit 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Toggles bit 43" "0,1"
|
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bitfld.long 0x04 10. "DIO42,Toggles bit 42" "0,1"
|
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bitfld.long 0x04 9. "DIO41,Toggles bit 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Toggles bit 40" "0,1"
|
|
newline
|
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bitfld.long 0x04 7. "DIO39,Toggles bit 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Toggles bit 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Toggles bit 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Toggles bit 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Toggles bit 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Toggles bit 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Toggles bit 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Toggles bit 32" "0,1"
|
|
rgroup.long 0xC0++0x07
|
|
line.long 0x00 "DIN31_0,Data Input from DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data input from DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data input from DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data input from DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data input from DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data input from DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data input from DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data input from DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data input from DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data input from DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data input from DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data input from DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data input from DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data input from DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data input from DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data input from DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data input from DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data input from DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data input from DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data input from DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data input from DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data input from DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data input from DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data input from DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data input from DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data input from DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data input from DIO 6" "0,1"
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|
bitfld.long 0x00 5. "DIO5,Data input from DIO 5" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "DIO4,Data input from DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data input from DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data input from DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data input from DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data input from DIO 0" "0,1"
|
|
line.long 0x04 "DIN47_32,Data Input from DIO 32 to 47"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data input from DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data input from DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data input from DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data input from DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data input from DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data input from DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data input from DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data input from DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Data input from DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data input from DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data input from DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data input from DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data input from DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data input from DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data input from DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data input from DIO 32" "0,1"
|
|
group.long 0xD0++0x07
|
|
line.long 0x00 "DOE31_0,Data Output Enable for DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data output enable for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data output enable for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data output enable for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data output enable for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data output enable for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data output enable for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data output enable for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data output enable for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data output enable for DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data output enable for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data output enable for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data output enable for DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data output enable for DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data output enable for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data output enable for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data output enable for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data output enable for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data output enable for DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data output enable for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data output enable for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data output enable for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data output enable for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data output enable for DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data output enable for DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data output enable for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data output enable for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Data output enable for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Data output enable for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data output enable for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data output enable for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data output enable for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data output enable for DIO 0" "0,1"
|
|
line.long 0x04 "DOE47_32,Data Output Enable for DIO 32 to 47"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data output enable for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data output enable for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data output enable for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data output enable for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data output enable for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data output enable for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data output enable for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data output enable for DIO 40" "0,1"
|
|
newline
|
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bitfld.long 0x04 7. "DIO39,Data output enable for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data output enable for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data output enable for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data output enable for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data output enable for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data output enable for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data output enable for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data output enable for DIO 32" "0,1"
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|
group.long 0xE0++0x07
|
|
line.long 0x00 "EVFLAGS31_0,Event Register for DIO 0 to 31Reading this registers will return 1 for triggered event and 0 for non-triggered events"
|
|
bitfld.long 0x00 31. "DIO31,Event for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Event for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Event for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Event for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Event for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Event for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Event for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Event for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Event for DIO 23" "0,1"
|
|
newline
|
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bitfld.long 0x00 22. "DIO22,Event for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Event for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Event for DIO 20" "0,1"
|
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bitfld.long 0x00 19. "DIO19,Event for DIO 19" "0,1"
|
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bitfld.long 0x00 18. "DIO18,Event for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Event for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Event for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Event for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Event for DIO 14" "0,1"
|
|
newline
|
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bitfld.long 0x00 13. "DIO13,Event for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Event for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Event for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Event for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Event for DIO 9" "0,1"
|
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bitfld.long 0x00 8. "DIO8,Event for DIO 8" "0,1"
|
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bitfld.long 0x00 7. "DIO7,Event for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Event for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Event for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Event for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Event for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Event for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Event for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Event for DIO 0" "0,1"
|
|
line.long 0x04 "EVFLAGS47_32,Event Register for DIO 32 to 47Reading this registers will return 1 for triggered event and 0 for non-triggered events"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Event for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Event for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Event for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Event for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Event for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Event for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Event for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Event for DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Event for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Event for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Event for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Event for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Event for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Event for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Event for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Event for DIO 32" "0,1"
|
|
tree.end
|
|
tree "GPT"
|
|
repeat 4. (list 0. 1. 2. 3. )(list ad:0x40010000 ad:0x40011000 ad:0x40012000 ad:0x40013000 )
|
|
tree "GPT$1"
|
|
base $2
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CFG,Configuration"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CFG,GPT Configuration0x2" "32-bit timer configuration,?,?,?,16-bit timer configuration. Configure for two..,?,?,?"
|
|
line.long 0x04 "TAMR,Timer A Mode"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 13.--15. "TCACT,Timer Compare Action Select " "Disable compare operations,Toggle State on Time-Out,Clear CCP output pin on Time-Out,Set CCP output pin on Time-Out ,Set CCP output pin immediately and toggle on..,Clear CCP output pin immediately and toggle on..,Set CCP output pin immediately and clear on..,Clear CCP output pin immediately and set on.."
|
|
newline
|
|
bitfld.long 0x04 12. "TACINTD,One-Shot/Periodic Interrupt Disable" "Time-out interrupt function as normal,Time-out interrupt are disabled"
|
|
newline
|
|
bitfld.long 0x04 11. "TAPLO,GPTM Timer A PWM Legacy Operation0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0.1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0.This bit is only valid in.." "Legacy operation,CCP output pin is set to 1 on time-out"
|
|
newline
|
|
bitfld.long 0x04 10. "TAMRSU,Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated.If the timer is disabled (CTL.TAEN = 0) when this bit is set TAMATCHR and TAPR are updated when the timer is enabled.If the timer is stalled.." "Update TAMATCHR and TAPR if used on the next..,Update TAMATCHR and TAPR if used on the next.."
|
|
newline
|
|
bitfld.long 0x04 9. "TAPWMIE,GPTM Timer A PWM Interrupt EnableThis bit enables interrupts in PWM mode on rising falling or both edges of the CCP output as defined by the CTL.TAEVENTIn addition when this bit is set and a capture event occurs Timer Aautomatically generates.." "Interrupt is disabled. ,Interrupt is enabled. This bit is only valid in.."
|
|
newline
|
|
bitfld.long 0x04 8. "TAILD,GPT Timer A PWM Interval Load" "Update the TAR register with the value in the..,Update the TAR register with the value in the.."
|
|
newline
|
|
bitfld.long 0x04 7. "TASNAPS,GPT Timer A Snap-Shot Mode" "Snap-shot mode is disabled. ,If Timer A is configured in the periodic mode .."
|
|
newline
|
|
bitfld.long 0x04 6. "TAWOT,GPT Timer A Wait-On-Trigger" "Timer A begins counting as soon as it is enabled.,If Timer A is enabled (CTL.TAEN = 1) Timer A.."
|
|
newline
|
|
bitfld.long 0x04 5. "TAMIE,GPT Timer A Match Interrupt Enable" "The match interrupt is disabled for match..,An interrupt is generated when the match value.."
|
|
newline
|
|
bitfld.long 0x04 4. "TACDIR,GPT Timer A Count Direction" "The timer counts down. ,The timer counts up. When counting up the timer.."
|
|
newline
|
|
bitfld.long 0x04 3. "TAAMS,GPT Timer A Alternate Mode Note: To enable PWM mode you must also clear TACM and then configure TAMR field to 0x2" "Capture/Compare mode is enabled.,PWM mode is enabled"
|
|
newline
|
|
bitfld.long 0x04 2. "TACM,GPT Timer A Capture Mode" "Edge-Count mode,Edge-Time mode"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "TAMR,GPT Timer A Mode0x0 Reserved0x1 One-Shot Timer mode0x2 Periodic Timer mode0x3 Capture modeThe Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register" "?,One-Shot Timer mode,Periodic Timer mode ,Capture mode"
|
|
line.long 0x08 "TBMR,Timer B Mode"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 13.--15. "TCACT,Timer Compare Action Select" "Disable compare operations,Toggle State on Time-Out,Clear CCP output pin on Time-Out,Set CCP output pin on Time-Out ,Set CCP output pin immediately and toggle on..,Clear CCP output pin immediately and toggle on..,Set CCP output pin immediately and clear on..,Clear CCP output pin immediately and set on.."
|
|
newline
|
|
bitfld.long 0x08 12. "TBCINTD,One-Shot/Periodic Interrupt Mode" "Normal Time-Out Interrupt ,Mask Time-Out Interrupt"
|
|
newline
|
|
bitfld.long 0x08 11. "TBPLO,GPTM Timer B PWM Legacy Operation0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0.1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0.This bit is only valid in.." "Legacy operation,CCP output pin is set to 1 on time-out"
|
|
newline
|
|
bitfld.long 0x08 10. "TBMRSU,Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updatedIf the timer is disabled (CTL.TBEN is clear) when this bit is set TBMATCHR and TBPR are updated when the timer is enabled.If the timer is stalled.." "Update TBMATCHR and TBPR if used on the next..,Update TBMATCHR and TBPR if used on the next.."
|
|
newline
|
|
bitfld.long 0x08 9. "TBPWMIE,GPTM Timer B PWM Interrupt EnableThis bit enables interrupts in PWM mode on rising falling or both edges of the CCP output as defined by the CTL.TBEVENTIn addition when this bit is set and a capture event occurs Timer Aautomatically generates.." "Interrupt is disabled. ,Interrupt is enabled. This bit is only valid in.."
|
|
newline
|
|
bitfld.long 0x08 8. "TBILD,GPT Timer B PWM Interval Load" "Update the TBR register with the value in the..,Update the TBR register with the value in the.."
|
|
newline
|
|
bitfld.long 0x08 7. "TBSNAPS,GPT Timer B Snap-Shot Mode" "Snap-shot mode is disabled. ,If Timer B is configured in the periodic mode"
|
|
newline
|
|
bitfld.long 0x08 6. "TBWOT,GPT Timer B Wait-On-Trigger" "Timer B begins counting as soon as it is enabled. ,If Timer B is enabled (CTL.TBEN is set) Timer B.."
|
|
newline
|
|
bitfld.long 0x08 5. "TBMIE,GPT Timer B Match Interrupt Enable" "The match interrupt is disabled for match..,An interrupt is generated when the match value.."
|
|
newline
|
|
bitfld.long 0x08 4. "TBCDIR,GPT Timer B Count Direction" "The timer counts down. ,The timer counts up. When counting up the timer.."
|
|
newline
|
|
bitfld.long 0x08 3. "TBAMS,GPT Timer B Alternate Mode Note: To enable PWM mode you must also clear TBCM bit and configure TBMR field to 0x2" "Capture/Compare mode is enabled.,PWM mode is enabled"
|
|
newline
|
|
bitfld.long 0x08 2. "TBCM,GPT Timer B Capture Mode" "Edge-Count mode,Edge-Time mode"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "TBMR,GPT Timer B Mode0x0 Reserved0x1 One-Shot Timer mode0x2 Periodic Timer mode0x3 Capture modeThe Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register" "?,One-Shot Timer mode,Periodic Timer mode ,Capture mode"
|
|
line.long 0x0C "CTL,Control"
|
|
hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 14. "TBPWML,GPT Timer B PWM Output Level0: Output is unaffected" "Output is unaffected,Output is inverted"
|
|
newline
|
|
bitfld.long 0x0C 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 10.--11. "TBEVENT,GPT Timer B Event ModeThe values in this register are defined as follows:Value Description0x0 Positive edge0x1 Negative edge0x2 Reserved0x3 Both edgesNote: If PWM output inversion is enabled edge detection interruptbehavior is reversed" "Positive edge,Negative edge ,?,Both edges"
|
|
newline
|
|
bitfld.long 0x0C 9. "TBSTALL,GPT Timer B Stall Enable" "Timer B continues counting while the processor..,Timer B freezes counting while the processor is.."
|
|
newline
|
|
bitfld.long 0x0C 8. "TBEN,GPT Timer B Enable" "Timer B is disabled. ,Timer B is enabled and begins counting or the.."
|
|
newline
|
|
rbitfld.long 0x0C 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "TAPWML,GPT Timer A PWM Output Level" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x0C 4.--5. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 2.--3. "TAEVENT,GPT Timer A Event ModeThe values in this register are defined as follows:Value Description0x0 Positive edge0x1 Negative edge0x2 Reserved0x3 Both edgesNote: If PWM output inversion is enabled edge detection interruptbehavior is reversed" "Positive edge,Negative edge ,?,Both edges"
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|
newline
|
|
bitfld.long 0x0C 1. "TASTALL,GPT Timer A Stall Enable" "Timer A continues counting while the processor..,Timer A freezes counting while the processor is.."
|
|
newline
|
|
bitfld.long 0x0C 0. "TAEN,GPT Timer A Enable" "Timer A is disabled. ,Timer A is enabled and begins counting or the.."
|
|
line.long 0x10 "SYNC,Synch Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "SYNC3,Synchronize GPT Timer 3" "No Sync. GPT3 is not affected. ,A timeout event for Timer A of GPT3 is triggered,A timeout event for Timer B of GPT3 is triggered,A timeout event for both Timer A and Timer B of.."
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|
newline
|
|
bitfld.long 0x10 4.--5. "SYNC2,Synchronize GPT Timer 2" "No Sync. GPT2 is not affected. ,A timeout event for Timer A of GPT2 is triggered,A timeout event for Timer B of GPT2 is triggered,A timeout event for both Timer A and Timer B of.."
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|
newline
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bitfld.long 0x10 2.--3. "SYNC1,Synchronize GPT Timer 1" "No Sync. GPT1 is not affected. ,A timeout event for Timer A of GPT1 is triggered,A timeout event for Timer B of GPT1 is triggered,A timeout event for both Timer A and Timer B of.."
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newline
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bitfld.long 0x10 0.--1. "SYNC0,Synchronize GPT Timer 0" "No Sync. GPT0 is not affected. ,A timeout event for Timer A of GPT0 is triggered,A timeout event for Timer B of GPT0 is triggered,A timeout event for both Timer A and Timer B of.."
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|
group.long 0x18++0x3F
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|
line.long 0x00 "IMR,Interrupt MaskThis register is used to enable the interrupts.Associated registers:RIS. MIS. ICLR"
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|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 13. "DMABIM,Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS" "Disable Interrupt,Enable Interrupt"
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newline
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rbitfld.long 0x00 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 11. "TBMIM,Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 10. "CBEIM,Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 9. "CBMIM,Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 8. "TBTOIM,Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS" "Disable Interrupt,Enable Interrupt"
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newline
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rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 5. "DMAAIM,Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 4. "TAMIM,Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 2. "CAEIM,Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 1. "CAMIM,Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 0. "TATOIM,Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS" "Disable Interrupt,Enable Interrupt"
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line.long 0x04 "RIS,Raw Interrupt StatusAssociated registers:IMR. MIS. ICLR"
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hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 13. "DMABRIS,GPT Timer B DMA Done Raw Interrupt Status0: Transfer has not completed1: Transfer has completed" "Transfer has not completed,Transfer has completed"
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newline
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bitfld.long 0x04 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x04 11. "TBMRIS,GPT Timer B Match Raw Interrupt0: The match value has not been reached1: The match value is reached.TBMR.TBMIE is set and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode" "The match value has not been reached,The match value is reached.TBMR.TBMIE is set and.."
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newline
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bitfld.long 0x04 10. "CBERIS,GPT Timer B Capture Mode Event Raw Interrupt0: The event has not occured.1: The event has occured.This interrupt asserts when the subtimer is configured in Input Edge-Time mode" "The event has not occured,The event has occured.This interrupt asserts.."
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newline
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bitfld.long 0x04 9. "CBMRIS,GPT Timer B Capture Mode Match Raw Interrupt0: The capture mode match for Timer B has not occurred.1: A capture mode match has occurred for Timer B" "The capture mode match for Timer B has not..,A capture mode match has occurred for Timer B"
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newline
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bitfld.long 0x04 8. "TBTORIS,GPT Timer B Time-out Raw Interrupt0: Timer B has not timed out1: Timer B has timed out" "Timer B has not timed out,Timer B has timed out"
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newline
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bitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x04 5. "DMAARIS,GPT Timer A DMA Done Raw Interrupt Status0: Transfer has not completed1: Transfer has completed" "Transfer has not completed,Transfer has completed"
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newline
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bitfld.long 0x04 4. "TAMRIS,GPT Timer A Match Raw Interrupt0: The match value has not been reached1: The match value is reached.TAMR.TAMIE is set and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode" "The match value has not been reached,The match value is reached.TAMR.TAMIE is set and.."
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newline
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bitfld.long 0x04 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x04 2. "CAERIS,GPT Timer A Capture Mode Event Raw Interrupt0: The event has not occured.1: The event has occured.This interrupt asserts when the subtimer is configured in Input Edge-Time mode" "The event has not occured,The event has occured.This interrupt asserts.."
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newline
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bitfld.long 0x04 1. "CAMRIS,GPT Timer A Capture Mode Match Raw Interrupt0: The capture mode match for Timer A has not occurred.1: A capture mode match has occurred for Timer A" "The capture mode match for Timer A has not..,A capture mode match has occurred for Timer A"
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newline
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bitfld.long 0x04 0. "TATORIS,GPT Timer A Time-out Raw Interrupt0: Timer A has not timed out1: Timer A has timed out" "Timer A has not timed out,Timer A has timed out"
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line.long 0x08 "MIS,Masked Interrupt StatusValues are result of bitwise AND operation between RIS and IMRAssosciated clear register: ICLR"
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hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 13. "DMABMIS," "0,1"
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newline
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bitfld.long 0x08 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x08 11. "TBMMIS," "0,1"
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newline
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bitfld.long 0x08 10. "CBEMIS," "0,1"
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newline
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bitfld.long 0x08 9. "CBMMIS," "0,1"
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newline
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bitfld.long 0x08 8. "TBTOMIS," "0,1"
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newline
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bitfld.long 0x08 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x08 5. "DMAAMIS," "0,1"
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newline
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bitfld.long 0x08 4. "TAMMIS," "0,1"
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newline
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bitfld.long 0x08 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x08 2. "CAEMIS," "0,1"
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newline
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bitfld.long 0x08 1. "CAMMIS," "0,1"
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newline
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bitfld.long 0x08 0. "TATOMIS," "0,1"
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line.long 0x0C "ICLR,Interrupt ClearThis register is used to clear status bits in the RIS and MIS registers"
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hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 13. "DMABINT," "0,1"
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newline
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bitfld.long 0x0C 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x0C 11. "TBMCINT," "0,1"
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newline
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bitfld.long 0x0C 10. "CBECINT," "0,1"
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newline
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bitfld.long 0x0C 9. "CBMCINT," "0,1"
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newline
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bitfld.long 0x0C 8. "TBTOCINT," "0,1"
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newline
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rbitfld.long 0x0C 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
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newline
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bitfld.long 0x0C 5. "DMAAINT," "0,1"
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newline
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bitfld.long 0x0C 4. "TAMCINT," "0,1"
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newline
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bitfld.long 0x0C 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x0C 2. "CAECINT," "0,1"
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newline
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bitfld.long 0x0C 1. "CAMCINT," "0,1"
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newline
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bitfld.long 0x0C 0. "TATOCINT," "0,1"
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line.long 0x10 "TAILR,Timer A Interval Load Register"
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line.long 0x14 "TBILR,Timer B Interval Load Register"
|
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line.long 0x18 "TAMATCHR,Timer A Match RegisterInterrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode.In Edge-Count mode. this register along with TAILR. determines how many edge events are counted.The total.."
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line.long 0x1C "TBMATCHR,Timer B Match Register When a GPT is configured to one of the 32-bit modes. the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR.Reads from this register return the current match value of Timer B and writes.."
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "TBMATCHR,GPT Timer B Match Register"
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line.long 0x20 "TAPR,Timer A Pre-scaleThis register allows software to extend the range of the timers when they are used individually.When in one-shot or periodic down count modes. this register acts as a true prescaler for the timer counter.When acting as a true.."
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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abitfld.long 0x20 0.--7. "TAPSR,Timer A Pre-scale.Prescaler ratio in one-shot and periodic count mode is TAPSR + 1 that is:0: Prescaler ratio =" "0x00=Prescaler ratio = 1,0x01=Prescaler ratio = 2,0x02=Prescaler ratio = 3,0xFF=Prescaler ratio = 256"
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line.long 0x24 "TBPR,Timer B Pre-scaleThis register allows software to extend the range of the timers when they are used individually.When in one-shot or periodic down count modes. this register acts as a true prescaler for the timer counter.When acting as a true.."
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hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
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newline
|
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abitfld.long 0x24 0.--7. "TBPSR,Timer B Pre-scale.Prescale ratio in one-shot and periodic count mode is TBPSR + 1 that is:0: Prescaler ratio =" "0x00=Prescaler ratio = 1,0x01=Prescaler ratio = 2,0x02=Prescaler ratio = 3,0xFF=Prescaler ratio = 256"
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line.long 0x28 "TAPMR,Timer A Pre-scale MatchThis register allows software to extend the range of the TAMATCHR when used individually"
|
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hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
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newline
|
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hexmask.long.byte 0x28 0.--7. 1. "TAPSMR,GPT Timer A Pre-scale Match"
|
|
line.long 0x2C "TBPMR,Timer B Pre-scale MatchThis register allows software to extend the range of the TBMATCHR when used individually"
|
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hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
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newline
|
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hexmask.long.byte 0x2C 0.--7. 1. "TBPSMR,GPT Timer B Pre-scale Match Register"
|
|
line.long 0x30 "TAR,Timer A RegisterThis register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes"
|
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line.long 0x34 "TBR,Timer B RegisterThis register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes"
|
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line.long 0x38 "TAV,Timer A Value When read. this register shows the current. free-running value of Timer A in all modes"
|
|
line.long 0x3C "TBV,Timer B Value When read. this register shows the current. free-running value of Timer B in all modes"
|
|
rgroup.long 0x5C++0x13
|
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line.long 0x00 "TAPS,Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD. this register is updated with the value from TAPR register either on the next cycle or on the next timeout.This register shows the current value of the Timer A.."
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "PSS,GPT Timer A Pre-scaler"
|
|
line.long 0x04 "TBPS,Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD. this register is updated with the value from TBPR register either on the next cycle or on the next timeout.This register shows the current value of the Timer B.."
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|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "PSS,GPT Timer B Pre-scaler"
|
|
line.long 0x08 "TAPV,Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "PSV,GPT Timer A Pre-scaler Value"
|
|
line.long 0x0C "TBPV,Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PSV,GPT Timer B Pre-scaler Value"
|
|
line.long 0x10 "DMAEV,DMA Event This register allows software to enable/disable GPT DMA trigger events"
|
|
hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved field"
|
|
newline
|
|
bitfld.long 0x10 11. "TBMDMAEN,GPT Timer B Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CBEDMAEN,GPT Timer B Capture Event DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CBMDMAEN,GPT Timer B Capture Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "TBTODMAEN,GPT Timer B Time-Out DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5.--7. "RESERVED5,Software should not rely on the value of a reserved field" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 4. "TAMDMAEN,GPT Timer A Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "CAEDMAEN,GPT Timer A Capture Event DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CAMDMAEN,GPT Timer A Capture Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "TATODMAEN,GPT Timer A Time-Out DMA Trigger Enable" "0,1"
|
|
rgroup.long 0xFB0++0x07
|
|
line.long 0x00 "VERSION,Peripheral VersionThis register provides information regarding the GPT version"
|
|
line.long 0x04 "ANDCCP,Combined CCP OutputThis register is used to logically AND CCP output pairs for each timer"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 1. "LD_TO_EN,PWM assertion would happen at timeout0: PWM assertion happens when counter matches load value1: PWM assertion happens at timeout of the counter" "PWM assertion happens when counter matches load..,PWM assertion happens at timeout of the counter"
|
|
newline
|
|
bitfld.long 0x04 0. "CCP_AND_EN,Enables AND operation of the CCP outputs for timers A and B.0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers.1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals.." "PWM outputs of Timer A and Timer B are the..,PWM output of Timer A is ANDed version of Timer.."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
sif (cpuis("CC2640R"))
|
|
tree "Hidden"
|
|
base ad:0x00
|
|
rgroup.quad 0x00++0x07
|
|
line.quad 0x00 "JSTATE4,Digital JTAG State Register"
|
|
bitfld.quad 0x00 62. "MODACT10,CLK.I2C0" "0,1"
|
|
bitfld.quad 0x00 61. "MODACT11,CLK.I2S0" "0,1"
|
|
bitfld.quad 0x00 60. "MODACT12,CLK.DMA" "0,1"
|
|
bitfld.quad 0x00 59. "MODACT13,CLK.TRNG" "0,1"
|
|
bitfld.quad 0x00 58. "MODACT14,CLK.SEC" "0,1"
|
|
bitfld.quad 0x00 57. "MODACT15,CLK.PKA" "0,1"
|
|
bitfld.quad 0x00 56. "MODACT16,CLK.SSI0" "0,1"
|
|
bitfld.quad 0x00 55. "MODACT17,CLK.SSI1" "0,1"
|
|
bitfld.quad 0x00 54. "MODACT18,CLK.UART0" "0,1"
|
|
bitfld.quad 0x00 53. "MODACT19,CLK.UART1" "0,1"
|
|
newline
|
|
bitfld.quad 0x00 51.--52. "PWRSTATE0,CPU%CORTEXM_PM" "0,1,2,3"
|
|
bitfld.quad 0x00 49. "MODACT5,MCU.CPU_PD" "0,1"
|
|
bitfld.quad 0x00 48. "MODACT4,MCU.SERIAL_PD" "0,1"
|
|
bitfld.quad 0x00 47. "MODACT3,MCU.PERIPH_PD" "0,1"
|
|
bitfld.quad 0x00 46. "MODACT2,MCU.RFCORE_PD" "0,1"
|
|
bitfld.quad 0x00 45. "MODACT1,MCU.VIMS_PD" "0,1"
|
|
bitfld.quad 0x00 44. "MODACT0,MCU.MCU_CTL" "0,1"
|
|
bitfld.quad 0x00 43. "MODACT9,CLK.XOSC_EN" "0,1"
|
|
bitfld.quad 0x00 42. "MODACT8,CLK.SCLK_HF_SRC" "0,1"
|
|
bitfld.quad 0x00 36.--39. "PWRSTATE1,RF%LPRF_PM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 28.--35. 1. "MODACT7,PRCM:PWRPROFSTAT"
|
|
bitfld.quad 0x00 27. "MODACT20,PC_Error" "0,1"
|
|
hexmask.quad.tbyte 0x00 6.--26. 1. "PC,PC"
|
|
bitfld.quad 0x00 0.--5. "MODACT6,Interrupts%HWI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
endif
|
|
tree "I2C0"
|
|
base ad:0x40002000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SOAR,Slave Own AddressThis register consists of seven address bits that identify this I2C device on the I2C bus"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--6. 1. "OAR,I2C slave own addressThis field specifies bits a6 through a0 of the slave address"
|
|
line.long 0x04 "SSTAT,Slave Status Note: This register shares address with SCTL. meaning that this register functions as a control register when written. and a status register when"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 2. "FBR,First byte received0: The first byte has not been received.1: The first byte following the slave's own address has been received.This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR.." "The first byte has not been received,The first byte following the slave's own address.."
|
|
newline
|
|
bitfld.long 0x04 1. "TREQ,Transmit request0: No outstanding transmit request.1: The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the SDR register" "No outstanding transmit request,The I2C controller has been addressed as a slave.."
|
|
bitfld.long 0x04 0. "RREQ,Receive request0: No outstanding receive data1: The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until data has been read from the SDR register." "No outstanding receive data,The I2C controller has outstanding receive data.."
|
|
wgroup.long 0x04++0x17
|
|
line.long 0x00 "SCTL,Slave ControlNote: This register shares address with SSTAT. meaning that this register functions as a control register when written. and a status register when"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved field"
|
|
bitfld.long 0x00 0. "DA,Device active0: Disables the I2C slave operation1: Enables the I2C slave operation" "Disables the I2C slave operation,Enables the I2C slave operation"
|
|
line.long 0x04 "SDR,Slave DataThis register contains the data to be transmitted when in the Slave Transmit state. and the data received when in the Slave Receive state"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "DATA,Data for transferThis field contains the data for transfer during a slave receive or transmit operation"
|
|
line.long 0x08 "SIMR,Slave Interrupt MaskThis register controls whether a raw interrupt is promoted to a controller interrupt"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 2. "STOPIM,Stop condition interrupt mask0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt controller." "The SRIS.STOPRIS interrupt is suppressed and not..,The SRIS.STOPRIS interrupt is enabled and sent.."
|
|
newline
|
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bitfld.long 0x08 1. "STARTIM,Start condition interrupt mask0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt controller." "The SRIS.STARTRIS interrupt is suppressed and..,The SRIS.STARTRIS interrupt is enabled and sent.."
|
|
bitfld.long 0x08 0. "DATAIM,Data interrupt mask0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt controller" "The SRIS.DATARIS interrupt is suppressed and not..,The SRIS.DATARIS interrupt is enabled and sent.."
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|
line.long 0x0C "SRIS,Slave Raw Interrupt StatusThis register shows the unmasked interrupt status"
|
|
hexmask.long 0x0C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 2. "STOPRIS,Stop condition raw interrupt status0: No interrupt1: A Stop condition interrupt is pending.This bit is cleared by writing a 1 to SICR.STOPIC" "No interrupt,A Stop condition interrupt is.."
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|
newline
|
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bitfld.long 0x0C 1. "STARTRIS,Start condition raw interrupt status0: No interrupt1: A Start condition interrupt is pending.This bit is cleared by writing a 1 to SICR.STARTIC" "No interrupt,A Start condition interrupt is.."
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|
bitfld.long 0x0C 0. "DATARIS,Data raw interrupt status0: No interrupt1: A data received or data requested interrupt is pending.This bit is cleared by writing a 1 to the SICR.DATAIC" "No interrupt,A data received or data requested.."
|
|
line.long 0x10 "SMIS,Slave Masked Interrupt StatusThis register show which interrupt is active (based on result from SRIS and SIMR)"
|
|
hexmask.long 0x10 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 2. "STOPMIS,Stop condition masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked Stop condition interrupt is pending.This bit is cleared by writing a 1 to the SICR.STOPIC" "An interrupt has not occurred or is..,An unmasked Stop condition interrupt is.."
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|
newline
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bitfld.long 0x10 1. "STARTMIS,Start condition masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked Start condition interrupt is pending.This bit is cleared by writing a 1 to the SICR.STARTIC" "An interrupt has not occurred or is..,An unmasked Start condition interrupt is.."
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|
bitfld.long 0x10 0. "DATAMIS,Data masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked data received or data requested interrupt is pending.This bit is cleared by writing a 1 to the SICR.DATAIC" "An interrupt has not occurred or is..,An unmasked data received or data requested.."
|
|
line.long 0x14 "SICR,Slave Interrupt ClearThis register clears the raw interrupt SRIS"
|
|
hexmask.long 0x14 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 2. "STOPIC,Stop condition interrupt clearWriting 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS" "0,1"
|
|
newline
|
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bitfld.long 0x14 1. "STARTIC,Start condition interrupt clearWriting 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS" "0,1"
|
|
bitfld.long 0x14 0. "DATAIC,Data interrupt clearWriting 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS" "0,1"
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "MSA,Master Salve AddressThis register contains seven address bits of the slave to be accessed by the master (a6-a0). and an RS bit determining if the next operation is a receive or transmit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,I2C master slave addressDefines which slave is addressed for the transaction in master mode"
|
|
newline
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bitfld.long 0x00 0. "RS,Receive or SendThis bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA" "Transmit/send data to slave,Receive data from slave"
|
|
line.long 0x04 "MSTAT,Master Status"
|
|
hexmask.long 0x04 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 6. "BUSBSY,Bus busy0: The I2C bus is idle.1: The I2C bus is busy.The bit changes based on the MCTRL.START and MCTRL.STOP conditions" "The I2C bus is idle,The I2C bus is busy.The bit changes based on the.."
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|
newline
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bitfld.long 0x04 5. "IDLE,I2C idle0: The I2C controller is not idle.1: The I2C controller is idle" "The I2C controller is not idle,The I2C controller is idle"
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|
bitfld.long 0x04 4. "ARBLST,Arbitration lost0: The I2C controller won arbitration.1: The I2C controller lost arbitration" "The I2C controller won arbitration,The I2C controller lost arbitration"
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|
newline
|
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bitfld.long 0x04 3. "DATACK_N,Data Was Not Acknowledge0: The transmitted data was acknowledged.1: The transmitted data was not acknowledged" "The transmitted data was acknowledged,The transmitted data was not acknowledged"
|
|
bitfld.long 0x04 2. "ADRACK_N,Address Was Not Acknowledge0: The transmitted address was acknowledged.1: The transmitted address was not acknowledged" "The transmitted address was acknowledged,The transmitted address was not acknowledged"
|
|
newline
|
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bitfld.long 0x04 1. "ERR,Error0: No error was detected on the last operation.1: An error occurred on the last operation" "No error was detected on the last operation,An error occurred on the last operation"
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bitfld.long 0x04 0. "BUSY,I2C busy0: The controller is idle.1: The controller is busy.When this bit-field is set the other status bits are not valid.Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been.." "The controller is idle,The controller is busy.When this bit-field is.."
|
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wgroup.long 0x804++0x1F
|
|
line.long 0x00 "MCTRL,Master ControlThis register accesses status bits when read and control bits when written"
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hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
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bitfld.long 0x00 3. "ACK,Data acknowledge enable0: The received data byte is not acknowledged automatically by the master.1: The received data byte is acknowledged automatically by the master.This bit-field must be cleared when the I2C bus controller requires no further.." "The received data byte is not acknowledged..,The received data byte is acknowledged.."
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newline
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bitfld.long 0x00 2. "STOP,This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.0: The controller does not generate the Stop condition.1: The controller generates the Stop condition" "The controller does not generate the Stop..,The controller generates the Stop condition"
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bitfld.long 0x00 1. "START,This bit-field generates the Start or Repeated Start condition" "The controller does not generate the Start..,The controller generates the Start condition"
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newline
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bitfld.long 0x00 0. "RUN,I2C master enable0: The master is disabled.1: The master is enabled to transmit or receive data." "The master is disabled,The master is enabled to transmit or receive data"
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|
line.long 0x04 "MDR,Master DataThis register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x04 0.--7. 1. "DATA,When Read: Last RX Data is returnedWhen Written: Data is transferred during TX transaction"
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line.long 0x08 "MTPR,I2C Master Timer PeriodThis register specifies the period of the SCL clock"
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hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
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bitfld.long 0x08 7. "TPR_7,Must be set to 0 to set TPR" "0,1"
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|
newline
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hexmask.long.byte 0x08 0.--6. 1. "TPR,SCL clock periodThis field specifies the period of the SCL clock.SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRDwhere:SCL_PRD is the SCL line period (I2C clock).TPR is the timer period register value (range of 1 to 127)SCL_LP is the SCL low period.."
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line.long 0x0C "MIMR,Master Interrupt MaskThis register controls whether a raw interrupt is promoted to a controller interrupt"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
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bitfld.long 0x0C 0. "IM,Interrupt mask0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt controller.1: The master interrupt is sent to the interrupt controller when the MRIS.RIS is set." "The MRIS.RIS interrupt is suppressed and not..,The master interrupt is sent to the interrupt.."
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line.long 0x10 "MRIS,Master Raw Interrupt StatusThis register show the unmasked interrupt status"
|
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hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x10 0. "RIS,Raw interrupt status0: No interrupt1: A master interrupt is pending.This bit is cleared by writing 1 to the MICR.IC bit" "No interrupt,A master interrupt is pending.This.."
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|
line.long 0x14 "MMIS,Master Masked Interrupt StatusThis register show which interrupt is active (based on result from MRIS and MIMR)"
|
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hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "MIS,Masked interrupt status0: An interrupt has not occurred or is masked.1: A master interrupt is pending.This bit is cleared by writing 1 to the MICR.IC bit" "An interrupt has not occurred or is masked,A master interrupt is pending.This bit is.."
|
|
line.long 0x18 "MICR,Master Interrupt ClearThis register clears the raw and masked interrupt"
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hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x18 0. "IC,Interrupt clearWriting 1 to this bit clears MRIS.RIS and MMIS.MIS .Reading this register returns no meaningful data" "0,1"
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line.long 0x1C "MCR,Master ConfigurationThis register configures the mode (Master or Slave) and sets the interface for test mode loopback"
|
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hexmask.long 0x1C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 5. "SFE,I2C slave function enable" "Slave mode is disabled.,Slave mode is enabled."
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|
newline
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bitfld.long 0x1C 4. "MFE,I2C master function enable" "Master mode is disabled.,Master mode is enabled."
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rbitfld.long 0x1C 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x1C 0. "LPBK,I2C loopback0: Normal operation1: Loopback operation (test mode)" "Normal operation,Loopback operation (test mode)"
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tree.end
|
|
tree "I2S0"
|
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base ad:0x40021000
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group.long 0x00++0x2F
|
|
line.long 0x00 "AIFWCLKSRC,WCLK Source Selection"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 2. "WCLK_INV,Inverts WCLK source (pad or internal) when set.0: Not inverted1: Inverted" "Not inverted,Inverted"
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|
newline
|
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bitfld.long 0x00 0.--1. "WCLK_SRC,Selects WCLK source for AIF (should be the same as the BCLK source)" "None ('0'),External WCLK generator from pad,Internal WCLK generator from module PRCM,Not supported. Will give same WCLK as 'NONE'.."
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line.long 0x04 "AIFDMACFG,DMA Buffer Size Configuration"
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x04 0.--7. 1. "END_FRAME_IDX,Defines the length of the DMA buffer"
|
|
line.long 0x08 "AIFDIRCFG,Pin Direction"
|
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hexmask.long 0x08 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 4.--5. "AD1,Configures the AD1 audio data pin usage:0x3: Reserved" "Not in use (disabled),Input mode,Output mode,?"
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|
newline
|
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rbitfld.long 0x08 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x08 0.--1. "AD0,Configures the AD0 audio data pin usage:0x3: Reserved" "Not in use (disabled),Input mode,Output mode,?"
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line.long 0x0C "AIFFMTCFG,Serial Interface Format Configuration"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
abitfld.long 0x0C 8.--15. "DATA_DELAY,The number of BCLK periods between a WCLK edge and MSB of the first word in a phase:0x00: LJF and DSP" "0x00=LJF and DSP format,0x01=I2S and DSP format,0x02=RJF format,0xFF=RJF format"
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|
newline
|
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bitfld.long 0x0C 7. "MEM_LEN_24,The size of each word stored to or loaded from memory" "16-bit (one 16 bit access per sample),24-bit (one 8 bit and one 16 bit locked access.."
|
|
newline
|
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bitfld.long 0x0C 6. "SMPL_EDGE,On the serial audio interface data (and wclk) is sampled and clocked out on opposite edges of BCLK" "Data is sampled on the negative edge and clocked..,Data is sampled on the positive edge and clocked.."
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|
newline
|
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bitfld.long 0x0C 5. "DUAL_PHASE,Selects dual- or single-phase format.0: Single-phase: DSP format1" "Single-phase,Dual-phase"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "WORD_LEN,Number of bits per word (8-24):In single-phase format this is the exact number of bits per word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x10 "AIFWMASK0,Word Selection Bit Mask for Pin 0"
|
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "MASK,Bit-mask indicating valid channels in a frame on AD0.In single-phase mode each bit represents one channel starting with LSB for the first word in the frame"
|
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line.long 0x14 "AIFWMASK1,Word Selection Bit Mask for Pin 1"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "MASK,Bit-mask indicating valid channels in a frame on AD1.In single-phase mode each bit represents one channel starting with LSB for the first word in the frame"
|
|
line.long 0x18 "AIFWMASK2,Internal"
|
|
line.long 0x1C "AIFPWMVALUE,Audio Interface PWM Debug Value"
|
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
abitfld.long 0x1C 0.--15. "PULSE_WIDTH,The value written to this register determines the width of the active high PWM pulse (pwm_debug) which starts together with MSB of the first output word in a DMA" "0x0000=Constant low,0x0001=Width of the pulse (number of BCLK cycles..,0xFFFE=Width of the pulse (number of BCLK cycles..,0xFFFF=Constant high"
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|
line.long 0x20 "AIFINPTRNEXT,DMA Input Buffer Next Pointer"
|
|
line.long 0x24 "AIFINPTR,DMA Input Buffer Current Pointer"
|
|
line.long 0x28 "AIFOUTPTRNEXT,DMA Output Buffer Next Pointer"
|
|
line.long 0x2C "AIFOUTPTR,DMA Output Buffer Current Pointer"
|
|
group.long 0x34++0x37
|
|
line.long 0x00 "STMPCTL,Samplestamp Generator Control Register"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 2. "OUT_RDY,Low until the output pins are ready to be started by the samplestamp generator" "0,1"
|
|
newline
|
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rbitfld.long 0x00 1. "IN_RDY,Low until the input pins are ready to be started by the samplestamp generator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STMP_EN,Enables the samplestamp generator" "0,1"
|
|
line.long 0x04 "STMPXCNTCAPT0,Captured XOSC Counter Value. Capture Channel 0"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "CAPT_VALUE,The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0)"
|
|
line.long 0x08 "STMPXPER,XOSC Period Value"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "VALUE,The number of 24 MHz clock cycles in the previous WCLK period (that is - the next value of the XOSC counter at the positive WCLK edge had it not been reset to 0).The value is cleared when STMPCTL.STMP_EN = 0."
|
|
line.long 0x0C "STMPWCNTCAPT0,Captured WCLK Counter Value. Capture Channel 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--15. 1. "CAPT_VALUE,The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel 0)"
|
|
line.long 0x10 "STMPWPER,WCLK Counter Period Value"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x10 0.--15. 1. "VALUE,Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer"
|
|
line.long 0x14 "STMPINTRIG,WCLK Counter Trigger Value for Input Pins"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "IN_START_WCNT,Compare value used to start the incoming audio streams.This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very.."
|
|
line.long 0x18 "STMPOUTTRIG,WCLK Counter Trigger Value for Output Pins"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "OUT_START_WCNT,Compare value used to start the outgoing audio streams.This bit field must equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very.."
|
|
line.long 0x1C "STMPWSET,WCLK Counter Set Operation"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "VALUE,WCLK counter modification: Sets the running WCLK counter equal to the written value"
|
|
line.long 0x20 "STMPWADD,WCLK Counter Add Operation"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "VALUE_INC,WCLK counter modification: Adds the written value to the running WCLK counter"
|
|
line.long 0x24 "STMPXPERMIN,XOSC Minimum Period ValueMinimum Value of STMPXPER"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "VALUE,Each time STMPXPER is updated the value is also loaded into this register provided that the value is smaller than the current value in this register.When written the register is reset to 0xFFFF (65535) regardless of the value written.The minimum.."
|
|
line.long 0x28 "STMPWCNT,Current Value of WCNT"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "CURR_VALUE,Current value of the WCLK counter"
|
|
line.long 0x2C "STMPXCNT,Current Value of XCNT"
|
|
hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x2C 0.--15. 1. "CURR_VALUE,Current value of the XOSC counter latched when reading STMPWCNT"
|
|
line.long 0x30 "STMPXCNTCAPT1,Internal"
|
|
hexmask.long.word 0x30 16.--31. 1. "RESERVED16,Internal"
|
|
newline
|
|
hexmask.long.word 0x30 0.--15. 1. "CAPT_VALUE,Internal"
|
|
line.long 0x34 "STMPWCNTCAPT1,Internal"
|
|
hexmask.long.word 0x34 16.--31. 1. "RESERVED16,Internal"
|
|
newline
|
|
hexmask.long.word 0x34 0.--15. 1. "CAPT_VALUE,Internal"
|
|
group.long 0x70++0x0F
|
|
line.long 0x00 "IRQMASK,Interrupt Mask RegisterSelects mask states of the flags in IRQFLAGS that contribute to the I2S_IRQ event"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 5. "AIF_DMA_IN,IRQFLAGS.AIF_DMA_IN interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "AIF_DMA_OUT,IRQFLAGS.AIF_DMA_OUT interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "WCLK_TIMEOUT,IRQFLAGS.WCLK_TIMEOUT interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 2. "BUS_ERR,IRQFLAGS.BUS_ERR interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. "WCLK_ERR,IRQFLAGS.WCLK_ERR interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 0. "PTR_ERR,IRQFLAGS.PTR_ERR interrupt mask.0: Disable1: Enable" "Disable,Enable"
|
|
line.long 0x04 "IRQFLAGS,Raw Interrupt Status Register"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "AIF_DMA_IN,Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT) see description of AIFINPTRNEXT register for details" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "AIF_DMA_OUT,Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTRNEXT) see description of AIFOUTPTRNEXT register for details" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "WCLK_TIMEOUT,Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "BUS_ERR,Set when a DMA operation is not completed in time (that is audio output buffer underflow or audio input buffer overflow)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "WCLK_ERR,Set when: - An unexpected WCLK edge occurs during the data delay period of a phase" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "PTR_ERR,Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time" "0,1"
|
|
line.long 0x08 "IRQSET,Interrupt Set Register"
|
|
hexmask.long 0x08 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 5. "AIF_DMA_IN," "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "AIF_DMA_OUT," "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "WCLK_TIMEOUT," "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "BUS_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "WCLK_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PTR_ERR," "0,1"
|
|
line.long 0x0C "IRQCLR,Interrupt Clear Register"
|
|
hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 5. "AIF_DMA_IN," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "AIF_DMA_OUT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "WCLK_TIMEOUT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "BUS_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "WCLK_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "PTR_ERR," "0,1"
|
|
tree.end
|
|
tree "IOC"
|
|
base ad:0x40081000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IOCFG0,Configuration of DIO0"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO0Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO1"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO1Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
repeat 15. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO17"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO17Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
repeat 15. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO32"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO32Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "IOCFG43,Configuration of DIO43"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "EDGE_IRQ_EN,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO43Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
tree.end
|
|
tree "PRCM"
|
|
base ad:0x40082000
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "INFRCLKDIVR,Infrastructure Clock Division Factor For Run Mode"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x04 "INFRCLKDIVS,Infrastructure Clock Division Factor For Sleep Mode"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x08 "INFRCLKDIVDS,Infrastructure Clock Division Factor For DeepSleep Mode"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x0C "VDCTL,MCU Voltage Domain Control"
|
|
hexmask.long 0x0C 1.--31. 1. "SPARE1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ULDO,Request PMCTL to switch to uLDO.0: No request1: Assert request when possibleThe bit will have no effect before the following requirements are met:1" "No request,Assert request when.."
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "CLKLOADCTL,Load PRCM Settings To CLKCTRL Power Domain"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "LOAD_DONE,Status of LOAD" "One or more registers have been write accessed..,No registers are write accessed after last LOAD"
|
|
newline
|
|
bitfld.long 0x00 0. "LOAD," "No action,Load settings to CLKCTRL"
|
|
line.long 0x04 "RFCCLKG,RFC Clock Gate"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "CLK_EN," "Disable Clock,Enable clock if RFC power domain is.."
|
|
line.long 0x08 "VIMSCLKG,VIMS Clock Gate"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "CLK_EN," "0,1,2,3"
|
|
group.long 0x3C++0x53
|
|
line.long 0x00 "SECDMACLKGR,SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 24. "DMA_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "PKA_ZERIOZE_RESET_N,Zeroization logic hardware reset.0: pka_zeroize logic inactive.1: pka_zeroize of memory is enabled" "pka_zeroize logic inactive,pka_zeroize of memory is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "PKA_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
bitfld.long 0x00 17. "TRNG_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
bitfld.long 0x00 16. "CRYPTO_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x00 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x00 1. "TRNG_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x00 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x04 "SECDMACLKGS,SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode"
|
|
hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x04 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x04 1. "TRNG_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x04 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x08 "SECDMACLKGDS,SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode"
|
|
hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x08 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x08 1. "TRNG_CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
newline
|
|
bitfld.long 0x08 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
line.long 0x0C "GPIOCLKGR,GPIO Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 8. "AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x10 "GPIOCLKGS,GPIO Clock Gate For Sleep Mode"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x14 "GPIOCLKGDS,GPIO Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x18 "GPTCLKGR,GPT Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "AM_CLK_EN,Each bit below has the following meaning:0: No force1: Force clock on for all modes (Run Sleep and Deep Sleep)Overrides CLK_EN GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled.ENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD.." "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x18 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clock Can be forced on by AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clock Can be forced on by..,?..."
|
|
line.long 0x1C "GPTCLKGS,GPT Clock Gate For Sleep Mode"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clockCan be forced on by GPTCLKGR.AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x20 "GPTCLKGDS,GPT Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x20 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clockCan be forced on by GPTCLKGR.AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x24 "I2CCLKGR,I2C Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 8.--9. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x24 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x24 0.--1. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x28 "I2CCLKGS,I2C Clock Gate For Sleep Mode"
|
|
hexmask.long 0x28 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0.--1. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x2C "I2CCLKGDS,I2C Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x2C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x2C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x30 "UARTCLKGR,UART Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x30 8.--11. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x30 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x30 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x34 "UARTCLKGS,UART Clock Gate For Sleep Mode"
|
|
hexmask.long 0x34 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x34 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x38 "UARTCLKGDS,UART Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x38 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x38 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x3C "SSICLKGR,SSI Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x3C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x3C 8.--11. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x3C 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x3C 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x40 "SSICLKGS,SSI Clock Gate For Sleep Mode"
|
|
hexmask.long 0x40 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x40 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x44 "SSICLKGDS,SSI Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x44 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x44 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x48 "I2SCLKGR,I2S Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x48 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x48 8. "AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x48 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x48 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x4C "I2SCLKGS,I2S Clock Gate For Sleep Mode"
|
|
hexmask.long 0x4C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x4C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x50 "I2SCLKGDS,I2S Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x50 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x50 0. "CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
group.long 0xB4++0x2B
|
|
line.long 0x00 "SYSBUSCLKDIV,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?"
|
|
line.long 0x04 "CPUCLKDIV,Internal"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Internal"
|
|
newline
|
|
bitfld.long 0x04 0. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
line.long 0x08 "PERBUSCPUCLKDIV,Internal"
|
|
hexmask.long 0x08 4.--31. 1. "RESERVED4,Internal"
|
|
newline
|
|
bitfld.long 0x08 0.--3. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.long 0x0C "PERBUSDMACLKDIV,Internal"
|
|
line.long 0x10 "PERDMACLKDIV,Internal"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Internal"
|
|
newline
|
|
bitfld.long 0x10 0.--3. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.long 0x14 "I2SBCLKSEL,I2S Clock Control"
|
|
hexmask.long 0x14 1.--31. 1. "SPARE1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "SRC,BCLK source selector0: Use external BCLK1: Use internally generated clockFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Use external BCLK,Use internally generated clockFor changes to.."
|
|
line.long 0x18 "GPTCLKDIV,GPT Scalar"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "RATIO,Scalar used for GPTs" "Divide by 1,Divide by 2,Divide by 4,Divide by 8,Divide by 16,Divide by 32,Divide by 64,Divide by 128,Divide by 256,?,?,?,?,?,?,?"
|
|
line.long 0x1C "I2SCLKCTL,I2S Clock Control"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 3. "SMPL_ON_POSEDGE,On the I2S serial interface data and WCLK is sampled and clocked out on opposite edges of BCLK" "data and WCLK are sampled on the negative edge..,data and WCLK are sampled on the positive edge.."
|
|
newline
|
|
bitfld.long 0x1C 1.--2. "WCLK_PHASE,Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV)" "Single phase,Dual phase,User Defined,Reserved/UndefinedFor changes to.."
|
|
newline
|
|
bitfld.long 0x1C 0. "EN," "MCLK BCLK and WCLK will be static low,Enables the generation of MCLK BCLK and WCLKFor.."
|
|
line.long 0x20 "I2SMCLKDIV,MCLK Division Ratio"
|
|
hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--9. 1. "MDIV,An unsigned factor of the division ratio used to generate MCLK [2-1024]:MCLK = MCUCLK/MDIV[Hz]MCUCLK is 48MHz.A value of 0 is interpreted as 1024.A value of 1 is invalid.If MDIV is odd the low phase of the clock is one MCUCLK period longer than the.."
|
|
line.long 0x24 "I2SBCLKDIV,BCLK Division Ratio"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--9. 1. "BDIV,An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]:BCLK = MCUCLK/BDIV[Hz]MCUCLK is 48MHz.A value of 0 is interpreted as 1024.A value of 1 is invalid.If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0 the low phase of the.."
|
|
line.long 0x28 "I2SWCLKDIV,WCLK Division Ratio"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "WDIV,If I2SCLKCTL.WCLK_PHASE = 0 Single phase.WCLK is high one BCLK period and low WDIV[9:0] (unsigned [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]MCUCLK is 48MHz.If I2SCLKCTL.WCLK_PHASE = 1 Dual phase.Each phase on WCLK (50% duty.."
|
|
group.long 0xF0++0x1B
|
|
line.long 0x00 "RESETSECDMA,RESET For SEC (PKA And TRNG And CRYPTO) And UDMA"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA,Write 1 to reset" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "PKA,Write 1 to reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRNG,Write 1 to reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CRYPTO,Write 1 to reset" "0,1"
|
|
line.long 0x04 "RESETGPIO,RESET For GPIO IPs"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "GPIO," "No action,Reset GPIO"
|
|
line.long 0x08 "RESETGPT,RESET For GPT Ips"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "GPT," "No action,Reset all GPTs"
|
|
line.long 0x0C "RESETI2C,RESET For I2C IPs"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "I2C1," "No action,Reset I2C1"
|
|
newline
|
|
bitfld.long 0x0C 0. "I2C0," "No action,Reset I2C0"
|
|
line.long 0x10 "RESETUART,RESET For UART IPs"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 3. "UART3," "No action,Reset UART3"
|
|
newline
|
|
bitfld.long 0x10 2. "UART2," "No action,Reset UART2"
|
|
newline
|
|
bitfld.long 0x10 1. "UART1," "No action,Reset UART1"
|
|
newline
|
|
bitfld.long 0x10 0. "UART0," "No action,Reset UART0"
|
|
line.long 0x14 "RESETSSI,RESET For SSI IPs"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3. "SSI3," "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "SSI2," "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "SSI1," "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SSI0," "0,1"
|
|
line.long 0x18 "RESETI2S,RESET For I2S IP"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 0. "I2S," "No action,Reset module"
|
|
group.long 0x12C++0x0F
|
|
line.long 0x00 "PDCTL0,Power Domain Control"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "PERIPH_ON,PERIPH Power domain.0: PERIPH power domain is powered down1: PERIPH power domain is powered up" "PERIPH power domain is powered down,PERIPH power domain is powered up"
|
|
newline
|
|
bitfld.long 0x00 1. "SERIAL_ON,SERIAL Power domain.0: SERIAL power domain is powered down1: SERIAL power domain is powered up" "SERIAL power domain is powered down,SERIAL power domain is powered up"
|
|
newline
|
|
bitfld.long 0x00 0. "RFC_ON," "RFC power domain powered off if also..,RFC power domain powered on"
|
|
line.long 0x04 "PDCTL0RFC,RFC Power Domain Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,Alias for PDCTL0.RFC_ON" "0,1"
|
|
line.long 0x08 "PDCTL0SERIAL,SERIAL Power Domain Control"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,Alias for PDCTL0.SERIAL_ON" "0,1"
|
|
line.long 0x0C "PDCTL0PERIPH,PERIPH Power Domain Control"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,Alias for PDCTL0.PERIPH_ON" "0,1"
|
|
rgroup.long 0x140++0x0F
|
|
line.long 0x00 "PDSTAT0,Power Domain Status"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "PERIPH_ON,PERIPH Power domain.0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
newline
|
|
bitfld.long 0x00 1. "SERIAL_ON,SERIAL Power domain.0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
newline
|
|
bitfld.long 0x00 0. "RFC_ON,RFC Power domain0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
line.long 0x04 "PDSTAT0RFC,RFC Power Domain Status"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,Alias for PDSTAT0.RFC_ON" "0,1"
|
|
line.long 0x08 "PDSTAT0SERIAL,SERIAL Power Domain Status"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,Alias for PDSTAT0.SERIAL_ON" "0,1"
|
|
line.long 0x0C "PDSTAT0PERIPH,PERIPH Power Domain Status"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,Alias for PDSTAT0.PERIPH_ON" "0,1"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "PDCTL1,Power Domain Control"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "VIMS_MODE," "VIMS power domain is only powered when CPU power..,VIMS power domain is powered whenever the BUS..,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "RFC_ON," "RFC power domain powered off if also..,RFC power domain powered on Bit shall be used by.."
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_ON," "Causes a power down of the CPU power domain when..,Initiates power-on of the CPU power domain.This.."
|
|
newline
|
|
rbitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
group.long 0x184++0x0B
|
|
line.long 0x00 "PDCTL1CPU,CPU Power Domain Direct Control"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "ON,This is an alias for PDCTL1.CPU_ON" "0,1"
|
|
line.long 0x04 "PDCTL1RFC,RFC Power Domain Direct Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,This is an alias for PDCTL1.RFC_ON" "0,1"
|
|
line.long 0x08 "PDCTL1VIMS,VIMS Mode Direct Control"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "MODE,This is an alias for PDCTL1.VIMS_MODE" "0,1,2,3"
|
|
rgroup.long 0x194++0x13
|
|
line.long 0x00 "PDSTAT1,Power Manager Status"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4. "BUS_ON," "BUS domain not accessible,BUS domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 3. "VIMS_ON," "VIMS domain not accessible,VIMS domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 2. "RFC_ON," "RFC domain not accessible,RFC domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_ON," "CPU and BUS domain not accessible,CPU and BUS domains are both currently accessible"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x04 "PDSTAT1BUS,BUS Power Domain Direct Read Status"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,This is an alias for PDSTAT1.BUS_ON" "0,1"
|
|
line.long 0x08 "PDSTAT1RFC,RFC Power Domain Direct Read Status"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,This is an alias for PDSTAT1.RFC_ON" "0,1"
|
|
line.long 0x0C "PDSTAT1CPU,CPU Power Domain Direct Read Status"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,This is an alias for PDSTAT1.CPU_ON" "0,1"
|
|
line.long 0x10 "PDSTAT1VIMS,VIMS Mode Direct Read Status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "ON,This is an alias for PDSTAT1.VIMS_ON" "0,1"
|
|
group.long 0x1CC++0x0B
|
|
line.long 0x00 "RFCBITS,Control To RFC"
|
|
line.long 0x04 "RFCMODESEL,Selected RFC Mode"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "CURR,Selects the set of commands that the RFC will accept" "Select Mode 0,Select Mode 1,Select Mode 2,Select Mode 3,Select Mode 4,Select Mode 5,Select Mode 6,Select Mode 7"
|
|
line.long 0x08 "RFCMODEHWOPT,Allowed RFC Modes"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "AVAIL,Permitted RFC modes"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "PWRPROFSTAT,Power Profiler Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VALUE,SW can use these bits to timestamp the application"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "MCUSRAMCFG,MCU SRAM configuration"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "PARITY_EN,Parity enable0: Parity disabled Parity section available as GPRAM1: Parity enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BM_OFF,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PAGE,Page Mode select0: Page Mode disabled" "Page Mode disabled,Page Mode enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "PGS,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BM,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PCH_F,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PCH_L,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "RAMRETEN,Memory Retention Control"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3. "RFCULL," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RFC," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "VIMS," "VIMS,VIMS,?..."
|
|
group.long 0x290++0x0B
|
|
line.long 0x00 "OSCIMSC,Oscillator Interrupt Mask Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "HFSRCPENDIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LFSRCDONEIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "XOSCDLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "XOSCLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RCOSCDLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RCOSCLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "XOSCHFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RCOSCHFIM," "0,1"
|
|
line.long 0x04 "OSCRIS,Oscillator Raw Interrupt Status"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 7. "HFSRCPENDRIS,SCLK_HF source switch pending interrupt.After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source change request then the requested SCLK_HF source will be enabled and qualified" "Indicates SCLK_HF source is not ready to be..,Indicates SCLK_HF source is ready to be.."
|
|
newline
|
|
bitfld.long 0x04 6. "LFSRCDONERIS,SCLK_LF source switch done.The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that the SCLK_LF source shall be changed" "Indicates SCLK_LF source switch has not completed,Indicates SCLK_LF source switch has completed.."
|
|
newline
|
|
bitfld.long 0x04 5. "XOSCDLFRIS,The XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF" "XOSCDLF has not been qualified,XOSCDLF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 4. "XOSCLFRIS,The XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator has been qualified with respect to frequency" "XOSCLF has not been qualified,XOSCLF has been qualified Interrupt is qualified.."
|
|
newline
|
|
bitfld.long 0x04 3. "RCOSCDLFRIS,The RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF" "RCOSCDLF has not been qualified,RCOSCDLF has been qualifiedInterrupt is.."
|
|
newline
|
|
bitfld.long 0x04 2. "RCOSCLFRIS,The RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF oscillator has been qualified with respect to frequency" "RCOSCLF has not been qualified,RCOSCLF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 1. "XOSCHFRIS,The XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been qualified for use as a clock source" "XOSC_HF has not been qualified,XOSC_HF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 0. "RCOSCHFRIS,The RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been qualified for use as a clock source When the RCOSCHFRIS interrupt is high the oscillator is qualified and will be used as a clock source when selected" "RCOSC_HF has not been qualified,RCOSC_HF has been qualifiedInterrupt is.."
|
|
line.long 0x08 "OSCICR,Oscillator Raw Interrupt Clear"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 7. "HFSRCPENDC,Writing 1 to this field clears the HFSRCPEND raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. "LFSRCDONEC,Writing 1 to this field clears the LFSRCDONE raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "XOSCDLFC,Writing 1 to this field clears the XOSCDLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "XOSCLFC,Writing 1 to this field clears the XOSCLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "RCOSCDLFC,Writing 1 to this field clears the RCOSCDLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "RCOSCLFC,Writing 1 to this field clears the RCOSCLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "XOSCHFC,Writing 1 to this field clears the XOSCHF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "RCOSCHFC,Writing 1 to this field clears the RCOSCHF raw interrupt status" "0,1"
|
|
group.long 0x2B0++0x17
|
|
line.long 0x00 "NVMNSCADDR,NVM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x00 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "BOUNDARY,Non-Secure callable boundary address"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "NVMNSADDR,NVM Non-Secure boundary Address"
|
|
rbitfld.long 0x04 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 21.--30. 1. "RESERVED21,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x04 20. "BOUNDARY_MSB,Non-Secure boundary address MSBHW controlled." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 13.--19. 1. "BOUNDARY,Non-Secure boundary address.Writing this field when BUSSECCFG.VALID is set may result in undefined behavior."
|
|
newline
|
|
hexmask.long.word 0x04 0.--12. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x08 "SRAMNSCADDR,SRAM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x08 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x08 19.--30. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 10.--18. 1. "BOUNDARY,Non-Secure callable boundary address"
|
|
newline
|
|
hexmask.long.word 0x08 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "SRAMNSADDR,SRAM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x0C 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0C 19.--30. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x0C 10.--18. 1. "BOUNDARY,Non-Secure boundary address.Writing this field when BUSSECCFG.VALID is set may result in undefined behavior."
|
|
newline
|
|
hexmask.long.word 0x0C 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x10 "BUSSECCFG,BUS Secuirty Configuration Register"
|
|
bitfld.long 0x10 31. "VALID,Security configuration validRegisters that needs to be followed by VALID before settings being applied are:- NVMNSCADDR- NVMNSADDR- SRAMNSCADDR- SRAMNSADDR- BUSSECCFG- CPULOCK" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x10 8.--30. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "BUS_CFG,Bus interconnect security and firewall configuration"
|
|
line.long 0x14 "CPULOCK,CPU Lock Register"
|
|
rbitfld.long 0x14 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long 0x14 5.--30. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 4. "LOCKNSVTOR,When set will lock non-secure vector table base addressWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LOCKSVTAIRCR,When set will lock- Secure vector table base address- Secure interrupt priority- Busfault- Hardfault NMI security targetWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "LOCKSAU,When set will lock SAU regionsWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LOCKNSMPU,When set will lock non-secure MPUWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "LOCKSMPU,When set will lock secure MPUWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
tree.end
|
|
tree "RFC"
|
|
tree "RFC_DBELL"
|
|
base ad:0x40041000
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "CMDR,Doorbell Command Register"
|
|
line.long 0x04 "CMDSTA,Doorbell Command Status Register"
|
|
line.long 0x08 "RFHWIFG,Interrupt Flags From RF Hardware Modules"
|
|
hexmask.long.word 0x08 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 19. "RATCH7,Radio timer channel 7 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 18. "RATCH6,Radio timer channel 6 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 17. "RATCH5,Radio timer channel 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. "RATCH4,Radio timer channel 4 interrupt flag" "0,1"
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newline
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bitfld.long 0x08 15. "RATCH3,Radio timer channel 3 interrupt flag" "0,1"
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newline
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bitfld.long 0x08 14. "RATCH2,Radio timer channel 2 interrupt flag" "0,1"
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newline
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bitfld.long 0x08 13. "RATCH1,Radio timer channel 1 interrupt flag" "0,1"
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newline
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bitfld.long 0x08 12. "RATCH0,Radio timer channel 0 interrupt flag" "0,1"
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newline
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bitfld.long 0x08 11. "RFESOFT2,RF engine software defined interrupt 2 flag" "0,1"
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newline
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bitfld.long 0x08 10. "RFESOFT1,RF engine software defined interrupt 1 flag" "0,1"
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newline
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bitfld.long 0x08 9. "RFESOFT0,RF engine software defined interrupt 0 flag" "0,1"
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newline
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bitfld.long 0x08 8. "RFEDONE,RF engine command done interrupt flag" "0,1"
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newline
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bitfld.long 0x08 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x08 6. "TRCTK,Debug tracer system tick interrupt flag" "0,1"
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newline
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bitfld.long 0x08 5. "MDMSOFT,Modem software defined interrupt flag" "0,1"
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newline
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bitfld.long 0x08 4. "MDMOUT,Modem FIFO output interrupt flag" "0,1"
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newline
|
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bitfld.long 0x08 3. "MDMIN,Modem FIFO input interrupt flag" "0,1"
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newline
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bitfld.long 0x08 2. "MDMDONE,Modem command done interrupt flag" "0,1"
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newline
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bitfld.long 0x08 1. "FSCA,Frequency synthesizer calibration accelerator interrupt flag" "0,1"
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newline
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bitfld.long 0x08 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x0C "RFHWIEN,Interrupt Enable For RF Hardware Modules"
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hexmask.long.word 0x0C 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 19. "RATCH7,Interrupt enable for RFHWIFG.RATCH7" "0,1"
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newline
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bitfld.long 0x0C 18. "RATCH6,Interrupt enable for RFHWIFG.RATCH6" "0,1"
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newline
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bitfld.long 0x0C 17. "RATCH5,Interrupt enable for RFHWIFG.RATCH5" "0,1"
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newline
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bitfld.long 0x0C 16. "RATCH4,Interrupt enable for RFHWIFG.RATCH4" "0,1"
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newline
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bitfld.long 0x0C 15. "RATCH3,Interrupt enable for RFHWIFG.RATCH3" "0,1"
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newline
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bitfld.long 0x0C 14. "RATCH2,Interrupt enable for RFHWIFG.RATCH2" "0,1"
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newline
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bitfld.long 0x0C 13. "RATCH1,Interrupt enable for RFHWIFG.RATCH1" "0,1"
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newline
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bitfld.long 0x0C 12. "RATCH0,Interrupt enable for RFHWIFG.RATCH0" "0,1"
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newline
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bitfld.long 0x0C 11. "RFESOFT2,Interrupt enable for RFHWIFG.RFESOFT2" "0,1"
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newline
|
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bitfld.long 0x0C 10. "RFESOFT1,Interrupt enable for RFHWIFG.RFESOFT1" "0,1"
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newline
|
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bitfld.long 0x0C 9. "RFESOFT0,Interrupt enable for RFHWIFG.RFESOFT0" "0,1"
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newline
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bitfld.long 0x0C 8. "RFEDONE,Interrupt enable for RFHWIFG.RFEDONE" "0,1"
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newline
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bitfld.long 0x0C 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x0C 6. "TRCTK,Interrupt enable for RFHWIFG.TRCTK" "0,1"
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newline
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bitfld.long 0x0C 5. "MDMSOFT,Interrupt enable for RFHWIFG.MDMSOFT" "0,1"
|
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newline
|
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bitfld.long 0x0C 4. "MDMOUT,Interrupt enable for RFHWIFG.MDMOUT" "0,1"
|
|
newline
|
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bitfld.long 0x0C 3. "MDMIN,Interrupt enable for RFHWIFG.MDMIN" "0,1"
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newline
|
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bitfld.long 0x0C 2. "MDMDONE,Interrupt enable for RFHWIFG.MDMDONE" "0,1"
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newline
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bitfld.long 0x0C 1. "FSCA,Interrupt enable for RFHWIFG.FSCA" "0,1"
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newline
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bitfld.long 0x0C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x10 "RFCPEIFG,Interrupt Flags For Command and Packet Engine Generated Interrupts"
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bitfld.long 0x10 31. "INTERNAL_ERROR,Interrupt flag 31" "0,1"
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newline
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bitfld.long 0x10 30. "BOOT_DONE,Interrupt flag 30" "0,1"
|
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newline
|
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bitfld.long 0x10 29. "MODULES_UNLOCKED,Interrupt flag 29" "0,1"
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newline
|
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bitfld.long 0x10 28. "SYNTH_NO_LOCK,Interrupt flag 28" "0,1"
|
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newline
|
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bitfld.long 0x10 27. "IRQ27,Interrupt flag 27" "0,1"
|
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newline
|
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bitfld.long 0x10 26. "RX_ABORTED,Interrupt flag 26" "0,1"
|
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newline
|
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bitfld.long 0x10 25. "RX_N_DATA_WRITTEN,Interrupt flag 25" "0,1"
|
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newline
|
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bitfld.long 0x10 24. "RX_DATA_WRITTEN,Interrupt flag 24" "0,1"
|
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newline
|
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bitfld.long 0x10 23. "RX_ENTRY_DONE,Interrupt flag 23" "0,1"
|
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newline
|
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bitfld.long 0x10 22. "RX_BUF_FULL,Interrupt flag 22" "0,1"
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newline
|
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bitfld.long 0x10 21. "RX_CTRL_ACK,Interrupt flag 21" "0,1"
|
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newline
|
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bitfld.long 0x10 20. "RX_CTRL,Interrupt flag 20" "0,1"
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newline
|
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bitfld.long 0x10 19. "RX_EMPTY,Interrupt flag 19" "0,1"
|
|
newline
|
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bitfld.long 0x10 18. "RX_IGNORED,Interrupt flag 18" "0,1"
|
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newline
|
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bitfld.long 0x10 17. "RX_NOK,Interrupt flag 17" "0,1"
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newline
|
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bitfld.long 0x10 16. "RX_OK,Interrupt flag 16" "0,1"
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newline
|
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bitfld.long 0x10 15. "IRQ15,Interrupt flag 15" "0,1"
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newline
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bitfld.long 0x10 14. "IRQ14,Interrupt flag 14" "0,1"
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newline
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bitfld.long 0x10 13. "FG_COMMAND_STARTED,Interrupt flag 13" "0,1"
|
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newline
|
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bitfld.long 0x10 12. "COMMAND_STARTED,Interrupt flag 12" "0,1"
|
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newline
|
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bitfld.long 0x10 11. "TX_BUFFER_CHANGED,Interrupt flag 11" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "TX_ENTRY_DONE,Interrupt flag 10" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "TX_RETRANS,Interrupt flag 9" "0,1"
|
|
newline
|
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bitfld.long 0x10 8. "TX_CTRL_ACK_ACK,Interrupt flag 8" "0,1"
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newline
|
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bitfld.long 0x10 7. "TX_CTRL_ACK,Interrupt flag 7" "0,1"
|
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newline
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bitfld.long 0x10 6. "TX_CTRL,Interrupt flag 6" "0,1"
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newline
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bitfld.long 0x10 5. "TX_ACK,Interrupt flag 5" "0,1"
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newline
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bitfld.long 0x10 4. "TX_DONE,Interrupt flag 4" "0,1"
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newline
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bitfld.long 0x10 3. "LAST_FG_COMMAND_DONE,Interrupt flag 3" "0,1"
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newline
|
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bitfld.long 0x10 2. "FG_COMMAND_DONE,Interrupt flag 2" "0,1"
|
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newline
|
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bitfld.long 0x10 1. "LAST_COMMAND_DONE,Interrupt flag 1" "0,1"
|
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newline
|
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bitfld.long 0x10 0. "COMMAND_DONE,Interrupt flag 0" "0,1"
|
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line.long 0x14 "RFCPEIEN,Interrupt Enable For Command and Packet Engine Generated Interrupts"
|
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bitfld.long 0x14 31. "INTERNAL_ERROR,Interrupt enable for RFCPEIFG.INTERNAL_ERROR" "0,1"
|
|
newline
|
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bitfld.long 0x14 30. "BOOT_DONE,Interrupt enable for RFCPEIFG.BOOT_DONE" "0,1"
|
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newline
|
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bitfld.long 0x14 29. "MODULES_UNLOCKED,Interrupt enable for RFCPEIFG.MODULES_UNLOCKED" "0,1"
|
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newline
|
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bitfld.long 0x14 28. "SYNTH_NO_LOCK,Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK" "0,1"
|
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newline
|
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bitfld.long 0x14 27. "IRQ27,Interrupt enable for RFCPEIFG.IRQ27" "0,1"
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newline
|
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bitfld.long 0x14 26. "RX_ABORTED,Interrupt enable for RFCPEIFG.RX_ABORTED" "0,1"
|
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newline
|
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bitfld.long 0x14 25. "RX_N_DATA_WRITTEN,Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN" "0,1"
|
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newline
|
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bitfld.long 0x14 24. "RX_DATA_WRITTEN,Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN" "0,1"
|
|
newline
|
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bitfld.long 0x14 23. "RX_ENTRY_DONE,Interrupt enable for RFCPEIFG.RX_ENTRY_DONE" "0,1"
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newline
|
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bitfld.long 0x14 22. "RX_BUF_FULL,Interrupt enable for RFCPEIFG.RX_BUF_FULL" "0,1"
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newline
|
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bitfld.long 0x14 21. "RX_CTRL_ACK,Interrupt enable for RFCPEIFG.RX_CTRL_ACK" "0,1"
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newline
|
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bitfld.long 0x14 20. "RX_CTRL,Interrupt enable for RFCPEIFG.RX_CTRL" "0,1"
|
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newline
|
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bitfld.long 0x14 19. "RX_EMPTY,Interrupt enable for RFCPEIFG.RX_EMPTY" "0,1"
|
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newline
|
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bitfld.long 0x14 18. "RX_IGNORED,Interrupt enable for RFCPEIFG.RX_IGNORED" "0,1"
|
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newline
|
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bitfld.long 0x14 17. "RX_NOK,Interrupt enable for RFCPEIFG.RX_NOK" "0,1"
|
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newline
|
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bitfld.long 0x14 16. "RX_OK,Interrupt enable for RFCPEIFG.RX_OK" "0,1"
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newline
|
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bitfld.long 0x14 15. "IRQ15,Interrupt enable for RFCPEIFG.IRQ15" "0,1"
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newline
|
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bitfld.long 0x14 14. "IRQ14,Interrupt enable for RFCPEIFG.IRQ14" "0,1"
|
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newline
|
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bitfld.long 0x14 13. "FG_COMMAND_STARTED,Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED" "0,1"
|
|
newline
|
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bitfld.long 0x14 12. "COMMAND_STARTED,Interrupt enable for RFCPEIFG.COMMAND_STARTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "TX_BUFFER_CHANGED,Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED" "0,1"
|
|
newline
|
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bitfld.long 0x14 10. "TX_ENTRY_DONE,Interrupt enable for RFCPEIFG.TX_ENTRY_DONE" "0,1"
|
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newline
|
|
bitfld.long 0x14 9. "TX_RETRANS,Interrupt enable for RFCPEIFG.TX_RETRANS" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "TX_CTRL_ACK_ACK,Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "TX_CTRL_ACK,Interrupt enable for RFCPEIFG.TX_CTRL_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "TX_CTRL,Interrupt enable for RFCPEIFG.TX_CTRL" "0,1"
|
|
newline
|
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bitfld.long 0x14 5. "TX_ACK,Interrupt enable for RFCPEIFG.TX_ACK" "0,1"
|
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newline
|
|
bitfld.long 0x14 4. "TX_DONE,Interrupt enable for RFCPEIFG.TX_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LAST_FG_COMMAND_DONE,Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "FG_COMMAND_DONE,Interrupt enable for RFCPEIFG.FG_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LAST_COMMAND_DONE,Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "COMMAND_DONE,Interrupt enable for RFCPEIFG.COMMAND_DONE" "0,1"
|
|
line.long 0x18 "RFCPEISL,Interrupt Vector Selection For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x18 31. "INTERNAL_ERROR,Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 30. "BOOT_DONE,Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
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|
newline
|
|
bitfld.long 0x18 29. "MODULES_UNLOCKED,Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 28. "SYNTH_NO_LOCK,Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 27. "IRQ27,Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
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|
newline
|
|
bitfld.long 0x18 26. "RX_ABORTED,Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 25. "RX_N_DATA_WRITTEN,Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 24. "RX_DATA_WRITTEN,Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 23. "RX_ENTRY_DONE,Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 22. "RX_BUF_FULL,Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 21. "RX_CTRL_ACK,Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 20. "RX_CTRL,Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 19. "RX_EMPTY,Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 18. "RX_IGNORED,Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 17. "RX_NOK,Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 16. "RX_OK,Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 15. "IRQ15,Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 14. "IRQ14,Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 13. "FG_COMMAND_STARTED,Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 12. "COMMAND_STARTED,Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 11. "TX_BUFFER_CHANGED,Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 10. "TX_ENTRY_DONE,Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 9. "TX_RETRANS,Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 8. "TX_CTRL_ACK_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 7. "TX_CTRL_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 6. "TX_CTRL,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 5. "TX_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 4. "TX_DONE,Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 3. "LAST_FG_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 2. "FG_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 1. "LAST_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 0. "COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
line.long 0x1C "RFACKIFG,Doorbell Command Acknowledgement Interrupt Flag"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0. "ACKFLAG,Interrupt flag for Command ACK" "0,1"
|
|
line.long 0x20 "SYSGPOCTL,RF Core General Purpose Output Control"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 12.--15. "GPOCTL3,RF Core GPO control bit 3" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 8.--11. "GPOCTL2,RF Core GPO control bit 2" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 4.--7. "GPOCTL1,RF Core GPO control bit 1" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 0.--3. "GPOCTL0,RF Core GPO control bit 0" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
tree.end
|
|
tree "RFC_PWR"
|
|
base ad:0x40040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCLKEN,RF Core Power Management and Clock Enable"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 13. "DEMOD,Enable clock to the Demodulator" "0,1"
|
|
bitfld.long 0x00 12. "MOD,Enable clock to the Modulator" "0,1"
|
|
bitfld.long 0x00 11. "IQRAM,Enable clock to IQ RAM in coherent demodulator" "0,1"
|
|
bitfld.long 0x00 10. "RFCTRC,Enable clock to the RF Core Tracer (RFCTRC) module" "0,1"
|
|
bitfld.long 0x00 9. "FSCA,Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) module" "0,1"
|
|
bitfld.long 0x00 8. "PHA,Enable clock to the Packet Handling Accelerator (PHA) module" "0,1"
|
|
bitfld.long 0x00 7. "RAT,Enable clock to the Radio Timer (RAT) module" "0,1"
|
|
bitfld.long 0x00 6. "RFERAM,Enable clock to the RF Engine RAM module" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RFE,Enable clock to the RF Engine (RFE) module" "0,1"
|
|
bitfld.long 0x00 4. "MDMRAM,Enable clock to the Modem RAM module" "0,1"
|
|
bitfld.long 0x00 3. "MDM,Enable clock to the Modem (MDM) module" "0,1"
|
|
bitfld.long 0x00 2. "CPERAM,Enable clock to the Command and Packet Engine (CPE) RAM module" "0,1"
|
|
bitfld.long 0x00 1. "CPE,Enable processor clock (hclk) to the Command and Packet Engine (CPE)" "0,1"
|
|
rbitfld.long 0x00 0. "RFC,Enable essential clocks for the RF Core interface" "0,1"
|
|
tree.end
|
|
tree "RFC_RAT"
|
|
base ad:0x40043000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RATCNT,Radio Timer Counter Value"
|
|
group.long 0x80++0x1F
|
|
line.long 0x00 "RATCH0VAL,Timer Channel 0 Capture/Compare Register"
|
|
line.long 0x04 "RATCH1VAL,Timer Channel 1 Capture/Compare Register"
|
|
line.long 0x08 "RATCH2VAL,Timer Channel 2 Capture/Compare Register"
|
|
line.long 0x0C "RATCH3VAL,Timer Channel 3 Capture/Compare Register"
|
|
line.long 0x10 "RATCH4VAL,Timer Channel 4 Capture/Compare Register"
|
|
line.long 0x14 "RATCH5VAL,Timer Channel 5 Capture/Compare Register"
|
|
line.long 0x18 "RATCH6VAL,Timer Channel 6 Capture/Compare Register"
|
|
line.long 0x1C "RATCH7VAL,Timer Channel 7 Capture/Compare Register"
|
|
tree.end
|
|
tree.end
|
|
tree "SMPH"
|
|
base ad:0x40084000
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SMPH$1,MCU SEMAPHORE 0"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is availableReading the register causes it to change value to 0" "Semaphore is taken,Semaphore is availableReading the register.."
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "SMPH$1,MCU SEMAPHORE 16"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is availableReading the register causes it to change value to 0" "Semaphore is taken,Semaphore is availableReading the register.."
|
|
repeat.end
|
|
rgroup.long 0x800++0x7F
|
|
line.long 0x00 "PEEK0,MCU SEMAPHORE 0 ALIAS"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x04 "PEEK1,MCU SEMAPHORE 1 ALIAS"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x08 "PEEK2,MCU SEMAPHORE 2 ALIAS"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x0C "PEEK3,MCU SEMAPHORE 3 ALIAS"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x10 "PEEK4,MCU SEMAPHORE 4 ALIAS"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x14 "PEEK5,MCU SEMAPHORE 5 ALIAS"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x18 "PEEK6,MCU SEMAPHORE 6 ALIAS"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x1C "PEEK7,MCU SEMAPHORE 7 ALIAS"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x20 "PEEK8,MCU SEMAPHORE 8 ALIAS"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x24 "PEEK9,MCU SEMAPHORE 9 ALIAS"
|
|
hexmask.long 0x24 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x28 "PEEK10,MCU SEMAPHORE 10 ALIAS"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x2C "PEEK11,MCU SEMAPHORE 11 ALIAS"
|
|
hexmask.long 0x2C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x30 "PEEK12,MCU SEMAPHORE 12 ALIAS"
|
|
hexmask.long 0x30 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x30 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x34 "PEEK13,MCU SEMAPHORE 13 ALIAS"
|
|
hexmask.long 0x34 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x34 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x38 "PEEK14,MCU SEMAPHORE 14 ALIAS"
|
|
hexmask.long 0x38 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x38 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x3C "PEEK15,MCU SEMAPHORE 15 ALIAS"
|
|
hexmask.long 0x3C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x3C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x40 "PEEK16,MCU SEMAPHORE 16 ALIAS"
|
|
hexmask.long 0x40 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x40 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x44 "PEEK17,MCU SEMAPHORE 17 ALIAS"
|
|
hexmask.long 0x44 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x44 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x48 "PEEK18,MCU SEMAPHORE 18 ALIAS"
|
|
hexmask.long 0x48 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x48 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x4C "PEEK19,MCU SEMAPHORE 19 ALIAS"
|
|
hexmask.long 0x4C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x4C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x50 "PEEK20,MCU SEMAPHORE 20 ALIAS"
|
|
hexmask.long 0x50 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x50 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x54 "PEEK21,MCU SEMAPHORE 21 ALIAS"
|
|
hexmask.long 0x54 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x54 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x58 "PEEK22,MCU SEMAPHORE 22 ALIAS"
|
|
hexmask.long 0x58 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x58 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x5C "PEEK23,MCU SEMAPHORE 23 ALIAS"
|
|
hexmask.long 0x5C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x5C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x60 "PEEK24,MCU SEMAPHORE 24 ALIAS"
|
|
hexmask.long 0x60 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x60 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x64 "PEEK25,MCU SEMAPHORE 25 ALIAS"
|
|
hexmask.long 0x64 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x64 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x68 "PEEK26,MCU SEMAPHORE 26 ALIAS"
|
|
hexmask.long 0x68 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x68 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x6C "PEEK27,MCU SEMAPHORE 27 ALIAS"
|
|
hexmask.long 0x6C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x6C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x70 "PEEK28,MCU SEMAPHORE 28 ALIAS"
|
|
hexmask.long 0x70 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x70 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x74 "PEEK29,MCU SEMAPHORE 29 ALIAS"
|
|
hexmask.long 0x74 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x74 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x78 "PEEK30,MCU SEMAPHORE 30 ALIAS"
|
|
hexmask.long 0x78 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x78 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x7C "PEEK31,MCU SEMAPHORE 31 ALIAS"
|
|
hexmask.long 0x7C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x7C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
tree.end
|
|
tree "SSI"
|
|
repeat 2. (list 0. 1. )(list ad:0x40000000 ad:0x40008000 )
|
|
tree "SSI$1"
|
|
base $2
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CR0,Control 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "SCR,Serial clock rate:This is used to generate the transmit and receive bit rate of the SSI"
|
|
newline
|
|
bitfld.long 0x00 7. "SPH,CLKOUT phase (Motorola SPI frame format only)This bit selects the clock edge that captures data and enables it to change state" "Data is captured on the first clock edge..,Data is captured on the second clock edge.."
|
|
newline
|
|
bitfld.long 0x00 6. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "SSI produces a steady state LOW value on..,SSI produces a steady state HIGH value on the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "FRF,Frame format" "Motorola SPI frame format,TI synchronous serial frame format,National Microwire frame format,?"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DSS,Data Size Select" "?,?,?,4-bit data,5-bit data,6-bit data,7-bit data,8-bit data,9-bit data,10-bit data,11-bit data,12-bit data,13-bit data,14-bit data,15-bit data,16-bit data"
|
|
line.long 0x04 "CR1,Control 1"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 3. "SOD,Slave-mode output disabledThis bit is relevant only in the slave mode MS=1" "SSI can drive the TXD output in slave mode,SSI cannot drive the TXD output in slave mode"
|
|
newline
|
|
bitfld.long 0x04 2. "MS,Master or slave mode select" "Device configured as master,Device configured as slave"
|
|
newline
|
|
bitfld.long 0x04 1. "SSE,Synchronous serial interface enable" "Operation disabled,Operation enabled"
|
|
newline
|
|
bitfld.long 0x04 0. "LBM,Loop back mode:0: Normal serial port operation enabled.1: Output of transmit serial shifter is connected to input of receive serial shifter internally" "Normal serial port operation enabled,Output of transmit serial shifter is connected.."
|
|
line.long 0x08 "DR,Data16-bits wide data register:When read. the entry in the receive FIFO. pointed to by the current FIFO read pointer. is accessed"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "DATA,Transmit/receive dataThe values read from this field or written to this field must be right-justified when SSI is programmed for a data size that is less than 16 bits (CR0.DSS != 0b1111)"
|
|
line.long 0x0C "SR,Status"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 4. "BSY,Serial interface busy:0: SSI is idle1: SSI is currently transmitting and/or receiving a frame or the transmit FIFO is not empty" "SSI is idle,SSI is currently transmitting.."
|
|
newline
|
|
bitfld.long 0x0C 3. "RFF,Receive FIFO full:0: Receive FIFO is not full.1: Receive FIFO is full" "Receive FIFO is not full,Receive FIFO is full"
|
|
newline
|
|
bitfld.long 0x0C 2. "RNE,Receive FIFO not empty0: Receive FIFO is empty.1: Receive FIFO is not empty" "Receive FIFO is empty,Receive FIFO is not empty"
|
|
newline
|
|
bitfld.long 0x0C 1. "TNF,Transmit FIFO not full:0: Transmit FIFO is full.1: Transmit FIFO is not full" "Transmit FIFO is full,Transmit FIFO is not full"
|
|
newline
|
|
bitfld.long 0x0C 0. "TFE,Transmit FIFO empty:0: Transmit FIFO is not empty.1: Transmit FIFO is empty" "Transmit FIFO is not empty,Transmit FIFO is empty"
|
|
line.long 0x10 "CPSR,Clock Prescale"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "CPSDVSR,Clock prescale divisor:This field specifies the division factor by which the input system clock to SSI must be internally divided before further use.The value programmed into this field must be an even non-zero number (2-254)"
|
|
line.long 0x14 "IMSC,Interrupt Mask Set and Clear"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3. "TXIM,Transmit FIFO interrupt mask:A read returns the current mask for transmit FIFO interrupt" "0,1"
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|
newline
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bitfld.long 0x14 2. "RXIM,Receive FIFO interrupt mask:A read returns the current mask for receive FIFO interrupt" "0,1"
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|
newline
|
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bitfld.long 0x14 1. "RTIM,Receive timeout interrupt mask:A read returns the current mask for receive timeout interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x14 0. "RORIM,Receive overrun interrupt mask:A read returns the current mask for receive overrun interrupt" "0,1"
|
|
line.long 0x18 "RIS,Raw Interrupt Status"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 3. "TXRIS,Raw transmit FIFO interrupt status:The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO" "0,1"
|
|
newline
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bitfld.long 0x18 2. "RXRIS,Raw interrupt state of receive FIFO interrupt:The receive interrupt is asserted when there are four or more valid entries in the receive FIFO" "0,1"
|
|
newline
|
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bitfld.long 0x18 1. "RTRIS,Raw interrupt state of receive timeout interrupt:The receive timeout interrupt is asserted when the receive FIFO is not empty and SSI has remained idle for a fixed 32 bit period" "0,1"
|
|
newline
|
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bitfld.long 0x18 0. "RORRIS,Raw interrupt state of receive overrun interrupt:The receive overrun interrupt is asserted when the FIFO is already full and an additional data frame is received causing an overrun of the FIFO" "0,1"
|
|
line.long 0x1C "MIS,Masked Interrupt Status"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 3. "TXMIS,Masked interrupt state of transmit FIFO interrupt:This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM" "0,1"
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|
newline
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bitfld.long 0x1C 2. "RXMIS,Masked interrupt state of receive FIFO interrupt:This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM" "0,1"
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|
newline
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bitfld.long 0x1C 1. "RTMIS,Masked interrupt state of receive timeout interrupt:This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM" "0,1"
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|
newline
|
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bitfld.long 0x1C 0. "RORMIS,Masked interrupt state of receive overrun interrupt:This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM" "0,1"
|
|
line.long 0x20 "ICR,Interrupt ClearOn a write of 1. the corresponding interrupt is cleared"
|
|
hexmask.long 0x20 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 1. "RTIC,Clear the receive timeout interrupt:Writing 1 to this field clears the timeout interrupt (RIS.RTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "RORIC,Clear the receive overrun interrupt:Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS)" "0,1"
|
|
line.long 0x24 "DMACR,DMA Control"
|
|
hexmask.long 0x24 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 1. "TXDMAE,Transmit DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "RXDMAE,Receive DMA enable" "0,1"
|
|
repeat 2. (list 1. 2. )(list 0x00 0x68 )
|
|
rgroup.long ($2+0x28)++0x03
|
|
line.long 0x00 "RESERVED$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "TRNG"
|
|
base ad:0x40028000
|
|
rgroup.long 0x00++0x3B
|
|
line.long 0x00 "OUT0,Random Number Lower Word Readout Value"
|
|
line.long 0x04 "OUT1,Random Number Upper Word Readout Value"
|
|
line.long 0x08 "IRQFLAGSTAT,Interrupt Status"
|
|
bitfld.long 0x08 31. "NEED_CLOCK," "0,1"
|
|
hexmask.long 0x08 2.--30. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "SHUTDOWN_OVF," "0,1"
|
|
bitfld.long 0x08 0. "RDY," "0,1"
|
|
line.long 0x0C "IRQFLAGMASK,Interrupt Mask"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 1. "SHUTDOWN_OVF," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "RDY," "0,1"
|
|
line.long 0x10 "IRQFLAGCLR,Interrupt Flag Clear"
|
|
hexmask.long 0x10 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 1. "SHUTDOWN_OVF," "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "RDY," "0,1"
|
|
line.long 0x14 "CTL,Control"
|
|
abitfld.long 0x14 16.--31. "STARTUP_CYCLES,This field determines the number of samples (between 2^8 and 2^24) taken to gather entropy from the FROs during startup" "0x0000=2^24 samples,0x0001=1*2^8 samples,0x0002=2*2^8 samples,0x0003=3*2^8 samples,0x8000=32768*2^8 samples,0xC000=49152*2^8 samples,0xFFFF=65535*2^8 samplesThis field can only be.."
|
|
rbitfld.long 0x14 11.--15. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x14 10. "TRNG_EN," "0,1"
|
|
hexmask.long.byte 0x14 3.--9. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 2. "NO_LFSR_FB," "0,1"
|
|
bitfld.long 0x14 1. "TEST_MODE," "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x18 "CFG0,Configuration 0"
|
|
abitfld.long 0x18 16.--31. "MAX_REFILL_CYCLES,This field determines the maximum number of samples (between 2^8 and 2^24) taken to re-generate entropy from the FROs after reading out a 64 bits random number" "0x0000=2^24 samples,0x0001=1*2^8 samples,0x0002=2*2^8 samples,0x0003=3*2^8 samples,0x8000=32768*2^8 samples,0xC000=49152*2^8 samples,0xFFFF=65535*2^8 samplesThis field can only be.."
|
|
rbitfld.long 0x18 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x18 8.--11. "SMPL_DIV,This field directly controls the number of clock cycles between samples taken from the FROs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
abitfld.long 0x18 0.--7. "MIN_REFILL_CYCLES,This field determines the minimum number of samples (between 2^6 and 2^14) taken to re-generate entropy from the FROs after reading out a 64 bits random number" "0x00=Minimum samples = MAX_REFILL_CYCLES (all..,0x01=1*2^6 samples,0x02=2*2^6 samples,0xFF=255*2^6 samples"
|
|
line.long 0x1C "ALARMCNT,Alarm Control"
|
|
rbitfld.long 0x1C 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x1C 24.--29. "SHUTDOWN_CNT,Read-only indicates the number of '1' bits in ALARMSTOP register.The maximum value equals the number of FROs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x1C 21.--23. "RESERVED21,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 16.--20. "SHUTDOWN_THR,Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "ALARM_THR,Alarm detection threshold for the repeating pattern detectors on each FRO"
|
|
line.long 0x20 "FROEN,FRO Enable"
|
|
hexmask.long.byte 0x20 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "FRO_MASK,Enable bits for the individual FROs"
|
|
line.long 0x24 "FRODETUNE,FRO De-tune Bit"
|
|
hexmask.long.byte 0x24 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "FRO_MASK,De-tune bits for the individual FROs"
|
|
line.long 0x28 "ALARMMASK,Alarm Event"
|
|
hexmask.long.byte 0x28 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "FRO_MASK,Logging bits for the 'alarm events' of individual FROs"
|
|
line.long 0x2C "ALARMSTOP,Alarm Shutdown"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "FRO_FLAGS,Logging bits for the 'alarm events' of individual FROs"
|
|
line.long 0x30 "LFSR0,LFSR Readout Value"
|
|
line.long 0x34 "LFSR1,LFSR Readout Value"
|
|
line.long 0x38 "LFSR2,LFSR Readout Value"
|
|
hexmask.long.word 0x38 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x38 0.--16. 1. "LFSR_80_64,Bits [80:64] of the main entropy accumulation LFSR"
|
|
rgroup.long 0x78++0x07
|
|
line.long 0x00 "HWOPT,TRNG Engine Options Information"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 6.--11. "NR_OF_FROS,Number of FROs implemented in this TRNG value 24 (decimal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "HWVER0,HW Version 0EIP Number And Core Revision"
|
|
bitfld.long 0x04 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. "HW_MAJOR_VER,4 bits binary encoding of the major hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 20.--23. "HW_MINOR_VER,4 bits binary encoding of the minor hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. "HW_PATCH_LVL,4 bits binary encoding of the hardware patch level initial release will carry value zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "EIP_NUM_COMPL,Bit-by-bit logic complement of bits [7:0]"
|
|
hexmask.long.byte 0x04 0.--7. 1. "EIP_NUM,8 bits binary encoding of the module number"
|
|
rgroup.long 0x1FD8++0x03
|
|
line.long 0x00 "IRQSTATMASK,Interrupt Status After Masking"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "SHUTDOWN_OVF,Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with IRQFLAGMASK.SHUTDOWN_OVF)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RDY,New random value available (result of IRQFLAGSTAT.RDY AND'ed with IRQFLAGMASK.RDY)" "0,1"
|
|
rgroup.long 0x1FE0++0x03
|
|
line.long 0x00 "HWVER1,HW Version 1TRNG Revision Number"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,The revision number of this module is Rev 2.0"
|
|
group.long 0x1FEC++0x07
|
|
line.long 0x00 "IRQSET,Interrupt Set"
|
|
line.long 0x04 "SWRESET,SW Reset Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "RESET,Write '1' to soft reset reset will be low for 4-5 clock cycles" "0,1"
|
|
rgroup.long 0x1FF8++0x03
|
|
line.long 0x00 "IRQSTAT,Interrupt Status"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,TRNG Interrupt status" "0,1"
|
|
tree.end
|
|
tree "UART0"
|
|
base ad:0x40001000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,DataFor words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1). data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0). data is stored in the transmitter holding register (the bottom.."
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 11. "OE,UART Overrun Error:This bit is set to 1 if data is received and the receive FIFO is already full" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "BE,UART Break Error:This bit is set to 1 if a break condition was detected indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits).In FIFO mode.." "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "PE,UART Parity Error:When set to 1 it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select.In FIFO mode this error is associated with the character at the top of the FIFO (that is the.." "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "FE,UART Framing Error:When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).In FIFO mode this error is associated with the character at the top of the FIFO (that is. the oldest received data.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Data transmitted or received:On writes the transmit data character is pushed into the FIFO.On reads the oldest received data character since the last read is returned"
|
|
line.long 0x04 "RSR,StatusThis register is mapped to the same address as ECR register"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 3. "OE,UART Overrun Error:This bit is set to 1 if data is received and the receive FIFO is already full" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "BE,UART Break Error:This bit is set to 1 if a break condition was detected indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits).When a break.." "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "PE,UART Parity Error:When set to 1 it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "FE,UART Framing Error:When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1)" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ECR,Error ClearThis register is mapped to the same address as RSR register"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3. "OE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "FE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
|
|
repeat 5. (list 0. 2. 1. 3. 4. )(list 0x00 0x14 0x44 0x88 0xFC8 )
|
|
rgroup.long ($2+0x08)++0x03
|
|
line.long 0x00 "RESERVED$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "FR,FlagReads from this register return the UART flags"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "TXFE,UART Transmit FIFO Empty:The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled this bit is set when the transmit holding register is empty. - If the FIFO is enabled this bit is set when the transmit FIFO is empty.This.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RXFF,UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled this bit is set when the receive holding register is full. - If the FIFO is enabled this bit is set when the receive FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TXFF,UART Transmit FIFO Full:Transmit FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXFE,UART Receive FIFO Empty:Receive FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BUSY,UART Busy: If this bit is set to 1 the UART is busy transmitting data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "CTS,Clear To Send: This bit is the complement of the active-low UART CTS input pin.That is the bit is 1 when CTS input pin is LOW" "0,1"
|
|
group.long 0x24++0x27
|
|
line.long 0x00 "IBRD,Integer Baud-Rate DivisorIf this register is modified while transmission or reception is on-going. the baud rate will not be updated until transmission or reception of the current character is complete"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DIVINT,The integer baud rate divisor:The baud rate divisor is calculated using the formula below:Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)Baud rate divisor must be minimum 1 and maximum 65535"
|
|
line.long 0x04 "FBRD,Fractional Baud-Rate DivisorIf this register is modified while trasmission or reception is on-going. the baudrate will not be updated until transmission or reception of the current character is complete"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "DIVFRAC,Fractional Baud-Rate Divisor:The baud rate divisor is calculated using the formula below:Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)Baud rate divisor must be minimum 1 and maximum 65535" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "LCRH,Line Control"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 7. "SPS,UART Stick Parity Select:0: Stick parity is disabled1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0).This bit has no effect when PEN disables parity checking and.." "Stick parity is disabled,The parity bit is transmitted and checked as.."
|
|
newline
|
|
bitfld.long 0x08 5.--6. "WLEN,UART Word Length:These bits indicate the number of data bits transmitted or received in a frame" "Word Length 5 bits,Word Length 6 bits,Word Length 7 bits,Word Length 8 bits"
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|
newline
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bitfld.long 0x08 4. "FEN,UART Enable FIFOs" "FIFOs are disabled (character mode) that is the..,Transmit and receive FIFO buffers are enabled.."
|
|
newline
|
|
bitfld.long 0x08 3. "STP2,UART Two Stop Bits Select:If this bit is set to 1 two stop bits are transmitted at the end of the frame" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "EPS,UART Even Parity Select" "Odd parity: The UART generates or checks for an..,Even parity: The UART generates or checks for an.."
|
|
newline
|
|
bitfld.long 0x08 1. "PEN,UART Parity EnableThis bit controls generation and checking of parity bit" "Parity is disabled and no parity bit is added to..,Parity checking and generation is enabled."
|
|
newline
|
|
bitfld.long 0x08 0. "BRK,UART Send BreakIf this bit is set to 1 a low-level is continually output on the UARTTXD output pin after completing transmission of the current character" "0,1"
|
|
line.long 0x0C "CTL,Control"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 15. "CTSEN,CTS hardware flow control enable" "CTS hardware flow control disabled,CTS hardware flow control enabled"
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|
newline
|
|
bitfld.long 0x0C 14. "RTSEN,RTS hardware flow control enable" "RTS hardware flow control disabled,RTS hardware flow control enabled"
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|
newline
|
|
bitfld.long 0x0C 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 11. "RTS,Request to SendThis bit is the complement of the active-low UART RTS output" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 10. "RESERVED10,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RXE,UART Receive EnableIf the UART is disabled in the middle of reception it completes the current character before stopping" "UART Receive disabled,UART Receive enabled"
|
|
newline
|
|
bitfld.long 0x0C 8. "TXE,UART Transmit EnableIf the UART is disabled in the middle of transmission it completes the current character before stopping" "UART Transmit disabled,UART Transmit enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. "LBE,UART Loop Back Enable:Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART" "Loop Back disabled,Loop Back enabled"
|
|
newline
|
|
bitfld.long 0x0C 1.--6. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
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bitfld.long 0x0C 0. "UARTEN,UART Enable" "UART disabled,UART enabled"
|
|
line.long 0x10 "IFLS,Interrupt FIFO Level Select"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 3.--5. "RXSEL,Receive interrupt FIFO level select:This field sets the trigger points for the receive interrupt" "Receive FIFO becomes >= 1/8 full,Receive FIFO becomes >= 1/4 full,Receive FIFO becomes >= 1/2 full,Receive FIFO becomes >= 3/4 full,Receive FIFO becomes >= 7/8 full,?,?,?"
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|
newline
|
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bitfld.long 0x10 0.--2. "TXSEL,Transmit interrupt FIFO level select:This field sets the trigger points for the transmit interrupt" "Transmit FIFO becomes <= 1/8 full,Transmit FIFO becomes <= 1/4 full,Transmit FIFO becomes <= 1/2 full,Transmit FIFO becomes <= 3/4 full,Transmit FIFO becomes <= 7/8 full,?,?,?"
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|
line.long 0x14 "IMSC,Interrupt Mask Set/Clear"
|
|
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 11. "EOTIM,End of Transmission interrupt mask" "0,1"
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newline
|
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bitfld.long 0x14 10. "OEIM,Overrun error interrupt mask" "0,1"
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newline
|
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bitfld.long 0x14 9. "BEIM,Break error interrupt mask" "0,1"
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newline
|
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bitfld.long 0x14 8. "PEIM,Parity error interrupt mask" "0,1"
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newline
|
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bitfld.long 0x14 7. "FEIM,Framing error interrupt mask" "0,1"
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|
newline
|
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bitfld.long 0x14 6. "RTIM,Receive timeout interrupt mask" "0,1"
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|
newline
|
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bitfld.long 0x14 5. "TXIM,Transmit interrupt mask" "0,1"
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|
newline
|
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bitfld.long 0x14 4. "RXIM,Receive interrupt mask" "0,1"
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newline
|
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bitfld.long 0x14 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
|
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bitfld.long 0x14 1. "CTSMIM,Clear to Send (CTS) modem interrupt mask" "0,1"
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|
newline
|
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bitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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|
line.long 0x18 "RIS,Raw Interrupt Status"
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hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 11. "EOTRIS,End of Transmission interrupt status: This field returns the raw interrupt state of UART's end of transmission interrupt" "0,1"
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newline
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bitfld.long 0x18 10. "OERIS,Overrun error interrupt status: This field returns the raw interrupt state of UART's overrun error interrupt" "0,1"
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newline
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bitfld.long 0x18 9. "BERIS,Break error interrupt status:This field returns the raw interrupt state of UART's break error interrupt" "0,1"
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newline
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bitfld.long 0x18 8. "PERIS,Parity error interrupt status:This field returns the raw interrupt state of UART's parity error interrupt" "0,1"
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|
newline
|
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bitfld.long 0x18 7. "FERIS,Framing error interrupt status:This field returns the raw interrupt state of UART's framing error interrupt" "0,1"
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|
newline
|
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bitfld.long 0x18 6. "RTRIS,Receive timeout interrupt status:This field returns the raw interrupt state of UART's receive timeout interrupt" "0,1"
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|
newline
|
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bitfld.long 0x18 5. "TXRIS,Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt.When FIFOs are enabled (LCRH.FEN = 1) the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the.." "0,1"
|
|
newline
|
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bitfld.long 0x18 4. "RXRIS,Receive interrupt status:This field returns the raw interrupt state of UART's receive interrupt" "0,1"
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|
newline
|
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bitfld.long 0x18 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x18 1. "CTSRMIS,Clear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of UART's clear to send interrupt" "0,1"
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|
newline
|
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bitfld.long 0x18 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x1C "MIS,Masked Interrupt Status"
|
|
hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 11. "EOTMIS,End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM" "0,1"
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|
newline
|
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bitfld.long 0x1C 10. "OEMIS,Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM" "0,1"
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|
newline
|
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bitfld.long 0x1C 9. "BEMIS,Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM" "0,1"
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|
newline
|
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bitfld.long 0x1C 8. "PEMIS,Parity error masked interrupt status:This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM" "0,1"
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|
newline
|
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bitfld.long 0x1C 7. "FEMIS,Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM" "0,1"
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|
newline
|
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bitfld.long 0x1C 6. "RTMIS,Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt.The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1)" "0,1"
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|
newline
|
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bitfld.long 0x1C 5. "TXMIS,Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM" "0,1"
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|
newline
|
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bitfld.long 0x1C 4. "RXMIS,Receive masked interrupt status:This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM" "0,1"
|
|
newline
|
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bitfld.long 0x1C 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 1. "CTSMMIS,Clear to Send (CTS) modem masked interrupt status:This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x20 "ICR,Interrupt ClearOn a write of 1. the corresponding interrupt is cleared"
|
|
hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 11. "EOTIC,End of Transmission interrupt clear:Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 10. "OEIC,Overrun error interrupt clear:Writing 1 to this field clears the overrun error interrupt (RIS.OERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 9. "BEIC,Break error interrupt clear:Writing 1 to this field clears the break error interrupt (RIS.BERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEIC,Parity error interrupt clear:Writing 1 to this field clears the parity error interrupt (RIS.PERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "FEIC,Framing error interrupt clear:Writing 1 to this field clears the framing error interrupt (RIS.FERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTIC,Receive timeout interrupt clear:Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 5. "TXIC,Transmit interrupt clear:Writing 1 to this field clears the transmit interrupt (RIS.TXRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXIC,Receive interrupt clear:Writing 1 to this field clears the receive interrupt (RIS.RXRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 1. "CTSMIC,Clear to Send (CTS) modem interrupt clear:Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x24 "DMACTL,DMA Control"
|
|
hexmask.long 0x24 3.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 2. "DMAONERR,DMA on error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "TXDMAE,Transmit DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "RXDMAE,Receive DMA enable" "0,1"
|
|
tree.end
|
|
tree "UDMA0"
|
|
base ad:0x40020000
|
|
rgroup.long 0x00++0x3F
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 28.--31. "TEST," "Controller does not include the integration test..,Controller includes the integration test logic,Undefined,?,?,?,?,?,?,?,?,?,?,?,?,Undefined"
|
|
hexmask.long.byte 0x00 21.--27. 1. "RESERVED21,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TOTALCHANNELS,Register value returns number of available uDMA channels minus one" "Show that the controller is configured to use 1..,Shows that the controller is configured to use 2..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Shows that the controller is configured to use.."
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "STATE,Current state of the control state machine" "Idle,Reading channel controller data,Reading source data end pointer,Reading destination data end pointer,Reading source data,Writing destination data,Waiting for uDMA request to clear,Writing channel controller data,Stalled,Done,Peripheral scatter-gather transition,Undefined,?,?,?,Undefined"
|
|
bitfld.long 0x00 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTERENABLE,Shows the enable status of the controller as configured by CFG.MASTERENABLE:0: Controller is disabled1: Controller is enabled" "Controller is disabled,Controller is enabled"
|
|
line.long 0x04 "CFG,Configuration"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5.--7. "PRTOCTRL,Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows:Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring.Bit [6] Controls HProt[2] to indicate if a bufferable access is.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 1.--4. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0. "MASTERENABLE,Enables the controller:0: Disables the controller1: Enables the controller" "Disables the controller,Enables the controller"
|
|
line.long 0x08 "CTRL,Channel Control Data Base Pointer"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "BASEPTR,This register point to the base address for the primary data structures of each DMA channel"
|
|
hexmask.long.word 0x08 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "ALTCTRL,Channel Alternate Control Data Base Pointer"
|
|
line.long 0x10 "WAITONREQ,Channel Wait On Request Status"
|
|
line.long 0x14 "SOFTREQ,Channel Software Request"
|
|
line.long 0x18 "SETBURST,Channel Set UseBurst"
|
|
line.long 0x1C "CLEARBURST,Channel Clear UseBurst"
|
|
line.long 0x20 "SETREQMASK,Channel Set Request Mask"
|
|
line.long 0x24 "CLEARREQMASK,Clear Channel Request Mask"
|
|
line.long 0x28 "SETCHANNELEN,Set Channel Enable"
|
|
line.long 0x2C "CLEARCHANNELEN,Clear Channel Enable"
|
|
line.long 0x30 "SETCHNLPRIALT,Channel Set Primary-Alternate"
|
|
line.long 0x34 "CLEARCHNLPRIALT,Channel Clear Primary-Alternate"
|
|
line.long 0x38 "SETCHNLPRIORITY,Set Channel Priority"
|
|
line.long 0x3C "CLEARCHNLPRIORITY,Clear Channel Priority"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ERROR,Error Status and Clear"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STATUS,Returns the status of bus error flag in uDMA or clears this bit Read as:0: No bus error detected1: Bus error detectedWrite as:0: No effect status of bus error flag is unchanged.1: Clears the bus error flag" "No effect status of bus error flag is unchanged,Clears the bus error flag"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "REQDONE,Channel Request Done"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "DONEMASK,Channel Request Done Mask"
|
|
tree.end
|
|
tree "VIMS"
|
|
base ad:0x40034000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "STAT,StatusDisplays current VIMS mode and line buffer status"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 5. "IDCODE_LB_DIS,Icode/Dcode flash line buffer status0: Enabled or in transition to disabled1: Disabled and flushed" "Enabled or in transition to disabled,Disabled and flushed"
|
|
newline
|
|
bitfld.long 0x00 4. "SYSBUS_LB_DIS,Sysbus flash line buffer control0: Enabled or in transition to disabled1: Disabled and flushed" "Enabled or in transition to disabled,Disabled and flushed"
|
|
bitfld.long 0x00 3. "MODE_CHANGING,VIMS mode change status0: VIMS is in the mode defined by MODE1: VIMS is in the process of changing to the mode given in CTL.MODE" "VIMS is in the mode defined by MODE,VIMS is in the process of changing to the mode.."
|
|
newline
|
|
bitfld.long 0x00 2. "INV,This bit is set when invalidation of the cache memory is active / ongoing" "0,1"
|
|
bitfld.long 0x00 0.--1. "MODE,Current VIMS mode" "VIMS GPRAM mode,VIMS Cache mode,?,VIMS Off mode"
|
|
line.long 0x04 "CTL,ControlConfigure VIMS mode and line buffer settings"
|
|
bitfld.long 0x04 31. "STATS_CLR,Set this bit to clear statistic counters" "0,1"
|
|
bitfld.long 0x04 30. "STATS_EN,Set this bit to enable statistic counters" "0,1"
|
|
newline
|
|
bitfld.long 0x04 29. "DYN_CG_EN," "0,1"
|
|
hexmask.long.tbyte 0x04 6.--28. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "IDCODE_LB_DIS,Icode/Dcode flash line buffer control0: Enable1: Disable" "Enable,Disable"
|
|
bitfld.long 0x04 4. "SYSBUS_LB_DIS,Sysbus flash line buffer control0: Enable1: Disable" "Enable,Disable"
|
|
newline
|
|
bitfld.long 0x04 3. "ARB_CFG,Icode/Dcode and sysbus arbitation scheme0: Static arbitration (icode/docde > sysbus)1: Round-robin arbitration" "Static arbitration (icode/docde > sysbus),Round-robin arbitration"
|
|
bitfld.long 0x04 2. "PREF_EN,Tag prefetch control0: Disabled1: Enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "MODE,VIMS mode request.Write accesses to this field will be blocked while STAT.MODE_CHANGING is set to 1" "VIMS GPRAM mode,VIMS Cache mode,?,VIMS Off mode"
|
|
tree.end
|
|
tree "WDT"
|
|
base ad:0x40080000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "LOAD,Configuration"
|
|
line.long 0x04 "VALUE,Current Count Value"
|
|
line.long 0x08 "CTL,Control"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 2. "INTTYPE,WDT Interrupt Type0: WDT interrupt is a standard interrupt" "WDT interrupt is a standard interrupt,WDT interrupt is a non-maskable interrupt"
|
|
newline
|
|
bitfld.long 0x08 1. "RESEN,WDT Reset Enable" "Disabled,Enable the Watchdog.."
|
|
bitfld.long 0x08 0. "INTEN,WDT Interrupt Enable0: Interrupt event disabled" "Interrupt event disabled,Interrupt event enabled"
|
|
line.long 0x0C "ICR,Interrupt Clear"
|
|
line.long 0x10 "RIS,Raw Interrupt Status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "WDTRIS,This register is the raw interrupt status register" "The WDT has not timed out,A WDT time-out event has occurred"
|
|
line.long 0x14 "MIS,Masked Interrupt Status"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "WDTMIS,This register is the masked interrupt status register" "The WDT has not timed out or is masked,An unmasked WDT time-out event has occurred"
|
|
group.long 0x418++0x07
|
|
line.long 0x00 "TEST,Test Mode"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "STALL,WDT Stall Enable0: The WDT timer continues counting if the CPU is stopped with a debugger.1: If the CPU is stopped with a debugger the WDT stops counting" "The WDT timer continues counting if the CPU is..,If the CPU is stopped with a debugger the WDT.."
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "TEST_EN,The test enable bit" "Enable external reset,Disables the generation of an external reset"
|
|
line.long 0x04 "INT_CAUS,Interrupt Cause Test Mode"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 1. "CAUSE_RESET,Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "CAUSE_INTR,Replica of RIS.WDTRIS" "0,1"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "LOCK,Lock"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CC2642R")||cpuis("CC2652P")||cpuis("CC2652R")||cpuis("CC2652R7")||cpuis("CC2652RB")||cpuis("CC2662R")||cpuis("CC2672P3")||cpuis("CC2672R3"))
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|
tree "AON"
|
|
tree "AON_BATMON"
|
|
base ad:0x40095000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTL,Internal"
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|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Internal"
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|
bitfld.long 0x00 1. "CALC_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MEAS_EN,Internal" "0,1"
|
|
line.long 0x04 "MEASCFG,Internal"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Internal"
|
|
bitfld.long 0x04 0.--1. "PER,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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|
group.long 0x0C++0x2B
|
|
line.long 0x00 "TEMPP0,Internal"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Internal"
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|
hexmask.long.byte 0x00 0.--7. 1. "CFG,Internal"
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|
line.long 0x04 "TEMPP1,Internal"
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|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Internal"
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|
bitfld.long 0x04 0.--5. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "TEMPP2,Internal"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED5,Internal"
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|
bitfld.long 0x08 0.--4. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "BATMONP0,Internal"
|
|
hexmask.long 0x0C 7.--31. 1. "RESERVED6,Internal"
|
|
hexmask.long.byte 0x0C 0.--6. 1. "CFG,Internal"
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|
line.long 0x10 "BATMONP1,Internal"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED6,Internal"
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|
bitfld.long 0x10 0.--5. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "IOSTRP0,Internal"
|
|
hexmask.long 0x14 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x14 4.--5. "CFG2,Internal" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x14 0.--3. "CFG1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "FLASHPUMPP0,Internal"
|
|
hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x18 9. "DIS_NOISE_FILTER,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "FALLB,Internal" "0,1"
|
|
bitfld.long 0x18 6.--7. "HIGHLIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 5. "LOWLIM,Internal" "0,1"
|
|
bitfld.long 0x18 4. "OVR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "BAT,Last Measured Battery VoltageThis register may be read while BATUPD.STAT = 1"
|
|
hexmask.long.tbyte 0x1C 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x1C 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x20 "BATUPD,Battery UpdateIndicates BAT Updates"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT," "No update since last clear,New battery voltage is present.Write 1 to clear.."
|
|
line.long 0x24 "TEMP,TemperatureLast Measured Temperature in Degrees CelsiusThis register may be read while TEMPUPD.STAT = 1."
|
|
hexmask.long.word 0x24 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x24 8.--16. "INT,Integer part (signed) of temperature value" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x28 "TEMPUPD,Temperature UpdateIndicates TEMP Updates"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "STAT," "No update since last clear,New temperature is present.Write 1 to clear the.."
|
|
group.long 0x48++0x17
|
|
line.long 0x00 "EVENTMASK,Event Mask"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 5. "TEMP_UPDATE_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "BATT_UPDATE_MASK," "0,1"
|
|
bitfld.long 0x00 3. "TEMP_BELOW_LL_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TEMP_OVER_UL_MASK," "0,1"
|
|
bitfld.long 0x00 1. "BATT_BELOW_LL_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BATT_OVER_UL_MASK," "0,1"
|
|
line.long 0x04 "EVENT,Event"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5. "TEMP_UPDATE,Alias to TEMPUPD.STAT" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "BATT_UPDATE,Alias to BATUPD.STAT" "0,1"
|
|
bitfld.long 0x04 3. "TEMP_BELOW_LL,Read:1: Temperature level is below the lower limit set by TEMPLL.0: Temperature level is not below the lower limit set by TEMPLL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
newline
|
|
bitfld.long 0x04 2. "TEMP_OVER_UL,Read:1: Temperature level is above the upper limit set by TEMPUL.0: Temperature level is not above the upper limit set by TEMPUL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
bitfld.long 0x04 1. "BATT_BELOW_LL,Read:1: Battery level is below the lower limit set by BATTLL.0: Battery level is not below the lower limit set by BATTLL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
newline
|
|
bitfld.long 0x04 0. "BATT_OVER_UL,Read:1: Battery level is above the upper limit set by BATTUL.0: Battery level is not above the upper limit set by BATTUL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
line.long 0x08 "BATTUL,Battery Upper Limit"
|
|
hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x08 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x0C "BATTLL,Battery Lower Limit"
|
|
hexmask.long.tbyte 0x0C 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x0C 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x10 "TEMPUL,Temperature Upper Limit"
|
|
hexmask.long.word 0x10 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x10 8.--16. "INT,Integer part (signed) of temperature upper limit" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "FRAC,Fractional part of temperature upper limit.Total value = INTEGER + FRACTIONALThe encoding is an extension of the 2's complement encoding.00" "0.0C,0.25C,?..."
|
|
rbitfld.long 0x10 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "TEMPLL,Temperature Lower Limit"
|
|
hexmask.long.word 0x14 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x14 8.--16. "INT,Integer part (signed) of temperature lower limit" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
bitfld.long 0x14 6.--7. "FRAC,Fractional part of temperature lower limit.Total value = INTEGER + FRACTIONALThe encoding is an extension of the 2's complement encoding.00" "0.0C,0.25C,?..."
|
|
rbitfld.long 0x14 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "AON_EVENT"
|
|
base ad:0x40093000
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MCUWUSEL,Wake-up Selector For MCUThis register contains pointers to 4 of 8 events (events 0 to 3) which are routed to AON_PMCTRL as wakeup sources for MCU"
|
|
rbitfld.long 0x00 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "WU3_EV,MCU Wakeup Source #3AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "WU2_EV,MCU Wakeup Source #2AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "WU1_EV,MCU Wakeup Source #1AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "WU0_EV,MCU Wakeup Source #0AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
line.long 0x04 "MCUWUSEL1,Wake-up Selector For MCUThis register contains pointers to 4 of 8 events (events 4 to 7) which are routed to AON_PMCTRL as wakeup sources for MCU"
|
|
rbitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 24.--29. "WU7_EV,MCU Wakeup Source #7AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 16.--21. "WU6_EV,MCU Wakeup Source #6AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 8.--13. "WU5_EV,MCU Wakeup Source #5AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "WU4_EV,MCU Wakeup Source #4AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
line.long 0x08 "EVTOMCUSEL,Event Selector For MCU Event Fabric This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT"
|
|
hexmask.long.word 0x08 22.--31. 1. "RESERVED22,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 16.--21. "AON_PROG2_EV,Event selector for AON_PROG2 event.AON Event Source id# selecting event routed to EVENT as AON_PROG2 event." "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
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|
newline
|
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rbitfld.long 0x08 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x08 8.--13. "AON_PROG1_EV,Event selector for AON_PROG1 event.AON Event Source id# selecting event routed to EVENT as AON_PROG1 event." "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
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|
newline
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rbitfld.long 0x08 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x08 0.--5. "AON_PROG0_EV,Event selector for AON_PROG0 event.AON Event Source id# selecting event routed to EVENT as AON_PROG0 event." "Edge detect IO event from the DIO(s) which have..,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,0,?,?,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
|
|
line.long 0x0C "RTCSEL,RTC Capture Event Selector For AON_RTCThis register contains a pointer to select an AON event for RTC capture"
|
|
hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
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bitfld.long 0x0C 0.--5. "RTC_CH1_CAPT_EV,AON Event Source id# for RTCSEL event which is fed to AON_RTC" "Edge detect IO event from the DIO(s) which have..,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,0,?,?,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
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|
tree.end
|
|
tree "AON_IOC"
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base ad:0x40094000
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "IOSTRMIN,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x00 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "IOSTRMED,Internal"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x04 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "IOSTRMAX,Internal"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x08 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CLK32KCTL,SCLK_LF External Output Control"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "OE_N," "0,1"
|
|
line.long 0x04 "TCKCTL,TCK IO Pin Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "EN," "0,1"
|
|
tree.end
|
|
tree "AON_PMCTL"
|
|
base ad:0x40090000
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "AUXSCECLK,AUX SCE Clock ManagementThis register contains bitfields that are relevant for setting up the clock to the AUX domain"
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hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 8. "PD_SRC,Selects the clock source for the AUX domain when AUX is in powerdown mode.Note: Switching the clock source is guaranteed to be glitch-free" "No clock,LF clock (SCLK_LF )"
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newline
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hexmask.long.byte 0x00 1.--7. 1. "RESERVED3,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x00 0. "SRC,Selects the clock source for the AUX domain when AUX is in active mode.Note: Switching the clock source is guaranteed to be glitch-free" "HF Clock divided by 2 (SCLK_HFDIV2),MF Clock (SCLK_MF)"
|
|
line.long 0x04 "RAMCFG,RAM ConfigurationThis register contains power management related configuration for the SRAM in the MCU and AUX domain"
|
|
hexmask.long.word 0x04 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x04 17. "AUX_SRAM_PWR_OFF,Internal" "0,1"
|
|
newline
|
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bitfld.long 0x04 16. "AUX_SRAM_RET_EN,Internal" "0,1"
|
|
newline
|
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hexmask.long.word 0x04 4.--15. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 0.--3. "BUS_SRAM_RET_EN,MCU SRAM is partitioned into 8 banks" "Retention is disabled,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,?,?,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,?,?,?,?,?,?,Retention on for all banks BANK[0]: BANK[1]:.."
|
|
group.long 0x10++0x1F
|
|
line.long 0x00 "PWRCTL,Power Management ControlThis register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
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bitfld.long 0x00 2. "DCDC_ACTIVE,Select to use DCDC regulator for VDDR in active mode" "Use GLDO for regulation of VDDR in active mode,Use DCDC for regulation of VDDR in active mode"
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|
newline
|
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bitfld.long 0x00 1. "EXT_REG_MODE,Status of source for VDDRsupply:0: DCDC or GLDO are generating VDDR1: DCDC and GLDO are bypassed and an external regulator supplies VDDR" "DCDC or GLDO are generating VDDR,DCDC and GLDO are bypassed and an external.."
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|
newline
|
|
bitfld.long 0x00 0. "DCDC_EN,Select to use DCDC regulator during recharge of VDDR0: Use GLDO for recharge of VDDR1: Use DCDC for recharge of VDDRNote: This bitfield should be set to the same as DCDC_ACTIVE" "Use GLDO for recharge of VDDR,Use DCDC for recharge of VDDR"
|
|
line.long 0x04 "PWRSTAT,AON Power and Reset StatusThis register is used to monitor various power management related signals in AON"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 2. "JTAG_PD_ON,Indicates JTAG power state:0: JTAG is powered off1: JTAG is powered on" "JTAG is powered off,JTAG is powered on"
|
|
newline
|
|
bitfld.long 0x04 1. "AUX_BUS_RESET_DONE,Indicates Reset Done from AUX Bus:0: AUX Bus is being reset1: AUX Bus reset is released" "AUX Bus is being reset,AUX Bus reset is released"
|
|
newline
|
|
bitfld.long 0x04 0. "AUX_RESET_DONE,Indicates Reset Done from AUX:0: AUX is being reset1: AUX reset is released" "AUX is being reset,AUX reset is released"
|
|
line.long 0x08 "SHUTDOWN,Shutdown ControlThis register contains bitfields required for entering shutdown mode"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 0. "EN,Shutdown control.0: Do not write 0 to this bit" "Do not write 0 to this bit,Immediately start the process to enter shutdown.."
|
|
line.long 0x0C "RECHARGECFG,Recharge Controller ConfigurationThis register sets all relevant parameters for controlling the recharge algorithm"
|
|
bitfld.long 0x0C 30.--31. "MODE,Selects recharge algorithm for VDDR when the system is running on the uLDO" "Recharge disabled,Static timer,Adaptive timer,External recharge comparator. Note that the.."
|
|
newline
|
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rbitfld.long 0x0C 24.--29. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
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bitfld.long 0x0C 20.--23. "C2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x0C 16.--19. "C1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x0C 11.--15. "MAX_PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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newline
|
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bitfld.long 0x0C 8.--10. "MAX_PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0C 3.--7. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x0C 0.--2. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "RECHARGESTAT,Recharge Controller StatusThis register controls various status registers which are updated during recharge"
|
|
hexmask.long.word 0x10 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 16.--19. "VDDR_SMPLS,The last 4 VDDR samples.For each bit:0: VDDR was below VDDR_OK threshold when recharge started1: VDDR was above VDDR_OK threshold when recharge startedThe register is updated prior to every recharge period with a shift left and bit 0 is.." "VDDR was below VDDR_OK threshold when recharge..,VDDR was above VDDR_OK threshold when recharge..,?..."
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "MAX_USED_PER,Shows the maximum number of 32kHz periods that have separated two recharge cycles and VDDR still was above VDDR_OK threshold when the latter recharge started"
|
|
line.long 0x14 "OSCCFG,Oscillator ConfigurationThis register sets the period for Amplitude compensation requests sent to the oscillator control system"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3.--7. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "RESETCTL,Reset ManagementThis register contains bitfields related to system reset such as reset source and reset request and control of brown out resets"
|
|
bitfld.long 0x18 31. "SYSRESET,Cold reset register" "No effect,Generate system reset"
|
|
newline
|
|
rbitfld.long 0x18 26.--30. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 25. "BOOT_DET_1_CLR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "BOOT_DET_0_CLR,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 18.--23. "RESERVED18,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x18 17. "BOOT_DET_1_SET,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 16. "BOOT_DET_0_SET,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "WU_FROM_SD,A Wakeup from SHUTDOWN on an IO event has occurred or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached" "Wakeup occurred from cold reset or brown out as..,A wakeup has occurred from SHUTDOWN"
|
|
newline
|
|
bitfld.long 0x18 14. "GPIO_WU_FROM_SD,A wakeup from SHUTDOWN on an IO event has occurred Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources.0: The wakeup did not occur from SHUTDOWN on an IO event1: A wakeup from SHUTDOWN occurred from an IO.." "The wakeup did not occur from SHUTDOWN on an IO..,A wakeup from SHUTDOWN occurred from an IO.."
|
|
newline
|
|
rbitfld.long 0x18 13. "BOOT_DET_1,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "BOOT_DET_0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--11. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 8. "VDDS_LOSS_EN,Controls reset generation in case VDDS is lost0: Brown out detect of VDDS is ignored unless VDDS_LOSS_EN_OVR=11: Brown out detect of VDDS generates system reset " "Brown out detect of VDDS is ignored unless..,Brown out detect of VDDS generates system reset"
|
|
newline
|
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bitfld.long 0x18 7. "VDDR_LOSS_EN,Controls reset generation in case VDDR is lost0: Brown out detect of VDDR is ignored unless VDDR_LOSS_EN_OVR=11: Brown out detect of VDDR generates system reset" "Brown out detect of VDDR is ignored unless..,Brown out detect of VDDR generates system reset"
|
|
newline
|
|
bitfld.long 0x18 6. "VDD_LOSS_EN,Controls reset generation in case VDD is lost0: Brown out detect of VDD is ignored unless VDD_LOSS_EN_OVR=11: Brown out detect of VDD generates system reset" "Brown out detect of VDD is ignored unless..,Brown out detect of VDD generates system reset"
|
|
newline
|
|
bitfld.long 0x18 5. "CLK_LOSS_EN,Controls reset generation in case SCLK_LF SCLK_MF or SCLK_HF is lost when clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]0: Clock loss is ignored1: Clock loss generates system resetNote: Clock loss reset.." "Clock loss is ignored,Clock loss generates system reset"
|
|
newline
|
|
bitfld.long 0x18 4. "MCU_WARM_RESET,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 1.--3. "RESET_SRC,Shows the root cause of the last system reset" "Power on reset,Reset pin,Brown out detect on VDDS,?,Brown out detect on VDDR,SCLK_LF SCLK_MF or SCLK_HF clock loss detect,Software reset via SYSRESET or hardware power..,Software reset via PRCM warm reset request"
|
|
newline
|
|
rbitfld.long 0x18 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x1C "SLEEPCTL,Sleep ControlThis register is used to unfreeze the IO pad ring after waking up from SHUTDOWN"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0. "IO_PAD_SLEEP_DIS,Controls the I/O pad sleep mode" "I/O pad sleep mode is enabled meaning all..,I/O pad sleep mode is disabledApplication.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "JTAGCFG,JTAG ConfigurationThis register contains control for configuration of the JTAG domain"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "JTAG_PD_FORCE_ON,Controls JTAG Power domain power state:0: Controlled exclusively by debug subsystem" "Controlled exclusively by debug subsystem,JTAG Power Domain is forced on independent of.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "JTAGUSERCODE,JTAG USERCODEBoot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem"
|
|
group.long 0xC4++0x07
|
|
line.long 0x00 "WDTLOAD,ConfigurationLoad Value register"
|
|
line.long 0x04 "WDTTEST,Test Mode"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "STALLEN,WDT Stall Enable0: The WDT timer continues counting if the CPU is stopped with a debugger.1: If the CPU is stopped with a debugger the WDT stops counting" "The WDT timer continues counting if the CPU is..,If the CPU is stopped with a debugger the WDT.."
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "WDTLOCK,Lock"
|
|
tree.end
|
|
tree "AON_RTC"
|
|
base ad:0x40092000
|
|
group.long 0x00++0x37
|
|
line.long 0x00 "CTL,ControlThis register contains various bitfields for configuration of RTCRTL Name = CONFIG"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16.--18. "COMB_EV_MASK,Eventmask selecting which delayed events that form the combined event." "No event is selected for combined event.,Use Channel 0 delayed event in combined event,Use Channel 1 delayed event in combined event,?,Use Channel 2 delayed event in combined event,?,?,?"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "EV_DELAY,Number of SCLK_LF clock cycles waited before generating delayed events" "No delay on delayed event,Delay by 1 clock cycles,Delay by 2 clock cycles,Delay by 4 clock cycles,Delay by 8 clock cycles,Delay by 16 clock cycles,Delay by 32 clock cycles,Delay by 48 clock cycles,Delay by 64 clock cycles,Delay by 80 clock cycles,Delay by 96 clock cycles,Delay by 112 clock cycles,Delay by 128 clock cycles,Delay by 144 clock cycles,?,?"
|
|
newline
|
|
bitfld.long 0x00 7. "RESET,RTC Counter reset.Writing 1 to this bit will reset the RTC counter.This bit is cleared when reset takes effect" "0,1"
|
|
rbitfld.long 0x00 3.--6. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "RTC_4KHZ_EN,RTC_4KHZ is a 4 KHz reference output tapped from SUBSEC.VALUE bit 19 which is used by AUX timer" "RTC_4KHZ signal is forced to 0,RTC_4KHZ is enabled ( provied that RTC is.."
|
|
bitfld.long 0x00 1. "RTC_UPD_EN,RTC_UPD is a 16 KHz signal used to sync up the radio timer" "RTC_UPD signal is forced to 0,RTC_UPD signal is toggling @16 kHz"
|
|
newline
|
|
bitfld.long 0x00 0. "EN,Enable RTC counter0: Halted (frozen)1: Running" "Halted (frozen),Running"
|
|
line.long 0x04 "EVFLAGS,Event Flags. RTC StatusThis register contains event flags from the 3 RTC channels"
|
|
hexmask.long.word 0x04 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 16. "CH2,Channel 2 event flag set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value.An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "CH1,Channel 1 event flag set when CHCTL.CH1_EN = 1 and one of the following:- CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value.- CHCTL.CH1_CAPT_EN = 1 and capture occurs.An event will be scheduled to occur as soon as possible.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "CH0,Channel 0 event flag set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value.An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any.." "0,1"
|
|
line.long 0x08 "SEC,Second Counter Value. Integer Part"
|
|
line.long 0x0C "SUBSEC,Second Counter Value. Fractional Part"
|
|
line.long 0x10 "SUBSECINC,Subseconds IncrementValue added to SUBSEC.VALUE on every SCLK_LFclock cycle"
|
|
hexmask.long.byte 0x10 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "VALUEINC,This value compensates for a SCLK_LF clock which has an offset from 32768 Hz.The compensation value can be found as 2^38 / freq where freq is SCLK_LF clock frequency in HertzThis value is added to SUBSEC.VALUE on every cycle and carry of this.."
|
|
line.long 0x14 "CHCTL,Channel Configuration"
|
|
hexmask.long.word 0x14 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 18. "CH2_CONT_EN,Set to enable continuous operation of Channel 2" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 17. "RESERVED17,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x14 16. "CH2_EN,RTC Channel 2 Enable0: Disable RTC Channel 21: Enable RTC Channel 2" "Disable RTC Channel 2,Enable RTC Channel 2"
|
|
newline
|
|
rbitfld.long 0x14 10.--15. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 9. "CH1_CAPT_EN,Set Channel 1 mode0: Compare mode (default)1: Capture mode" "Compare mode (default),Capture mode"
|
|
newline
|
|
bitfld.long 0x14 8. "CH1_EN,RTC Channel 1 Enable0: Disable RTC Channel 11: Enable RTC Channel 1" "Disable RTC Channel 1,Enable RTC Channel 1"
|
|
hexmask.long.byte 0x14 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "CH0_EN,RTC Channel 0 Enable0: Disable RTC Channel 01: Enable RTC Channel 0" "Disable RTC Channel 0,Enable RTC Channel 0"
|
|
line.long 0x18 "CH0CMP,Channel 0 Compare Value"
|
|
line.long 0x1C "CH1CMP,Channel 1 Compare Value"
|
|
line.long 0x20 "CH2CMP,Channel 2 Compare Value"
|
|
line.long 0x24 "CH2CMPINC,Channel 2 Compare Value Auto-incrementThis register is primarily used to generate periodical wake-up for the AUX_SCE module. through the [AUX_EVCTL.EVSTAT0.AON_RTC] event."
|
|
line.long 0x28 "CH1CAPT,Channel 1 Capture ValueIf CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1. capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL."
|
|
hexmask.long.word 0x28 16.--31. 1. "SEC,Value of SEC.VALUE bits 15:0 at capture time"
|
|
hexmask.long.word 0x28 0.--15. 1. "SUBSEC,Value of SUBSEC.VALUE bits 31:16 at capture time"
|
|
line.long 0x2C "SYNC,AON SynchronizationThis register is used for synchronizing between MCU and entire AON domain"
|
|
hexmask.long 0x2C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "WBUSY,This register will always return 0 - however it will not return the value until there are no outstanding write requests between MCU and AONNote: Writing to this register prior to reading will force a wait until next SCLK_MF edge" "0,1"
|
|
line.long 0x30 "TIME,Current Counter Value"
|
|
hexmask.long.word 0x30 16.--31. 1. "SEC_L,Returns the lower halfword of SEC register"
|
|
hexmask.long.word 0x30 0.--15. 1. "SUBSEC_H,Returns the upper halfword of SUBSEC register"
|
|
line.long 0x34 "SYNCLF,Synchronization to SCLK_LFThis register is used for synchronizing MCU to positive or negative edge of SCLK_LF"
|
|
hexmask.long 0x34 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x34 0. "PHASE,This bit will always return the SCLK_LF phase" "Falling edge of SCLK_LF,Rising edge of SCLK_LF"
|
|
tree.end
|
|
tree.end
|
|
tree "AUX"
|
|
tree "AUX_ADI4"
|
|
base ad:0x400CB000
|
|
group.byte 0x00++0x05
|
|
line.byte 0x00 "MUX0,Internal"
|
|
bitfld.byte 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x00 6. "ADCCOMPB_IN,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
newline
|
|
bitfld.byte 0x00 4.--5. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "COMPA_REF,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.byte 0x01 "MUX1,Internal"
|
|
line.byte 0x02 "MUX2,Internal"
|
|
bitfld.byte 0x02 3.--7. "ADCCOMPB_IN,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x02 0.--2. "DAC_VREF_SEL,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?"
|
|
line.byte 0x03 "MUX3,Internal"
|
|
line.byte 0x04 "ISRC,Current SourceStrength and trim control for current source"
|
|
bitfld.byte 0x04 2.--7. "TRIM,Adjust current from current source.Output currents may be combined to get desired total current" "No current connected,0.25 uA,0.5 uA,?,1.0 uA,?,?,?,2.0 uA,?,?,?,?,?,?,?,4.5 uA,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,11.75 uA,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x04 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.byte 0x04 0. "EN,Current source enable" "0,1"
|
|
line.byte 0x05 "COMP,ComparatorControl COMPA and COMPB comparators"
|
|
bitfld.byte 0x05 7. "COMPA_REF_RES_EN,Enables 400kohm resistance from COMPA reference node to ground" "0,1"
|
|
bitfld.byte 0x05 6. "COMPA_REF_CURR_EN,Enables 2uA IPTAT current from ISRC to COMPA reference node" "0,1"
|
|
newline
|
|
bitfld.byte 0x05 3.--5. "LPM_BIAS_WIDTH_TRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x05 2. "COMPB_EN,COMPB enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x05 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x05 0. "COMPA_EN,COMPA enable" "0,1"
|
|
group.byte 0x07++0x04
|
|
line.byte 0x00 "MUX4,Internal"
|
|
line.byte 0x01 "ADC0,ADC Control 0ADC Sample Control"
|
|
bitfld.byte 0x01 7. "SMPL_MODE,ADC Sampling mode:0: Synchronous mode1: Asynchronous modeThe ADC does a sample-and-hold before conversion" "Synchronous mode,Asynchronous modeThe ADC does a.."
|
|
bitfld.byte 0x01 3.--6. "SMPL_CYCLE_EXP,Controls the sampling duration before conversion when the ADC is operated in synchronous mode (SMPL_MODE = 0)" "?,?,?,16x 6 MHz clock periods = 2.7us,32x 6 MHz clock periods = 5.3us,64x 6 MHz clock periods = 10.6us,128x 6 MHz clock periods = 21.3us,256x 6 MHz clock periods = 42.6us,512x 6 MHz clock periods = 85.3us,1024x 6 MHz clock periods = 170us,2048x 6 MHz clock periods = 341us,4096x 6 MHz clock periods = 682us,8192x 6 MHz clock periods = 1.37ms,16384x 6 MHz clock periods = 2.73ms,32768x 6 MHz clock periods = 5.46ms,65536x 6 MHz clock periods = 10.9ms"
|
|
newline
|
|
bitfld.byte 0x01 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x01 1. "RESET_N,Reset ADC digital subchip active low" "Reset,Normal.."
|
|
newline
|
|
bitfld.byte 0x01 0. "EN,ADC Enable0: Disable1: Enable" "Disable,Enable"
|
|
line.byte 0x02 "ADC1,ADC Control 1ADC Comparator Control"
|
|
hexmask.byte 0x02 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.byte 0x02 0. "SCALE_DIS,Internal" "0,1"
|
|
line.byte 0x03 "ADCREF0,ADC Reference 0Control reference used by the ADC"
|
|
bitfld.byte 0x03 7. "SPARE7,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x03 6. "REF_ON_IDLE,Enable ADCREF in IDLE state.0: Disabled in IDLE state1: Enabled in IDLE stateKeep ADCREF enabled when ADC0.SMPL_MODE =" "Disabled in IDLE state,Enabled in IDLE stateKeep ADCREF enabled when.."
|
|
newline
|
|
bitfld.byte 0x03 5. "IOMUX,Internal" "0,1"
|
|
bitfld.byte 0x03 4. "EXT,Internal" "0,1"
|
|
newline
|
|
bitfld.byte 0x03 3. "SRC,ADC reference source:0: Fixed reference =" "Fixed reference = 4.3V,Relative reference = VDDS"
|
|
bitfld.byte 0x03 1.--2. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x03 0. "EN,ADC reference module enable:0: ADC reference module powered down1: ADC reference module enabled" "ADC reference module powered down,ADC reference module enabled"
|
|
line.byte 0x04 "ADCREF1,ADC Reference 1Control reference used by the ADC"
|
|
bitfld.byte 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.byte 0x04 0.--5. "VTRIM,Trim output voltage of ADC fixed reference (64 steps 2's complement)" "nominal voltage 1.43V,nominal + 0.4% 1.435V,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,maximum voltage 1.6V,minimum voltage 1.3V,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,nominal - 0.4% 1.425V"
|
|
group.byte 0x0E++0x01
|
|
line.byte 0x00 "LPMBIAS,Internal"
|
|
bitfld.byte 0x00 6.--7. "SPARE6,Internal" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. "LPM_TRIM_IOUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "STAT,Software should not rely on the value of a reserved"
|
|
tree.end
|
|
repeat 4. (list 0. 1. 2. 3. )(list ad:0x400CC000 ad:0x400CD000 ad:0x400CE000 ad:0x400CF000 )
|
|
tree "AUX_AIODIO$1"
|
|
base $2
|
|
group.long 0x00++0x47
|
|
line.long 0x00 "IOMODE,Input Output ModeThis register controls pull-up. pull-down. and output mode for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "IO7,Selects mode for AUXIO[8i+7]" "Output Mode:When IOPOE bit 7 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 7 is 0:..,Open-Drain Mode: When IOPOE bit 7 is 0: - If..,Open-Source Mode: When IOPOE bit 7 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "IO6,Selects mode for AUXIO[8i+6]" "Output Mode:When IOPOE bit 6 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 6 is 0:..,Open-Drain Mode: When IOPOE bit 6 is 0: - If..,Open-Source Mode: When IOPOE bit 6 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "IO5,Selects mode for AUXIO[8i+5]" "Output Mode:When IOPOE bit 5 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 5 is 0:..,Open-Drain Mode: When IOPOE bit 5 is 0: - If..,Open-Source Mode: When IOPOE bit 5 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "IO4,Selects mode for AUXIO[8i+4]" "Output Mode:When IOPOE bit 4 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 4 is 0:..,Open-Drain Mode: When IOPOE bit 4 is 0: - If..,Open-Source Mode: When IOPOE bit 4 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "IO3,Selects mode for AUXIO[8i+3]" "Output Mode:When IOPOE bit 3 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 3 is 0:..,Open-Drain Mode: When IOPOE bit 3 is 0: - If..,Open-Source Mode: When IOPOE bit 3 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "IO2,Select mode for AUXIO[8i+2]" "Output Mode:When IOPOE bit 2 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 2 is 0:..,Open-Drain Mode: When IOPOE bit 2 is 0: - If..,Open-Source Mode: When IOPOE bit 2 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IO1,Select mode for AUXIO[8i+1]" "Output Mode:When IOPOE bit 1 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 1 is 0:..,Open-Drain Mode: When IOPOE bit 1 is 0: - If..,Open-Source Mode: When IOPOE bit 1 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "IO0,Select mode for AUXIO[8i+0]" "Output Mode:When IOPOE bit 0 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 0 is 0:..,Open-Drain Mode: When IOPOE bit 0 is 0: - If..,Open-Source Mode: When IOPOE bit 0 is 0: - If.."
|
|
line.long 0x04 "GPIODIE,General Purpose Input Output Digital Input EnableThis register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]"
|
|
line.long 0x08 "IOPOE,Input Output Peripheral Output EnableThis register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*].Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT"
|
|
line.long 0x0C "GPIODOUT,General Purpose Input Output Data OutThe output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to set AUXIO[8i+n].Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]"
|
|
line.long 0x10 "GPIODIN,General Purpose Input Output Data InThis register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "IO7_0,Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set"
|
|
line.long 0x14 "GPIODOUTSET,General Purpose Input Output Data Out SetSet bits in GPIODOUT in instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to set GPIODOUT bit n"
|
|
line.long 0x18 "GPIODOUTCLR,General Purpose Input Output Data Out ClearClear bits in GPIODOUT instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to clear GPIODOUT bit n.Read value is 0"
|
|
line.long 0x1C "GPIODOUTTGL,General Purpose Input Output Data Out ToggleToggle bits in GPIODOUT in instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n"
|
|
line.long 0x20 "IO0PSEL,Input Output 0 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1"
|
|
hexmask.long 0x20 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x24 "IO1PSEL,Input Output 1 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1"
|
|
hexmask.long 0x24 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x28 "IO2PSEL,Input Output 2 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1"
|
|
hexmask.long 0x28 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x2C "IO3PSEL,Input Output 3 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1"
|
|
hexmask.long 0x2C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x2C 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x30 "IO4PSEL,Input Output 4 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1"
|
|
hexmask.long 0x30 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x30 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x34 "IO5PSEL,Input Output 5 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1"
|
|
hexmask.long 0x34 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x34 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x38 "IO6PSEL,Input Output 6 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1"
|
|
hexmask.long 0x38 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x38 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x3C "IO7PSEL,Input Output 7 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1"
|
|
hexmask.long 0x3C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x3C 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x40 "IOMODEL,Input Output Mode LowThis is an alias register for IOMODE.IO0 thru IOMODE.IO3"
|
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hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x40 6.--7. "IO3,See IOMODE.IO3" "0,1,2,3"
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newline
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bitfld.long 0x40 4.--5. "IO2,See IOMODE.IO2" "0,1,2,3"
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|
newline
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bitfld.long 0x40 2.--3. "IO1,See IOMODE.IO1" "0,1,2,3"
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|
newline
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bitfld.long 0x40 0.--1. "IO0,See IOMODE.IO0" "0,1,2,3"
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|
line.long 0x44 "IOMODEH,Input Output Mode HighThis is an alias register for IOMODE.IO4 thru IOMODE.IO7"
|
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hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
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bitfld.long 0x44 6.--7. "IO7,See IOMODE.IO7" "0,1,2,3"
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|
newline
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bitfld.long 0x44 4.--5. "IO6,See IOMODE.IO6" "0,1,2,3"
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|
newline
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bitfld.long 0x44 2.--3. "IO5,See IOMODE.IO5" "0,1,2,3"
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newline
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bitfld.long 0x44 0.--1. "IO4,See IOMODE.IO4" "0,1,2,3"
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tree.end
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repeat.end
|
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tree "AUX_ANAIF"
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base ad:0x400C9000
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group.long 0x10++0x13
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line.long 0x00 "ADCCTL,ADC ControlConfiguration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion"
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hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 14. "START_POL,Select active polarity for START_SRC event" "Set ADC trigger on rising edge of event source.,Set ADC trigger on falling edge of event source."
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newline
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bitfld.long 0x00 8.--13. "START_SRC,Select ADC trigger event source from the asynchronous AUX event bus.Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10,AUX_EVCTL:EVSTAT0.AUXIO11,AUX_EVCTL:EVSTAT0.AUXIO12,AUX_EVCTL:EVSTAT0.AUXIO13,AUX_EVCTL:EVSTAT0.AUXIO14,AUX_EVCTL:EVSTAT0.AUXIO15,AUX_EVCTL:EVSTAT1.AUXIO16,AUX_EVCTL:EVSTAT1.AUXIO17,AUX_EVCTL:EVSTAT1.AUXIO18,AUX_EVCTL:EVSTAT1.AUXIO19,AUX_EVCTL:EVSTAT1.AUXIO20,AUX_EVCTL:EVSTAT1.AUXIO21,AUX_EVCTL:EVSTAT1.AUXIO22,AUX_EVCTL:EVSTAT1.AUXIO23,AUX_EVCTL:EVSTAT1.AUXIO24,AUX_EVCTL:EVSTAT1.AUXIO25,AUX_EVCTL:EVSTAT1.AUXIO26,AUX_EVCTL:EVSTAT1.AUXIO27,AUX_EVCTL:EVSTAT1.AUXIO28,AUX_EVCTL:EVSTAT1.AUXIO29,AUX_EVCTL:EVSTAT1.AUXIO30,AUX_EVCTL:EVSTAT1.AUXIO31,AUX_EVCTL:EVSTAT2.MANUAL_EV ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,?,?,AUX_EVCTL:EVSTAT2.AUX_COMPA,AUX_EVCTL:EVSTAT2.AUX_COMPB,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,?,?,?,?,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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rbitfld.long 0x00 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--1. "CMD,ADC interface command.Non-enumerated values are not supported" "Disable ADC interface.,Enable ADC interface.,?,Flush ADC FIFO.You must set CMD to EN or DIS.."
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line.long 0x04 "ADCFIFOSTAT,ADC FIFO StatusFIFO can hold up to four ADC samples"
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hexmask.long 0x04 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 4. "OVERFLOW,FIFO overflow flag.0: FIFO has not overflowed.1: FIFO has overflowed this flag is sticky until you flush the FIFO.When the flag is set the ADC FIFO write pointer is static" "FIFO has not overflowed,FIFO has overflowed this flag is sticky until.."
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newline
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bitfld.long 0x04 3. "UNDERFLOW,FIFO underflow flag.0: FIFO has not underflowed.1: FIFO has underflowed this flag is sticky until you flush the FIFO.When the flag is set the ADC FIFO read pointer is static" "FIFO has not underflowed,FIFO has underflowed this flag is sticky until.."
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newline
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bitfld.long 0x04 2. "FULL,FIFO full flag.0: FIFO is not full there is less than 4 samples in the FIFO" "FIFO is not full there is less than 4 samples in..,FIFO is full there are 4 samples in the.."
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newline
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bitfld.long 0x04 1. "ALMOST_FULL,FIFO almost full flag.0: There are less than 3 samples in the FIFO or the FIFO is full" "There are less than 3 samples in the FIFO or the..,There are 3 samples in the FIFO there is room.."
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newline
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bitfld.long 0x04 0. "EMPTY,FIFO empty flag.0: FIFO contains one or more samples.1: FIFO is empty.When the flag is set read returns the previous sample that was read and sets the UNDERFLOW flag" "FIFO contains one or more samples,FIFO is empty.When the flag is set read returns.."
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line.long 0x08 "ADCFIFO,ADC FIFO"
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hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
|
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hexmask.long.word 0x08 0.--11. 1. "DATA,FIFO data.Read:Get oldest ADC sample from FIFO.Write:Write dummy sample to FIFO"
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line.long 0x0C "ADCTRIG,ADC Trigger"
|
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hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x0C 0. "START,Manual ADC trigger" "0,1"
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line.long 0x10 "ISRCCTL,Current Source Control"
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hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x10 0. "RESET_N,ISRC reset control.0: ISRC drives 0 uA.1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN" "ISRC drives 0 uA,ISRC drives current ADI_4_AUX"
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|
group.long 0x30++0x1B
|
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line.long 0x00 "DACCTL,DAC ControlThis register controls the analog part of the DAC."
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hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 5. "DAC_EN,DAC module enable.0: Disable DAC.1: Enable DAC.The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA.The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA in Standby TI-RTOS power mode" "Disable DAC,Enable DAC.The Sensor.."
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newline
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bitfld.long 0x00 4. "DAC_BUFFER_EN,DAC buffer enable.DAC buffer reduces the time required to produce the programmed voltage at the expense of increased current consumption.0: Disable DAC buffer.1: Enable DAC buffer.Enable buffer when DAC_VOUT_SEL equals COMPA_IN.Do not.." "Disable DAC buffer,Enable DAC buffer.Enable buffer when.."
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newline
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bitfld.long 0x00 3. "DAC_PRECHARGE_EN,DAC precharge enable.Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and VDDS is higher than 2.65 V" "0 V to 1.28 V,1.28 V to 2.56 V"
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newline
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bitfld.long 0x00 0.--2. "DAC_VOUT_SEL,DAC output connection.An analog node must only have one driver" "Connect to nothingIt is recommended to use NC..,Connect to COMPB_REF analog node.Required..,Connect to COMPA_REF analog node.It is not..,?,Connect to COMPA_IN analog node.Required..,?,?,?"
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line.long 0x04 "LPMBIASCTL,Low Power Mode Bias ControlThe low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "EN,Module enable.0: Disable low power mode bias module.1: Enable low power mode bias module.Set EN to 1 15 us before you enable the DAC or Comparator A" "Disable low power mode bias module,Enable low power mode bias module.Set EN to 1 15.."
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line.long 0x08 "DACSMPLCTL,DAC Sample ControlThe DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor"
|
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hexmask.long 0x08 1.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x08 0. "EN,DAC sample clock enable.0: Disable sample clock" "Disable sample clock,Enable DAC sample clock"
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line.long 0x0C "DACSMPLCFG0,DAC Sample Configuration 0"
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hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 0.--5. "CLKDIV,Clock division.AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the sample clock base frequency" "Divide by 1,Divide by 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 64"
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line.long 0x10 "DACSMPLCFG1,DAC Sample Configuration 1The sample clock period equals (high time + low time) * base period"
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 14. "H_PER,High time.The sample clock period is high for this many base periods.0: 2 periods1: 4 periods" "2 periods,4 periods"
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newline
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bitfld.long 0x10 12.--13. "L_PER,Low time.The sample clock period is low for this many base periods.0: 1 period1: 2 periods2: 3 periods3: 4 periods" "1 period,2 periods,3 periods,4 periods"
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newline
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bitfld.long 0x10 8.--11. "SETUP_CNT,Setup count.Number of active sample clock periods during the setup phase.0: 1 sample clock period" "1 sample clock period,2 sample clock periods,?,?,?,?,?,?,?,?,?,?,?,?,?,16 sample clock periods"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "HOLD_INTERVAL,Hold interval.Number of inactive sample clock periods between each active sample clock period during hold phase"
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line.long 0x14 "DACVALUE,DAC Value"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
|
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hexmask.long.byte 0x14 0.--7. 1. "VALUE,DAC value.Digital data word for the DAC.Only change VALUE when DACCTL.DAC_EN is 0"
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line.long 0x18 "DACSTAT,DAC Status"
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hexmask.long 0x18 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 1. "SETUP_ACTIVE,DAC setup phase status.0: Sample clock is disabled or setup phase is complete.1: Setup phase in progress" "Sample clock is disabled or setup phase is..,Setup phase in progress"
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newline
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bitfld.long 0x18 0. "HOLD_ACTIVE,DAC hold phase status.0: Sample clock is disabled or DAC is not in hold phase.1: Hold phase in progress" "Sample clock is disabled or DAC is not in hold..,Hold phase in progress"
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tree.end
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tree "AUX_DDI0_OSC"
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base ad:0x400CA000
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group.long 0x00++0x37
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line.long 0x00 "CTL0,Control 0Controls clock source selects"
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bitfld.long 0x00 31. "XTAL_IS_24M,Set based on the accurate high frequency XTAL" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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newline
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bitfld.long 0x00 30. "RESERVED30,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 29. "BYPASS_XOSC_LF_CLK_QUAL,Internal" "0,1"
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newline
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bitfld.long 0x00 28. "BYPASS_RCOSC_LF_CLK_QUAL,Internal" "0,1"
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newline
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bitfld.long 0x00 26.--27. "DOUBLER_START_DURATION,Internal" "0,1,2,3"
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newline
|
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bitfld.long 0x00 25. "DOUBLER_RESET_DURATION,Internal" "0,1"
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newline
|
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bitfld.long 0x00 24. "CLK_DCDC_SRC_SEL,Select DCDC clock source.0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC1: CLK_DCDC is always 48 MHz clock from RCOSC" "CLK_DCDC is 48 MHz clock from RCOSC or XOSC /..,CLK_DCDC is always 48 MHz clock from RCOSC"
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newline
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hexmask.long.word 0x00 15.--23. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x00 14. "HPOSC_MODE_EN," "0,1"
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newline
|
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bitfld.long 0x00 13. "RESERVED13,Software should not rely on the value of a reserved" "0,1"
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newline
|
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bitfld.long 0x00 12. "RCOSC_LF_TRIMMED,Internal" "0,1"
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|
newline
|
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bitfld.long 0x00 11. "XOSC_HF_POWER_MODE,Internal" "0,1"
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|
newline
|
|
bitfld.long 0x00 10. "XOSC_LF_DIG_BYPASS,Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock.0: Use 32kHz XOSC as xosc_lf clock source1: Use digital input (from AON) as xosc_lf clock source.This bit will only have effect when SCLK_LF_SRC_SEL is.." "Use 32kHz XOSC as xosc_lf clock source,Use digital input (from AON) as xosc_lf clock.."
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newline
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bitfld.long 0x00 9. "CLK_LOSS_EN,Enable clock loss detection and hence the indicators to the system controller" "Disable,EnableClock loss.."
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newline
|
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bitfld.long 0x00 7.--8. "ACLK_TDC_SRC_SEL,Source select for aclk_tdc.00: RCOSC_HF (48MHz)01: RCOSC_HF (24MHz)10: XOSC_HF (24MHz)11: Not used" "RCOSC_HF (48MHz),RCOSC_HF (24MHz),?..."
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newline
|
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bitfld.long 0x00 4.--6. "ACLK_REF_SRC_SEL,Source select for aclk_ref000: RCOSC_HF derived (31.25kHz)001: XOSC_HF derived (31.25kHz)010: RCOSC_LF (32kHz)011: XOSC_LF (32.768kHz)100: RCOSC_MF (2MHz)101-111: Not used" "RCOSC_HF derived (31.25kHz),XOSC_HF derived (31.25kHz),?..."
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|
newline
|
|
bitfld.long 0x00 2.--3. "SCLK_LF_SRC_SEL,Source select for sclk_lf" "Low frequency clock derived from High Frequency..,Low frequency clock derived from High Frequency..,Low frequency RCOSC,Low frequency XOSC"
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newline
|
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bitfld.long 0x00 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "SCLK_HF_SRC_SEL,Source select for sclk_hf" "High frequency RCOSC clock,High frequency XOSC or HPOSC clk (use HPOSC when.."
|
|
line.long 0x04 "CTL1,Control 1This register contains OSC_DIG configuration"
|
|
hexmask.long.word 0x04 23.--31. 1. "RESERVED23,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x04 18.--22. "RCOSCHFCTRIMFRACT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
|
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bitfld.long 0x04 17. "RCOSCHFCTRIMFRACT_EN,Internal" "0,1"
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newline
|
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hexmask.long.byte 0x04 10.--16. 1. "SPARE10,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x04 9. "FORCE_RCOSC_LF,Force rcosc_lf to be enabled0: Disabled1: Enabled" "Disabled,Enabled"
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|
newline
|
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bitfld.long 0x04 8. "CLK_LF_LOSS_EN,Enable LF clock loss detection and hence the indicators to the system controller" "Disable,EnableClock loss.."
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|
newline
|
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bitfld.long 0x04 2.--7. "SPARE2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x04 0.--1. "XOSC_HF_FAST_START,Internal" "0,1,2,3"
|
|
line.long 0x08 "RADCEXTCFG,RADC External Configuration"
|
|
hexmask.long.word 0x08 22.--31. 1. "HPM_IBIAS_WAIT_CNT,Internal"
|
|
newline
|
|
bitfld.long 0x08 16.--21. "LPM_IBIAS_WAIT_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x08 12.--15. "IDAC_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x08 6.--11. "RADC_DAC_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x08 5. "RADC_MODE_IS_SAR,Internal" "0,1"
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newline
|
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bitfld.long 0x08 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "AMPCOMPCTL,Amplitude Compensation Control"
|
|
bitfld.long 0x0C 31. "SPARE31,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
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bitfld.long 0x0C 30. "AMPCOMP_REQ_MODE,Internal" "0,1"
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newline
|
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bitfld.long 0x0C 28.--29. "AMPCOMP_FSM_UPDATE_RATE,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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newline
|
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bitfld.long 0x0C 27. "AMPCOMP_SW_CTRL,Internal" "0,1"
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newline
|
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bitfld.long 0x0C 26. "AMPCOMP_SW_EN,Internal" "0,1"
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newline
|
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bitfld.long 0x0C 24.--25. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
|
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bitfld.long 0x0C 20.--23. "IBIAS_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x0C 16.--19. "IBIAS_INIT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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hexmask.long.byte 0x0C 8.--15. 1. "LPM_IBIAS_WAIT_CNT_FINAL,Internal"
|
|
newline
|
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bitfld.long 0x0C 4.--7. "CAP_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x0C 0.--3. "IBIASCAP_HPTOLP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x10 "AMPCOMPTH1,Amplitude Compensation Threshold 1This register contains threshold values for amplitude compensation algorithm"
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hexmask.long.byte 0x10 24.--31. 1. "SPARE24,Software should not rely on the value of a reserved"
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bitfld.long 0x10 18.--23. "HPMRAMP3_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 16.--17. "SPARE16,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x10 10.--15. "HPMRAMP3_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 6.--9. "IBIASCAP_LPTOHP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0.--5. "HPMRAMP1_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x14 "AMPCOMPTH2,Amplitude Compensation Threshold 2This register contains threshold values for amplitude compensation algorithm."
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bitfld.long 0x14 26.--31. "LPMUPDATE_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 24.--25. "SPARE24,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x14 18.--23. "LPMUPDATE_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 16.--17. "SPARE16,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x14 10.--15. "ADC_COMP_AMPTH_LPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 8.--9. "SPARE8,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x14 2.--7. "ADC_COMP_AMPTH_HPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 0.--1. "SPARE0,Software should not rely on the value of a reserved" "0,1,2,3"
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line.long 0x18 "ANABYPASSVAL1,Analog Bypass Values 1"
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hexmask.long.word 0x18 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
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bitfld.long 0x18 16.--19. "XOSC_HF_ROW_Q12,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x18 0.--15. 1. "XOSC_HF_COLUMN_Q12,Internal"
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line.long 0x1C "ANABYPASSVAL2,Internal"
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hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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hexmask.long.word 0x1C 0.--13. 1. "XOSC_HF_IBIASTHERM,Internal"
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line.long 0x20 "ATESTCTL,Analog Test Control"
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bitfld.long 0x20 31. "SCLK_LF_AUX_EN,Enable 32 kHz clock to AUX_COMPB." "0,1"
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hexmask.long.word 0x20 16.--30. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x20 14.--15. "TEST_RCOSCMF,Test mode control for RCOSC_MF0x0: test modes" "test modes disabled,boosted bias current into self biased inverter,clock qualification disabled,boosted bias current into self biased inverter +.."
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bitfld.long 0x20 12.--13. "ATEST_RCOSCMF,ATEST control for RCOSC_MF0x0: ATEST" "ATEST disabled,ATEST enabled VDD_LOCAL connected ATEST internal..,ATEST disabled,ATEST enabled bias current connected ATEST.."
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hexmask.long.word 0x20 0.--11. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x24 "ADCDOUBLERNANOAMPCTL,ADC Doubler Nanoamp Control"
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hexmask.long.byte 0x24 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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bitfld.long 0x24 24. "NANOAMP_BIAS_ENABLE,Internal" "0,1"
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bitfld.long 0x24 23. "SPARE23,Software should not rely on the value of a reserved" "0,1"
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hexmask.long.tbyte 0x24 6.--22. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x24 5. "ADC_SH_MODE_EN,Internal" "0,1"
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bitfld.long 0x24 4. "ADC_SH_VBUF_EN,Internal" "0,1"
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bitfld.long 0x24 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x24 0.--1. "ADC_IREF_CTRL,Internal" "0,1,2,3"
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line.long 0x28 "XOSCHFCTL,XOSCHF Control"
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hexmask.long.tbyte 0x28 14.--31. 1. "SPARE14,Software should not rely on the value of a reserved"
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bitfld.long 0x28 13. "TCXO_MODE_XOSC_HF_EN,If this register is 1 when TCXO_MODE is 1 then the XOSC_HF is enabled turning on the XOSC_HF bias current allowing a DC bias point to be provided to the clipped-sine wave clock signal on external input" "0,1"
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bitfld.long 0x28 12. "TCXO_MODE,If this register is 1 when BYPASS is 1 this will enable clock qualification on the TCXO clock on external input" "0,1"
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bitfld.long 0x28 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x28 8.--9. "PEAK_DET_ITRIM,Internal" "0,1,2,3"
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bitfld.long 0x28 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x28 6. "BYPASS,Internal" "0,1"
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bitfld.long 0x28 5. "RESERVED5,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x28 2.--4. "HP_BUF_ITRIM,Internal" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 0.--1. "LP_BUF_ITRIM,Internal" "0,1,2,3"
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line.long 0x2C "LFOSCCTL,Low Frequency Oscillator Control"
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hexmask.long.byte 0x2C 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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bitfld.long 0x2C 22.--23. "XOSCLF_REGULATOR_TRIM,Internal" "0,1,2,3"
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bitfld.long 0x2C 18.--21. "XOSCLF_CMIRRWR_RATIO,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 10.--17. 1. "RESERVED10,Software should not rely on the value of a reserved"
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bitfld.long 0x2C 8.--9. "RCOSCLF_RTUNE_TRIM,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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hexmask.long.byte 0x2C 0.--7. 1. "RCOSCLF_CTUNE_TRIM,Internal"
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line.long 0x30 "RCOSCHFCTL,RCOSCHF Control"
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hexmask.long.word 0x30 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x30 8.--15. 1. "RCOSCHF_CTRIM,Internal"
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hexmask.long.byte 0x30 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x34 "RCOSCMFCTL,RCOSC_MF Control"
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hexmask.long.word 0x34 16.--31. 1. "SPARE16,Software should not rely on the value of a reserved"
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abitfld.long 0x34 9.--15. "RCOSC_MF_CAP_ARRAY,Adjust RCOSC_MF capacitor" "0x00=nominal frequency 0.625pF,0x3F=lowest frequency 1.125pF,0x40=highest frequency 0.125pF"
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bitfld.long 0x34 8. "RCOSC_MF_REG_SEL,Choose regulator type.0: default1: alternate" "default,alternate"
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bitfld.long 0x34 6.--7. "RCOSC_MF_RES_COARSE,Select coarse resistor for frequency" "400kohms default,300kohms min,600kohms max,500kohms"
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bitfld.long 0x34 4.--5. "RCOSC_MF_RES_FINE,Select fine resistor for frequency" "11kohms minimum resistance max freq,13kohms,16kohms,20kohms max resistance min freq"
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bitfld.long 0x34 0.--3. "RCOSC_MF_BIAS_ADJ,Adjusts bias current to RCOSC_MF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x3C++0x0B
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line.long 0x00 "STAT0,Status 0This register contains status signals from OSC_DIG"
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bitfld.long 0x00 31. "RCOSC_LF_GOOD,RCOSC_LF_GOOD" "0,1"
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bitfld.long 0x00 29.--30. "SCLK_LF_SRC,Indicates source for the sclk_lf" "Low frequency clock derived from High Frequency..,Low frequency clock derived from High Frequency..,Low frequency RCOSC,Low frequency XOSC"
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bitfld.long 0x00 28. "SCLK_HF_SRC,Indicates source for the sclk_hf" "High frequency RCOSC clock,High frequency XOSC"
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bitfld.long 0x00 23.--27. "RESERVED23,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 22. "RCOSC_HF_EN,RCOSC_HF_EN" "0,1"
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bitfld.long 0x00 21. "RCOSC_LF_EN,RCOSC_LF_EN" "0,1"
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bitfld.long 0x00 20. "XOSC_LF_EN,XOSC_LF_EN" "0,1"
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bitfld.long 0x00 19. "CLK_DCDC_RDY,CLK_DCDC_RDY" "0,1"
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bitfld.long 0x00 18. "CLK_DCDC_RDY_ACK,CLK_DCDC_RDY_ACK" "0,1"
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bitfld.long 0x00 17. "SCLK_HF_LOSS,Indicates sclk_hf is lost" "0,1"
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bitfld.long 0x00 16. "SCLK_LF_LOSS,Indicates sclk_lf is lost" "0,1"
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bitfld.long 0x00 15. "XOSC_HF_EN,Indicates that XOSC_HF is enabled" "0,1"
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bitfld.long 0x00 14. "RESERVED14,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 13. "XB_48M_CLK_EN,Indicates that the 48MHz clock from the DOUBLER is enabled.It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal)" "0,1"
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bitfld.long 0x00 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 11. "XOSC_HF_LP_BUF_EN,XOSC_HF_LP_BUF_EN" "0,1"
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bitfld.long 0x00 10. "XOSC_HF_HP_BUF_EN,XOSC_HF_HP_BUF_EN" "0,1"
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bitfld.long 0x00 9. "RESERVED9,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 8. "ADC_THMET,ADC_THMET" "0,1"
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bitfld.long 0x00 7. "ADC_DATA_READY,indicates when adc_data is ready" "0,1"
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bitfld.long 0x00 1.--6. "ADC_DATA,adc_data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "PENDINGSCLKHFSWITCHING,Indicates when SCLK_HF clock source is ready to be switched" "0,1"
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line.long 0x04 "STAT1,Status 1This register contains status signals from OSC_DIG"
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bitfld.long 0x04 28.--31. "RAMPSTATE,AMPCOMP FSM State" "RESET,INITIALIZATION,HPM_RAMP1,HPM_RAMP2,HPM_RAMP3,HPM_UPDATE,IDAC_INCREMENT,IBIAS_CAP_UPDATE,IBIAS_DECREMENT_WITH_MEASURE,LPM_UPDATE,IBIAS_INCREMENT,IDAC_DECREMENT_WITH_MEASURE,DUMMY_TO_INIT_1,FAST_START,FAST_START_SETTLE,?"
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bitfld.long 0x04 22.--27. "HPM_UPDATE_AMP,XOSC_HF amplitude during HPM_UPDATE state.When amplitude compensation of XOSC_HF is enabled in high performance mode this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC divided by 15 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 16.--21. "LPM_UPDATE_AMP,XOSC_HF amplitude during LPM_UPDATE stateWhen amplitude compensation of XOSC_HF is enabled in low power mode this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC divided by 15 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 15. "FORCE_RCOSC_HF,force_rcosc_hf" "0,1"
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bitfld.long 0x04 14. "SCLK_HF_EN,SCLK_HF_EN" "0,1"
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bitfld.long 0x04 13. "SCLK_MF_EN,SCLK_MF_EN" "0,1"
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bitfld.long 0x04 12. "ACLK_ADC_EN,ACLK_ADC_EN" "0,1"
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bitfld.long 0x04 11. "ACLK_TDC_EN,ACLK_TDC_EN" "0,1"
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bitfld.long 0x04 10. "ACLK_REF_EN,ACLK_REF_EN" "0,1"
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bitfld.long 0x04 9. "CLK_CHP_EN,CLK_CHP_EN" "0,1"
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bitfld.long 0x04 8. "CLK_DCDC_EN,CLK_DCDC_EN" "0,1"
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bitfld.long 0x04 7. "SCLK_HF_GOOD,SCLK_HF_GOOD" "0,1"
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bitfld.long 0x04 6. "SCLK_MF_GOOD,SCLK_MF_GOOD" "0,1"
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bitfld.long 0x04 5. "SCLK_LF_GOOD,SCLK_LF_GOOD" "0,1"
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bitfld.long 0x04 4. "ACLK_ADC_GOOD,ACLK_ADC_GOOD" "0,1"
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bitfld.long 0x04 3. "ACLK_TDC_GOOD,ACLK_TDC_GOOD" "0,1"
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bitfld.long 0x04 2. "ACLK_REF_GOOD,ACLK_REF_GOOD" "0,1"
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|
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bitfld.long 0x04 1. "CLK_CHP_GOOD,CLK_CHP_GOOD" "0,1"
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|
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bitfld.long 0x04 0. "CLK_DCDC_GOOD,CLK_DCDC_GOOD" "0,1"
|
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line.long 0x08 "STAT2,Status 2This register contains status signals from AMPCOMP FSM"
|
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bitfld.long 0x08 26.--31. "ADC_DCBIAS,DC Bias read by RADC during SAR modeThe value is an unsigned integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
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bitfld.long 0x08 25. "HPM_RAMP1_THMET,Indication of threshold is met for hpm_ramp1" "0,1"
|
|
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|
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bitfld.long 0x08 24. "HPM_RAMP2_THMET,Indication of threshold is met for hpm_ramp2" "0,1"
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|
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bitfld.long 0x08 23. "HPM_RAMP3_THMET,Indication of threshold is met for hpm_ramp3" "0,1"
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|
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hexmask.long.byte 0x08 16.--22. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 12.--15. "RAMPSTATE,xosc_hf amplitude compensation FSMThis is identical to STAT1.RAMPSTATE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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hexmask.long.byte 0x08 4.--11. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
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newline
|
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bitfld.long 0x08 3. "AMPCOMP_REQ,ampcomp_req" "0,1"
|
|
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|
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bitfld.long 0x08 2. "XOSC_HF_AMPGOOD,amplitude of xosc_hf is within the required threshold (set by DDI)" "0,1"
|
|
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|
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bitfld.long 0x08 1. "XOSC_HF_FREQGOOD,frequency of xosc_hf is good to use for the digital clocks" "0,1"
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|
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|
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bitfld.long 0x08 0. "XOSC_HF_RF_FREQGOOD,frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations" "0,1"
|
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tree.end
|
|
tree "AUX_EVCTL"
|
|
base ad:0x400C5000
|
|
rgroup.long 0x00++0x1B
|
|
line.long 0x00 "EVSTAT0,Event Status 0Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 15. "AUXIO15,AUXIO15 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 7" "0,1"
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bitfld.long 0x00 14. "AUXIO14,AUXIO14 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 6" "0,1"
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bitfld.long 0x00 13. "AUXIO13,AUXIO13 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 5" "0,1"
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bitfld.long 0x00 12. "AUXIO12,AUXIO12 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 4" "0,1"
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bitfld.long 0x00 11. "AUXIO11,AUXIO11 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 3" "0,1"
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bitfld.long 0x00 10. "AUXIO10,AUXIO10 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 2" "0,1"
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bitfld.long 0x00 9. "AUXIO9,AUXIO9 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 1" "0,1"
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bitfld.long 0x00 8. "AUXIO8,AUXIO8 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 0" "0,1"
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bitfld.long 0x00 7. "AUXIO7,AUXIO7 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 7" "0,1"
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bitfld.long 0x00 6. "AUXIO6,AUXIO6 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 6" "0,1"
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bitfld.long 0x00 5. "AUXIO5,AUXIO5 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 5" "0,1"
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bitfld.long 0x00 4. "AUXIO4,AUXIO4 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 4" "0,1"
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bitfld.long 0x00 3. "AUXIO3,AUXIO3 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 3" "0,1"
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bitfld.long 0x00 2. "AUXIO2,AUXIO2 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 2" "0,1"
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bitfld.long 0x00 1. "AUXIO1,AUXIO1 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 1" "0,1"
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bitfld.long 0x00 0. "AUXIO0,AUXIO0 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 0" "0,1"
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line.long 0x04 "EVSTAT1,Event Status 1Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "AUXIO31,AUXIO31 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 7" "0,1"
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bitfld.long 0x04 14. "AUXIO30,AUXIO30 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 6" "0,1"
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bitfld.long 0x04 13. "AUXIO29,AUXIO29 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 5" "0,1"
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bitfld.long 0x04 12. "AUXIO28,AUXIO28 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 4" "0,1"
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bitfld.long 0x04 11. "AUXIO27,AUXIO27 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 3" "0,1"
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bitfld.long 0x04 10. "AUXIO26,AUXIO26 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 2" "0,1"
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bitfld.long 0x04 9. "AUXIO25,AUXIO25 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 1" "0,1"
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bitfld.long 0x04 8. "AUXIO24,AUXIO24 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 0" "0,1"
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bitfld.long 0x04 7. "AUXIO23,AUXIO23 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 7" "0,1"
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bitfld.long 0x04 6. "AUXIO22,AUXIO22 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 6" "0,1"
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bitfld.long 0x04 5. "AUXIO21,AUXIO21 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 5" "0,1"
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bitfld.long 0x04 4. "AUXIO20,AUXIO20 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 4" "0,1"
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bitfld.long 0x04 3. "AUXIO19,AUXIO19 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 3" "0,1"
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bitfld.long 0x04 2. "AUXIO18,AUXIO18 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 2" "0,1"
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bitfld.long 0x04 1. "AUXIO17,AUXIO17 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 1" "0,1"
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bitfld.long 0x04 0. "AUXIO16,AUXIO16 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 0" "0,1"
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line.long 0x08 "EVSTAT2,Event Status 2Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x08 15. "AUX_COMPB,Comparator B output" "0,1"
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bitfld.long 0x08 14. "AUX_COMPA,Comparator A output" "0,1"
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bitfld.long 0x08 13. "MCU_OBSMUX1,Observation input 1 from IOC" "0,1"
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bitfld.long 0x08 12. "MCU_OBSMUX0,Observation input 0 from IOC" "0,1"
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bitfld.long 0x08 11. "MCU_EV,Event from EVENT configured by EVENT:AUXSEL0" "0,1"
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bitfld.long 0x08 10. "ACLK_REF,TDC reference clock.It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ" "0,1"
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bitfld.long 0x08 9. "VDDR_RECHARGE,Event is high during VDDR recharge" "0,1"
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bitfld.long 0x08 8. "MCU_ACTIVE,Event is high while system(MCU AUX or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state)" "0,1"
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bitfld.long 0x08 7. "PWR_DWN,Event is high while system(MCU AUX or JTAG domains) is in powerdown (uLDO power supply)" "0,1"
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bitfld.long 0x08 6. "SCLK_LF,SCLK_LF clock" "0,1"
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bitfld.long 0x08 5. "AON_BATMON_TEMP_UPD,Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP" "0,1"
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bitfld.long 0x08 4. "AON_BATMON_BAT_UPD,Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT" "0,1"
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bitfld.long 0x08 3. "AON_RTC_4KHZ,AON_RTC:SUBSEC.VALUE bit" "0,1"
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bitfld.long 0x08 2. "AON_RTC_CH2_DLY,AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration" "0,1"
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bitfld.long 0x08 1. "AON_RTC_CH2,AON_RTC:EVFLAGS.CH2" "0,1"
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bitfld.long 0x08 0. "MANUAL_EV,Programmable event" "0,1"
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line.long 0x0C "EVSTAT3,Event Status 3Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 15. "AUX_TIMER2_CLKSWITCH_RDY,AUX_SYSIF:TIMER2CLKSWITCH.RDY" "0,1"
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bitfld.long 0x0C 14. "AUX_DAC_HOLD_ACTIVE,AUX_ANAIF:DACSTAT.HOLD_ACTIVE" "0,1"
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bitfld.long 0x0C 13. "AUX_SMPH_AUTOTAKE_DONE,See AUX_SMPH:AUTOTAKE.SMPH_ID for description" "0,1"
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bitfld.long 0x0C 12. "AUX_ADC_FIFO_NOT_EMPTY,AUX_ANAIF:ADCFIFOSTAT.EMPTY negated" "0,1"
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bitfld.long 0x0C 11. "AUX_ADC_FIFO_ALMOST_FULL,AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL" "0,1"
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bitfld.long 0x0C 10. "AUX_ADC_IRQ,The logical function for this event is configurable.When DMACTL.EN =" "0,1"
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bitfld.long 0x0C 9. "AUX_ADC_DONE,AUX_ANAIF ADC conversion done event" "0,1"
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bitfld.long 0x0C 8. "AUX_ISRC_RESET_N,AUX_ANAIF:ISRCCTL.RESET_N" "0,1"
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bitfld.long 0x0C 7. "AUX_TDC_DONE,AUX_TDC:STAT.DONE" "0,1"
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bitfld.long 0x0C 6. "AUX_TIMER0_EV,AUX_TIMER0_EV event see AUX_TIMER01:T0TARGET for description" "0,1"
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bitfld.long 0x0C 5. "AUX_TIMER1_EV,AUX_TIMER1_EV event see AUX_TIMER01:T1TARGET for description" "0,1"
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bitfld.long 0x0C 4. "AUX_TIMER2_PULSE,AUX_TIMER2 pulse event" "0,1"
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bitfld.long 0x0C 3. "AUX_TIMER2_EV3,AUX_TIMER2 event output 3" "0,1"
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bitfld.long 0x0C 2. "AUX_TIMER2_EV2,AUX_TIMER2 event output 2" "0,1"
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bitfld.long 0x0C 1. "AUX_TIMER2_EV1,AUX_TIMER2 event output 1" "0,1"
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bitfld.long 0x0C 0. "AUX_TIMER2_EV0,AUX_TIMER2 event output 0" "0,1"
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line.long 0x10 "SCEWEVCFG0,Sensor Controller Engine Wait Event Configuration 0Configuration of this register and SCEWEVCFG1 controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS"
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hexmask.long 0x10 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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bitfld.long 0x10 6. "COMB_EV_EN,Event combination control:0: Disable event combination.1: Enable event combination" "Disable event combination,Enable event combination"
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bitfld.long 0x10 0.--5. "EV0_SEL,Select the event source from the synchronous event bus to be used in event equation" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10 ,EVSTAT0.AUXIO11 ,EVSTAT0.AUXIO12 ,EVSTAT0.AUXIO13 ,EVSTAT0.AUXIO14 ,EVSTAT0.AUXIO15 ,EVSTAT1.AUXIO16 ,EVSTAT1.AUXIO17 ,EVSTAT1.AUXIO18 ,EVSTAT1.AUXIO19 ,EVSTAT1.AUXIO20 ,EVSTAT1.AUXIO21 ,EVSTAT1.AUXIO22 ,EVSTAT1.AUXIO23 ,EVSTAT1.AUXIO24 ,EVSTAT1.AUXIO25 ,EVSTAT1.AUXIO26 ,EVSTAT1.AUXIO27 ,EVSTAT1.AUXIO28 ,EVSTAT1.AUXIO29 ,EVSTAT1.AUXIO30 ,EVSTAT1.AUXIO31 ,Programmable delay event as described in PROGDLY,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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line.long 0x14 "SCEWEVCFG1,Sensor Controller Engine Wait Event Configuration 1See SCEWEVCFG0 for description"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 7. "EV0_POL,Polarity of SCEWEVCFG0.EV0_SEL event.When SCEWEVCFG0.COMB_EV_EN is" "Non-inverted,Inverted"
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newline
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bitfld.long 0x14 6. "EV1_POL,Polarity of EV1_SEL event.When SCEWEVCFG0.COMB_EV_EN is" "Non-inverted,Inverted"
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bitfld.long 0x14 0.--5. "EV1_SEL,Select the event source from the synchronous event bus to be used in event equation" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10 ,EVSTAT0.AUXIO11 ,EVSTAT0.AUXIO12 ,EVSTAT0.AUXIO13 ,EVSTAT0.AUXIO14 ,EVSTAT0.AUXIO15 ,EVSTAT1.AUXIO16 ,EVSTAT1.AUXIO17 ,EVSTAT1.AUXIO18 ,EVSTAT1.AUXIO19 ,EVSTAT1.AUXIO20 ,EVSTAT1.AUXIO21 ,EVSTAT1.AUXIO22 ,EVSTAT1.AUXIO23 ,EVSTAT1.AUXIO24 ,EVSTAT1.AUXIO25 ,EVSTAT1.AUXIO26 ,EVSTAT1.AUXIO27 ,EVSTAT1.AUXIO28 ,EVSTAT1.AUXIO29 ,EVSTAT1.AUXIO30 ,EVSTAT1.AUXIO31 ,Programmable delay event as described in PROGDLY,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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line.long 0x18 "DMACTL,Direct Memory Access Control"
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hexmask.long 0x18 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 2. "REQ_MODE,UDMA0 Request mode" "Burst requests are generated on UDMA0 channel 7..,Single requests are generated on UDMA0 channel 7.."
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bitfld.long 0x18 1. "EN,uDMA ADC interface enable.0: Disable UDMA0 interface to ADC.1: Enable UDMA0 interface to ADC" "Disable UDMA0 interface to ADC,Enable UDMA0 interface to ADC"
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bitfld.long 0x18 0. "SEL,Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data" "UDMA0 trigger event will be generated when there..,UDMA0 trigger event will be generated when the.."
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group.long 0x20++0x4B
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line.long 0x00 "SWEVSET,Software Event SetSet software event flags from AUX domain to AON and MCU domains"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 2. "SWEV2,Software event flag" "No effect,Set software event flag 2"
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bitfld.long 0x00 1. "SWEV1,Software event flag" "No effect,Set software event flag 1"
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bitfld.long 0x00 0. "SWEV0,Software event flag" "No effect,Set software event flag 0"
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line.long 0x04 "EVTOAONFLAGS,Events To AON FlagsThis register contains a collection of event flags routed to AON_EVENT"
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hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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bitfld.long 0x04 8. "AUX_TIMER1_EV,This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV" "0,1"
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bitfld.long 0x04 7. "AUX_TIMER0_EV,This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV" "0,1"
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bitfld.long 0x04 6. "AUX_TDC_DONE,This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE" "0,1"
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bitfld.long 0x04 5. "AUX_ADC_DONE,This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE" "0,1"
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bitfld.long 0x04 4. "AUX_COMPB,This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB" "0,1"
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bitfld.long 0x04 3. "AUX_COMPA,This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA" "0,1"
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bitfld.long 0x04 2. "SWEV2,This event flag is set when software writes a 1 to SWEVSET.SWEV2" "0,1"
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bitfld.long 0x04 1. "SWEV1,This event flag is set when software writes a 1 to SWEVSET.SWEV1" "0,1"
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bitfld.long 0x04 0. "SWEV0,This event flag is set when software writes a 1 to SWEVSET.SWEV0" "0,1"
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line.long 0x08 "EVTOAONPOL,Events To AON PolarityEvent source polarity configuration for EVTOAONFLAGS"
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hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 8. "AUX_TIMER1_EV,Select the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV" "High level,Low level"
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bitfld.long 0x08 7. "AUX_TIMER0_EV,Select the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV" "High level,Low level"
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bitfld.long 0x08 6. "AUX_TDC_DONE,Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE" "High level,Low level"
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bitfld.long 0x08 5. "AUX_ADC_DONE,Select the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE" "High level,Low level"
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bitfld.long 0x08 4. "AUX_COMPB,Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB" "Rising edge,Falling edge"
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bitfld.long 0x08 3. "AUX_COMPA,Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA" "Rising edge,Falling edge"
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rbitfld.long 0x08 0.--2. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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line.long 0x0C "EVTOAONFLAGSCLR,Events To AON ClearClear event flags in EVTOAONFLAGS"
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hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 8. "AUX_TIMER1_EV,Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV.Read value is 0" "0,1"
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bitfld.long 0x0C 7. "AUX_TIMER0_EV,Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 6. "AUX_TDC_DONE,Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 5. "AUX_ADC_DONE,Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE.Read value is 0" "0,1"
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bitfld.long 0x0C 4. "AUX_COMPB,Write 1 to clear EVTOAONFLAGS.AUX_COMPB.Read value is 0" "0,1"
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bitfld.long 0x0C 3. "AUX_COMPA,Write 1 to clear EVTOAONFLAGS.AUX_COMPA.Read value is 0" "0,1"
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bitfld.long 0x0C 2. "SWEV2,Write 1 to clear EVTOAONFLAGS.SWEV2.Read value is 0" "0,1"
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|
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bitfld.long 0x0C 1. "SWEV1,Write 1 to clear EVTOAONFLAGS.SWEV1.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "SWEV0,Write 1 to clear EVTOAONFLAGS.SWEV0.Read value is 0" "0,1"
|
|
line.long 0x10 "EVTOMCUFLAGS,Events to MCU FlagsThis register contains a collection of event flags routed to MCU domain"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 15. "AUX_TIMER2_PULSE,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE occurs on EVSTAT3.AUX_TIMER2_PULSE" "0,1"
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|
newline
|
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bitfld.long 0x10 14. "AUX_TIMER2_EV3,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 occurs on EVSTAT3.AUX_TIMER2_EV3" "0,1"
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|
newline
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|
bitfld.long 0x10 13. "AUX_TIMER2_EV2,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 occurs on EVSTAT3.AUX_TIMER2_EV2" "0,1"
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|
newline
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|
bitfld.long 0x10 12. "AUX_TIMER2_EV1,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 occurs on EVSTAT3.AUX_TIMER2_EV1" "0,1"
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|
newline
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|
bitfld.long 0x10 11. "AUX_TIMER2_EV0,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 occurs on EVSTAT3.AUX_TIMER2_EV0" "0,1"
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|
newline
|
|
bitfld.long 0x10 10. "AUX_ADC_IRQ,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "MCU_OBSMUX0,This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0" "0,1"
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|
newline
|
|
bitfld.long 0x10 8. "AUX_ADC_FIFO_ALMOST_FULL,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL" "0,1"
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|
newline
|
|
bitfld.long 0x10 7. "AUX_ADC_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE" "0,1"
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|
newline
|
|
bitfld.long 0x10 6. "AUX_SMPH_AUTOTAKE_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE" "0,1"
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|
newline
|
|
bitfld.long 0x10 5. "AUX_TIMER1_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "AUX_TIMER0_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "AUX_TDC_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE" "0,1"
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|
newline
|
|
bitfld.long 0x10 2. "AUX_COMPB,This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "AUX_COMPA,This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA" "0,1"
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|
newline
|
|
bitfld.long 0x10 0. "AUX_WU_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on reduction-OR of the AUX_SYSIF:WUFLAGS register" "0,1"
|
|
line.long 0x14 "EVTOMCUPOL,Event To MCU PolarityEvent source polarity configuration for EVTOMCUFLAGS"
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|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x14 15. "AUX_TIMER2_PULSE,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE" "High level,Low level"
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|
newline
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bitfld.long 0x14 14. "AUX_TIMER2_EV3,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3" "High level,Low level"
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newline
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bitfld.long 0x14 13. "AUX_TIMER2_EV2,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2" "High level,Low level"
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|
newline
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bitfld.long 0x14 12. "AUX_TIMER2_EV1,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1" "High level,Low level"
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|
newline
|
|
bitfld.long 0x14 11. "AUX_TIMER2_EV0,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0" "High level,Low level"
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|
newline
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|
bitfld.long 0x14 10. "AUX_ADC_IRQ,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ" "High level,Low level"
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|
newline
|
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bitfld.long 0x14 9. "MCU_OBSMUX0,Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0" "High level,Low level"
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|
newline
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bitfld.long 0x14 8. "AUX_ADC_FIFO_ALMOST_FULL,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL" "High level,Low level"
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newline
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bitfld.long 0x14 7. "AUX_ADC_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE" "High level,Low level"
|
|
newline
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bitfld.long 0x14 6. "AUX_SMPH_AUTOTAKE_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE" "High level,Low level"
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|
newline
|
|
bitfld.long 0x14 5. "AUX_TIMER1_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV" "High level,Low level"
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|
newline
|
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bitfld.long 0x14 4. "AUX_TIMER0_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV" "High level,Low level"
|
|
newline
|
|
bitfld.long 0x14 3. "AUX_TDC_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE" "High level,Low level"
|
|
newline
|
|
bitfld.long 0x14 2. "AUX_COMPB,Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.long 0x14 1. "AUX_COMPA,Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.long 0x14 0. "AUX_WU_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV" "High level,Low level"
|
|
line.long 0x18 "EVTOMCUFLAGSCLR,Events To MCU Flags ClearClear event flags in EVTOMCUFLAGS"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 15. "AUX_TIMER2_PULSE,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 14. "AUX_TIMER2_EV3,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "AUX_TIMER2_EV2,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "AUX_TIMER2_EV1,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "AUX_TIMER2_EV0,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 10. "AUX_ADC_IRQ,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "MCU_OBSMUX0,Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "AUX_ADC_FIFO_ALMOST_FULL,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "AUX_ADC_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "AUX_SMPH_AUTOTAKE_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "AUX_TIMER1_EV,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "AUX_TIMER0_EV,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "AUX_TDC_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "AUX_COMPB,Write 1 to clear EVTOMCUFLAGS.AUX_COMPB.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "AUX_COMPA,Write 1 to clear EVTOMCUFLAGS.AUX_COMPA.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "AUX_WU_EV,Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV.Read value is 0" "0,1"
|
|
line.long 0x1C "COMBEVTOMCUMASK,Combined Event To MCU MaskSelect event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU.The AUX_COMB event is high as long as one or more of the included event flags are set"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 15. "AUX_TIMER2_PULSE,EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 14. "AUX_TIMER2_EV3,EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 13. "AUX_TIMER2_EV2,EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 12. "AUX_TIMER2_EV1,EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 11. "AUX_TIMER2_EV0,EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 10. "AUX_ADC_IRQ,EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 9. "MCU_OBSMUX0,EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 8. "AUX_ADC_FIFO_ALMOST_FULL,EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 7. "AUX_ADC_DONE,EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 6. "AUX_SMPH_AUTOTAKE_DONE,EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 5. "AUX_TIMER1_EV,EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 4. "AUX_TIMER0_EV,EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 3. "AUX_TDC_DONE,EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 2. "AUX_COMPB,EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event.0: Exclude1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 1. "AUX_COMPA,EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 0. "AUX_WU_EV,EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
line.long 0x20 "EVOBSCFG,Event Observation Configuration"
|
|
hexmask.long 0x20 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--5. "EVOBS_SEL,Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIOn" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10,EVSTAT0.AUXIO11,EVSTAT0.AUXIO12,EVSTAT0.AUXIO13,EVSTAT0.AUXIO14,EVSTAT0.AUXIO15,EVSTAT1.AUXIO16,EVSTAT1.AUXIO17,EVSTAT1.AUXIO18,EVSTAT1.AUXIO19,EVSTAT1.AUXIO20,EVSTAT1.AUXIO21,EVSTAT1.AUXIO22,EVSTAT1.AUXIO23,EVSTAT1.AUXIO24,EVSTAT1.AUXIO25,EVSTAT1.AUXIO26,EVSTAT1.AUXIO27,EVSTAT1.AUXIO28,EVSTAT1.AUXIO29,EVSTAT1.AUXIO30,EVSTAT1.AUXIO31,EVSTAT2.MANUAL_EV,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
|
|
line.long 0x24 "PROGDLY,Programmable Delay"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "VALUE,VALUE decrements to 0 at a rate of 1 MHz.The event AUX_PROG_DLY_IDLE is high when VALUE is 0 otherwise it is low"
|
|
line.long 0x28 "MANUAL,ManualProgrammable event"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0. "EV,This bit field sets the value of EVSTAT2.MANUAL_EV" "0,1"
|
|
line.long 0x2C "EVSTAT0L,Event Status 0 Low"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "ALIAS_EV,Alias of EVSTAT0 event 7 down to 0"
|
|
line.long 0x30 "EVSTAT0H,Event Status 0 High"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "ALIAS_EV,Alias of EVSTAT0 event 15 down to 8"
|
|
line.long 0x34 "EVSTAT1L,Event Status 1 Low"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "ALIAS_EV,Alias of EVSTAT1 event 7 down to 0"
|
|
line.long 0x38 "EVSTAT1H,Event Status 1 High"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "ALIAS_EV,Alias of EVSTAT1 event 15 down to 8"
|
|
line.long 0x3C "EVSTAT2L,Event Status 2 Low"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "ALIAS_EV,Alias of EVSTAT2 event 7 down to 0"
|
|
line.long 0x40 "EVSTAT2H,Event Status 2 High"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "ALIAS_EV,Alias of EVSTAT2 event 15 down to 8"
|
|
line.long 0x44 "EVSTAT3L,Event Status 3 Low"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "ALIAS_EV,Alias of EVSTAT3 event 7 down to 0"
|
|
line.long 0x48 "EVSTAT3H,Event Status 3 High"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "ALIAS_EV,Alias of EVSTAT3 event 15 down to 8"
|
|
tree.end
|
|
tree "AUX_MAC"
|
|
base ad:0x400C2000
|
|
wgroup.long 0x00++0x9F
|
|
line.long 0x00 "OP0S,Signed Operand 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "OP0_VALUE,Signed operand 0.Operand for multiply multiply-and-accumulate or 32-bit add operations"
|
|
line.long 0x04 "OP0U,Unsigned Operand 0"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x04 0.--15. 1. "OP0_VALUE,Unsigned operand 0.Operand for multiply multiply-and-accumulate or 32-bit add operations"
|
|
line.long 0x08 "OP1SMUL,Signed Operand 1 and Multiply"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x08 0.--15. 1. "OP1_VALUE,Signed operand 1 and multiplication trigger.Write OP1_VALUE to set signed operand 1 and trigger the following operation:When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * OP0S.OP0_VALUE.When operand 0 was written to.."
|
|
line.long 0x0C "OP1UMUL,Unsigned Operand 1 and Multiply"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x0C 0.--15. 1. "OP1_VALUE,Unsigned operand 1 and multiplication trigger.Write OP1_VALUE to set unsigned operand 1 and trigger the following operation:When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * OP0S.OP0_VALUE.When operand 0 was written to.."
|
|
line.long 0x10 "OP1SMAC,Signed Operand 1 and Multiply-Accumulate"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x10 0.--15. 1. "OP1_VALUE,Signed operand 1 and multiply-accumulation trigger.Write OP1_VALUE to set signed operand 1 and trigger the following operation:When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * OP0S.OP0_VALUE ).When operand 0 was written.."
|
|
line.long 0x14 "OP1UMAC,Unsigned Operand 1 and Multiply-Accumulate"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "OP1_VALUE,Unsigned operand 1 and multiply-accumulation trigger.Write OP1_VALUE to set unsigned operand 1 and trigger the following operation:When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * OP0S.OP0_VALUE ).When operand 0 was.."
|
|
line.long 0x18 "OP1SADD16,Signed Operand 1 and 16-bit Addition"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x18 0.--15. 1. "OP1_VALUE,Signed operand 1 and 16-bit addition trigger.Write OP1_VALUE to set signed operand 1 and trigger the following operation:ACC = ACC + OP1_VALUE"
|
|
line.long 0x1C "OP1UADD16,Unsigned Operand 1 and 16-bit Addition"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x1C 0.--15. 1. "OP1_VALUE,Unsigned operand 1 and 16-bit addition trigger.Write OP1_VALUE to set unsigned operand 1 and trigger the following operation:ACC = ACC + OP1_VALUE"
|
|
line.long 0x20 "OP1SADD32,Signed Operand 1 and 32-bit Addition"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x20 0.--15. 1. "OP1_VALUE,Upper half of signed 32-bit operand and addition trigger.Write OP1_VALUE to set upper half of signed 32-bit operand and trigger the following operation:When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + (( OP1_VALUE.."
|
|
line.long 0x24 "OP1UADD32,Unsigned Operand 1 and 32-bit Addition"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x24 0.--15. 1. "OP1_VALUE,Upper half of unsigned 32-bit operand and addition trigger.Write OP1_VALUE to set upper half of unsigned 32-bit operand and trigger the following operation:When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + ((.."
|
|
line.long 0x28 "CLZ,Count Leading Zero"
|
|
hexmask.long 0x28 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0.--5. "VALUE,Number of leading zero bits in" "0 leading zeros,1 leading zero,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,40 leading zeros (accumulator value is 0),?..."
|
|
line.long 0x2C "CLS,Count Leading Sign"
|
|
hexmask.long 0x2C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0.--5. "VALUE,Number of leading sign bits in the accumulator.When MSB of accumulator is 0 VALUE is number of leading zeros MSB included.When MSB of accumulator is 1 VALUE is number of leading ones MSB included.VALUE range is 1 thru 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x30 "ACCSHIFT,Accumulator Shift Only one shift operation can be triggered per register"
|
|
hexmask.long 0x30 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x30 2. "LSL1,Logic shift left by 1 bit.Write 1 to shift the accumulator one bit to the left 0 inserted at bit 0" "0,1"
|
|
bitfld.long 0x30 1. "LSR1,Logic shift right by 1 bit.Write 1 to shift the accumulator one bit to the right 0 inserted at bit 39" "0,1"
|
|
bitfld.long 0x30 0. "ASR1,Arithmetic shift right by 1 bit.Write 1 to shift the accumulator one bit to the right previous sign bit inserted at bit 39" "0,1"
|
|
line.long 0x34 "ACCRESET,Accumulator Reset"
|
|
hexmask.long.word 0x34 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x34 0.--15. 1. "TRG,Write any value to this register to trigger a reset of all bits in the accumulator"
|
|
line.long 0x38 "ACC15_0,Accumulator Bits 15:0"
|
|
hexmask.long.word 0x38 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x38 0.--15. 1. "VALUE,Value of the accumulator bits 15:0.Write VALUE to initialize bits 15:0 of accumulator"
|
|
line.long 0x3C "ACC16_1,Accumulator Bits 16:1"
|
|
hexmask.long.word 0x3C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x3C 0.--15. 1. "VALUE,Value of the accumulator bits 16:1"
|
|
line.long 0x40 "ACC17_2,Accumulator Bits 17:2"
|
|
hexmask.long.word 0x40 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x40 0.--15. 1. "VALUE,Value of the accumulator bits 17:2"
|
|
line.long 0x44 "ACC18_3,Accumulator Bits 18:3"
|
|
hexmask.long.word 0x44 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x44 0.--15. 1. "VALUE,Value of the accumulator bits 18:3"
|
|
line.long 0x48 "ACC19_4,Accumulator Bits 19:4"
|
|
hexmask.long.word 0x48 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x48 0.--15. 1. "VALUE,Value of the accumulator bits 19:4"
|
|
line.long 0x4C "ACC20_5,Accumulator Bits 20:5"
|
|
hexmask.long.word 0x4C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x4C 0.--15. 1. "VALUE,Value of the accumulator bits 20:5"
|
|
line.long 0x50 "ACC21_6,Accumulator Bits 21:6"
|
|
hexmask.long.word 0x50 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x50 0.--15. 1. "VALUE,Value of the accumulator bits 21:6"
|
|
line.long 0x54 "ACC22_7,Accumulator Bits 22:7"
|
|
hexmask.long.word 0x54 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x54 0.--15. 1. "VALUE,Value of the accumulator bits 22:7"
|
|
line.long 0x58 "ACC23_8,Accumulator Bits 23:8"
|
|
hexmask.long.word 0x58 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x58 0.--15. 1. "VALUE,Value of the accumulator bits 23:8"
|
|
line.long 0x5C "ACC24_9,Accumulator Bits 24:9"
|
|
hexmask.long.word 0x5C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x5C 0.--15. 1. "VALUE,Value of the accumulator bits 24:9"
|
|
line.long 0x60 "ACC25_10,Accumulator Bits 25:10"
|
|
hexmask.long.word 0x60 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x60 0.--15. 1. "VALUE,Value of the accumulator bits 25:10"
|
|
line.long 0x64 "ACC26_11,Accumulator Bits 26:11"
|
|
hexmask.long.word 0x64 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x64 0.--15. 1. "VALUE,Value of the accumulator bits 26:11"
|
|
line.long 0x68 "ACC27_12,Accumulator Bits 27:12"
|
|
hexmask.long.word 0x68 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x68 0.--15. 1. "VALUE,Value of the accumulator bits 27:12"
|
|
line.long 0x6C "ACC28_13,Accumulator Bits 28:13"
|
|
hexmask.long.word 0x6C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x6C 0.--15. 1. "VALUE,Value of the accumulator bits 28:13"
|
|
line.long 0x70 "ACC29_14,Accumulator Bits 29:14"
|
|
hexmask.long.word 0x70 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x70 0.--15. 1. "VALUE,Value of the accumulator bits 29:14"
|
|
line.long 0x74 "ACC30_15,Accumulator Bits 30:15"
|
|
hexmask.long.word 0x74 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x74 0.--15. 1. "VALUE,Value of the accumulator bits 30:15"
|
|
line.long 0x78 "ACC31_16,Accumulator Bits 31:16"
|
|
hexmask.long.word 0x78 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x78 0.--15. 1. "VALUE,Value of the accumulator bits 31:16.Write VALUE to initialize bits 31:16 of accumulator"
|
|
line.long 0x7C "ACC32_17,Accumulator Bits 32:17"
|
|
hexmask.long.word 0x7C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x7C 0.--15. 1. "VALUE,Value of the accumulator bits 32:17"
|
|
line.long 0x80 "ACC33_18,Accumulator Bits 33:18"
|
|
hexmask.long.word 0x80 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x80 0.--15. 1. "VALUE,Value of the accumulator bits 33:18"
|
|
line.long 0x84 "ACC34_19,Accumulator Bits 34:19"
|
|
hexmask.long.word 0x84 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x84 0.--15. 1. "VALUE,Value of the accumulator bits 34:19"
|
|
line.long 0x88 "ACC35_20,Accumulator Bits 35:20"
|
|
hexmask.long.word 0x88 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x88 0.--15. 1. "VALUE,Value of the accumulator bits 35:20"
|
|
line.long 0x8C "ACC36_21,Accumulator Bits 36:21"
|
|
hexmask.long.word 0x8C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x8C 0.--15. 1. "VALUE,Value of the accumulator bits 36:21"
|
|
line.long 0x90 "ACC37_22,Accumulator Bits 37:22"
|
|
hexmask.long.word 0x90 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x90 0.--15. 1. "VALUE,Value of the accumulator bits 37:22"
|
|
line.long 0x94 "ACC38_23,Accumulator Bits 38:23"
|
|
hexmask.long.word 0x94 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x94 0.--15. 1. "VALUE,Value of the accumulator bits 38:23"
|
|
line.long 0x98 "ACC39_24,Accumulator Bits 39:24"
|
|
hexmask.long.word 0x98 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x98 0.--15. 1. "VALUE,Value of the accumulator bits 39:24"
|
|
line.long 0x9C "ACC39_32,Accumulator Bits 39:32"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "VALUE,Value of the accumulator bits 39:32.Write VALUE to initialize bits 39:32 of accumulator"
|
|
tree.end
|
|
tree "AUX_SCE"
|
|
base ad:0x400E1000
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CTL,Internal"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FORCE_EV_LOW,Internal"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FORCE_EV_HIGH,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESET_VECTOR,Internal"
|
|
rbitfld.long 0x00 7. "RESERVED7,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "DBG_FREEZE_EN,Internal" "0,1"
|
|
bitfld.long 0x00 5. "FORCE_WU_LOW,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "FORCE_WU_HIGH,Internal" "0,1"
|
|
bitfld.long 0x00 3. "RESTART,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SINGLE_STEP,Internal" "0,1"
|
|
bitfld.long 0x00 1. "SUSPEND,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CLK_EN,Internal" "0,1"
|
|
line.long 0x04 "FETCHSTAT,Internal"
|
|
hexmask.long.word 0x04 16.--31. 1. "OPCODE,Internal"
|
|
hexmask.long.word 0x04 0.--15. 1. "PC,Internal"
|
|
line.long 0x08 "CPUSTAT,Internal"
|
|
hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED12,Internal"
|
|
bitfld.long 0x08 11. "BUS_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. "SLEEP,Internal" "0,1"
|
|
bitfld.long 0x08 9. "WEV,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "HALTED,Internal" "0,1"
|
|
bitfld.long 0x08 4.--7. "RESERVED4,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 3. "V_FLAG,Internal" "0,1"
|
|
bitfld.long 0x08 2. "C_FLAG,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "N_FLAG,Internal" "0,1"
|
|
bitfld.long 0x08 0. "Z_FLAG,Internal" "0,1"
|
|
line.long 0x0C "WUSTAT,Internal"
|
|
hexmask.long.word 0x0C 19.--31. 1. "RESERVED20,Internal"
|
|
bitfld.long 0x0C 16.--18. "EXC_VECTOR,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0C 9.--15. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x0C 8. "WU_SIGNAL,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV_SIGNALS,Internal"
|
|
line.long 0x10 "REG1_0,Internal"
|
|
hexmask.long.word 0x10 16.--31. 1. "REG1,Internal"
|
|
hexmask.long.word 0x10 0.--15. 1. "REG0,Internal"
|
|
line.long 0x14 "REG3_2,Internal"
|
|
hexmask.long.word 0x14 16.--31. 1. "REG3,Internal"
|
|
hexmask.long.word 0x14 0.--15. 1. "REG2,Internal"
|
|
line.long 0x18 "REG5_4,Internal"
|
|
hexmask.long.word 0x18 16.--31. 1. "REG5,Internal"
|
|
hexmask.long.word 0x18 0.--15. 1. "REG4,Internal"
|
|
line.long 0x1C "REG7_6,Internal"
|
|
hexmask.long.word 0x1C 16.--31. 1. "REG7,Internal"
|
|
hexmask.long.word 0x1C 0.--15. 1. "REG6,Internal"
|
|
line.long 0x20 "LOOPADDR,Internal"
|
|
hexmask.long.word 0x20 16.--31. 1. "STOP,Internal"
|
|
hexmask.long.word 0x20 0.--15. 1. "START,Internal"
|
|
line.long 0x24 "LOOPCNT,Internal"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED8,Internal"
|
|
hexmask.long.byte 0x24 0.--7. 1. "ITER_LEFT,Internal"
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "NONSECDDIACC$1,Non-Secure DDI Access 0When system is in secure state. AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED23,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 22. "RD_EN,Read Enable0: AUX_SCE is not allowed to read DDI half-word given by ADDR.1: AUX_SCE is allowed to read DDI half-word given by ADDR." "AUX_SCE is not allowed to read DDI half-word..,AUX_SCE is allowed to read DDI half-word given.."
|
|
newline
|
|
bitfld.long 0x00 16.--21. "ADDR,AddressAUX_SCE is allowed to update this DDI half-word using SET or CLR access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "WR_MASK,MaskAUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask"
|
|
repeat.end
|
|
tree.end
|
|
tree "AUX_SMPH"
|
|
base ad:0x400C8000
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SMPH$1,Semaphore 0"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Request or release of semaphore.Request by read:0: Semaphore not available.1: Semaphore granted.Release by write:0: Do not use.1: Release semaphore" "Do not use,Release semaphore"
|
|
repeat.end
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AUTOTAKE,Auto TakeSticky Request for Single Semaphore"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--2. "SMPH_ID,Write the semaphore ID 0x0-0x7 to SMPH_ID to request this semaphore until it is granted" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "AUX_SPIM"
|
|
base ad:0x400C1000
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "SPIMCFG,SPI Master ConfigurationWrite operation stalls until current transfer completes"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 2.--7. "DIV,SCLK divider.Peripheral clock frequency division gives the SCLK clock frequency" "Divide by 2,Divide by 4,Divide by 6,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 128"
|
|
bitfld.long 0x00 1. "PHA,Phase of the MOSI and MISO data signals.0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) edges of SCLK.1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) edges of SCLK." "Sample MISO at leading (odd) edges and shift..,Sample MISO at trailing (even) edges and shift.."
|
|
newline
|
|
bitfld.long 0x00 0. "POL,Polarity of the SCLK signal.0: SCLK is low when idle first clock edge rises.1: SCLK is high when idle first clock edge falls." "SCLK is low when idle first clock edge rises,SCLK is high when idle first clock edge falls"
|
|
line.long 0x04 "MISOCFG,MISO ConfigurationWrite operation stalls until current transfer completes"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0.--4. "AUXIO,AUXIO to MISO mux.Select the AUXIO pin that connects to MISO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "MOSICTL,MOSI ControlWrite operation stalls until current transfer completes"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "VALUE,MOSI level control.0: Set MOSI low.1: Set MOSI high" "Set MOSI low,Set MOSI high"
|
|
line.long 0x0C "TX8,Transmit 8 BitWrite operation stalls until current transfer completes"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "DATA,8 bit data transfer.Write DATA to start transfer MSB first"
|
|
line.long 0x10 "TX16,Transmit 16 BitWrite operation stalls until current transfer completes"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x10 0.--15. 1. "DATA,16 bit data transfer.Write DATA to start transfer MSB first"
|
|
line.long 0x14 "RX8,Receive 8 BitRead operation stalls until current transfer completes"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA,Latest 8 bits received on MISO"
|
|
line.long 0x18 "RX16,Receive 16 BitRead operation stalls until current transfer completes"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x18 0.--15. 1. "DATA,Latest 16 bits received on MISO"
|
|
line.long 0x1C "SCLKIDLE,SCLK IdleRead operation stalls until SCLK is idle with no remaining clock edges"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "STAT,Wait for SCLK idle.Read operation stalls until SCLK is idle with no remaining clock edges" "0,1"
|
|
line.long 0x20 "DATAIDLE,Data IdleRead operation stalls until current transfer completes"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT,Wait for data idle.Read operation stalls until the SCLK period associated with LSB transmission completes" "0,1"
|
|
tree.end
|
|
tree "AUX_SYSIF"
|
|
base ad:0x400C6000
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "OPMODEREQ,Operational Mode RequestAUX can operate in three operational modes"
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hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--1. "REQ,AUX operational mode request" "Active operational mode characterized by:-..,Lowpower operational mode characterized by:-..,Powerdown operational mode with wakeup to active..,Powerdown operational mode with wakeup to.."
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line.long 0x04 "OPMODEACK,Operational Mode AcknowledgementAUX_SCE program must assume that the current operational mode is the one acknowledged"
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hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0.--1. "ACK,AUX operational mode acknowledgement" "Active operational mode is acknowledged.,Lowpower operational mode is acknowledged.,Powerdown operational mode with wakeup to active..,Powerdown operational mode with wakeup to.."
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line.long 0x08 "PROGWU0CFG,Programmable Wakeup 0 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x08 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x08 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x0C "PROGWU1CFG,Programmable Wakeup 1 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x0C 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x0C 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x10 "PROGWU2CFG,Programmable Wakeup 2 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x10 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x10 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x14 "PROGWU3CFG,Programmable Wakeup 3 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x14 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x14 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x18 "SWWUTRIG,Software Wakeup Triggers System CPU uses these wakeup flags to perform handshaking with AUX_SCE"
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hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 3. "SW_WU3,Software wakeup 3 trigger.0: No effect.1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU3 and.."
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newline
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bitfld.long 0x18 2. "SW_WU2,Software wakeup 2 trigger.0: No effect.1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU2 and.."
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newline
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bitfld.long 0x18 1. "SW_WU1,Software wakeup 1 trigger.0: No effect.1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU1 and.."
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newline
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bitfld.long 0x18 0. "SW_WU0,Software wakeup 0 trigger.0: No effect.1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU0 and.."
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line.long 0x1C "WUFLAGS,Wakeup FlagsThis register holds the eight AUX wakeup flags"
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hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 7. "SW_WU3,Software wakeup 3 flag.0: Software wakeup 3 not triggered.1: Software wakeup 3 triggered" "Software wakeup 3 not triggered,Software wakeup 3 triggered"
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newline
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bitfld.long 0x1C 6. "SW_WU2,Software wakeup 2 flag.0: Software wakeup 2 not triggered.1: Software wakeup 2 triggered" "Software wakeup 2 not triggered,Software wakeup 2 triggered"
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newline
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bitfld.long 0x1C 5. "SW_WU1,Software wakeup 1 flag.0: Software wakeup 1 not triggered.1: Software wakeup 1 triggered" "Software wakeup 1 not triggered,Software wakeup 1 triggered"
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newline
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bitfld.long 0x1C 4. "SW_WU0,Software wakeup 0 flag.0: Software wakeup 0 not triggered.1: Software wakeup 0 triggered" "Software wakeup 0 not triggered,Software wakeup 0 triggered"
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newline
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bitfld.long 0x1C 3. "PROG_WU3,Programmable wakeup" "Programmable wakeup 3 not triggered,Programmable wakeup 3 triggered"
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newline
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bitfld.long 0x1C 2. "PROG_WU2,Programmable wakeup" "Programmable wakeup 2 not triggered,Programmable wakeup 2 triggered"
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newline
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bitfld.long 0x1C 1. "PROG_WU1,Programmable wakeup" "Programmable wakeup 1 not triggered,Programmable wakeup 1 triggered"
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newline
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bitfld.long 0x1C 0. "PROG_WU0,Programmable wakeup" "Programmable wakeup 0 not triggered,Programmable wakeup 0 triggered"
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line.long 0x20 "WUFLAGSCLR,Wakeup Flags ClearThis register clears AUX wakeup flags WUFLAGS"
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 7. "SW_WU3,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU3"
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newline
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bitfld.long 0x20 6. "SW_WU2,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU2"
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newline
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bitfld.long 0x20 5. "SW_WU1,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU1"
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newline
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bitfld.long 0x20 4. "SW_WU0,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU0"
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newline
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bitfld.long 0x20 3. "PROG_WU3,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU3"
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newline
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bitfld.long 0x20 2. "PROG_WU2,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU2"
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newline
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bitfld.long 0x20 1. "PROG_WU1,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU1"
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newline
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bitfld.long 0x20 0. "PROG_WU0,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU0"
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line.long 0x24 "WUGATE,Wakeup GateYou must disable the AUX wakeup output:- Before you clear a programmable wakeup flag.- Before you change the value of [PROGWUnCFG.EN] or [PROGWUnCFG.WU_SRC].The AUX wakeup output must be re-enabled after clear operation or programmable.."
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hexmask.long 0x24 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 0. "EN,Wakeup output enable.0: Disable AUX wakeup output.1: Enable AUX wakeup output" "Disable AUX wakeup output,Enable AUX wakeup output"
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repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
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group.long ($2+0x28)++0x03
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line.long 0x00 "VECCFG$1,Vector Configuration 0AUX_SCE wakeup vector 0 configuration"
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hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--3. "VEC_EV,Select trigger event for vector 0.Non-enumerated values are treated as NONE" "Vector is disabled.,WUFLAGS.PROG_WU0,WUFLAGS.PROG_WU1,WUFLAGS.PROG_WU2,WUFLAGS.PROG_WU3,WUFLAGS.SW_WU0 ,WUFLAGS.SW_WU1 ,WUFLAGS.SW_WU2 ,WUFLAGS.SW_WU3 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY,?,?,?,?,?,?"
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repeat.end
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group.long 0x48++0x23
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line.long 0x00 "EVSYNCRATE,Event Synchronization Rate Configure synchronization rate for certain events to the synchronous AUX event bus.You must select SCE rate when AUX_SCE uses the event"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 2. "AUX_COMPA_SYNC_RATE,Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x00 1. "AUX_COMPB_SYNC_RATE,Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x00 0. "AUX_TIMER2_SYNC_RATE,Select synchronization rate for:- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3- AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE" "SCE rate,AUX bus rate"
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line.long 0x04 "PEROPRATE,Peripheral Operational Rate Some AUX peripherals are operated at either SCE or at AUX bus rate"
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hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 3. "ANAIF_DAC_OP_RATE,Select operational rate for AUX_ANAIF DAC sample clock state machine" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 2. "TIMER01_OP_RATE,Select operational rate for AUX_TIMER01" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 1. "SPIM_OP_RATE,Select operational rate for AUX_SPIM" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 0. "MAC_OP_RATE,Select operational rate for AUX_MAC" "SCE rate,AUX bus rate"
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line.long 0x08 "ADCCLKCTL,ADC Clock Control"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 1. "ACK,Clock acknowledgement.0: ADC clock is disabled.1: ADC clock is enabled" "ADC clock is disabled,ADC clock is enabled"
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newline
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bitfld.long 0x08 0. "REQ,ADC clock request.0: Disable ADC clock.1: Enable ADC clock.Only modify REQ when equal to ACK." "Disable ADC clock,Enable ADC clock.Only modify REQ when equal to ACK"
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line.long 0x0C "TDCCLKCTL,TDC Counter Clock ControlControls if the AUX_TDC counter clock source is enabled"
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hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 1. "ACK,TDC counter clock acknowledgement.0: TDC counter clock is disabled.1: TDC counter clock is enabled" "TDC counter clock is disabled,TDC counter clock is enabled"
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newline
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bitfld.long 0x0C 0. "REQ,TDC counter clock request.0: Disable TDC counter clock.1: Enable TDC counter clock.Only modify REQ when equal to ACK." "Disable TDC counter clock,Enable TDC counter clock.Only modify REQ when.."
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line.long 0x10 "TDCREFCLKCTL,TDC Reference Clock ControlControls if the AUX_TDC reference clock source is enabled"
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hexmask.long 0x10 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 1. "ACK,TDC reference clock acknowledgement.0: TDC reference clock is disabled.1: TDC reference clock is enabled" "TDC reference clock is disabled,TDC reference clock is enabled"
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newline
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bitfld.long 0x10 0. "REQ,TDC reference clock request.0: Disable TDC reference clock.1: Enable TDC reference clock.Only modify REQ when equal to ACK." "Disable TDC reference clock,Enable TDC reference clock.Only modify REQ when.."
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line.long 0x14 "TIMER2CLKCTL,AUX_TIMER2 Clock ControlAccess to AUX_TIMER2 is only possible when TIMER2CLKSTAT.STAT is different from NONE"
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hexmask.long 0x14 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 0.--2. "SRC,Select clock source for AUX_TIMER2.Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or TIMER2CLKSWITCH.RDY is 1.It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0" "no clock,SCLK_LF,SCLK_MF,?,SCLK_HF / 2,?,?,?"
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line.long 0x18 "TIMER2CLKSTAT,AUX_TIMER2 Clock Status"
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hexmask.long 0x18 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 0.--2. "STAT,AUX_TIMER2 clock source status" "No clock ,SCLK_LF,SCLK_MF,?,SCLK_HF / 2,?,?,?"
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line.long 0x1C "TIMER2CLKSWITCH,AUX_TIMER2 Clock Switch"
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hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 0. "RDY,Status of clock switcher.0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT.1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT.RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY" "TIMER2CLKCTL.SRC is different from..,TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT.RDY.."
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line.long 0x20 "TIMER2DBGCTL,AUX_TIMER2 Debug Control"
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hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 0. "DBG_FREEZE_EN,Debug freeze enable.0: AUX_TIMER2 does not halt when the system CPU halts in debug mode.1: Halt AUX_TIMER2 when the system CPU halts in debug mode" "AUX_TIMER2 does not halt when the system CPU..,Halt AUX_TIMER2 when the system CPU halts in.."
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group.long 0x70++0x27
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line.long 0x00 "CLKSHIFTDET,Clock Shift DetectionA transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF:- A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when.."
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "STAT,Clock shift detection.Write:0: Restart clock shift detection.1: Do not use.Read:0: MCU domain did not enter or exit active state since you wrote 0 to STAT" "MCU domain did not enter or exit active state..,MCU domain entered or exited active state since.."
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line.long 0x04 "RECHARGETRIG,VDDR Recharge Trigger"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "TRIG,Recharge trigger.0: No effect.1: Request VDDR recharge" "No effect,Request VDDR recharge"
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line.long 0x08 "RECHARGEDET,VDDR Recharge DetectionSome applications can be sensitive to power noise caused by recharge of VDDR"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 1. "STAT,VDDR recharge detector status.0: No recharge of VDDR has occurred since EN was set.1: Recharge of VDDR has occurred since EN was set" "No recharge of VDDR has occurred since EN was set,Recharge of VDDR has occurred since EN was set"
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newline
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bitfld.long 0x08 0. "EN,VDDR recharge detector enable.0: Disable recharge detection" "Disable recharge detection,Enable recharge detection"
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line.long 0x0C "RTCSUBSECINC0,Real Time Counter Sub Second Increment 0INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.AUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "INC15_0,New value for bits 15:0 in AON_RTC:SUBSECINC"
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line.long 0x10 "RTCSUBSECINC1,Real Time Counter Sub Second Increment 1INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.AUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "INC23_16,New value for bits 23:16 in AON_RTC:SUBSECINC"
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line.long 0x14 "RTCSUBSECINCCTL,Real Time Counter Sub Second Increment ControlAUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long 0x14 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 1. "UPD_ACK,Update acknowledgement.0: AON_RTC has not acknowledged UPD_REQ" "AON_RTC has not acknowledged UPD_REQ,AON_RTC has acknowledged UPD_REQ"
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newline
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bitfld.long 0x14 0. "UPD_REQ,Request AON_RTC to update AON_RTC:SUBSECINC.0: Clear request to update.1: Set request to update.Only change UPD_REQ when it equals UPD_ACK" "Clear request to update,Set request to update.Only change UPD_REQ when.."
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line.long 0x18 "RTCSEC,Real Time Counter Second System CPU must not access this register"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "SEC,Bits 15:0 in AON_RTC:SEC.VALUE"
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line.long 0x1C "RTCSUBSEC,Real Time Counter Sub-Second System CPU must not access this register"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "SUBSEC,Bits 31:16 in AON_RTC:SUBSEC.VALUE"
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line.long 0x20 "RTCEVCLR,AON_RTC Event ClearRequest to clear events:- AON_RTC:EVFLAGS.CH2.- AON_RTC:EVFLAGS.CH2 delayed version.- AUX_EVCTL:EVSTAT2.AON_RTC_CH2.- AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY"
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hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 0. "RTC_CH2_EV_CLR,Clear events from AON_RTC channel 2.0: No effect" "No effect,Clear events from AON_RTC.."
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line.long 0x24 "BATMONBAT,AON_BATMON Battery Voltage ValueRead access to AON_BATMON:BAT"
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hexmask.long.tbyte 0x24 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 8.--10. "INT,See AON_BATMON:BAT.INT" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x24 0.--7. 1. "FRAC,See AON_BATMON:BAT.FRAC"
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rgroup.long 0x9C++0x07
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line.long 0x00 "BATMONTEMP,AON_BATMON Temperature ValueRead access to AON_BATMON:TEMP"
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hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 11.--15. "SIGN,Sign extension of INT.Follow this procedure to get the correct value:- Do two dummy reads of SIGN.- Then read SIGN until two consecutive reads are equal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.word 0x00 2.--10. 1. "INT,See AON_BATMON:TEMP.INT"
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newline
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bitfld.long 0x00 0.--1. "FRAC,See AON_BATMON:TEMP.FRAC" "0,1,2,3"
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line.long 0x04 "TIMERHALT,Timer HaltDebug register"
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hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 3. "PROGDLY,Halt programmable delay.0: AUX_EVCTL:PROGDLY.VALUE decrements as normal.1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation" "AUX_EVCTL,Halt AUX_EVCTL"
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newline
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bitfld.long 0x04 2. "AUX_TIMER2,Halt AUX_TIMER2.0: AUX_TIMER2 operates as normal.1: Halt AUX_TIMER2 operation" "AUX_TIMER2 operates as normal,Halt AUX_TIMER2 operation"
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newline
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bitfld.long 0x04 1. "AUX_TIMER1,Halt AUX_TIMER01 Timer" "AUX_TIMER01 Timer 1 operates as normal,Halt AUX_TIMER01 Timer 1 operation"
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newline
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bitfld.long 0x04 0. "AUX_TIMER0,Halt AUX_TIMER01 Timer" "AUX_TIMER01 Timer 0 operates as normal,Halt AUX_TIMER01 Timer 0 operation"
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rgroup.long 0xB0++0x07
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line.long 0x00 "TIMER2BRIDGE,AUX_TIMER2 Bridge"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "BUSY,Status of bus transactions to AUX_TIMER2.0: No unfinished bus transactions.1: A bus transaction is ongoing" "No unfinished bus transactions,A bus transaction is ongoing"
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line.long 0x04 "SWPWRPROF,Software Power Profiler"
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hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0.--2. "STAT,Software status bits that can be read by the power profiler" "0,1,2,3,4,5,6,7"
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tree.end
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tree "AUX_TDC"
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base ad:0x400C4000
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group.long 0x00++0x27
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line.long 0x00 "CTL,Control"
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hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--1. "CMD,TDC commands" "Clear STAT.SAT STAT.DONE and RESULT.VALUE..,Synchronous counter start.The counter looks..,Asynchronous counter start.The counter starts..,Force TDC state machine back to IDLE.."
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line.long 0x04 "STAT,Status"
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 7. "SAT,TDC measurement saturation flag.0: Conversion has not saturated.1: Conversion stopped due to saturation.This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD" "Conversion has not saturated,Conversion stopped due to saturation.This field.."
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newline
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bitfld.long 0x04 6. "DONE,TDC measurement complete flag.0: TDC measurement has not yet completed.1: TDC measurement has completed.This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD" "TDC measurement has not yet completed,TDC measurement has completed.This field clears.."
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newline
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bitfld.long 0x04 0.--5. "STATE,TDC state machine status" "Current state is TDC_STATE_WAIT_START. The..,?,?,?,Current state is..,?,Current state is TDC_STATE_IDLE. This is the..,Current state is TDC_STATE_CLRCNT. The..,Current state is TDC_STATE_WAIT_STOP.The state..,?,?,?,Current state is TDC_STATE_WAIT_STOPCNTDOWN.The..,?,Current state is TDC_STATE_GETRESULTS.The state..,Current state is TDC_STATE_POR. This is the..,?,?,?,?,?,?,Current state is TDC_STATE_WAIT_CLRCNT_DONE..,?,?,?,?,?,?,?,Current state is TDC_WAIT_STARTFALL. The..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Current state is TDC_FORCESTOP.You wrote ABORT..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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line.long 0x08 "RESULT,ResultResult of last TDC conversion"
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hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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newline
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hexmask.long 0x08 0.--24. 1. "VALUE,TDC conversion result.The result of the TDC conversion is given in number of clock edges of the clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL"
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line.long 0x0C "SATCFG,Saturation Configuration"
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hexmask.long 0x0C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 0.--3. "LIMIT,Saturation limit.The flag STAT.SAT is set when the TDC counter saturates.Values not enumerated are not supported" "?,?,?,Result bit 12: TDC conversion saturates and..,Result bit 13: TDC conversion saturates and..,Result bit 14: TDC conversion saturates and..,Result bit 15: TDC conversion saturates and..,Result bit 16: TDC conversion saturates and..,Result bit 17: TDC conversion saturates and..,Result bit 18: TDC conversion saturates and..,Result bit 19: TDC conversion saturates and..,Result bit 20: TDC conversion saturates and..,Result bit 21: TDC conversion saturates and..,Result bit 22: TDC conversion saturates and..,Result bit 23: TDC conversion saturates and..,Result bit 24: TDC conversion saturates and.."
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line.long 0x10 "TRIGSRC,Trigger SourceSelect source and polarity for TDC start and stop events"
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 14. "STOP_POL,Polarity of stop source.Change only while STAT.STATE is IDLE" "TDC conversion stops when high level is detected.,TDC conversion stops when low level is detected."
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newline
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bitfld.long 0x10 8.--13. "STOP_SRC,Select stop source from the asynchronous AUX event bus.Change only while STAT.STATE is IDLE" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,Select TDC Prescaler event which is generated by..,No event."
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newline
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rbitfld.long 0x10 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x10 6. "START_POL,Polarity of start source.Change only while STAT.STATE is IDLE" "TDC conversion starts when high level is detected.,TDC conversion starts when low level is detected."
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newline
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bitfld.long 0x10 0.--5. "START_SRC,Select start source from the asynchronous AUX event bus.Change only while STAT.STATE is IDLE" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,Select TDC Prescaler event which is generated by..,No event."
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line.long 0x14 "TRIGCNT,Trigger CounterStop-counter control and status"
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hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x14 0.--15. 1. "CNT,Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.Read CNT to get the remaining number of stop events to ignore during a TDC measurement"
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line.long 0x18 "TRIGCNTLOAD,Trigger Counter LoadStop-counter load"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.word 0x18 0.--15. 1. "CNT,Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.To measure frequency of an event source: - Set start event equal to stop event.- Set CNT to number of periods to measure"
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line.long 0x1C "TRIGCNTCFG,Trigger Counter ConfigurationStop-counter configuration"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x1C 0. "EN,Enable stop-counter.0: Disable stop-counter.1: Enable stop-counter.Change only while STAT.STATE is IDLE" "Disable stop-counter,Enable stop-counter.Change only while STAT.STATE.."
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|
line.long 0x20 "PRECTL,Prescaler ControlThe prescaler can be used to count events that are faster than the AUX bus rate"
|
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 7. "RESET_N,Prescaler reset.0: Reset prescaler.1: Release reset of prescaler.AUX_TDC_PRE event becomes 0 when you reset the prescaler" "Reset prescaler,Release reset of prescaler.AUX_TDC_PRE.."
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newline
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bitfld.long 0x20 6. "RATIO,Prescaler ratio" "Prescaler divides input by 16. AUX_TDC_PRE..,Prescaler divides input by 64. AUX_TDC_PRE.."
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newline
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bitfld.long 0x20 0.--5. "SRC,Prescaler event source" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x24 "PRECNTR,Prescaler Counter"
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x24 0.--15. 1. "CNT,Prescaler counter value.Write a value to CNT to capture the value of the 16-bit prescaler counter into CNT"
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tree.end
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tree "AUX_TIMER01"
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base ad:0x400C7000
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group.long 0x00++0x1F
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line.long 0x00 "T0CFG,Timer 0 Configuration"
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hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 14. "TICK_SRC_POL,Tick source polarity for Timer 0" "Count on rising edges of TICK_SRC.,Count on falling edges of TICK_SRC."
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newline
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bitfld.long 0x00 8.--13. "TICK_SRC,Select Timer 0 tick source from the synchronous event bus" "AUX_EVCTL:EVSTAT0.AUXIO0..,AUX_EVCTL:EVSTAT0.AUXIO1..,AUX_EVCTL:EVSTAT0.AUXIO2..,AUX_EVCTL:EVSTAT0.AUXIO3..,AUX_EVCTL:EVSTAT0.AUXIO4..,AUX_EVCTL:EVSTAT0.AUXIO5..,AUX_EVCTL:EVSTAT0.AUXIO6..,AUX_EVCTL:EVSTAT0.AUXIO7..,AUX_EVCTL:EVSTAT0.AUXIO8..,AUX_EVCTL:EVSTAT0.AUXIO9..,AUX_EVCTL:EVSTAT0.AUXIO10..,AUX_EVCTL:EVSTAT0.AUXIO11..,AUX_EVCTL:EVSTAT0.AUXIO12..,AUX_EVCTL:EVSTAT0.AUXIO13..,AUX_EVCTL:EVSTAT0.AUXIO14..,AUX_EVCTL:EVSTAT0.AUXIO15..,AUX_EVCTL:EVSTAT1.AUXIO16..,AUX_EVCTL:EVSTAT1.AUXIO17..,AUX_EVCTL:EVSTAT1.AUXIO18..,AUX_EVCTL:EVSTAT1.AUXIO19..,AUX_EVCTL:EVSTAT1.AUXIO20..,AUX_EVCTL:EVSTAT1.AUXIO21..,AUX_EVCTL:EVSTAT1.AUXIO22..,AUX_EVCTL:EVSTAT1.AUXIO23..,AUX_EVCTL:EVSTAT1.AUXIO24..,AUX_EVCTL:EVSTAT1.AUXIO25..,AUX_EVCTL:EVSTAT1.AUXIO26..,AUX_EVCTL:EVSTAT1.AUXIO27..,AUX_EVCTL:EVSTAT1.AUXIO28..,AUX_EVCTL:EVSTAT1.AUXIO29..,AUX_EVCTL:EVSTAT1.AUXIO30..,AUX_EVCTL:EVSTAT1.AUXIO31..,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2..,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY..,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ..,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD..,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD..,AUX_EVCTL:EVSTAT2.SCLK_LF..,AUX_EVCTL:EVSTAT2.PWR_DWN..,AUX_EVCTL:EVSTAT2.MCU_ACTIVE..,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE..,AUX_EVCTL:EVSTAT2.ACLK_REF..,AUX_EVCTL:EVSTAT2.MCU_EV..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1..,AUX_EVCTL:EVSTAT2.AUX_COMPA..,AUX_EVCTL:EVSTAT2.AUX_COMPB..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE..,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV..,No event.,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N..,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE..,AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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newline
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bitfld.long 0x00 4.--7. "PRE,Prescaler division ratio is" "Divide by 1,Divide by 2,Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 32 768"
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newline
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rbitfld.long 0x00 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 1. "MODE,Timer 0 mode.Configure source for Timer 0 prescaler" "Use clock as source for prescaler. Note that..,Use event set by TICK_SRC as source for.."
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newline
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bitfld.long 0x00 0. "RELOAD,Timer 0 reload mode" "Manual mode.Timer 0 stops and T0CTL.EN becomes..,Continuous mode.Timer 0 restarts when the.."
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line.long 0x04 "T0CTL,Timer 0 Control"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "EN,Timer 0 enable.0: Disable Timer" "Disable Timer 0,Enable Timer 0.The counter restarts from 0.."
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line.long 0x08 "T0TARGET,Timer 0 Target"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x08 0.--15. 1. "VALUE,Timer 0 target value.Manual Reload Mode:- Timer 0 increments until the counter value becomes equal to or greater than VALUE"
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line.long 0x0C "T0CNTR,Timer 0 Counter"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "VALUE,Timer 0 counter value"
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line.long 0x10 "T1CFG,Timer 1 Configuration"
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 14. "TICK_SRC_POL,Tick source polarity for Timer 1" "Count on rising edges of TICK_SRC.,Count on falling edges of TICK_SRC."
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newline
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bitfld.long 0x10 8.--13. "TICK_SRC,Select Timer 1 tick source from the synchronous event bus" "AUX_EVCTL:EVSTAT0.AUXIO0..,AUX_EVCTL:EVSTAT0.AUXIO1..,AUX_EVCTL:EVSTAT0.AUXIO2..,AUX_EVCTL:EVSTAT0.AUXIO3..,AUX_EVCTL:EVSTAT0.AUXIO4..,AUX_EVCTL:EVSTAT0.AUXIO5..,AUX_EVCTL:EVSTAT0.AUXIO6..,AUX_EVCTL:EVSTAT0.AUXIO7..,AUX_EVCTL:EVSTAT0.AUXIO8..,AUX_EVCTL:EVSTAT0.AUXIO9..,AUX_EVCTL:EVSTAT0.AUXIO10..,AUX_EVCTL:EVSTAT0.AUXIO11..,AUX_EVCTL:EVSTAT0.AUXIO12..,AUX_EVCTL:EVSTAT0.AUXIO13..,AUX_EVCTL:EVSTAT0.AUXIO14..,AUX_EVCTL:EVSTAT0.AUXIO15..,AUX_EVCTL:EVSTAT1.AUXIO16..,AUX_EVCTL:EVSTAT1.AUXIO17..,AUX_EVCTL:EVSTAT1.AUXIO18..,AUX_EVCTL:EVSTAT1.AUXIO19..,AUX_EVCTL:EVSTAT1.AUXIO20..,AUX_EVCTL:EVSTAT1.AUXIO21..,AUX_EVCTL:EVSTAT1.AUXIO22..,AUX_EVCTL:EVSTAT1.AUXIO23..,AUX_EVCTL:EVSTAT1.AUXIO24..,AUX_EVCTL:EVSTAT1.AUXIO25..,AUX_EVCTL:EVSTAT1.AUXIO26..,AUX_EVCTL:EVSTAT1.AUXIO27..,AUX_EVCTL:EVSTAT1.AUXIO28..,AUX_EVCTL:EVSTAT1.AUXIO29..,AUX_EVCTL:EVSTAT1.AUXIO30..,AUX_EVCTL:EVSTAT1.AUXIO31..,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2..,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY..,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ..,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD..,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD..,AUX_EVCTL:EVSTAT2.SCLK_LF..,AUX_EVCTL:EVSTAT2.PWR_DWN..,AUX_EVCTL:EVSTAT2.MCU_ACTIVE..,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE..,AUX_EVCTL:EVSTAT2.ACLK_REF..,AUX_EVCTL:EVSTAT2.MCU_EV..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1..,AUX_EVCTL:EVSTAT2.AUX_COMPA..,AUX_EVCTL:EVSTAT2.AUX_COMPB..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE..,No event.,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV..,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N..,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE..,AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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newline
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bitfld.long 0x10 4.--7. "PRE,Prescaler division ratio is" "Divide by 1,Divide by 2,Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 32 768"
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newline
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rbitfld.long 0x10 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x10 1. "MODE,Timer 1 mode.Configure source for Timer 1 prescaler" "Use clock as source for prescaler. Note that..,Use event set by TICK_SRC as source for.."
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newline
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bitfld.long 0x10 0. "RELOAD,Timer 1 reload mode" "Manual mode.Timer 1 stops and T1CTL.EN becomes..,Continuous mode.Timer 1 restarts when the.."
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line.long 0x14 "T1CTL,Timer 1 Control"
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hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 0. "EN,Timer 1 enable.0: Disable Timer" "Disable Timer 1,Enable Timer 1.The counter restarts from 0.."
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line.long 0x18 "T1TARGET,Timer 1 TargetTimer 1 counter target value"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "VALUE,Timer 1 target value.Manual Reload Mode:- Timer 1 increments until the counter value becomes equal to or greater than VALUE"
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line.long 0x1C "T1CNTR,Timer 1 Counter"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "VALUE,Timer 1 counter value"
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tree.end
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tree "AUX_TIMER2"
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base ad:0x400C3000
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group.long 0x00++0x1B
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line.long 0x00 "CTL,Timer Control"
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hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 6. "CH3_RESET,Channel 3 reset.0: No effect.1: Reset CH3CC CH3PCC CH3EVCFG and CH3CCFG.Read returns 0" "No effect,Reset CH3CC CH3PCC.."
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newline
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bitfld.long 0x00 5. "CH2_RESET,Channel 2 reset.0: No effect.1: Reset CH2CC CH2PCC CH2EVCFG and CH2CCFG.Read returns 0" "No effect,Reset CH2CC CH2PCC.."
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newline
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bitfld.long 0x00 4. "CH1_RESET,Channel 1 reset.0: No effect.1: Reset CH1CC CH1PCC CH1EVCFG and CH1CCFG.Read returns 0" "No effect,Reset CH1CC CH1PCC.."
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newline
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bitfld.long 0x00 3. "CH0_RESET,Channel 0 reset.0: No effect.1: Reset CH0CC CH0PCC CH0EVCFG and CH0CCFG.Read returns 0" "No effect,Reset CH0CC CH0PCC.."
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newline
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bitfld.long 0x00 2. "TARGET_EN,Select counter target value.You must select TARGET to use shadow target functionality" "65535,TARGET.VALUE"
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newline
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bitfld.long 0x00 0.--1. "MODE,Timer mode control.The timer restarts from 0 when you set MODE to UP_ONCE UP_PER or UPDWN_PER" "Disable timer. Updates to counter channels and..,Count up once. The timer increments from 0 to..,Count up periodically. The timer increments from..,Count up and down periodically. The timer counts.."
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line.long 0x04 "TARGET,TargetUser defined counter target"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x04 0.--15. 1. "VALUE,16 bit user defined counter target value which is used when selected by CTL.TARGET_EN"
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line.long 0x08 "SHDWTARGET,Shadow Target"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x08 0.--15. 1. "VALUE,Target value for next counter period.The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0"
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line.long 0x0C "CNTR,Counter"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "VALUE,16 bit current counter value"
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line.long 0x10 "PRECFG,Clock Prescaler Configuration"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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abitfld.long 0x10 0.--7. "CLKDIV,Clock division.CLKDIV determines the timer clock frequency for counter synchronization and timer event updates" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
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line.long 0x14 "EVCTL,Event Control Set and clear individual events manually"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 7. "EV3_SET,Set event 3.Write 1 to set event 3" "0,1"
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newline
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bitfld.long 0x14 6. "EV3_CLR,Clear event 3.Write 1 to clear event 3" "0,1"
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newline
|
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bitfld.long 0x14 5. "EV2_SET,Set event 2.Write 1 to set event 2" "0,1"
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newline
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bitfld.long 0x14 4. "EV2_CLR,Clear event 2.Write 1 to clear event 2" "0,1"
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newline
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bitfld.long 0x14 3. "EV1_SET,Set event 1.Write 1 to set event 1" "0,1"
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newline
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bitfld.long 0x14 2. "EV1_CLR,Clear event 1.Write 1 to clear event 1" "0,1"
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newline
|
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bitfld.long 0x14 1. "EV0_SET,Set event 0.Write 1 to set event 0" "0,1"
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newline
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bitfld.long 0x14 0. "EV0_CLR,Clear event 0.Write 1 to clear event 0" "0,1"
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line.long 0x18 "PULSETRIG,Pulse Trigger"
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hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 0. "TRIG,Pulse trigger.Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE" "0,1"
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group.long 0x80++0x3F
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line.long 0x00 "CH0EVCFG,Channel 0 Event ConfigurationThis register configures channel function and enables event outputs.Each channel has an edge-detection circuit with memory"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 7. "EV3_GEN,Event 3 enable.0: Channel 0 does not control event" "Channel 0 does not control event 3,Channel 0 controls event 3"
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newline
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bitfld.long 0x00 6. "EV2_GEN,Event 2 enable.0: Channel 0 does not control event" "Channel 0 does not control event 2,Channel 0 controls event 2"
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newline
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bitfld.long 0x00 5. "EV1_GEN,Event 1 enable.0: Channel 0 does not control event" "Channel 0 does not control event 1,Channel 0 controls event 1"
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newline
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bitfld.long 0x00 4. "EV0_GEN,Event 0 enable.0: Channel 0 does not control event" "Channel 0 does not control event 0,Channel 0 controls event 0"
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newline
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bitfld.long 0x00 0.--3. "CCACT,Capture-Compare action.Capture-Compare action defines 15 different channel functions that utilize capture compare and zero events" "Disable channel.,Set on capture and then disable..,Clear on zero toggle on compare and then..,Set on zero toggle on compare and then disable..,Clear on compare and then disable..,Set on compare and then disable..,Toggle on compare and then disable..,Pulse on compare and then disable..,Period and pulse width..,Set on capture repeatedly.Channel function..,Clear on zero toggle on compare repeatedly...,Set on zero toggle on compare..,Clear on compare repeatedly.Channel function..,Set on compare repeatedly.Channel function..,Toggle on compare repeatedly.Channel function..,Pulse on compare repeatedly. Channel function.."
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line.long 0x04 "CH0CCFG,Channel 0 Capture Configuration"
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hexmask.long 0x04 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 1.--6. "CAPT_SRC,Select capture signal source from the asynchronous AUX event bus" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,?,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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bitfld.long 0x04 0. "EDGE,Edge configuration.Channel captures counter value at selected edge on signal source selected by CAPT_SRC" "Capture CNTR.VALUE at falling edge of CAPT_SRC.,Capture CNTR.VALUE at rising edge of CAPT_SRC."
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line.long 0x08 "CH0PCC,Channel 0 Pipeline Capture Compare"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x08 0.--15. 1. "VALUE,Pipeline Capture Compare value.16-bit user defined pipeline compare value or channel-updated capture value.Compare mode: An update of VALUE will be transferred to CH0CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS"
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line.long 0x0C "CH0CC,Channel 0 Capture Compare"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "VALUE,Capture Compare value.16-bit user defined compare value or channel-updated capture value.Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH0EVCFG.CCACT when these are equal"
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line.long 0x10 "CH1EVCFG,Channel 1 Event ConfigurationThis register configures channel function and enables event outputs.Each channel has an edge-detection circuit with memory"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 7. "EV3_GEN,Event 3 enable.0: Channel 1 does not control event" "Channel 1 does not control event 3,Channel 1 controls event 3"
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newline
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bitfld.long 0x10 6. "EV2_GEN,Event 2 enable.0: Channel 1 does not control event" "Channel 1 does not control event 2,Channel 1 controls event 2"
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newline
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bitfld.long 0x10 5. "EV1_GEN,Event 1 enable.0: Channel 1 does not control event" "Channel 1 does not control event 1,Channel 1 controls event 1"
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newline
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bitfld.long 0x10 4. "EV0_GEN,Event 0 enable.0: Channel 1 does not control event" "Channel 1 does not control event 0,Channel 1 controls event 0"
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newline
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bitfld.long 0x10 0.--3. "CCACT,Capture-Compare action.Capture-Compare action defines 15 different channel functions that utilize capture compare and zero events" "Disable channel.,Set on capture and then disable..,Clear on zero toggle on compare and then..,Set on zero toggle on compare and then disable..,Clear on compare and then disable..,Set on compare and then disable..,Toggle on compare and then disable..,Pulse on compare and then disable..,Period and pulse width..,Set on capture repeatedly.Channel function..,Clear on zero toggle on compare repeatedly...,Set on zero toggle on compare..,Clear on compare repeatedly.Channel function..,Set on compare repeatedly.Channel function..,Toggle on compare repeatedly.Channel function..,Pulse on compare repeatedly. Channel function.."
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line.long 0x14 "CH1CCFG,Channel 1 Capture Configuration"
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hexmask.long 0x14 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 1.--6. "CAPT_SRC,Select capture signal source from the asynchronous AUX event bus" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,?,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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bitfld.long 0x14 0. "EDGE,Edge configuration.Channel captures counter value at selected edge on signal source selected by CAPT_SRC" "Capture CNTR.VALUE at falling edge of CAPT_SRC.,Capture CNTR.VALUE at rising edge of CAPT_SRC."
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line.long 0x18 "CH1PCC,Channel 1 Pipeline Capture Compare"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "VALUE,Pipeline Capture Compare value.16-bit user defined pipeline compare value or channel-updated capture value.Compare mode: An update of VALUE will be transferred to CH1CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS"
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line.long 0x1C "CH1CC,Channel 1 Capture Compare"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "VALUE,Capture Compare value.16-bit user defined compare value or channel-updated capture value.Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH1EVCFG.CCACT when these are equal"
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line.long 0x20 "CH2EVCFG,Channel 2 Event ConfigurationThis register configures channel function and enables event outputs.Each channel has an edge-detection circuit with memory"
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 7. "EV3_GEN,Event 3 enable.0: Channel 2 does not control event" "Channel 2 does not control event 3,Channel 2 controls event 3"
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newline
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bitfld.long 0x20 6. "EV2_GEN,Event 2 enable.0: Channel 2 does not control event" "Channel 2 does not control event 2,Channel 2 controls event 2"
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newline
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bitfld.long 0x20 5. "EV1_GEN,Event 1 enable.0: Channel 2 does not control event" "Channel 2 does not control event 1,Channel 2 controls event 1"
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newline
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bitfld.long 0x20 4. "EV0_GEN,Event 0 enable.0: Channel 2 does not control event" "Channel 2 does not control event 0,Channel 2 controls event 0"
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newline
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bitfld.long 0x20 0.--3. "CCACT,Capture-Compare action.Capture-Compare action defines 15 different channel functions that utilize capture compare and zero events" "Disable channel.,Set on capture and then disable..,Clear on zero toggle on compare and then..,Set on zero toggle on compare and then disable..,Clear on compare and then disable..,Set on compare and then disable..,Toggle on compare and then disable..,Pulse on compare and then disable..,Period and pulse width..,Set on capture repeatedly.Channel function..,Clear on zero toggle on compare repeatedly...,Set on zero toggle on compare..,Clear on compare repeatedly.Channel function..,Set on compare repeatedly.Channel function..,Toggle on compare repeatedly.Channel function..,Pulse on compare repeatedly. Channel function.."
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line.long 0x24 "CH2CCFG,Channel 2 Capture Configuration"
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hexmask.long 0x24 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 1.--6. "CAPT_SRC,Select capture signal source from the asynchronous AUX event bus" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,?,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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bitfld.long 0x24 0. "EDGE,Edge configuration.Channel captures counter value at selected edge on signal source selected by CAPT_SRC" "Capture CNTR.VALUE at falling edge of CAPT_SRC.,Capture CNTR.VALUE at rising edge of CAPT_SRC."
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line.long 0x28 "CH2PCC,Channel 2 Pipeline Capture Compare"
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hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x28 0.--15. 1. "VALUE,Pipeline Capture Compare value.16-bit user defined pipeline compare value or channel-updated capture value.Compare mode: An update of VALUE will be transferred to CH2CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS"
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line.long 0x2C "CH2CC,Channel 2 Capture Compare"
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hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x2C 0.--15. 1. "VALUE,Capture Compare value.16-bit user defined compare value or channel-updated capture value.Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH2EVCFG.CCACT when these are equal"
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line.long 0x30 "CH3EVCFG,Channel 3 Event ConfigurationThis register configures channel function and enables event outputs.Each channel has an edge-detection circuit with memory"
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hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x30 7. "EV3_GEN,Event 3 enable.0: Channel 3 does not control event" "Channel 3 does not control event 3,Channel 3 controls event 3"
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newline
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bitfld.long 0x30 6. "EV2_GEN,Event 2 enable.0: Channel 3 does not control event" "Channel 3 does not control event 2,Channel 3 controls event 2"
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newline
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bitfld.long 0x30 5. "EV1_GEN,Event 1 enable.0: Channel 3 does not control event" "Channel 3 does not control event 1,Channel 3 controls event 1"
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newline
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bitfld.long 0x30 4. "EV0_GEN,Event 0 enable.0: Channel 3 does not control event" "Channel 3 does not control event 0,Channel 3 controls event 0"
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newline
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bitfld.long 0x30 0.--3. "CCACT,Capture-Compare action.Capture-Compare action defines 15 different channel functions that utilize capture compare and zero events" "Disable channel.,Set on capture and then disable..,Clear on zero toggle on compare and then..,Set on zero toggle on compare and then disable..,Clear on compare and then disable..,Set on compare and then disable..,Toggle on compare and then disable..,Pulse on compare and then disable..,Period and pulse width..,Set on capture repeatedly.Channel function..,Clear on zero toggle on compare repeatedly...,Set on zero toggle on compare..,Clear on compare repeatedly.Channel function..,Set on compare repeatedly.Channel function..,Toggle on compare repeatedly.Channel function..,Pulse on compare repeatedly. Channel function.."
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line.long 0x34 "CH3CCFG,Channel 3 Capture Configuration"
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hexmask.long 0x34 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x34 1.--6. "CAPT_SRC,Select capture signal source from the asynchronous AUX event bus" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,?,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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bitfld.long 0x34 0. "EDGE,Edge configuration.Channel captures counter value at selected edge on signal source selected by CAPT_SRC" "Capture CNTR.VALUE at falling edge of CAPT_SRC.,Capture CNTR.VALUE at rising edge of CAPT_SRC."
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line.long 0x38 "CH3PCC,Channel 3 Pipeline Capture Compare"
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hexmask.long.word 0x38 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x38 0.--15. 1. "VALUE,Pipeline Capture Compare value.16-bit user defined pipeline compare value or channel-updated capture value.Compare mode: An update of VALUE will be transferred to CH3CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS"
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line.long 0x3C "CH3CC,Channel 3 Capture Compare"
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hexmask.long.word 0x3C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x3C 0.--15. 1. "VALUE,Capture Compare value.16-bit user defined compare value or channel-updated capture value.Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH3EVCFG.CCACT when these are equal"
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tree.end
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tree.end
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tree "CCFG"
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base ad:0x50003000
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rgroup.long 0x00++0x47
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line.long 0x00 "SIZE_AND_DIS_FLAGS,CCFG Size and Disable Flags"
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hexmask.long.word 0x00 16.--31. 1. "SIZE_OF_CCFG,Total size of CCFG in bytes"
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newline
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hexmask.long.word 0x00 4.--15. 1. "DISABLE_FLAGS,Reserved for future use"
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newline
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bitfld.long 0x00 3. "DIS_TCXO,Deprecated" "0,1"
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newline
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bitfld.long 0x00 2. "DIS_GPRAM,Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).0: GPRAM is enabled and hence CACHE disabled.1: GPRAM is disabled and instead CACHE is enabled (default).Notes:- Disabling CACHE will reduce CPU execution speed (up to 60%).- GPRAM is 8.." "GPRAM is enabled and hence CACHE disabled,GPRAM is disabled and instead CACHE is enabled.."
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newline
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bitfld.long 0x00 1. "DIS_ALT_DCDC_SETTING,Disable alternate DC/DC settings" "Enable alternate DC/DC settings,Disable alternate DC/DC settings.See"
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newline
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bitfld.long 0x00 0. "DIS_XOSC_OVR,Disable XOSC override functionality.0: Enable XOSC override functionality.1: Disable XOSC override functionality.See:MODE_CONF_1.DELTA_IBIAS_INITMODE_CONF_1.DELTA_IBIAS_OFFSETMODE_CONF_1.XOSC_MAX_START" "Enable XOSC override functionality,Disable XOSC override functionality.See"
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line.long 0x04 "MODE_CONF,Mode Configuration 0"
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bitfld.long 0x04 28.--31. "VDDR_TRIM_SLEEP_DELTA,Signed delta value to apply to theVDDR_TRIM_SLEEP target minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 27. "DCDC_RECHARGE,DC/DC during recharge in powerdown.0: Use the DC/DC during recharge in powerdown.1: Do not use the DC/DC during recharge in powerdown (default).NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly.." "Use the DC/DC during recharge in powerdown,Do not use the DC/DC during recharge in.."
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newline
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bitfld.long 0x04 26. "DCDC_ACTIVE,DC/DC in active mode.0: Use the DC/DC during active mode.1: Do not use the DC/DC during active mode (default).NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled.." "Use the DC/DC during active mode,Do not use the DC/DC during active mode.."
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newline
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bitfld.long 0x04 25. "VDDR_EXT_LOAD,Reserved for future use" "0,1"
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|
newline
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bitfld.long 0x04 24. "VDDS_BOD_LEVEL,VDDS BOD level.0: VDDS BOD level is 2.0V (necessary for external load mode or for maximum PA output power on CC13xx).1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default)." "VDDS BOD level is 2.0V (necessary for external..,VDDS BOD level is 1.8V (or 1.65V for external.."
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newline
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bitfld.long 0x04 22.--23. "SCLK_LF_OPTION,Select source for SCLK_LF" "31.25kHz clock derived from 48MHz XOSC or HPOSC..,External low frequency clock on DIO defined by..,32.768kHz low frequency XOSC,Low frequency RCOSC (default)"
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newline
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bitfld.long 0x04 21. "VDDR_TRIM_SLEEP_TC," "0,1"
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|
newline
|
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bitfld.long 0x04 20. "RTC_COMP,Reserved for future use" "0,1"
|
|
newline
|
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bitfld.long 0x04 18.--19. "XOSC_FREQ,Selects which high frequency oscillator is used (required for radio usage)" "External 48Mhz TCXO.Refer to..,Internal high precision oscillator.,48 MHz XOSC_HF,24 MHz XOSC_HF. Not supported."
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newline
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bitfld.long 0x04 17. "XOSC_CAP_MOD,Enable modification (delta) to XOSC cap-array" "Apply cap-array delta,Do not apply cap-array delta (default)"
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newline
|
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bitfld.long 0x04 16. "HF_COMP,Reserved for future use" "0,1"
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|
newline
|
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hexmask.long.byte 0x04 8.--15. 1. "XOSC_CAPARRAY_DELTA,Signed 8-bit value directly modifying trimmed XOSC cap-array step value"
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|
newline
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hexmask.long.byte 0x04 0.--7. 1. "VDDR_CAP,Unsigned 8-bit integer representing the minimum decoupling capacitance (worst case) on VDDR in units of 100nF"
|
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line.long 0x08 "MODE_CONF_1,Mode Configuration 1"
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bitfld.long 0x08 31. "TCXO_TYPE,Selects the TCXO type.0: CMOS type" "CMOS type,Clipped-sine type"
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newline
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hexmask.long.byte 0x08 24.--30. 1. "TCXO_MAX_START,Maximum TCXO startup time in units of 100us.Bit field value is only valid if MODE_CONF.XOSC_FREQ=0"
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newline
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bitfld.long 0x08 20.--23. "ALT_DCDC_VMIN,Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).Voltage = (28 + ALT_DCDC_VMIN) /" "1.75V,1.8125V,?,?,?,?,?,?,?,?,?,?,?,?,2.625V,2.6875VNOTE! The.."
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newline
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bitfld.long 0x08 19. "ALT_DCDC_DITHER_EN,Enable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).0: Dither disable1: Dither enable" "Dither disable,Dither enable"
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newline
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bitfld.long 0x08 16.--18. "ALT_DCDC_IPEAK,Inductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x08 12.--15. "DELTA_IBIAS_INIT,Signed delta value for IBIAS_INIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x08 8.--11. "DELTA_IBIAS_OFFSET,Signed delta value for IBIAS_OFFSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x08 0.--7. 1. "XOSC_MAX_START,Unsigned value of maximum XOSC startup time (worst case) in units of 100us"
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line.long 0x0C "VOLT_LOAD_0,Voltage Load 0Enabled by MODE_CONF.VDDR_EXT_LOAD"
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hexmask.long.byte 0x0C 24.--31. 1. "VDDR_EXT_TP45,Reserved for future use"
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|
newline
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hexmask.long.byte 0x0C 16.--23. 1. "VDDR_EXT_TP25,Reserved for future use"
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|
newline
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hexmask.long.byte 0x0C 8.--15. 1. "VDDR_EXT_TP5,Reserved for future use"
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|
newline
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hexmask.long.byte 0x0C 0.--7. 1. "VDDR_EXT_TM15,Reserved for future use"
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line.long 0x10 "VOLT_LOAD_1,Voltage Load 1Enabled by MODE_CONF.VDDR_EXT_LOAD"
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hexmask.long.byte 0x10 24.--31. 1. "VDDR_EXT_TP125,Reserved for future use"
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|
newline
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hexmask.long.byte 0x10 16.--23. 1. "VDDR_EXT_TP105,Reserved for future use"
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|
newline
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hexmask.long.byte 0x10 8.--15. 1. "VDDR_EXT_TP85,Reserved for future use"
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|
newline
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hexmask.long.byte 0x10 0.--7. 1. "VDDR_EXT_TP65,Reserved for future use"
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line.long 0x14 "EXT_LF_CLK,Extern LF clock configuration"
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hexmask.long.byte 0x14 24.--31. 1. "DIO,Unsigned integer selecting the DIO to supply external 32kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL"
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newline
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hexmask.long.tbyte 0x14 0.--23. 1. "RTC_INCREMENT,Unsigned integer defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC"
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line.long 0x18 "IEEE_MAC_0,IEEE MAC Address 0"
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line.long 0x1C "IEEE_MAC_1,IEEE MAC Address 1"
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line.long 0x20 "IEEE_BLE_0,IEEE BLE Address 0"
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line.long 0x24 "IEEE_BLE_1,IEEE BLE Address 1"
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line.long 0x28 "BL_CONFIG,Bootloader ConfigurationConfigures the functionality of the ROM boot loader.If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the.."
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hexmask.long.byte 0x28 24.--31. 1. "BOOTLOADER_ENABLE,Bootloader enable"
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newline
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hexmask.long.byte 0x28 17.--23. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x28 16. "BL_LEVEL,Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field.0: Active low.1: Active high" "Active low,Active high"
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newline
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hexmask.long.byte 0x28 8.--15. 1. "BL_PIN_NUMBER,DIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field"
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newline
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hexmask.long.byte 0x28 0.--7. 1. "BL_ENABLE,Enables the boot loader"
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line.long 0x2C "ERASE_CONF,Erase Configuration"
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hexmask.long.tbyte 0x2C 9.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 8. "CHIP_ERASE_DIS_N,Chip erase.This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD.A successful chip erase operation will force the content of the flash main bank back to.." "Disable,Enable"
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newline
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hexmask.long.byte 0x2C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 0. "BANK_ERASE_DIS_N,Bank erase.This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE).A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration.." "Disable the boot loader bank erase function,Enable the boot loader bank erase function"
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line.long 0x30 "ERASE_CONF_1,Erase Configuration 1"
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hexmask.long 0x30 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x30 0. "WEPROT_CCFG_N,WriteErase protect the CCFG sectorSetting this bit = 0 will set FLASH:WEPROT_AUX_BY1.WEPROT_B0_CCFG_BY1 = 1 during boot and hence WriteErase protect the CCFG" "0,1"
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line.long 0x34 "CCFG_TI_OPTIONS,TI Options"
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hexmask.long.word 0x34 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.byte 0x34 8.--15. 1. "IDAU_CFG_ENABLE,IDAU"
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newline
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hexmask.long.byte 0x34 0.--7. 1. "TI_FA_ENABLE,TI Failure"
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line.long 0x38 "CCFG_TAP_DAP_0,Test Access Points Enable 0"
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hexmask.long.byte 0x38 24.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x38 16.--23. 1. "CPU_DAP_ENABLE,Enable CPU"
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newline
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hexmask.long.byte 0x38 8.--15. 1. "PWRPROF_TAP_ENABLE,Enable PWRPROF TAP.0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PWRPROF TAP access will remain disabled out of.."
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newline
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hexmask.long.byte 0x38 0.--7. 1. "TEST_TAP_ENABLE,Enable Test TAP.0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: TEST TAP access will remain disabled out of.."
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line.long 0x3C "CCFG_TAP_DAP_1,Test Access Points Enable 1"
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hexmask.long.byte 0x3C 24.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.byte 0x3C 16.--23. 1. "PBIST2_TAP_ENABLE,Enable PBIST2 TAP.0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PBIST2 TAP access will remain disabled out of.."
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newline
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hexmask.long.byte 0x3C 8.--15. 1. "PBIST1_TAP_ENABLE,Enable PBIST1 TAP.0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PBIST1 TAP access will remain disabled out of.."
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newline
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hexmask.long.byte 0x3C 0.--7. 1. "AON_TAP_ENABLE,Enable AON TAP0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: AON TAP access will remain disabled out of.."
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line.long 0x40 "IMAGE_VALID_CONF,Image Valid"
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line.long 0x44 "CCFG_WEPROT_31_0_BY2K,Protect Sectors 0-31Each bit write protects one 2KB flash sector from being both programmed and erased"
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bitfld.long 0x44 31. "WEPROT_SEC_31_N," "0,1"
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newline
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bitfld.long 0x44 30. "WEPROT_SEC_30_N," "0,1"
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newline
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bitfld.long 0x44 29. "WEPROT_SEC_29_N," "0,1"
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newline
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bitfld.long 0x44 28. "WEPROT_SEC_28_N," "0,1"
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newline
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bitfld.long 0x44 27. "WEPROT_SEC_27_N," "0,1"
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newline
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bitfld.long 0x44 26. "WEPROT_SEC_26_N," "0,1"
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newline
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bitfld.long 0x44 25. "WEPROT_SEC_25_N," "0,1"
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newline
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bitfld.long 0x44 24. "WEPROT_SEC_24_N," "0,1"
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newline
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bitfld.long 0x44 23. "WEPROT_SEC_23_N," "0,1"
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newline
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bitfld.long 0x44 22. "WEPROT_SEC_22_N," "0,1"
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newline
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bitfld.long 0x44 21. "WEPROT_SEC_21_N," "0,1"
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newline
|
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bitfld.long 0x44 20. "WEPROT_SEC_20_N," "0,1"
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newline
|
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bitfld.long 0x44 19. "WEPROT_SEC_19_N," "0,1"
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newline
|
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bitfld.long 0x44 18. "WEPROT_SEC_18_N," "0,1"
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newline
|
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bitfld.long 0x44 17. "WEPROT_SEC_17_N," "0,1"
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newline
|
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bitfld.long 0x44 16. "WEPROT_SEC_16_N," "0,1"
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newline
|
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bitfld.long 0x44 15. "WEPROT_SEC_15_N," "0,1"
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newline
|
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bitfld.long 0x44 14. "WEPROT_SEC_14_N," "0,1"
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newline
|
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bitfld.long 0x44 13. "WEPROT_SEC_13_N," "0,1"
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newline
|
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bitfld.long 0x44 12. "WEPROT_SEC_12_N," "0,1"
|
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newline
|
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bitfld.long 0x44 11. "WEPROT_SEC_11_N," "0,1"
|
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newline
|
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bitfld.long 0x44 10. "WEPROT_SEC_10_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 9. "WEPROT_SEC_9_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 8. "WEPROT_SEC_8_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 7. "WEPROT_SEC_7_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 6. "WEPROT_SEC_6_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 5. "WEPROT_SEC_5_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 4. "WEPROT_SEC_4_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 3. "WEPROT_SEC_3_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 2. "WEPROT_SEC_2_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 1. "WEPROT_SEC_1_N," "0,1"
|
|
newline
|
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bitfld.long 0x44 0. "WEPROT_SEC_0_N," "0,1"
|
|
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x48)++0x03
|
|
line.long 0x00 "CCFG_WEPROT_SPARE_$1,Spare register for WriteErase configuration"
|
|
repeat.end
|
|
rgroup.long 0x54++0x0B
|
|
line.long 0x00 "TRUSTZONE_FLASH_CFG,Trustzone configuration register for flash"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x00 10.--16. 1. "NSADDR_BOUNDARY,Value will be written to PRCM:NVMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
newline
|
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hexmask.long.word 0x00 0.--9. 1. "NSCADDR_BOUNDARY,Value will be written to PRCM:NVMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
line.long 0x04 "TRUSTZONE_SRAM_CFG,Trustzone configuration register for MCU SRAM"
|
|
hexmask.long.word 0x04 18.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x04 9.--17. 1. "NSADDR_BOUNDARY,Value will be written to PRCM:SRAMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
newline
|
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hexmask.long.word 0x04 0.--8. 1. "NSCADDR_BOUNDARY,Value will be written to PRCM:SRAMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
line.long 0x08 "SRAM_CFG,Configuration register for MCU SRAM"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "MEM_SEL,Value will be written to SRAM_MMR:MEM_CTL.MEM_SEL by ROM boot FW"
|
|
newline
|
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hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "PARITY_DIS,Value will be inverted and then written to PRCM:MCUSRAMCFG.PARITY_EN by ROM boot FW" "0,1"
|
|
rgroup.long 0x64++0x07
|
|
line.long 0x00 "CPU_LOCK_CFG,Configuration register for MCU CPU lock options"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4. "LOCKNSVTOR_N,Value will be inverted and written to PRCM:CPULOCK.LOCKNSVTOR by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "LOCKSVTAIRCR_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSVTAIRCR by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "LOCKSAU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSAU by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKNSMPU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKNSMPU by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LOCKSMPU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSMPU by ROM boot FW" "0,1"
|
|
line.long 0x04 "DEB_AUTH_CFG,Configuration register for debug authentication"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 3. "INTSPNIDEN,Value will be written to CPU_DCB:DAUTHCTRL.INTSPNIDEN by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "SPNIDENSEL,Value will be written to CPU_DCB:DAUTHCTRL.SPNIDENSEL by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "INTSPIDEN,Value will be written to CPU_DCB:DAUTHCTRL.INTSPIDEN by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "SPIDENSEL,Value will be written to CPU_DCB:DAUTHCTRL.SPIDENSEL by ROM boot FW" "0,1"
|
|
tree.end
|
|
tree "CPU"
|
|
tree "CPU_DWT"
|
|
base ad:0xE0001000
|
|
rgroup.long 0x00++0x1F
|
|
line.long 0x00 "CTRL,Provides configuration and status information for the DWT unit. and used to control features of the unit"
|
|
bitfld.long 0x00 28.--31. "NUMCOMP,Number of DWT comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "NOTRCPKT,Indicates whether the implementation does not support trace" "0,1"
|
|
bitfld.long 0x00 26. "NOEXTTRIG,Reserved RAZ" "0,1"
|
|
bitfld.long 0x00 25. "NOCYCCNT,Indicates whether the implementation does not include a cycle counter" "0,1"
|
|
bitfld.long 0x00 24. "NOPRFCNT,Indicates whether the implementation does not include the profiling counters" "0,1"
|
|
bitfld.long 0x00 23. "CYCDISS,Controls whether the cycle counter is disabled in Secure state" "0,1"
|
|
bitfld.long 0x00 22. "CYCEVTENA,Enables Event Counter packet generation on POSTCNT underflow" "0,1"
|
|
bitfld.long 0x00 21. "FOLDEVTENA,Enables DWT_FOLDCNT counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LSUEVTENA,Enables DWT_LSUCNT counter" "0,1"
|
|
bitfld.long 0x00 19. "SLEEPEVTENA,Enable DWT_SLEEPCNT counter" "0,1"
|
|
bitfld.long 0x00 18. "EXCEVTENA,Enables DWT_EXCCNT counter" "0,1"
|
|
bitfld.long 0x00 17. "CPIEVTENA,Enables DWT_CPICNT counter" "0,1"
|
|
bitfld.long 0x00 16. "EXTTRCENA,Enables generation of Exception Trace packets" "0,1"
|
|
bitfld.long 0x00 13.--15. "RESERVED13,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "PCSAMPLENA,Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation" "0,1"
|
|
bitfld.long 0x00 10.--11. "SYNCTAP,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "CYCTAP,Selects the position of the POSTCNT tap on the CYCCNT counter" "0,1"
|
|
bitfld.long 0x00 5.--8. "POSTINIT,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "POSTPRESET,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "CYCCNTENA,Enables CYCCNT" "0,1"
|
|
line.long 0x04 "CYCCNT,Shows or sets the value of the processor cycle counter. CYCCNT"
|
|
line.long 0x08 "CPICNT,CPI Count Register"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x08 0.--7. 1. "CPICNT,Counts one on each cycle when all of the following are true:- DWT_CTRL.CPIEVTENA == 1 and DEMCR.TRCENA == 1.- No instruction is executed.- No load-store operation is in progress see DWT_LSUCNT.- No exception-entry or exception-exit operation is.."
|
|
line.long 0x0C "EXCCNT,Counts the total cycles spent in exception processing"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EXCCNT,Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x10 "SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SLEEPCNT,Counts one on each cycle when all of the following are true:- DWT_CTRL.SLEEPEVTENA == 1 and DEMCR.TRCENA == 1.- No instruction is executed see DWT_CPICNT.- No load-store operation is in progress see DWT_LSUCNT.- No exception-entry or.."
|
|
line.long 0x14 "LSUCNT,Increments on the additional cycles required to execute all load or store instructions"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x14 0.--7. 1. "LSUCNT,Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x18 "FOLDCNT,Increments on the additional cycles required to execute all load or store instructions"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FOLDCNT,Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x1C "PCSR,Program Counter Sample Register"
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x10 0x20 0x30 )
|
|
hgroup.long ($2+0x20)++0x03
|
|
hide.long 0x00 "COMP$1,Provides a reference value for use by watchpoint comparator 0"
|
|
repeat.end
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x10 0x20 0x30 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "FUNCTION$1,Controls the operation of watchpoint comparator 0"
|
|
rbitfld.long 0x00 27.--31. "ID,Identifies the capabilities for MATCH for comparator *n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 25.--26. "RESERVED25,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 24. "MATCHED,Set to 1 when the comparator matches" "0,1"
|
|
hexmask.long.word 0x00 12.--23. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,Defines the size of the object being watched for by Data Value and Data Address comparators" "0,1,2,3"
|
|
rbitfld.long 0x00 6.--9. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "ACTION,Defines the action on a match" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "MATCH,Controls the type of match generated by this comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the DWT"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_FPB"
|
|
base ad:0xE0002000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Provides FPB implementation information. and the global enable for the FPB unit"
|
|
rbitfld.long 0x00 28.--31. "REV,Flash Patch and Breakpoint Unit architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 15.--27. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 12.--14. "NUM_CODE_14_12_,Indicates the number of implemented instruction address comparators" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--11. "NUM_LIT,Indicates the number of implemented literal address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "NUM_CODE_7_4_,Indicates the number of implemented instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "KEY,Writes to the FP_CTRL are ignored unless KEY is concurrently written to one" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the FPB" "0,1"
|
|
line.long 0x04 "REMAP,Indicates whether the implementation supports Flash Patch remap and. if it does. holds the target address for remap"
|
|
bitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x04 29. "RMPSPT,Indicates whether the FPB unit supports the Flash Patch remap function" "0,1"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. "REMAP,Holds the bits[28:5] of the Flash Patch remap address"
|
|
bitfld.long 0x04 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "COMP$1,Holds an address for comparison"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "BE,Selects between flashpatch and breakpoint functionality" "0,1"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the FPB"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the FPB"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the FP"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_ITM"
|
|
base ad:0xE0000000
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "STIM$1,Provides the interface for generating Instrumentation packets"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "DISABLED,Indicates whether the Stimulus Port is enabled or disabled" "0,1"
|
|
bitfld.long 0x00 0. "FIFOREADY,Indicates whether the Stimulus Port can accept data" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "STIM$1,Provides the interface for generating Instrumentation packets"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "DISABLED,Indicates whether the Stimulus Port is enabled or disabled" "0,1"
|
|
bitfld.long 0x00 0. "FIFOREADY,Indicates whether the Stimulus Port can accept data" "0,1"
|
|
repeat.end
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "TER0,Provide an individual enable bit for each ITM_STIM register"
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "TPR,Controls which stimulus ports can be accessed by unprivileged code"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "TCR,Configures and controls transfers through the ITM interface"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 23. "BUSY,Indicates whether the ITM is currently processing events" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "TraceBusID,Identifier for multi-source trace stream formatting"
|
|
rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "GTSFREQ,Defines how often the ITM generates a global timestamp based on the global timestamp clock frequency or disables generation of global timestamps" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "TSPrescale,Local timestamp prescaler used with the trace packet reference clock" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x00 5. "STALLENA,Stall the PE to guarantee delivery of Data Trace packets" "0,1"
|
|
bitfld.long 0x00 4. "SWOENA,Enables asynchronous clocking of the timestamp counter" "0,1"
|
|
bitfld.long 0x00 3. "TXENA,Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU" "0,1"
|
|
bitfld.long 0x00 2. "SYNCENA,Enables Synchronization packet transmission for a synchronous TPIU" "0,1"
|
|
bitfld.long 0x00 1. "TSENA,Enables Local timestamp generation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ITMENA,Enables the ITM" "0,1"
|
|
rgroup.long 0xEF0++0x03
|
|
line.long 0x00 "INT_ATREADY,Integration Mode: Read ATB Ready"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFVALID,A read of this bit returns the value of AFVALID" "0,1"
|
|
bitfld.long 0x00 0. "ATREADY,A read of this bit returns the value of ATREADY" "0,1"
|
|
group.long 0xEF8++0x03
|
|
line.long 0x00 "INT_ATVALID,Integration Mode: Write ATB Valid"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFREADY,A write to this bit gives the value of AFREADY" "0,1"
|
|
bitfld.long 0x00 0. "ATREADY,A write to this bit gives the value of ATVALID" "0,1"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ITCTRL,Integration Mode Control Register"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "IME,Integration mode enable bit - The possible values are" "The trace unit is not in integration mode,The trace unit is in integration mode"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the ITM"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_SCS"
|
|
base ad:0xE000E000
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "RESERVED000,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "ICTR,Interrupt Control TypeRead this register to see the number of interrupt lines that the NVIC supports"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "INTLINESNUM,Total number of interrupt lines in groups of" "0...32,33...64,65...96,97...128,129...160,161...192,193...224,225...256"
|
|
line.long 0x08 "ACTLR,Auxiliary ControlThis register is used to disable certain aspects of functionality within the processor"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 9. "DISOOFP,Disables floating point instructions completing out of order with respect to integer instructions" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "DISFPCA,Disable automatic update of CONTROL.FPCA" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "DISFOLD,Disables folding of IT instruction" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "DISDEFWBUF,Disables write buffer use during default memory map accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "DISMCYCINT,Disables interruption of multi-cycle instructions" "0,1"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "STCSR,SysTick Control and StatusThis register enables the SysTick features and returns status flags related to SysTick"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 16. "COUNTFLAG,Returns 1 if timer counted to 0 since last time this was" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 3.--15. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "CLKSOURCE,Clock source:0: External reference clock.1: Core clockExternal clock is not available in this device" "External reference clock,Core clockExternal clock is not available in.."
|
|
newline
|
|
bitfld.long 0x00 1. "TICKINT," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,Enable SysTick counter0: Counter disabled1: Counter operates in a multi-shot way" "Counter disabled,Counter operates in a multi-shot way"
|
|
line.long 0x04 "STRVR,SysTick Reload ValueThis register is used to specify the start value to load into the current value register STCVR.CURRENT when the counter reaches 0"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x04 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current ValueRead from this register returns the current value of SysTick counter"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "CURRENT,Current value at the time the register is accessed"
|
|
line.long 0x0C "STCR,SysTick Calibration ValueUsed to enable software to scale to any required speed using divide and multiply"
|
|
bitfld.long 0x0C 31. "NOREF,Reads as one" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 30. "SKEW,Reads as one" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 24.--29. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. "TENMS,An optional Reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "NVIC_ISER0,Irq 0 to 31 Set EnableThis register is used to enable interrupts and determine which interrupts are currently enabled"
|
|
bitfld.long 0x00 31. "SETENA31,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SETENA30,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "SETENA29,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "SETENA28,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "SETENA27,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "SETENA26,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "SETENA25,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "SETENA24,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "SETENA23,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "SETENA22,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "SETENA21,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "SETENA20,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "SETENA19,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "SETENA18,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "SETENA17,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "SETENA16,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "SETENA15,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "SETENA14,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "SETENA13,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "SETENA12,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SETENA11,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "SETENA10,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SETENA9,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SETENA8,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SETENA7,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SETENA6,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SETENA5,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SETENA4,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SETENA3,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SETENA2,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SETENA1,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SETENA0,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
|
|
line.long 0x04 "NVIC_ISER1,Irq 32 to 63 Set EnableThis register is used to enable interrupts and determine which interrupts are currently enabled"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "SETENA37,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "SETENA36,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "SETENA35,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "SETENA34,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "SETENA33,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "SETENA32,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
|
|
group.long 0x180++0x07
|
|
line.long 0x00 "NVIC_ICER0,Irq 0 to 31 Clear EnableThis register is used to disable interrupts and determine which interrupts are currently enabled"
|
|
bitfld.long 0x00 31. "CLRENA31,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLRENA30,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CLRENA29,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "CLRENA28,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CLRENA27,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "CLRENA26,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "CLRENA25,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "CLRENA24,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CLRENA23,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "CLRENA22,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CLRENA21,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "CLRENA20,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CLRENA19,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CLRENA18,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CLRENA17,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "CLRENA16,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CLRENA15,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "CLRENA14,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CLRENA13,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CLRENA12,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CLRENA11,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CLRENA10,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CLRENA9,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CLRENA8,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CLRENA7,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "CLRENA6,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CLRENA5,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "CLRENA4,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CLRENA3,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
|
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bitfld.long 0x00 2. "CLRENA2,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "CLRENA1,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "CLRENA0,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
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line.long 0x04 "NVIC_ICER1,Irq 32 to 63 Clear EnableThis register is used to disable interrupts and determine which interrupts are currently enabled"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x04 5. "CLRENA37,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "CLRENA36,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "CLRENA35,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "CLRENA34,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "CLRENA33,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "CLRENA32,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
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group.long 0x200++0x07
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line.long 0x00 "NVIC_ISPR0,Irq 0 to 31 Set PendingThis register is used to force interrupts into the pending state and determine which interrupts are currently pending"
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bitfld.long 0x00 31. "SETPEND31,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
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bitfld.long 0x00 30. "SETPEND30,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
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bitfld.long 0x00 29. "SETPEND29,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
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bitfld.long 0x00 28. "SETPEND28,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
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bitfld.long 0x00 27. "SETPEND27,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
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bitfld.long 0x00 26. "SETPEND26,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
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bitfld.long 0x00 25. "SETPEND25,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
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bitfld.long 0x00 24. "SETPEND24,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
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bitfld.long 0x00 23. "SETPEND23,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
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bitfld.long 0x00 22. "SETPEND22,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
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bitfld.long 0x00 21. "SETPEND21,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
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bitfld.long 0x00 20. "SETPEND20,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
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bitfld.long 0x00 19. "SETPEND19,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
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bitfld.long 0x00 18. "SETPEND18,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
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bitfld.long 0x00 17. "SETPEND17,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
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bitfld.long 0x00 16. "SETPEND16,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
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bitfld.long 0x00 15. "SETPEND15,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
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bitfld.long 0x00 14. "SETPEND14,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
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bitfld.long 0x00 13. "SETPEND13,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
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bitfld.long 0x00 12. "SETPEND12,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
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bitfld.long 0x00 11. "SETPEND11,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
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bitfld.long 0x00 10. "SETPEND10,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
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bitfld.long 0x00 9. "SETPEND9,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
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bitfld.long 0x00 8. "SETPEND8,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
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bitfld.long 0x00 7. "SETPEND7,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "SETPEND6,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "SETPEND5,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "SETPEND4,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "SETPEND3,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "SETPEND2,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "SETPEND1,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "SETPEND0,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
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line.long 0x04 "NVIC_ISPR1,Irq 32 to 63 Set PendingThis register is used to force interrupts into the pending state and determine which interrupts are currently pending"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x04 5. "SETPEND37,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "SETPEND36,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "SETPEND35,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "SETPEND34,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "SETPEND33,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "SETPEND32,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
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group.long 0x280++0x07
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line.long 0x00 "NVIC_ICPR0,Irq 0 to 31 Clear PendingThis register is used to clear pending interrupts and determine which interrupts are currently pending"
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bitfld.long 0x00 31. "CLRPEND31,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
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bitfld.long 0x00 30. "CLRPEND30,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
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bitfld.long 0x00 29. "CLRPEND29,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
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bitfld.long 0x00 28. "CLRPEND28,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
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bitfld.long 0x00 27. "CLRPEND27,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
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bitfld.long 0x00 26. "CLRPEND26,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
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bitfld.long 0x00 25. "CLRPEND25,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
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bitfld.long 0x00 24. "CLRPEND24,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
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bitfld.long 0x00 23. "CLRPEND23,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
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bitfld.long 0x00 22. "CLRPEND22,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
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bitfld.long 0x00 21. "CLRPEND21,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
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bitfld.long 0x00 20. "CLRPEND20,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
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bitfld.long 0x00 19. "CLRPEND19,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
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bitfld.long 0x00 18. "CLRPEND18,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
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bitfld.long 0x00 17. "CLRPEND17,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
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bitfld.long 0x00 16. "CLRPEND16,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
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bitfld.long 0x00 15. "CLRPEND15,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
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bitfld.long 0x00 14. "CLRPEND14,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
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bitfld.long 0x00 13. "CLRPEND13,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
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bitfld.long 0x00 12. "CLRPEND12,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
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bitfld.long 0x00 11. "CLRPEND11,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
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bitfld.long 0x00 10. "CLRPEND10,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
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bitfld.long 0x00 9. "CLRPEND9,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
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bitfld.long 0x00 8. "CLRPEND8,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
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bitfld.long 0x00 7. "CLRPEND7,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "CLRPEND6,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "CLRPEND5,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "CLRPEND4,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "CLRPEND3,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "CLRPEND2,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "CLRPEND1,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "CLRPEND0,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
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line.long 0x04 "NVIC_ICPR1,Irq 32 to 63 Clear PendingThis register is used to clear pending interrupts and determine which interrupts are currently pending"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x04 5. "CLRPEND37,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "CLRPEND36,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "CLRPEND35,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "CLRPEND34,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "CLRPEND33,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "CLRPEND32,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
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rgroup.long 0x300++0x07
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line.long 0x00 "NVIC_IABR0,Irq 0 to 31 Active BitThis register is used to determine which interrupts are active"
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bitfld.long 0x00 31. "ACTIVE31,Reading 0 from this bit implies that interrupt line 31 is not active" "0,1"
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bitfld.long 0x00 30. "ACTIVE30,Reading 0 from this bit implies that interrupt line 30 is not active" "0,1"
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bitfld.long 0x00 29. "ACTIVE29,Reading 0 from this bit implies that interrupt line 29 is not active" "0,1"
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bitfld.long 0x00 28. "ACTIVE28,Reading 0 from this bit implies that interrupt line 28 is not active" "0,1"
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bitfld.long 0x00 27. "ACTIVE27,Reading 0 from this bit implies that interrupt line 27 is not active" "0,1"
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bitfld.long 0x00 26. "ACTIVE26,Reading 0 from this bit implies that interrupt line 26 is not active" "0,1"
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bitfld.long 0x00 25. "ACTIVE25,Reading 0 from this bit implies that interrupt line 25 is not active" "0,1"
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bitfld.long 0x00 24. "ACTIVE24,Reading 0 from this bit implies that interrupt line 24 is not active" "0,1"
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bitfld.long 0x00 23. "ACTIVE23,Reading 0 from this bit implies that interrupt line 23 is not active" "0,1"
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bitfld.long 0x00 22. "ACTIVE22,Reading 0 from this bit implies that interrupt line 22 is not active" "0,1"
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bitfld.long 0x00 21. "ACTIVE21,Reading 0 from this bit implies that interrupt line 21 is not active" "0,1"
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bitfld.long 0x00 20. "ACTIVE20,Reading 0 from this bit implies that interrupt line 20 is not active" "0,1"
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bitfld.long 0x00 19. "ACTIVE19,Reading 0 from this bit implies that interrupt line 19 is not active" "0,1"
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bitfld.long 0x00 18. "ACTIVE18,Reading 0 from this bit implies that interrupt line 18 is not active" "0,1"
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bitfld.long 0x00 17. "ACTIVE17,Reading 0 from this bit implies that interrupt line 17 is not active" "0,1"
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bitfld.long 0x00 16. "ACTIVE16,Reading 0 from this bit implies that interrupt line 16 is not active" "0,1"
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bitfld.long 0x00 15. "ACTIVE15,Reading 0 from this bit implies that interrupt line 15 is not active" "0,1"
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bitfld.long 0x00 14. "ACTIVE14,Reading 0 from this bit implies that interrupt line 14 is not active" "0,1"
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bitfld.long 0x00 13. "ACTIVE13,Reading 0 from this bit implies that interrupt line 13 is not active" "0,1"
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bitfld.long 0x00 12. "ACTIVE12,Reading 0 from this bit implies that interrupt line 12 is not active" "0,1"
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bitfld.long 0x00 11. "ACTIVE11,Reading 0 from this bit implies that interrupt line 11 is not active" "0,1"
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bitfld.long 0x00 10. "ACTIVE10,Reading 0 from this bit implies that interrupt line 10 is not active" "0,1"
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bitfld.long 0x00 9. "ACTIVE9,Reading 0 from this bit implies that interrupt line 9 is not active" "0,1"
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bitfld.long 0x00 8. "ACTIVE8,Reading 0 from this bit implies that interrupt line 8 is not active" "0,1"
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bitfld.long 0x00 7. "ACTIVE7,Reading 0 from this bit implies that interrupt line 7 is not active" "0,1"
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bitfld.long 0x00 6. "ACTIVE6,Reading 0 from this bit implies that interrupt line 6 is not active" "0,1"
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bitfld.long 0x00 5. "ACTIVE5,Reading 0 from this bit implies that interrupt line 5 is not active" "0,1"
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bitfld.long 0x00 4. "ACTIVE4,Reading 0 from this bit implies that interrupt line 4 is not active" "0,1"
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bitfld.long 0x00 3. "ACTIVE3,Reading 0 from this bit implies that interrupt line 3 is not active" "0,1"
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bitfld.long 0x00 2. "ACTIVE2,Reading 0 from this bit implies that interrupt line 2 is not active" "0,1"
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bitfld.long 0x00 1. "ACTIVE1,Reading 0 from this bit implies that interrupt line 1 is not active" "0,1"
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bitfld.long 0x00 0. "ACTIVE0,Reading 0 from this bit implies that interrupt line 0 is not active" "0,1"
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line.long 0x04 "NVIC_IABR1,Irq 32 to 63 Active BitThis register is used to determine which interrupts are active"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x04 5. "ACTIVE37,Reading 0 from this bit implies that interrupt line 37 is not active" "0,1"
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bitfld.long 0x04 4. "ACTIVE36,Reading 0 from this bit implies that interrupt line 36 is not active" "0,1"
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bitfld.long 0x04 3. "ACTIVE35,Reading 0 from this bit implies that interrupt line 35 is not active" "0,1"
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bitfld.long 0x04 2. "ACTIVE34,Reading 0 from this bit implies that interrupt line 34 is not active" "0,1"
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bitfld.long 0x04 1. "ACTIVE33,Reading 0 from this bit implies that interrupt line 33 is not active" "0,1"
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bitfld.long 0x04 0. "ACTIVE32,Reading 0 from this bit implies that interrupt line 32 is not active" "0,1"
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group.long 0x400++0x27
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line.long 0x00 "NVIC_IPR0,Irq 0 to 3 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details)"
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hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details)"
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hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details)"
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hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details)"
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line.long 0x04 "NVIC_IPR1,Irq 4 to 7 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x04 24.--31. 1. "PRI_7,Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details)"
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hexmask.long.byte 0x04 16.--23. 1. "PRI_6,Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details)"
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hexmask.long.byte 0x04 8.--15. 1. "PRI_5,Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details)"
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hexmask.long.byte 0x04 0.--7. 1. "PRI_4,Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details)"
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line.long 0x08 "NVIC_IPR2,Irq 8 to 11 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x08 24.--31. 1. "PRI_11,Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details)"
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hexmask.long.byte 0x08 16.--23. 1. "PRI_10,Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details)"
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hexmask.long.byte 0x08 8.--15. 1. "PRI_9,Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details)"
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hexmask.long.byte 0x08 0.--7. 1. "PRI_8,Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details)"
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line.long 0x0C "NVIC_IPR3,Irq 12 to 15 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x0C 24.--31. 1. "PRI_15,Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details)"
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hexmask.long.byte 0x0C 16.--23. 1. "PRI_14,Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details)"
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hexmask.long.byte 0x0C 8.--15. 1. "PRI_13,Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details)"
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hexmask.long.byte 0x0C 0.--7. 1. "PRI_12,Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details)"
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line.long 0x10 "NVIC_IPR4,Irq 16 to 19 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x10 24.--31. 1. "PRI_19,Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details)"
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hexmask.long.byte 0x10 16.--23. 1. "PRI_18,Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details)"
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hexmask.long.byte 0x10 8.--15. 1. "PRI_17,Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details)"
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hexmask.long.byte 0x10 0.--7. 1. "PRI_16,Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details)"
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line.long 0x14 "NVIC_IPR5,Irq 20 to 23 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x14 24.--31. 1. "PRI_23,Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details)"
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hexmask.long.byte 0x14 16.--23. 1. "PRI_22,Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details)"
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hexmask.long.byte 0x14 8.--15. 1. "PRI_21,Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details)"
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hexmask.long.byte 0x14 0.--7. 1. "PRI_20,Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details)"
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line.long 0x18 "NVIC_IPR6,Irq 24 to 27 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x18 24.--31. 1. "PRI_27,Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details)"
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hexmask.long.byte 0x18 16.--23. 1. "PRI_26,Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details)"
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hexmask.long.byte 0x18 8.--15. 1. "PRI_25,Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details)"
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hexmask.long.byte 0x18 0.--7. 1. "PRI_24,Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details)"
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line.long 0x1C "NVIC_IPR7,Irq 28 to 31 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x1C 24.--31. 1. "PRI_31,Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details)"
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hexmask.long.byte 0x1C 16.--23. 1. "PRI_30,Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details)"
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hexmask.long.byte 0x1C 8.--15. 1. "PRI_29,Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details)"
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hexmask.long.byte 0x1C 0.--7. 1. "PRI_28,Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details)"
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line.long 0x20 "NVIC_IPR8,Irq 32 to 35 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x20 24.--31. 1. "PRI_35,Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details)"
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hexmask.long.byte 0x20 16.--23. 1. "PRI_34,Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details)"
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hexmask.long.byte 0x20 8.--15. 1. "PRI_33,Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details)"
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hexmask.long.byte 0x20 0.--7. 1. "PRI_32,Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details)"
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line.long 0x24 "NVIC_IPR9,Irq 32 to 35 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x24 8.--15. 1. "PRI_37,Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details)"
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hexmask.long.byte 0x24 0.--7. 1. "PRI_36,Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details)"
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rgroup.long 0xD00++0x4F
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line.long 0x00 "CPUID,CPUID BaseThis register determines the ID number of the processor core. the version number of the processor core and the implementation details of the processor core"
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hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementor code"
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bitfld.long 0x00 20.--23. "VARIANT,Implementation defined variant number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "CONSTANT,Reads as 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "PARTNO,Number of processor within family"
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bitfld.long 0x00 0.--3. "REVISION,Implementation defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "ICSR,Interrupt Control StateThis register is used to set a pending Non-Maskable Interrupt (NMI). set or clear a pending SVC. set or clear a pending SysTick. check for pending exceptions. check the vector number of the highest priority pended exception.."
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bitfld.long 0x04 31. "NMIPENDSET,Set pending NMI bit" "No action,Set pending NMI"
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bitfld.long 0x04 29.--30. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x04 28. "PENDSVSET,Set pending pendSV bit.0: No action1: Set pending PendSV" "No action,Set pending PendSV"
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bitfld.long 0x04 27. "PENDSVCLR,Clear pending pendSV bit0: No action1: Clear pending pendSV" "No action,Clear pending pendSV"
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bitfld.long 0x04 26. "PENDSTSET,Set a pending SysTick bit.0: No action1: Set pending SysTick" "No action,Set pending SysTick"
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bitfld.long 0x04 25. "PENDSTCLR,Clear pending SysTick bit0: No action1: Clear pending SysTick" "No action,Clear pending SysTick"
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rbitfld.long 0x04 24. "RESERVED24,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x04 23. "ISRPREEMPT,This field can only be used at debug time" "A pending exception is not serviced,A pending exception is serviced on exit from the.."
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bitfld.long 0x04 22. "ISRPENDING,Interrupt pending flag" "Interrupt not pending,Interrupt pending"
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rbitfld.long 0x04 18.--21. "RESERVED18,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x04 12.--17. "VECTPENDING,Pending ISR number field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 11. "RETTOBASE,Indicates whether there are preempted active exceptions:0: There are preempted active exceptions to execute1: There are no active exceptions or the currently-executing exception is the only active exception" "There are preempted active exceptions to execute,There are no active exceptions or the.."
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rbitfld.long 0x04 9.--10. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3"
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hexmask.long.word 0x04 0.--8. 1. "VECTACTIVE,Active ISR number field"
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line.long 0x08 "VTOR,Vector Table OffsetThis register is used to relocated the vector table base address"
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bitfld.long 0x08 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
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hexmask.long.tbyte 0x08 7.--29. 1. "TBLOFF,Bits 29 down to 7 of the vector table base offset"
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hexmask.long.byte 0x08 0.--6. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x0C "AIRCR,Application Interrupt/Reset ControlThis register is used to determine data endianness. clear all active state information for debug or to recover from a hard failure. execute a system reset. alter the priority grouping position (binary point)"
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hexmask.long.word 0x0C 16.--31. 1. "VECTKEY,Register key"
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rbitfld.long 0x0C 15. "ENDIANESS,Data endianness bit" "Little endian,Big endian"
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rbitfld.long 0x0C 11.--14. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--10. "PRIGROUP,Interrupt priority grouping field" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 2. "SYSRESETREQ,Requests a warm reset" "0,1"
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bitfld.long 0x0C 1. "VECTCLRACTIVE,Clears all active state information for active NMI fault and interrupts" "0,1"
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bitfld.long 0x0C 0. "VECTRESET,System Reset bit" "0,1"
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line.long 0x10 "SCR,System ControlThis register is used for power-management functions. i.e.. signaling to the system when the processor can enter a low power state. controlling how the processor enters and exits low power states"
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hexmask.long 0x10 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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bitfld.long 0x10 4. "SEVONPEND,Send Event on Pending bit:0: Only enabled interrupts or events can wakeup the processor disabled interrupts are excluded1: Enabled events and all interrupts including disabled interrupts can wakeup the processor.When an event or interrupt.." "Only enabled interrupts or events can wakeup the..,Enabled events and all interrupts including.."
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bitfld.long 0x10 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x10 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low power mode" "Sleep,Deep sleep"
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bitfld.long 0x10 1. "SLEEPONEXIT,Sleep on exit when returning from Handler mode to Thread mode" "Do not sleep when returning to thread mode,Sleep on ISR exit"
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bitfld.long 0x10 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x14 "CCR,Configuration ControlThis register is used to enable NMI. HardFault and FAULTMASK to ignore bus fault. trap divide by zero and unaligned accesses. enable user access to the Software Trigger Interrupt Register (STIR). control entry to Thread Mode"
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hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
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bitfld.long 0x14 9. "STKALIGN,Stack alignment bit.0: Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.1: On exception entry the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved" "Only 4-byte alignment is guaranteed for the SP..,On exception entry the SP used prior to the.."
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bitfld.long 0x14 8. "BFHFNMIGN,Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions" "Data BusFaults caused by load and store..,Data BusFaults caused by load and store.."
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bitfld.long 0x14 5.--7. "RESERVED5,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4. "DIV_0_TRP,Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of" "Do not trap divide by 0,Trap divide by 0"
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bitfld.long 0x14 3. "UNALIGN_TRP,Enables unaligned access traps:0: Do not trap unaligned halfword and word accesses1: Trap unaligned halfword and word accesses" "Do not trap unaligned halfword and word accesses,Trap unaligned halfword and word accesses"
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bitfld.long 0x14 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x14 1. "USERSETMPEND,Enables unprivileged software access to STIR:0: User code is not allowed to write to the Software Trigger Interrupt register (STIR).1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception.." "User code is not allowed to write to the..,User code can write the Software Trigger.."
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bitfld.long 0x14 0. "NONBASETHREDENA,Indicates how the processor enters Thread mode:0: Processor can enter Thread mode only when no exception is active.1: Processor can enter Thread mode from any level using the appropriate return value (EXC_RETURN).Exception returns occur.." "Processor can enter Thread mode only when no..,Processor can enter Thread mode from any level.."
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line.long 0x18 "SHPR1,System Handlers 4-7 PriorityThis register is used to prioritize the following system handlers: Memory manage. Bus fault. and Usage fault"
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hexmask.long.byte 0x18 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x18 16.--23. 1. "PRI_6,Priority of system handler 6"
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hexmask.long.byte 0x18 8.--15. 1. "PRI_5,Priority of system handler"
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hexmask.long.byte 0x18 0.--7. 1. "PRI_4,Priority of system handler"
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line.long 0x1C "SHPR2,System Handlers 8-11 PriorityThis register is used to prioritize the SVC handler"
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hexmask.long.byte 0x1C 24.--31. 1. "PRI_11,Priority of system handler 11"
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hexmask.long.tbyte 0x1C 0.--23. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
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line.long 0x20 "SHPR3,System Handlers 12-15 PriorityThis register is used to prioritize the following system handlers: SysTick. PendSV and Debug Monitor"
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hexmask.long.byte 0x20 24.--31. 1. "PRI_15,Priority of system handler 15"
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hexmask.long.byte 0x20 16.--23. 1. "PRI_14,Priority of system handler 14"
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hexmask.long.byte 0x20 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x20 0.--7. 1. "PRI_12,Priority of system handler 12"
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line.long 0x24 "SHCSR,System Handler Control and StateThis register is used to enable or disable the system handlers. determine the pending status of bus fault. mem manage fault. and SVC. determine the active status of the system handlers"
|
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hexmask.long.word 0x24 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
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bitfld.long 0x24 18. "USGFAULTENA,Usage fault system handler enable" "Exception disabled,Exception enabled"
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bitfld.long 0x24 17. "BUSFAULTENA,Bus fault system handler enable" "Exception disabled,Exception enabled"
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bitfld.long 0x24 16. "MEMFAULTENA,MemManage fault system handler enable" "Exception disabled,Exception enabled"
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rbitfld.long 0x24 15. "SVCALLPENDED,SVCall pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 14. "BUSFAULTPENDED,BusFault pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 13. "MEMFAULTPENDED,MemManage exception pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 12. "USGFAULTPENDED,Usage fault pending" "Exception is not active,Exception is pending."
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bitfld.long 0x24 11. "SYSTICKACT,SysTick active" "Not active,Active"
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bitfld.long 0x24 10. "PENDSVACT,PendSV" "Not active,Active"
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rbitfld.long 0x24 9. "RESERVED9,Software should not rely on the value of a reserved" "0,1"
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rbitfld.long 0x24 8. "MONITORACT,Debug monitor active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 7. "SVCALLACT,SVCall active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 4.--6. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 3. "USGFAULTACT,UsageFault exception active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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rbitfld.long 0x24 1. "BUSFAULTACT,BusFault exception active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 0. "MEMFAULTACT,MemManage exception active" "Exception is not active,Exception is active"
|
|
line.long 0x28 "CFSR,Configurable Fault StatusThis register is used to obtain information about local faults"
|
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bitfld.long 0x28 26.--31. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 25. "DIVBYZERO,When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0 this fault occurs The instruction is executed and the return PC points to it" "0,1"
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bitfld.long 0x28 24. "UNALIGNED,When CCR.UNALIGN_TRP is enabled and there is an attempt to make an unaligned memory access then this fault occurs" "0,1"
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bitfld.long 0x28 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 19. "NOCP,Attempt to use a coprocessor instruction" "0,1"
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bitfld.long 0x28 18. "INVPC,Attempt to load EXC_RETURN into PC illegally" "0,1"
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bitfld.long 0x28 17. "INVSTATE,Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state)" "0,1"
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bitfld.long 0x28 16. "UNDEFINSTR,This bit is set when the processor attempts to execute an undefined instruction" "0,1"
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bitfld.long 0x28 15. "BFARVALID,This bit is set if the Bus Fault Address Register (BFAR) contains a valid address" "0,1"
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bitfld.long 0x28 13.--14. "RESERVED13,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x28 12. "STKERR,Stacking from exception has caused one or more bus faults" "0,1"
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bitfld.long 0x28 11. "UNSTKERR,Unstack from exception return has caused one or more bus faults" "0,1"
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bitfld.long 0x28 10. "IMPRECISERR,Imprecise data bus error" "0,1"
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bitfld.long 0x28 9. "PRECISERR,Precise data bus error return" "0,1"
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bitfld.long 0x28 8. "IBUSERR,Instruction bus error flag" "0,1"
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bitfld.long 0x28 7. "MMARVALID,Memory Manage Address Register (MMFAR) address valid flag" "0,1"
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bitfld.long 0x28 5.--6. "RESERVED5,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x28 4. "MSTKERR,Stacking from exception has caused one or more access violations" "0,1"
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bitfld.long 0x28 3. "MUNSTKERR,Unstack from exception return has caused one or more access violations" "0,1"
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bitfld.long 0x28 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x28 1. "DACCVIOL,Data access violation flag" "0,1"
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bitfld.long 0x28 0. "IACCVIOL,Instruction access violation flag" "0,1"
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line.long 0x2C "HFSR,Hard Fault StatusThis register is used to obtain information about events that activate the Hard Fault handler"
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bitfld.long 0x2C 31. "DEBUGEVT,This bit is set if there is a fault related to debug" "0,1"
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newline
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bitfld.long 0x2C 30. "FORCED,Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled" "0,1"
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hexmask.long 0x2C 2.--29. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x2C 1. "VECTTBL,This bit is set if there is a fault because of vector table read on exception processing (Bus Fault)" "0,1"
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bitfld.long 0x2C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x30 "DFSR,Debug Fault StatusThis register is used to monitor external debug requests. vector catches. data watchpoint match. BKPT instruction execution. halt requests"
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|
hexmask.long 0x30 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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bitfld.long 0x30 4. "EXTERNAL,External debug request flag" "External debug request signal not asserted,External debug request signal asserted"
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bitfld.long 0x30 3. "VCATCH,Vector catch flag" "No vector catch occurred,Vector catch occurred"
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bitfld.long 0x30 2. "DWTTRAP,Data Watchpoint and Trace (DWT) flag" "No DWT match,DWT match"
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bitfld.long 0x30 1. "BKPT,BKPT flag" "No BKPT instruction execution,BKPT instruction execution"
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bitfld.long 0x30 0. "HALTED,Halt request flag" "No halt request,Halt requested by NVIC including step"
|
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line.long 0x34 "MMFAR,Mem Manage Fault AddressThis register is used to read the address of the location that caused a Memory Manage Fault"
|
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line.long 0x38 "BFAR,Bus Fault AddressThis register is used to read the address of the location that generated a Bus Fault"
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line.long 0x3C "AFSR,Auxiliary Fault StatusThis register is used to determine additional system fault information to software"
|
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line.long 0x40 "ID_PFR0,Processor Feature 0"
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|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x40 4.--7. "STATE1,State1 (T-bit ==" "N/A,N/A,Thumb-2 encoding with the 16-bit basic..,Thumb-2 encoding with all Thumb-2 basic..,?..."
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bitfld.long 0x40 0.--3. "STATE0,State0 (T-bit ==" "No ARM..,N/A,?..."
|
|
line.long 0x44 "ID_PFR1,Processor Feature 1"
|
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hexmask.long.tbyte 0x44 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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bitfld.long 0x44 8.--11. "MICROCONTROLLER_PROGRAMMERS_MODEL,Microcontroller programmer's model0x0: Not supported0x2: Two-stack support" "Not supported,?,Two-stack support,?..."
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hexmask.long.byte 0x44 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x48 "ID_DFR0,Debug Feature 0This register provides a high level view of the debug system"
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hexmask.long.byte 0x48 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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bitfld.long 0x48 20.--23. "MICROCONTROLLER_DEBUG_MODEL,Microcontroller Debug Model - memory mapped0x0: Not supported0x1: Microcontroller debug v1 (ITMv1 and DWTv1)" "Not supported,Microcontroller debug v1 (ITMv1 and..,?..."
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hexmask.long.tbyte 0x48 0.--19. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x4C "ID_AFR0,Auxiliary Feature 0This register provides some freedom for implementation defined features to be registered"
|
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repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
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rgroup.long ($2+0xD50)++0x03
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line.long 0x00 "ID_MMFR$1,Memory Model Feature 0General information on the memory model and memory management support"
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repeat.end
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature 2General information on the memory model and memory management support"
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hexmask.long.byte 0x00 25.--31. 1. "RESERVED28,Software should not rely on the value of a reserved"
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bitfld.long 0x00 24. "WAIT_FOR_INTERRUPT_STALLING,wait for interrupt stalling0x0: Not supported0x1: Wait for interrupt supported" "Not supported,Wait for interrupt supported"
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hexmask.long.tbyte 0x00 0.--23. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
repeat 5. (list 0. 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0xD60)++0x03
|
|
line.long 0x00 "ID_ISAR$1,ISA Feature 0Information on the instruction set attributes register"
|
|
repeat.end
|
|
group.long 0xD88++0x03
|
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line.long 0x00 "CPACR,Coprocessor Access ControlThis register specifies the access privileges for coprocessors"
|
|
rgroup.long 0xD90++0x2B
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line.long 0x00 "MPU_TYPE,MPU TypeThis register indicates many regions the MPU supports"
|
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hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Reads 0"
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hexmask.long.byte 0x00 16.--23. 1. "IREGION,The processor core uses only a unified MPU this field always reads 0x0"
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hexmask.long.byte 0x00 8.--15. 1. "DREGION,Number of supported MPU regions field"
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hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Reads 0"
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bitfld.long 0x00 0. "SEPARATE,The processor core uses only a unified MPU thus this field is always 0" "0,1"
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line.long 0x04 "MPU_CTRL,MPU ControlThis register is used to enable the MPU. enable the default memory map (background region). and enable the MPU when in Hard Fault. Non-maskable Interrupt (NMI). and FAULTMASK escalated handlers"
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hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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bitfld.long 0x04 2. "PRIVDEFENA,This bit enables the default memory map for privileged access as a background region when the MPU is enabled" "0,1"
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bitfld.long 0x04 1. "HFNMIENA,This bit enables the MPU when in Hard Fault NMI and FAULTMASK escalated handlers" "0,1"
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bitfld.long 0x04 0. "ENABLE,Enable MPU0: MPU disabled1: MPU enabled" "MPU disabled,MPU enabled"
|
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line.long 0x08 "MPU_RNR,MPU Region NumberThis register is used to select which protection region is accessed"
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hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x08 0.--7. 1. "REGION,Region select field"
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line.long 0x0C "MPU_RBAR,MPU Region Base AddressThis register writes the base address of a region"
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hexmask.long 0x0C 5.--31. 1. "ADDR,Region base address field"
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newline
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bitfld.long 0x0C 4. "VALID,MPU region number valid:0: MPU_RNR remains unchanged and is interpreted.1: MPU_RNR is overwritten by REGION" "MPU_RNR remains unchanged and is interpreted,MPU_RNR is overwritten by REGION"
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newline
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bitfld.long 0x0C 0.--3. "REGION,MPU region override field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x10 "MPU_RASR,MPU Region Attribute and SizeThis register controls the MPU access permissions"
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bitfld.long 0x10 29.--31. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x10 28. "XN,Instruction access disable:0: Enable instruction" "Enable instruction fetches,Disable instruction fetches"
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bitfld.long 0x10 27. "RESERVED27,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x10 24.--26. "AP,Data access permission:0x0: Priviliged permissions: No access" "Priviliged permissions,Priviliged permissions,Priviliged permissions,Priviliged permissions,Reserved,Priviliged permissions,Priviliged permissions,Priviliged permissions"
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bitfld.long 0x10 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x10 19.--21. "TEX,Type extension" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x10 18. "S,Shareable bit:0: Not shareable1: Shareable" "Not shareable,Shareable"
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newline
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bitfld.long 0x10 17. "C,Cacheable bit:0: Not" "Not cacheable,Cacheable"
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bitfld.long 0x10 16. "B,Bufferable bit:0: Not bufferable1: Bufferable" "Not bufferable,Bufferable"
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newline
|
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hexmask.long.byte 0x10 8.--15. 1. "SRD,Sub-Region Disable field:Setting a bit in this field disables the corresponding sub-region"
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bitfld.long 0x10 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
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bitfld.long 0x10 1.--5. "SIZE,MPU Protection Region Size" "?,?,?,?,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
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newline
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bitfld.long 0x10 0. "ENABLE,Region enable bit:0: Disable region" "Disable region,Enable region"
|
|
line.long 0x14 "MPU_RBAR_A1,MPU Alias 1 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x18 "MPU_RASR_A1,MPU Alias 1 Region Attribute and SizeAlias for MPU_RASR"
|
|
line.long 0x1C "MPU_RBAR_A2,MPU Alias 2 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x20 "MPU_RASR_A2,MPU Alias 2 Region Attribute and SizeAlias for MPU_RASR"
|
|
line.long 0x24 "MPU_RBAR_A3,MPU Alias 3 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x28 "MPU_RASR_A3,MPU Alias 3 Region Attribute and SizeAlias for MPU_RASR"
|
|
group.long 0xDF0++0x0F
|
|
line.long 0x00 "DHCSR,Debug Halting Control and StatusThe purpose of this register is to provide status information about the state of the processor. enable core debug. halt and step the processor"
|
|
bitfld.long 0x00 26.--31. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 25. "S_RESET_ST,Indicates that the core has been reset or is now being reset since the last time this bit was" "0,1"
|
|
newline
|
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bitfld.long 0x00 24. "S_RETIRE_ST,Indicates that an instruction has completed since last" "0,1"
|
|
newline
|
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bitfld.long 0x00 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 19. "S_LOCKUP,Reads as one if the core is running (not halted) and a lockup condition is present.When writing to this register 1 must be written this bit-field otherwise the write operation is ignored and no bits are written into the register" "0,1"
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newline
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bitfld.long 0x00 18. "S_SLEEP,Indicates that the core is sleeping (WFI WFE or **SLEEP-ON-EXIT**)" "0,1"
|
|
newline
|
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bitfld.long 0x00 17. "S_HALT,The core is in debug state when this bit is set.When writing to this register 1 must be written this bit-field otherwise the write operation is ignored and no bits are written into the register" "0,1"
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|
newline
|
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bitfld.long 0x00 16. "S_REGRDY,Register Read/Write on the Debug Core Register Selector register is available" "0,1"
|
|
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|
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hexmask.long.word 0x00 6.--15. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 5. "C_SNAPSTALL,If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "RESERVED4,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "C_MASKINTS,Mask interrupts when stepping or running in halted debug" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "C_STEP,Steps the core in halted debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "C_HALT,Halts the core" "0,1"
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|
newline
|
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bitfld.long 0x00 0. "C_DEBUGEN,Enables debug" "0,1"
|
|
line.long 0x04 "DCRSR,Deubg Core Register SelectorThe purpose of this register is to select the processor register to transfer data to or from"
|
|
hexmask.long.word 0x04 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 16. "REGWNR," "0,1"
|
|
newline
|
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hexmask.long.word 0x04 5.--15. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "REGSEL,Register select0x00: R00x01: R10x02: R20x03: R30x04: R40x05: R50x06: R60x07: R70x08: R80x09: R90x0A: R100x0B: R110x0C: R120x0D: Current SP0x0E: LR0x0F" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,XPSR/flags..,MSP (Main SP),PSP (Process SP),?,CONTROL<<24 |..,?..."
|
|
line.long 0x08 "DCRDR,Debug Core Register Data"
|
|
line.long 0x0C "DEMCR,Debug Exception and Monitor ControlThe purpose of this register is vector catching and debug monitor control"
|
|
hexmask.long.byte 0x0C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 24. "TRCENA,This bit must be set to 1 to enable use of the trace and debug blocks: DWT ITM ETM and TPIU" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 19. "MON_REQ,This enables the monitor to identify how it wakes up" "Woken up by debug exception,Woken up by MON_PEND"
|
|
newline
|
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bitfld.long 0x0C 18. "MON_STEP,When MON_EN = 1 this steps the core" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 17. "MON_PEND,Pend the monitor to activate when priority permits" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. "MON_EN,Enable the debug monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 11.--15. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 10. "VC_HARDERR,Debug trap on Hard Fault" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "VC_INTERR,Debug trap on a fault occurring during an exception entry or return sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "VC_BUSERR,Debug Trap on normal Bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 7. "VC_STATERR,Debug trap on Usage Fault state errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "VC_CHKERR,Debug trap on Usage Fault enabled checking errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "VC_NOCPERR,Debug trap on a UsageFault access to a Coprocessor" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "VC_MMERR,Debug trap on Memory Management faults" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0C 0. "VC_CORERESET,Reset Vector Catch" "0,1"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID field"
|
|
group.long 0xF34++0x13
|
|
line.long 0x00 "FPCCR,Floating Point Context ControlThis register holds control data for the floating-point unit"
|
|
bitfld.long 0x00 31. "ASPEN,Automatic State Preservation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "LSPEN,Lazy State Preservation enable" "Disable automatic lazy state preservation for..,Enable automatic lazy state preservation for.."
|
|
newline
|
|
hexmask.long.tbyte 0x00 9.--29. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "MONRDY,Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending.0: DebugMonitor is disabled or priority did not permit setting DEMCR.MON_PEND when the.." "DebugMonitor is disabled or priority did not..,DebugMonitor is enabled and priority permits.."
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "BFRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending.0: BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when.." "BusFault is disabled or priority did not permit..,BusFault is enabled and priority permitted.."
|
|
newline
|
|
bitfld.long 0x00 5. "MMRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending.0: MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when.." "MemManage is disabled or priority did not permit..,MemManage is enabled and priority permitted.."
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|
newline
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bitfld.long 0x00 4. "HFRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending.0: Priority did not permit setting the HardFault handler to the pending state when the floating-point stack.." "Priority did not permit setting the HardFault..,Priority permitted setting the HardFault handler.."
|
|
newline
|
|
bitfld.long 0x00 3. "THREAD,Indicates the processor mode was Thread when it allocated the FP stack frame.0: Mode was not Thread Mode when the floating-point stack frame was allocated.1: Mode was Thread Mode when the floating-point stack frame was allocated" "Mode was not Thread Mode when the floating-point..,Mode was Thread Mode when the floating-point.."
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "USER,Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame:0: Privilege level was not user when the floating-point stack frame was allocated.1: Privilege level was user when the.." "Privilege level was not user when the..,Privilege level was user when the floating-point.."
|
|
newline
|
|
bitfld.long 0x00 0. "LSPACT,Indicates whether Lazy preservation of the FP state is active:0: Lazy state preservation is not active.1: Lazy state preservation is active" "Lazy state preservation is not active,Lazy state preservation is active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address This register holds the location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
hexmask.long 0x04 2.--31. 1. "ADDRESS,Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
line.long 0x08 "FPDSCR,Floating Point Default Status ControlThis register holds the default values for the floating-point status control data that the processor assigns to the FPSCR when it creates a new floating-point context"
|
|
bitfld.long 0x08 27.--31. "RESERVED27,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x08 26. "AHP,Default value for Alternative Half Precision bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. "DN,Default value for Default NaN mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 24. "FZ,Default value for Flush-to-Zero mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22.--23. "RMODE,Default value for Rounding Mode control field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--21. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "MVFR0,Media and FP Feature 0Describes the features provided by the Floating-point extension"
|
|
bitfld.long 0x0C 28.--31. "FP_ROUNDING_MODES,Indicates the rounding modes supported by the FP floating-point hardware" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 24.--27. "SHORT_VECTORS,Indicates the hardware support for FP short vectors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x0C 20.--23. "SQUARE_ROOT,Indicates the hardware support for FP square root operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x0C 16.--19. "DIVIDE,Indicates the hardware support for FP divide operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x0C 12.--15. "FP_EXCEPTION_TRAPPING,Indicates whether the FP hardware implementation supports exception trapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x0C 8.--11. "DOUBLE_PRECISION,Indicates the hardware support for FP double-precision operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 4.--7. "SINGLE_PRECISION,Indicates the hardware support for FP single-precision operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "A_SIMD,Indicates the size of the FP register bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "MVFR1,Media and FP Feature 1Describes the features provided by the Floating-point extension"
|
|
bitfld.long 0x10 28.--31. "FP_FUSED_MAC,Indicates whether the FP supports fused multiply accumulate operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 24.--27. "FP_HPFP,Indicates whether the FP supports half-precision floating-point conversion operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
|
hexmask.long.word 0x10 8.--23. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 4.--7. "D_NAN_MODE,Indicates whether the FP hardware implementation supports only the Default NaN mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x10 0.--3. "FTZ_MODE,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_TIPROP"
|
|
base ad:0xE00FE000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RESERVED000,Software should not rely on the value of a reserved"
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "TRACECLKMUX,Internal"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x00 0. "TRACECLK_N_SWV,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
tree.end
|
|
tree "CPU_TPIU"
|
|
base ad:0xE0040000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "SSPSR,Supported Sync Port SizesThis register represents a single port size that is supported on the device. that is. 4. 2 or 1"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "FOUR,4-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 2. "THREE,3-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 1. "TWO,2-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 0. "ONE,1-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
line.long 0x04 "CSPSR,Current Sync Port SizeThis register has the same format as SSPSR but only one bit can be set. and all others must be zero"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 3. "FOUR,4-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "THREE,3-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
bitfld.long 0x04 1. "TWO,2-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "ONE,1-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ACPR,Async Clock PrescalerThis register scales the baud rate of the asynchronous output"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x00 0.--12. 1. "PRESCALER,Divisor for input trace clock is (PRESCALER + 1)"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "SPPR,Selected Pin ProtocolThis register selects the protocol to be used for trace output"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--1. "PROTOCOL,Trace output protocol" "TracePort mode,SerialWire Output (Manchester). This is the..,SerialWire Output (NRZ),?"
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "FFSR,Formatter and Flush Status"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "FTNONSTOP," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RESERVED0,This field always reads as zero" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FFCR,Formatter and Flush ControlWhen one of the two single wire output (SWO) modes is selected. ENFCONT enables the formatter to be bypassed"
|
|
hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "TRIGIN,Indicates that triggers are inserted when a trigger pin is asserted" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 1. "ENFCONT,Enable continuous formatting:0: Continuous formatting disabled1: Continuous formatting enabled" "Continuous formatting disabled,Continuous formatting enabled"
|
|
newline
|
|
bitfld.long 0x04 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x08 "FSCR,Formatter Synchronization Counter"
|
|
rgroup.long 0xFA0++0x03
|
|
line.long 0x00 "CLAIMMASK,Claim Tag Mask"
|
|
wgroup.long 0xFA0++0x07
|
|
line.long 0x00 "CLAIMSET,Claim Tag Set"
|
|
line.long 0x04 "CLAIMTAG,Current Claim Tag"
|
|
wgroup.long 0xFA4++0x03
|
|
line.long 0x00 "CLAIMCLR,Claim Tag Clear"
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVID,Device ID"
|
|
tree.end
|
|
tree.end
|
|
tree "CRYPTO"
|
|
base ad:0x40024000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DMACH0CTL,Channel 0 ControlThis register is used for channel enabling and priority selection"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "PRIO,Channel priority0: Low1: HighIf both channels have the same priority access of the channels to the external port is arbitrated using the round robin scheme" "Low,HighIf.."
|
|
newline
|
|
bitfld.long 0x00 0. "EN,Channel enable0: Disabled1: EnableNote: Disabling an active channel interrupts the DMA operation" "Disabled,Enable"
|
|
line.long 0x04 "DMACH0EXTADDR,Channel 0 External Address"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMACH0LEN,Channel 0 DMA Length"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DMALEN,Channel DMA length in bytesDuring configuration this register contains the DMA transfer length in bytes"
|
|
rgroup.long 0x18++0x0F
|
|
line.long 0x00 "DMASTAT,DMAC StatusThis register provides the actual state of each DMA channel"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 17. "PORT_ERR,Reflects possible transfer errors on the AHB port" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--16. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_ACT,A value of 1 indicates that channel 1 is active (DMA transfer on-going)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CH0_ACT,A value of 1 indicates that channel 0 is active (DMA transfer on-going)" "0,1"
|
|
line.long 0x04 "DMASWRESET,DMAC Software ResetSoftware reset is used to reset the DMAC to stop all transfers and clears the port error status register"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "SWRES,Software reset enable0 : Disabled1 : Enabled (self-cleared to 0)Completion of the software reset must be checked through the DMASTAT" "Disabled,Enabled (self-cleared.."
|
|
line.long 0x08 "DMACH1CTL,Channel 1 ControlThis register is used for channel enabling and priority selection"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "PRIO,Channel priority0: Low1: HighIf both channels have the same priority access of the channels to the external port is arbitrated using the round robin scheme" "Low,HighIf.."
|
|
newline
|
|
bitfld.long 0x08 0. "EN,Channel enable0: Disabled1: EnableNote: Disabling an active channel interrupts the DMA operation" "Disabled,Enable"
|
|
line.long 0x0C "DMACH1EXTADDR,Channel 1 External Address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMACH1LEN,Channel 1 DMA Length"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DMALEN,Channel DMA length in bytes.During configuration this register contains the DMA transfer length in bytes"
|
|
group.long 0x78++0x07
|
|
line.long 0x00 "DMABUSCFG,DMAC Master Run-time ParametersThis register defines all the run-time parameters for the AHB master interface port"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "AHB_MST1_BURST_SIZE,Maximum burst size that can be performed on the AHB bus" "?,?,4 bytes,8 bytes ,16 bytes ,32 bytes ,64 bytes ,?,?,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x00 11. "AHB_MST1_IDLE_EN,Idle insertion between consecutive burst transfers on AHB" "Do not insert idle transfers.,Idle transfer insertion enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "AHB_MST1_INCR_EN,Burst length type of AHB transfer" "Unspecified length burst transfers,Fixed length bursts or single transfers"
|
|
newline
|
|
bitfld.long 0x00 9. "AHB_MST1_LOCK_EN,Locked transform on AHB" "Transfers are not locked,Transfers are locked"
|
|
newline
|
|
bitfld.long 0x00 8. "AHB_MST1_BIGEND,Endianess for the AHB master" "Little Endian,Big Endian"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "DMAPORTERR,DMAC Port Error Raw StatusThis register provides the actual status of individual port errors"
|
|
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 12. "PORT1_AHB_ERROR,A value of 1 indicates that the EIP-101 has detected an AHB bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 9. "PORT1_CHANNEL,Indicates which channel has serviced last (channel 0 or channel 1) by AHB master port" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 0.--8. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "DMAHWVER,DMAC VersionThis register contains an indication (or signature) of the EIP type of this DMAC. as well as the hardware version/patch numbers"
|
|
bitfld.long 0x00 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "HW_MAJOR_VERSION,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "HW_MINOR_VERSION,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HW_PATCH_LEVEL,Patch levelStarts at 0 at first delivery of this version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "EIP_NUMBER_COMPL,Bit-by-bit complement of the EIP_NUMBER field bits"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EIP_NUMBER,Binary encoding of the EIP-number of this DMA controller (209)"
|
|
group.long 0x400++0x0F
|
|
line.long 0x00 "KEYWRITEAREA,Key Store Write AreaThis register defines where the keys should be written in the key store RAM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "RAM_AREA7,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA7 is not selected to be written.1: RAM_AREA7 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA7 is not selected to be written,RAM_AREA7 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 6. "RAM_AREA6,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA6 is not selected to be written.1: RAM_AREA6 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA6 is not selected to be written,RAM_AREA6 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 5. "RAM_AREA5,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA5 is not selected to be written.1: RAM_AREA5 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA5 is not selected to be written,RAM_AREA5 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 4. "RAM_AREA4,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA4 is not selected to be written.1: RAM_AREA4 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA4 is not selected to be written,RAM_AREA4 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 3. "RAM_AREA3,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA3 is not selected to be written.1: RAM_AREA3 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA3 is not selected to be written,RAM_AREA3 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 2. "RAM_AREA2,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA2 is not selected to be written.1: RAM_AREA2 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA2 is not selected to be written,RAM_AREA2 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 1. "RAM_AREA1,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA1 is not selected to be written.1: RAM_AREA1 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA1 is not selected to be written,RAM_AREA1 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 0. "RAM_AREA0,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA0 is not selected to be written.1: RAM_AREA0 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA0 is not selected to be written,RAM_AREA0 is selected to be written.Writing to.."
|
|
line.long 0x04 "KEYWRITTENAREA,Key Store Written AreaThis register shows which areas of the key store RAM contain valid written keys.When a new key needs to be written to the key store. on a location that is already occupied by a valid key. this key area must be.."
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 7. "RAM_AREA_WRITTEN7,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
|
|
newline
|
|
bitfld.long 0x04 6. "RAM_AREA_WRITTEN6,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
|
|
newline
|
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bitfld.long 0x04 5. "RAM_AREA_WRITTEN5,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 4. "RAM_AREA_WRITTEN4,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 3. "RAM_AREA_WRITTEN3,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 2. "RAM_AREA_WRITTEN2,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 1. "RAM_AREA_WRITTEN1,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 0. "RAM_AREA_WRITTEN0,On read this bit returns the key area written status.This bit can be reset by writing a" "0,1"
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line.long 0x08 "KEYSIZE,Key Store SizeThis register defines the size of the keys that are written with DMA"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x08 0.--1. "SIZE,Key size:00: ReservedWhen writing this to this register the KEY_STORE_WRITTEN_AREA register is reset" "?,128 bits,192 bits,256 bits"
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line.long 0x0C "KEYREADAREA,Key Store Read AreaThis register selects the key store RAM area from where the key needs to be read that will be used for an AES operation"
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bitfld.long 0x0C 31. "BUSY,Key store operation busy status flag (read only):0: Operation is complete.1: Operation is not completed and the key store is busy" "Operation is complete,Operation is not completed and the key store is.."
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hexmask.long 0x0C 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 0.--3. "RAM_AREA,Selects the area of the key store RAM from where the key needs to be read that will be writen to the AES engineRAM_AREA:RAM areas RAM_AREA0 RAM_AREA2 RAM_AREA4 and RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes.Only RAM.." "RAM Area 0,RAM Area 1,RAM Area 2,RAM Area 3,RAM Area 4,RAM Area 5,RAM Area 6,RAM Area 7,No RAM,?,?,?,?,?,?,?"
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wgroup.long 0x500++0x03
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line.long 0x00 "AESKEY2,AES_KEY2_0 / AES_GHASH_H_IN_0Second Key / GHASH Key (internal. but clearable)The following registers are not accessible through the host for reading and writing"
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wgroup.long 0x510++0x03
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line.long 0x00 "AESKEY3,AES_KEY3_0 / AES_KEY2_4Third Key / Second Key (internal. but clearable)The following registers are not accessible through the host for reading and writing"
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group.long 0x540++0x03
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line.long 0x00 "AESIV,AES initialization vector registersThese registers are used to provide and read the IV from the AES engine"
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group.long 0x550++0x0F
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line.long 0x00 "AESCTL,AES ControlAES input/output buffer control and mode registerThis register specifies the AES mode of operation for the EIP-120t.Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0"
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rbitfld.long 0x00 31. "CONTEXT_READY,If 1 this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context" "0,1"
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bitfld.long 0x00 30. "SAVED_CONTEXT_RDY,If 1 this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the host to retrieve" "0,1"
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bitfld.long 0x00 29. "SAVE_CONTEXT,This bit indicates that an authentication TAG or result IV needs to be stored as a result context.Typically this bit must be set for authentication modes returning a TAG (CBC-MAC GCM and CCM) or for basic encryption modes that require.." "0,1"
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bitfld.long 0x00 28. "GCM_CCM_CONTINUE,Continue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase.Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation to continue processing from the.." "0,1"
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bitfld.long 0x00 27. "GET_DIGEST,Interrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation.Set this write-only signal to '1b' to interrupt GCM or CCM processing at the next full block (128 bits) boundary" "0,1"
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bitfld.long 0x00 26. "GCM_CCM_CONTINUE_AAD,Continue processing of an interrupted AES-GCM or AES-CCM operation in the AAD phase.Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation to continue processing from the next full.." "0,1"
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bitfld.long 0x00 25. "XCBC_MAC,Set to '1' to select AES-XCBC MAC mode.The direction bit must be set to '1' for this mode.Selecting this mode requires writing the length register" "0,1"
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bitfld.long 0x00 22.--24. "CCM_M,Defines M which indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one).Note: The EIP-120t always returns a 128-bit authentication field of which the M.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--21. "CCM_L,Defines L which indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18. "CCM,If set to 1 AES-CCM is selectedAES-CCM is a combined mode using AES for authentication and encryption.Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers.Note: The CTR mode bit in this register must.." "0,1"
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bitfld.long 0x00 16.--17. "GCM,Set these bits to 11 to select AES-GCM mode.AES-GCM is a combined mode using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption.Note: The CTR mode bit in this register must also be set to 1 to.." "No GCM mode,Reserved do not select,?..."
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bitfld.long 0x00 15. "CBC_MAC,Set to 1 to select AES-CBC MAC mode.The direction bit must be set to 1 for this mode.Selecting this mode requires writing the length register after all other registers" "0,1"
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bitfld.long 0x00 9.--14. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7.--8. "CTR_WIDTH,Specifies the counter width for AES-CTR mode00 = 32-bit counter01 = 64-bit counter10 = 96-bit counter11 = 128-bit counter" "32-bit counter,64-bit counter,?..."
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bitfld.long 0x00 6. "CTR,If set to 1 AES counter mode (CTR) is selected.Note: This bit must also be set for GCM and CCM when encryption/decryption is required" "0,1"
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bitfld.long 0x00 5. "CBC,If set to 1 cipher-block-chaining (CBC) mode is selected" "0,1"
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bitfld.long 0x00 3.--4. "KEY_SIZE,This read-only field specifies the key size.The key size is automatically configured when a new key is loaded through the key store module.00 = N/A - Reserved01 =" "N/A - Reserved,128-bit,?..."
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bitfld.long 0x00 2. "DIR,If set to 1 an encrypt operation is performed.If set to 0 a decrypt operation is performed.This bit must be written with a 1 when CBC-MAC is selected" "0,1"
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bitfld.long 0x00 1. "INPUT_READY,If 1 this status bit indicates that the 16-byte AES input buffer is empty" "0,1"
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bitfld.long 0x00 0. "OUTPUT_READY,If 1 this status bit indicates that an AES output block is available to be retrieved by the host.Writing 0 clears the bit to 0 and indicates that output data is read by the host" "0,1"
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line.long 0x04 "AESDATALEN0,AES Crypto Length 0 (LSW)These registers are used to write the Length values to the EIP-120t"
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line.long 0x08 "AESDATALEN1,AES Crypto Length 1 (MSW)These registers are used to write the Length values to the EIP-120t"
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bitfld.long 0x08 29.--31. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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hexmask.long 0x08 0.--28. 1. "C_LENGTH,C_LENGTH[60:32]Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes"
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line.long 0x0C "AESAUTHLEN,AES Authentication Length"
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repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
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rgroup.long ($2+0x560)++0x03
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line.long 0x00 "AESDATAOUT$1,Data Input/Output"
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repeat.end
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repeat 2. (list 0. 1. )(list 0x00 0x04 )
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wgroup.long ($2+0x560)++0x03
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line.long 0x00 "AESDATAIN$1,AES Data Input_Output 0The data registers are typically accessed through the DMA and not with host writes and/or reads"
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repeat.end
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wgroup.long 0x568++0x0B
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line.long 0x00 "AESDATAIN2,AES Data Input_Output 2The data registers are typically accessed via DMA and not with host writes and/or reads"
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line.long 0x04 "AESDATAIN3,AES Data Input_Output 3The data registers are typically accessed via DMA and not with host writes and/or reads"
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line.long 0x08 "AESTAGOUT,AES Tag Out 0The tag registers can be accessed via DMA or directly with host reads.These registers buffer the TAG from the EIP-120t"
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group.long 0x5D4++0x0B
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line.long 0x00 "AESCCMALNWRD,This register needs to be read and stored when an AES-CCM operation is interrupted"
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line.long 0x04 "AESBLKCNT0,This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations"
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line.long 0x08 "AESBLKCNT1,This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations"
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hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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hexmask.long 0x08 0.--24. 1. "AES_BLK_CNT_56_32,[56:32] of Internal block counter for AES GCM and CCM operations.These bits read the block count value that represents the number of blocks to go"
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repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
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wgroup.long ($2+0x604)++0x03
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line.long 0x00 "HASHDATAIN$1,HASH Data Input 1The data input registers should be used to provide input data to the hash module through the slave interface"
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repeat.end
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repeat 15. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
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wgroup.long ($2+0x644)++0x03
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line.long 0x00 "HASHDATAIN$1,HASH Data Input 17The data input registers should be used to provide input data to the hash module through the slave interface"
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repeat.end
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group.long 0x680++0x0F
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line.long 0x00 "HASHIOBUFCTRL,HASH Input_Output Buffer ControlThis register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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bitfld.long 0x00 7. "PAD_DMA_MESSAGE,Note: This bit must only be used when data is supplied through the DMA" "0,1"
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bitfld.long 0x00 6. "GET_DIGEST,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 5. "PAD_MESSAGE,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 3.--4. "RESERVED3,Write 0s and ignore on reading" "0,1,2,3"
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bitfld.long 0x00 2. "RFD_IN,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 1. "DATA_IN_AV,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 0. "OUTPUT_FULL,Indicates that the output buffer registers (HASHDIGESTn) are available for reading by the host.When this bit reads 0 the output buffer registers are released; the hash engine is allowed to write new data to it" "0,1"
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line.long 0x04 "HASHMODE,HASH Mode"
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hexmask.long 0x04 7.--31. 1. "RESERVED7,Write 0s and ignore on reading"
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bitfld.long 0x04 6. "SHA384_MODE,The host must write this bit with 1 prior to processing a SHA 384 session" "0,1"
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bitfld.long 0x04 5. "SHA512_MODE,The host must write this bit with 1 prior to processing a SHA 512 session" "0,1"
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bitfld.long 0x04 4. "SHA224_MODE,The host must write this bit with 1 prior to processing a SHA 224 session" "0,1"
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bitfld.long 0x04 3. "SHA256_MODE,The host must write this bit with 1 prior to processing a SHA 256 session" "0,1"
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bitfld.long 0x04 1.--2. "RESERVED1,Write 0s and ignore on reading" "0,1,2,3"
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bitfld.long 0x04 0. "NEW_HASH,When set to 1 it indicates that the hash engine must start processing a new hash session" "0,1"
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line.long 0x08 "HASHINLENL,HASH Input Length LSB"
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line.long 0x0C "HASHINLENH,HASH Input Length MSB"
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group.long 0x6C0++0x47
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line.long 0x00 "HASHDIGESTA,HASH Digest AThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x04 "HASHDIGESTB,HASH Digest BThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x08 "HASHDIGESTC,HASH Digest CThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x0C "HASHDIGESTD,HASH Digest DThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x10 "HASHDIGESTE,HASH Digest EThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x14 "HASHDIGESTF,HASH Digest FThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x18 "HASHDIGESTG,HASH Digest GThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x1C "HASHDIGESTH,HASH Digest HThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x20 "HASHDIGESTI,HASH Digest IThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x24 "HASHDIGESTJ,HASH Digest JThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x28 "HASHDIGESTK,HASH Digest KThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x2C "HASHDIGESTL,HASH Digest LThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x30 "HASHDIGESTM,HASH Digest MThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x34 "HASHDIGESTN,HASH Digest NThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x38 "HASHDIGESTO,HASH Digest 0The hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x3C "HASHDIGESTP,HASH Digest PThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x40 "ALGSEL,Algorithm SelectThis algorithm selection register configures the internal destination of the DMA controller"
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bitfld.long 0x40 31. "TAG,If this bit is cleared to 0 the DMA operation involves only data.If this bit is set the DMA operation includes a TAG (Authentication Result / Digest).For SHA-256 operation a DMA must be set up for both input data and TAG" "0,1"
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hexmask.long 0x40 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
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bitfld.long 0x40 3. "HASH_SHA_512,If set to one selects the hash engine in 512B mode as destination for the DMAThe maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out.." "0,1"
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bitfld.long 0x40 2. "HASH_SHA_256,If set to one selects the hash engine in 256B mode as destination for the DMAThe maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out.." "0,1"
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bitfld.long 0x40 1. "AES,If set to one selects the AES engine as source/destination for the DMAThe read and write maximum transfer size to the DMA engine is set to 16 bytes" "0,1"
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bitfld.long 0x40 0. "KEY_STORE,If set to one selects the Key Store as destination for the DMAThe maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16 24 and 32 bytes are allowed)" "0,1"
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line.long 0x44 "DMAPROTCTL,DMA Protection ControlMaster PROT privileged access enableThis register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys.."
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hexmask.long 0x44 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x44 0. "PROT_EN,Select AHB transfer protection control for DMA transfers using the key store area as destination.0 : transfers use 'USER' type access.1 : transfers use 'PRIVILEGED' type access" "transfers use 'USER' type access,transfers use 'PRIVILEGED' type access"
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group.long 0x740++0x03
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line.long 0x00 "SWRESET,Software Reset"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "SW_RESET,If this bit is set to 1 the following modules are reset: - Master control internal state is reset" "0,1"
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group.long 0x780++0x13
|
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line.long 0x00 "IRQTYPE,Control Interrupt Configuration"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "LEVEL,If this bit is 0 the interrupt output is a pulse.If this bit is set to 1 the interrupt is a level interrupt that must be cleared by writing the interrupt clear register.This bit is applicable for both interrupt output signals" "0,1"
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line.long 0x04 "IRQEN,Control Interrupt Enable"
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hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 1. "DMA_IN_DONE,If this bit is set to 0 the DMA input done interrupt disabledIf this bit is set to 1 the DMA input done interrupt enabled." "0,1"
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newline
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bitfld.long 0x04 0. "RESULT_AVAIL,If this bit is set to 0 the Result Available interrupt is disabledIf this bit is set to 1 the Result Available interrupt is enabled." "0,1"
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line.long 0x08 "IRQCLR,Control Interrupt Clear"
|
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bitfld.long 0x08 31. "DMA_BUS_ERR,If 1 is written to this bit the DMA bus error status is cleared.Writing 0 has no effect" "0,1"
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newline
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bitfld.long 0x08 30. "KEY_ST_WR_ERR,If 1 is written to this bit the key store write error status is cleared.Writing 0 has no effect" "0,1"
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newline
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bitfld.long 0x08 29. "KEY_ST_RD_ERR,If 1 is written to this bit the key store read error status is cleared.Writing 0 has no effect" "0,1"
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newline
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hexmask.long 0x08 2.--28. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 1. "DMA_IN_DONE,If 1 is written to this bit the DMA in done interrupt status is cleared.Writing 0 has no effect.Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE)." "0,1"
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newline
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bitfld.long 0x08 0. "RESULT_AVAIL,If 1 is written to this bit the result available interrupt status is cleared.Writing 0 has no effect.Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE)." "0,1"
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line.long 0x0C "IRQSET,Control Interrupt Set"
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hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 1. "DMA_IN_DONE,If 1 is written to this bit the DMA data in done interrupt is set.Writing 0 has no effect.If the interrupt configuration register is programmed to pulse clearing the DMA data in done interrupt is not needed" "0,1"
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newline
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bitfld.long 0x0C 0. "RESULT_AVAIL,If 1 is written to this bit the result available interrupt is setWriting 0 has no effect.If the interrupt configuration register is programmed to pulse clearing the result available interrupt is not needed" "0,1"
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|
line.long 0x10 "IRQSTAT,Control Interrupt Status"
|
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bitfld.long 0x10 31. "DMA_BUS_ERR,This bit is set when a DMA bus error is detected during a DMA operation" "0,1"
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newline
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bitfld.long 0x10 30. "KEY_ST_WR_ERR,This bit is set when a write error is detected during the DMA write operation to the key store memory" "0,1"
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|
newline
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bitfld.long 0x10 29. "KEY_ST_RD_ERR,This bit is set when a read error is detected during the read of a key from the key store while copying it to the AES core" "0,1"
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newline
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hexmask.long 0x10 2.--28. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
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newline
|
|
bitfld.long 0x10 1. "DMA_IN_DONE,This read only bit returns the actual DMA data in done interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "RESULT_AVAIL,This read only bit returns the actual result available interrupt status" "0,1"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "HWVER,Hardware Version"
|
|
bitfld.long 0x00 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "HW_MAJOR_VER,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "HW_MINOR_VER,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HW_PATCH_LVL,Patch levelStarts at 0 at first delivery of this version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "VER_NUM_COMPL,These bits simply contain the complement of bits [7:0] (0x87) used by a driver to ascertain that the EIP-120t register is indeed"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VER_NUM,These bits encode the EIP number for the EIP-120t this field contains the value 120 (decimal) or 0x78"
|
|
tree.end
|
|
tree "EVENT"
|
|
base ad:0x40083000
|
|
rgroup.long 0x00++0xAB
|
|
line.long 0x00 "CPUIRQSEL0,Output Selection for CPU Interrupt 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x04 "CPUIRQSEL1,Output Selection for CPU Interrupt 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x08 "CPUIRQSEL2,Output Selection for CPU Interrupt 2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "CPUIRQSEL3,Output Selection for CPU Interrupt 3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "CPUIRQSEL4,Output Selection for CPU Interrupt 4"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "CPUIRQSEL5,Output Selection for CPU Interrupt 5"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "CPUIRQSEL6,Output Selection for CPU Interrupt 6"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "CPUIRQSEL7,Output Selection for CPU Interrupt 7"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "CPUIRQSEL8,Output Selection for CPU Interrupt 8"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "CPUIRQSEL9,Output Selection for CPU Interrupt 9"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x28 "CPUIRQSEL10,Output Selection for CPU Interrupt 10"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x2C "CPUIRQSEL11,Output Selection for CPU Interrupt 11"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x30 "CPUIRQSEL12,Output Selection for CPU Interrupt 12"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x34 "CPUIRQSEL13,Output Selection for CPU Interrupt 13"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x38 "CPUIRQSEL14,Output Selection for CPU Interrupt 14"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x3C "CPUIRQSEL15,Output Selection for CPU Interrupt 15"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x40 "CPUIRQSEL16,Output Selection for CPU Interrupt 16"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x44 "CPUIRQSEL17,Output Selection for CPU Interrupt 17"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x48 "CPUIRQSEL18,Output Selection for CPU Interrupt 18"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x4C "CPUIRQSEL19,Output Selection for CPU Interrupt 19"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x50 "CPUIRQSEL20,Output Selection for CPU Interrupt 20"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x54 "CPUIRQSEL21,Output Selection for CPU Interrupt 21"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x58 "CPUIRQSEL22,Output Selection for CPU Interrupt 22"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x5C "CPUIRQSEL23,Output Selection for CPU Interrupt 23"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x60 "CPUIRQSEL24,Output Selection for CPU Interrupt 24"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x64 "CPUIRQSEL25,Output Selection for CPU Interrupt 25"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x68 "CPUIRQSEL26,Output Selection for CPU Interrupt 26"
|
|
hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x68 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x6C "CPUIRQSEL27,Output Selection for CPU Interrupt 27"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x70 "CPUIRQSEL28,Output Selection for CPU Interrupt 28"
|
|
hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x70 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x74 "CPUIRQSEL29,Output Selection for CPU Interrupt 29"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x78 "CPUIRQSEL30,Output Selection for CPU Interrupt 30"
|
|
hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x78 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x7C "CPUIRQSEL31,Output Selection for CPU Interrupt 31"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x80 "CPUIRQSEL32,Output Selection for CPU Interrupt 32"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x84 "CPUIRQSEL33,Output Selection for CPU Interrupt 33"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x88 "CPUIRQSEL34,Output Selection for CPU Interrupt 34"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x8C "CPUIRQSEL35,Output Selection for CPU Interrupt 35"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x90 "CPUIRQSEL36,Output Selection for CPU Interrupt 36"
|
|
hexmask.long.tbyte 0x90 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x90 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x94 "CPUIRQSEL37,Output Selection for CPU Interrupt 37"
|
|
hexmask.long.tbyte 0x94 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x94 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x98 "CPUIRQSEL38,Output Selection for CPU Interrupt 38"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x9C "CPUIRQSEL39,Output Selection for CPU Interrupt 39"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA0 "CPUIRQSEL40,Output Selection for CPU Interrupt 40"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA4 "CPUIRQSEL41,Output Selection for CPU Interrupt 41"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA8 "CPUIRQSEL42,Output Selection for CPU Interrupt 42"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--7. 1. "EV,Read only selection value"
|
|
rgroup.long 0x100++0x27
|
|
line.long 0x00 "RFCSEL0,Output Selection for RFC Event 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x04 "RFCSEL1,Output Selection for RFC Event 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x08 "RFCSEL2,Output Selection for RFC Event 2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "RFCSEL3,Output Selection for RFC Event 3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "RFCSEL4,Output Selection for RFC Event 4"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "RFCSEL5,Output Selection for RFC Event 5"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "RFCSEL6,Output Selection for RFC Event 6"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "RFCSEL7,Output Selection for RFC Event 7"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "RFCSEL8,Output Selection for RFC Event 8"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "RFCSEL9,Output Selection for RFC Event 9"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "GPT0ACAPTSEL,Output Selection for GPT0 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT0BCAPTSEL,Output Selection for GPT0 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "GPT1ACAPTSEL,Output Selection for GPT1 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT1BCAPTSEL,Output Selection for GPT1 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "GPT2ACAPTSEL,Output Selection for GPT2 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT2BCAPTSEL,Output Selection for GPT2 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
rgroup.long 0x500++0x107
|
|
line.long 0x00 "UDMACH0SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "UDMACH0BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x08 "UDMACH1SSEL,Output Selection for DMA Channel 1 SREQ"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "UDMACH1BSEL,Output Selection for DMA Channel 1 REQ"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "UDMACH2SSEL,Output Selection for DMA Channel 2 SREQ"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "UDMACH2BSEL,Output Selection for DMA Channel 2 REQ"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "UDMACH3SSEL,Output Selection for DMA Channel 3 SREQ"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "UDMACH3BSEL,Output Selection for DMA Channel 3 REQ"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "UDMACH4SSEL,Output Selection for DMA Channel 4 SREQ"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "UDMACH4BSEL,Output Selection for DMA Channel 4 REQ"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x28 "UDMACH5SSEL,Output Selection for DMA Channel 5 SREQ"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x2C "UDMACH5BSEL,Output Selection for DMA Channel 5 REQ"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x30 "UDMACH6SSEL,Output Selection for DMA Channel 6 SREQ"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x34 "UDMACH6BSEL,Output Selection for DMA Channel 6 REQ"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x38 "UDMACH7SSEL,Output Selection for DMA Channel 7 SREQ"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x3C "UDMACH7BSEL,Output Selection for DMA Channel 7 REQ"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x40 "UDMACH8SSEL,Output Selection for DMA Channel 8 SREQSingle request is ignored for this channel"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x44 "UDMACH8BSEL,Output Selection for DMA Channel 8 REQ"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x48 "UDMACH9SSEL,Output Selection for DMA Channel 9 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x4C "UDMACH9BSEL,Output Selection for DMA Channel 9 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x50 "UDMACH10SSEL,Output Selection for DMA Channel 10 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x54 "UDMACH10BSEL,Output Selection for DMA Channel 10 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x58 "UDMACH11SSEL,Output Selection for DMA Channel 11 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x5C "UDMACH11BSEL,Output Selection for DMA Channel 11 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x60 "UDMACH12SSEL,Output Selection for DMA Channel 12 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x64 "UDMACH12BSEL,Output Selection for DMA Channel 12 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x68 "UDMACH13SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x6C "UDMACH13BSEL,Output Selection for DMA Channel 13 REQ"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x70 "UDMACH14SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x74 "UDMACH14BSEL,Output Selection for DMA Channel 14 REQ"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x78 "UDMACH15SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x7C "UDMACH15BSEL,Output Selection for DMA Channel 15 REQ"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x80 "UDMACH16SSEL,Output Selection for DMA Channel 16 SREQ"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x84 "UDMACH16BSEL,Output Selection for DMA Channel 16 REQ"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x88 "UDMACH17SSEL,Output Selection for DMA Channel 17 SREQ"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x8C "UDMACH17BSEL,Output Selection for DMA Channel 17 REQ"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x90 "UDMACH18SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x94 "UDMACH18BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x98 "UDMACH19SSEL,Output Selection for DMA Channel 19 SREQ"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x9C "UDMACH19BSEL,Output Selection for DMA Channel 19 REQ"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA0 "UDMACH20SSEL,Output Selection for DMA Channel 20 SREQ"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA4 "UDMACH20BSEL,Output Selection for DMA Channel 20 REQ"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA8 "UDMACH21SSEL,Output Selection for DMA Channel 21 SREQ"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xAC "UDMACH21BSEL,Output Selection for DMA Channel 21 REQ"
|
|
hexmask.long.tbyte 0xAC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xAC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB0 "UDMACH22SSEL,Output Selection for DMA Channel 22 SREQ"
|
|
hexmask.long.tbyte 0xB0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB4 "UDMACH22BSEL,Output Selection for DMA Channel 22 REQ"
|
|
hexmask.long.tbyte 0xB4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB8 "UDMACH23SSEL,Output Selection for DMA Channel 23 SREQ"
|
|
hexmask.long.tbyte 0xB8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xBC "UDMACH23BSEL,Output Selection for DMA Channel 23 REQ"
|
|
hexmask.long.tbyte 0xBC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC0 "UDMACH24SSEL,Output Selection for DMA Channel 24 SREQ"
|
|
hexmask.long.tbyte 0xC0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC4 "UDMACH24BSEL,Output Selection for DMA Channel 24 REQ"
|
|
hexmask.long.tbyte 0xC4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC8 "UDMACH25SSEL,Output Selection for DMA Channel 25 SREQ"
|
|
hexmask.long.tbyte 0xC8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xCC "UDMACH25BSEL,Output Selection for DMA Channel 25 REQ"
|
|
hexmask.long.tbyte 0xCC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD0 "UDMACH26SSEL,Output Selection for DMA Channel 26 SREQ"
|
|
hexmask.long.tbyte 0xD0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xD0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD4 "UDMACH26BSEL,Output Selection for DMA Channel 26 REQ"
|
|
hexmask.long.tbyte 0xD4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xD4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD8 "UDMACH27SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0xDC "UDMACH27BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0xE0 "UDMACH28SSEL,Output Selection for DMA Channel 28 SREQ"
|
|
hexmask.long.tbyte 0xE0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xE4 "UDMACH28BSEL,Output Selection for DMA Channel 28 REQ"
|
|
hexmask.long.tbyte 0xE4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xE8 "UDMACH29SSEL,Output Selection for DMA Channel 29 SREQ"
|
|
hexmask.long.tbyte 0xE8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xEC "UDMACH29BSEL,Output Selection for DMA Channel 29 REQ"
|
|
hexmask.long.tbyte 0xEC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xEC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF0 "UDMACH30SSEL,Output Selection for DMA Channel 30 SREQ"
|
|
hexmask.long.tbyte 0xF0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF4 "UDMACH30BSEL,Output Selection for DMA Channel 30 REQ"
|
|
hexmask.long.tbyte 0xF4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF8 "UDMACH31SSEL,Output Selection for DMA Channel 31 SREQ"
|
|
hexmask.long.tbyte 0xF8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xFC "UDMACH31BSEL,Output Selection for DMA Channel 31 REQ"
|
|
hexmask.long.tbyte 0xFC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xFC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x100 "GPT3ACAPTSEL,Output Selection for GPT3 0"
|
|
hexmask.long.tbyte 0x100 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x100 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x104 "GPT3BCAPTSEL,Output Selection for GPT3 1"
|
|
hexmask.long.tbyte 0x104 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x104 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "AUXSEL0,Output Selection for AUX Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "CM3NMISEL0,Output Selection for NMI Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "I2SSTMPSEL0,Output Selection for I2S Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "FRZSEL0,Output Selection for FRZ SubscriberThe halted debug signal is passed to peripherals such as the General Purpose Timer. Sensor Controller with Digital and Analog Peripherals (AUX). Radio. and RTC"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "SWEV,Set or Clear Software Events"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 24. "SWEV3,Writing '1' to this bit when the value is '0' triggers the Software 3 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "SWEV2,Writing '1' to this bit when the value is '0' triggers the Software 2 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "SWEV1,Writing '1' to this bit when the value is '0' triggers the Software 1 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "SWEV0,Writing '1' to this bit when the value is '0' triggers the Software 0 event" "0,1"
|
|
tree.end
|
|
tree "FCFG1"
|
|
base ad:0x50001000
|
|
repeat 4. (list 0. 4. 140. 324. )(list 0x00 0x04 0x150 0x324 )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "RESERVED_$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "MISC_CONF_1,Misc configurations"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DEVICE_MINOR_REV,HW minor revision number (a value of 0xFF shall be treated equally to 0x00).Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer.Value may change without warning"
|
|
line.long 0x04 "MISC_CONF_2,Internal"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "HPOSC_COMP_P3,Internal"
|
|
repeat 5. (list 5. 4. 3. 2. 1. )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0xB0)++0x03
|
|
line.long 0x00 "HPOSC_MEAS_$1,Internal"
|
|
hexmask.long.word 0x00 16.--31. 1. "HPOSC_D5,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "HPOSC_T5,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "HPOSC_DT5,Internal"
|
|
repeat.end
|
|
rgroup.long 0xC4++0x1B
|
|
line.long 0x00 "CONFIG_CC26_FE,Internal"
|
|
bitfld.long 0x00 28.--31. "IFAMP_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "LNA_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "IFAMP_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--18. "CTL_PA0_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13. "PATRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RSSITRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSSI_OFFSET,Internal"
|
|
line.long 0x04 "CONFIG_CC13_FE,Internal"
|
|
bitfld.long 0x04 28.--31. "IFAMP_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 24.--27. "LNA_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 19.--23. "IFAMP_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 14.--18. "CTL_PA0_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 13. "PATRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12. "RSSITRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8.--11. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "RSSI_OFFSET,Internal"
|
|
line.long 0x08 "CONFIG_RF_COMMON,Internal"
|
|
bitfld.long 0x08 31. "DISABLE_CORNER_CAP,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25.--30. "SLDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 22.--24. "RESERVED,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 21. "PA20DBMTRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16.--20. "CTL_PA_20DBM_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x08 9.--15. 1. "RFLDO_TRIM_OUTPUT,Internal"
|
|
newline
|
|
bitfld.long 0x08 6.--8. "QUANTCTLTHRES,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "DACTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CONFIG_SYNTH_DIV2_CC26_2G4,Internal"
|
|
bitfld.long 0x0C 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x0C 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x0C 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x0C 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "CONFIG_SYNTH_DIV2_CC13_2G4,Internal"
|
|
bitfld.long 0x10 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x10 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x10 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x10 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "CONFIG_SYNTH_DIV2_CC26_1G,Internal"
|
|
bitfld.long 0x14 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x14 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x14 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x14 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "CONFIG_SYNTH_DIV2_CC13_1G,Internal"
|
|
bitfld.long 0x18 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x18 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x18 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x18 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xE0)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV4_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
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bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
repeat.end
|
|
repeat 4. (list 5. 10. 15. 30. )(list 0x00 0x0C 0x18 0x1C )
|
|
rgroup.long ($2+0xE8)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
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bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
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bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xEC)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV6_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xF8)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV12_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "IOCONF,IO Configuration"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "GPIO_CNT,Number of available DIOs."
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "USER_ID,User Identification.Reading this register and the FCFG1:ICEPICK_DEVICE_ID register is the only supported way of identifying a device.The value of this register will be written to AON_PMCTL:JTAGUSERCODE by boot FW while in safezone"
|
|
bitfld.long 0x00 28.--31. "PG_REV,Field used to distinguish revisions of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "VER,Version number.0x0: Bits [25:12] of this register has the stated meaning.Any other setting indicate a different encoding of these bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 25. "PA," "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED24,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CC13," "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "SEQUENCE,Sequence.Used to differentiate between marketing/orderable product where other fields of this register are the same (temp range flash size voltage range etc)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PKG,Package type.0x0: 4x4mm QFN (RHB) package0x1: 5x5mm QFN (RSM) package0x2: 7x7mm QFN (RGZ) package0x3: Wafer sale package (naked" "4x4mm QFN (RHB) package,5x5mm QFN (RSM) package,7x7mm QFN (RGZ) package,Wafer sale package (naked die),WCSP (YFV),7x7mm QFN package with Wettable FlanksOther..,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PROTOCOL,Protocols supported.0x1: BLE" "?,BLE,RF4CE,?,Zigbee/6lowpan,?,?,?,ProprietaryMore than..,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
rgroup.long 0x2B0++0x0B
|
|
line.long 0x00 "FLASH_OTP_DATA3,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FLASH_SIZE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "ANA2_TRIM,Internal"
|
|
bitfld.long 0x04 31. "RCOSCHFCTRIMFRACT_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 26.--30. "RCOSCHFCTRIMFRACT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 25. "RESERVED0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 23.--24. "SET_RCOSC_HF_FINE_RESISTOR,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 22. "ATESTLF_UDIGLDO_IBIAS_TRIM,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 15.--21. 1. "NANOAMP_RES_TRIM,Internal"
|
|
newline
|
|
bitfld.long 0x04 12.--14. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 11. "DITHER_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8.--10. "DCDC_IPEAK,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 6.--7. "DEAD_TIME_TRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 3.--5. "DCDC_LOW_EN_SEL,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "DCDC_HIGH_EN_SEL,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "LDO_TRIM,Internal"
|
|
bitfld.long 0x08 29.--31. "RESERVED4,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 24.--28. "VDDR_TRIM_SLEEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 19.--23. "RESERVED3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 16.--18. "GLDO_CURSRC,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 13.--15. "RESERVED2,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 11.--12. "ITRIM_DIGLDO_LOAD,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 8.--10. "ITRIM_UDIGLDO,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 3.--7. "RESERVED1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "VTRIM_DELTA,Internal" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2E8++0x0F
|
|
line.long 0x00 "MAC_BLE_0,MAC BLE Address 0"
|
|
line.long 0x04 "MAC_BLE_1,MAC BLE Address 1"
|
|
line.long 0x08 "MAC_15_4_0,MAC IEEE 802.15.4 Address 0"
|
|
line.long 0x0C "MAC_15_4_1,MAC IEEE 802.15.4 Address 1"
|
|
rgroup.long 0x30C++0x07
|
|
line.long 0x00 "MISC_TRIM,Miscellaneous Trim Parameters"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--16. "TRIM_RECHARGE_COMP_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TRIM_RECHARGE_COMP_REFLEVEL,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEMPVSLOPE,Signed byte value representing the TEMP slope with battery voltage in degrees C / V with four fractional bits"
|
|
line.long 0x04 "RCOSC_HF_TEMPCOMP,Internal"
|
|
hexmask.long.byte 0x04 24.--31. 1. "FINE_RESISTOR,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. "CTRIM,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "CTRIMFRACT_QUAD,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "CTRIMFRACT_SLOPE,Internal"
|
|
rgroup.long 0x318++0x0B
|
|
line.long 0x00 "ICEPICK_DEVICE_ID,IcePick Device IdentificationReading this register and the FCFG1:USER_ID register is the only supported way of identifying a device"
|
|
bitfld.long 0x00 28.--31. "PG_REV,Field used to distinguish revisions of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "WAFER_ID,Field used to identify silicon die"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "MANUFACTURER_ID,Manufacturer"
|
|
line.long 0x04 "FCFG1_REVISION,Factory Configuration (FCFG1) Revision"
|
|
line.long 0x08 "MISC_OTP_DATA,Misc OTP Data"
|
|
bitfld.long 0x08 28.--31. "RCOSC_HF_ITUNE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x08 20.--27. 1. "RCOSC_HF_CRIM,Internal"
|
|
newline
|
|
bitfld.long 0x08 15.--19. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 12.--14. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
rgroup.long 0x34C++0x07
|
|
line.long 0x00 "CONFIG_IF_ADC,Internal"
|
|
bitfld.long 0x00 28.--31. "FF2ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FF3ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "INT3ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "FF1ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "AAFCAP,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--13. "INT2ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "IFDIGLDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "IFANALDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CONFIG_OSC_TOP,Internal"
|
|
bitfld.long 0x04 30.--31. "RESERVED,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 26.--29. "XOSC_HF_ROW_Q12,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x04 10.--25. 1. "XOSC_HF_COLUMN_Q12,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 2.--9. 1. "RCOSCLF_CTUNE_TRIM,Internal"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RCOSCLF_RTUNE_TRIM,Internal" "0,1,2,3"
|
|
rgroup.long 0x35C++0x07
|
|
line.long 0x00 "SOC_ADC_ABS_GAIN,AUX_ADC Gain in Absolute Reference Mode"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "SOC_ADC_ABS_GAIN_TEMP1,SOC_ADC gain in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REL_GAIN,AUX_ADC Gain in Relative Reference Mode"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "SOC_ADC_REL_GAIN_TEMP1,SOC_ADC gain in relative reference mode at temperature 1 (30C)"
|
|
rgroup.long 0x368++0x17
|
|
line.long 0x00 "SOC_ADC_OFFSET_INT,AUX_ADC Temperature Offsets in Absolute Reference Mode"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "SOC_ADC_REL_OFFSET_TEMP1,SOC_ADC offset in relative reference mode at temperature 1 (30C)"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SOC_ADC_ABS_OFFSET_TEMP1,SOC_ADC offset in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REF_TRIM_AND_OFFSET_EXT,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "SOC_ADC_REF_VOLTAGE_TRIM_TEMP1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "AMPCOMP_TH1,Internal"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED1,Internal"
|
|
newline
|
|
bitfld.long 0x08 18.--23. "HPMRAMP3_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 16.--17. "RESERVED0,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 10.--15. "HPMRAMP3_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 6.--9. "IBIASCAP_LPTOHP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "HPMRAMP1_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "AMPCOMP_TH2,Internal"
|
|
bitfld.long 0x0C 26.--31. "LPMUPDATE_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 24.--25. "RESERVED3,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 18.--23. "LPMUPDATE_HTM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 16.--17. "RESERVED2,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 10.--15. "ADC_COMP_AMPTH_LPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x0C 8.--9. "RESERVED1,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 2.--7. "ADC_COMP_AMPTH_HPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x0C 0.--1. "RESERVED0,Internal" "0,1,2,3"
|
|
line.long 0x10 "AMPCOMP_CTRL1,Internal"
|
|
bitfld.long 0x10 31. "RESERVED1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "AMPCOMP_REQ_MODE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24.--29. "RESERVED0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x10 20.--23. "IBIAS_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. "IBIAS_INIT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "LPM_IBIAS_WAIT_CNT_FINAL,Internal"
|
|
newline
|
|
bitfld.long 0x10 4.--7. "CAP_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 0.--3. "IBIASCAP_HPTOLP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "ANABYPASS_VALUE2,Internal"
|
|
hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.word 0x14 0.--13. 1. "XOSC_HF_IBIASTHERM,Internal"
|
|
rgroup.long 0x388++0x0B
|
|
line.long 0x00 "VOLT_TRIM,Internal"
|
|
bitfld.long 0x00 29.--31. "RESERVED3,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24.--28. "VDDR_TRIM_HH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 21.--23. "RESERVED2,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "VDDR_TRIM_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "VDDR_TRIM_SLEEP_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED0,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "TRIMBOD_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "OSC_CONF,OSC Configuration"
|
|
bitfld.long 0x04 30.--31. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 29. "ADC_SH_VBUF_EN,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x04 28. "ADC_SH_MODE_EN,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x04 27. "ATESTLF_RCOSCLF_IBIAS_TRIM,Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM" "0,1"
|
|
newline
|
|
bitfld.long 0x04 25.--26. "XOSCLF_REGULATOR_TRIM,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 21.--24. "XOSCLF_CMIRRWR_RATIO,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 19.--20. "XOSC_HF_FAST_START,Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 18. "XOSC_OPTION," "0,1"
|
|
newline
|
|
bitfld.long 0x04 17. "HPOSC_OPTION,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "HPOSC_BIAS_HOLD_MODE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12.--15. "HPOSC_CURRMIRR_RATIO,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. "HPOSC_BIAS_RES_SET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. "HPOSC_FILTER_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5.--6. "HPOSC_BIAS_RECHARGE_DELAY,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 3.--4. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 1.--2. "HPOSC_SERIES_CAP,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0. "HPOSC_DIV3_BYPASS,Internal" "0,1"
|
|
line.long 0x08 "FREQ_OFFSET,Internal"
|
|
hexmask.long.word 0x08 16.--31. 1. "HPOSC_COMP_P0,Internal"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. "HPOSC_COMP_P1,Internal"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "HPOSC_COMP_P2,Internal"
|
|
rgroup.long 0x398++0x03
|
|
line.long 0x00 "MISC_OTP_DATA_1,Internal"
|
|
bitfld.long 0x00 29.--31. "RESERVED,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "PEAK_DET_ITRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "HP_BUF_ITRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "LP_BUF_ITRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DBLR_LOOP_FILTER_RESET_VOLTAGE,Internal" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "HPM_IBIAS_WAIT_CNT,Internal"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "LPM_IBIAS_WAIT_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "IDAC_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x3D0++0x0F
|
|
line.long 0x00 "SHDW_DIE_ID_0,Shadow of DIE_ID_0 register in eFuse"
|
|
line.long 0x04 "SHDW_DIE_ID_1,Shadow of DIE_ID_1 register in eFuse"
|
|
line.long 0x08 "SHDW_DIE_ID_2,Shadow of DIE_ID_2 register in eFuse"
|
|
line.long 0x0C "SHDW_DIE_ID_3,Shadow of DIE_ID_3 register in eFuse"
|
|
rgroup.long 0x3F8++0x07
|
|
line.long 0x00 "SHDW_SCAN_MCU3_SEC,Internal"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SECURITY,Internal"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 11.--22. 1. "ULL_MCU_RAM_0_REP,Internal"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "ULL_MCU_RAM_1_REP_1,Internal"
|
|
line.long 0x04 "SHDW_SCAN_DATA1_CRC,Internal"
|
|
bitfld.long 0x04 31. "FLASH_RDY,Internal" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x04 9.--30. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 1.--8. 1. "CRC,Internal"
|
|
newline
|
|
bitfld.long 0x04 0. "TAP_DAP_LOCK_N,Internal" "0,1"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "DAC_BIAS_CNF,Internal"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "LPM_TRIM_IOUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "LPM_BIAS_WIDTH_TRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "LPM_BIAS_BACKUP_EN,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED1,Internal"
|
|
rgroup.long 0x418++0x17
|
|
line.long 0x00 "TFW_PROBE,Internal"
|
|
line.long 0x04 "TFW_FT,Internal"
|
|
line.long 0x08 "DAC_CAL0,Internal"
|
|
hexmask.long.word 0x08 16.--31. 1. "SOC_DAC_VOUT_CAL_DECOUPLE_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "SOC_DAC_VOUT_CAL_DECOUPLE_C1,Internal"
|
|
line.long 0x0C "DAC_CAL1,Internal"
|
|
hexmask.long.word 0x0C 16.--31. 1. "SOC_DAC_VOUT_CAL_PRECH_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--15. 1. "SOC_DAC_VOUT_CAL_PRECH_C1,Internal"
|
|
line.long 0x10 "DAC_CAL2,Internal"
|
|
hexmask.long.word 0x10 16.--31. 1. "SOC_DAC_VOUT_CAL_ADCREF_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "SOC_DAC_VOUT_CAL_ADCREF_C1,Internal"
|
|
line.long 0x14 "DAC_CAL3,Internal"
|
|
hexmask.long.word 0x14 16.--31. 1. "SOC_DAC_VOUT_CAL_VDDS_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "SOC_DAC_VOUT_CAL_VDDS_C1,Internal"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "RESERVED_N,Software should not rely on the value of a reserved"
|
|
tree.end
|
|
tree "FLASH"
|
|
base ad:0x40030000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "WEPROT_B0_31_0_BY1,Internal"
|
|
line.long 0x04 "WEPROT_AUX_BY1,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x04 5. "WEPROT_B1_ENGR_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "WEPROT_B0_ENGR_BY1,Internal" "0,1"
|
|
bitfld.long 0x04 3. "WEPROT_B1_TRIM_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "WEPROT_B0_TRIM_BY1,Internal" "0,1"
|
|
bitfld.long 0x04 1. "WEPROT_B1_FCFG_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "WEPROT_B0_CCFG_BY1,Internal" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STAT,NW and Efuse Status"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "STALLSTAT,An ocp1 or ocp3 read stall has occurred.0 : No stall or stall acknowledged by writing a" "No stall or stall acknowledged by writing a 1,Stall condition occurred/occurringThis is a.."
|
|
newline
|
|
bitfld.long 0x00 15. "EFUSE_BLANK,Efuse scanning detected if fuse ROM is blank:0 : Not blank1 : Blank" "Not blank,Blank"
|
|
bitfld.long 0x00 14. "EFUSE_TIMEOUT,Efuse scanning resulted in timeout error.0 : No Timeout error1 : Timeout Error" "No Timeout error,Timeout Error"
|
|
newline
|
|
bitfld.long 0x00 13. "SPRS_BYTE_NOT_OK,Efuse scanning resulted in scan chain Sparse byte error.0 : No Sparse error1 : Sparse Error" "No Sparse error,Sparse Error"
|
|
rbitfld.long 0x00 8.--12. "EFUSE_ERRCODE,Same as EFUSEERROR.CODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED7,Software should not rely on the value of a reserved bit" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "BUSY,NW FW_SMSTAT.CMD_IN_PROGRESS bit.This flag is valid immediately after the operation setting it" "Not busy,BusyBit 4 is for the..,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "READY1T,1T access readiness status indicator from NW" "FLASH banks are not ready for 1T accesses,FLASH banks are ready for 1T accesses"
|
|
bitfld.long 0x00 2. "READY2T,2T access readiness status indicator from NW1: FLASH banks are ready for 2T accesses0: FLASH banks are not ready for 2T accesses" "FLASH banks are not ready for 2T accesses,FLASH banks are ready for 2T accesses"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "POWER_MODE,Power state of each of the 2 flash arbiter FSM instances in the flash sub-system" "Active,Ready for Low..,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFG,Internal"
|
|
bitfld.long 0x00 31. "RESERVED31,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x00 30. "DIS_FWTEST,Internal" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 12.--29. 1. "RESERVED12,Internal"
|
|
bitfld.long 0x00 11. "MAIN_STICKY_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CCFG_STICKY_EN,Internal" "0,1"
|
|
bitfld.long 0x00 9. "FCFG_STICKY_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ENGR_TRIM_STICKY_EN,Internal" "0,1"
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "DIS_EFUSECLK,Internal" "0,1"
|
|
bitfld.long 0x00 4. "DIS_READACCESS,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "BP_TRIMCFG_EN,Internal" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FLASH_SIZE,Internal"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED10,Internal"
|
|
bitfld.long 0x00 7.--9. "SECTORS,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "RESERVED0,Internal"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "FWLOCK,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x00 0.--2. "FWLOCK,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FWFLAG,Internal"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x04 0.--2. "FWFLAG,Internal" "0,1,2,3,4,5,6,7"
|
|
repeat 2. (list 3. 2. )(list 0x00 0x04 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "BANK0_TRIM_CFG_$1,Internal"
|
|
repeat.end
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "BANK0_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x00 28.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--27. "REDSWSELW3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "REDSWSELW2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. "REDSWSELW1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "REDSWSELW0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3. "REDSWENW3,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REDSWENW2,Internal" "0,1"
|
|
bitfld.long 0x00 1. "REDSWENW1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "REDSWENW0,Internal" "0,1"
|
|
line.long 0x04 "BANK0_TRIM_CFG_0,Internal"
|
|
repeat 2. (list 3. 2. )(list 0x00 0x04 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "BANK1_TRIM_CFG_$1,Internal"
|
|
repeat.end
|
|
group.long 0x68++0x13
|
|
line.long 0x00 "BANK1_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x00 28.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--27. "REDSWSELW3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "REDSWSELW2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. "REDSWSELW1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "REDSWSELW0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3. "REDSWENW3,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REDSWENW2,Internal" "0,1"
|
|
bitfld.long 0x00 1. "REDSWENW1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "REDSWENW0,Internal" "0,1"
|
|
line.long 0x04 "BANK1_TRIM_CFG_0,Internal"
|
|
line.long 0x08 "PUMP_TRIM_CFG_2,Internal"
|
|
bitfld.long 0x08 26.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--25. "VWLCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 14.--19. "VSLCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 9.--13. "VREADCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 4.--8. "VINLOWCCORCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--3. "VINHICCORCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "PUMP_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x0C 31. "VINHICCORCTLSB,Internal" "0,1"
|
|
bitfld.long 0x0C 25.--30. "VINHCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 20.--24. "VCGCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 15.--19. "IREFVRDCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 10.--14. "IREFTCCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 6.--9. "IREFCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 0.--5. "FOSCCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "PUMP_TRIM_CFG_0,Internal"
|
|
bitfld.long 0x10 30.--31. "RESERVED2,Internal" "0,1,2,3"
|
|
hexmask.long.word 0x10 20.--29. 1. "VHVCT_PV,Internal"
|
|
newline
|
|
hexmask.long.word 0x10 10.--19. 1. "VHVCT_PGM,Internal"
|
|
hexmask.long.word 0x10 0.--9. 1. "VHVCT_ERS,Internal"
|
|
group.long 0x1000++0x4F
|
|
line.long 0x00 "EFUSE,Internal"
|
|
rbitfld.long 0x00 29.--31. "RESERVED29,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "INSTRUCTION,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RESERVED16,Internal"
|
|
hexmask.long.word 0x00 0.--15. 1. "DUMPWORD,Internal"
|
|
line.long 0x04 "EFUSEADDR,Internal"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Internal"
|
|
bitfld.long 0x04 11.--15. "BLOCK,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x04 0.--10. 1. "ROW,Internal"
|
|
line.long 0x08 "DATAUPPER,Internal"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Internal"
|
|
bitfld.long 0x08 3.--7. "SPARE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "P,Internal" "0,1"
|
|
bitfld.long 0x08 1. "R,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "EEN,Internal" "0,1"
|
|
line.long 0x0C "DATALOWER,Internal"
|
|
line.long 0x10 "EFUSECFG,Internal"
|
|
hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x10 8. "IDLEGATING,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 5.--7. "RESERVED5,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 3.--4. "SLAVEPOWER,Internal" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x10 1.--2. "RESERVED1,Internal" "0,1,2,3"
|
|
bitfld.long 0x10 0. "GATING,Internal" "0,1"
|
|
line.long 0x14 "EFUSESTAT,Internal"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x14 0. "RESETDONE,Internal" "0,1"
|
|
line.long 0x18 "ACC,Internal"
|
|
hexmask.long.byte 0x18 24.--31. 1. "RESERVED24,Internal"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "ACCUMULATOR,Internal"
|
|
line.long 0x1C "BOUNDARY,Internal"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "RESERVED24,Internal"
|
|
bitfld.long 0x1C 23. "DISROW0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "SPARE,Internal" "0,1"
|
|
bitfld.long 0x1C 21. "EFC_SELF_TEST_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 20. "EFC_INSTRUCTION_INFO,Internal" "0,1"
|
|
bitfld.long 0x1C 19. "EFC_INSTRUCTION_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 18. "EFC_AUTOLOAD_ERROR,Internal" "0,1"
|
|
bitfld.long 0x1C 14.--17. "OUTPUTENABLE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 13. "SYS_ECC_SELF_TEST_EN,Internal" "0,1"
|
|
bitfld.long 0x1C 12. "SYS_ECC_OVERRIDE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "EFC_FDI,Internal" "0,1"
|
|
bitfld.long 0x1C 10. "SYS_DIEID_AUTOLOAD_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8.--9. "SYS_REPAIR_EN,Internal" "0,1,2,3"
|
|
bitfld.long 0x1C 4.--7. "SYS_WS_READ_STATES,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 0.--3. "INPUTENABLE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "EFUSEFLAG,Internal"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x20 0. "KEY,Internal" "0,1"
|
|
line.long 0x24 "EFUSEKEY,Internal"
|
|
line.long 0x28 "EFUSERELEASE,Internal"
|
|
hexmask.long.byte 0x28 25.--31. 1. "ODPYEAR,Internal"
|
|
bitfld.long 0x28 21.--24. "ODPMONTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x28 16.--20. "ODPDAY,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x28 9.--15. 1. "EFUSEYEAR,Internal"
|
|
newline
|
|
bitfld.long 0x28 5.--8. "EFUSEMONTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 0.--4. "EFUSEDAY,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "EFUSEPINS,Internal"
|
|
hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Internal"
|
|
bitfld.long 0x2C 15. "EFC_SELF_TEST_DONE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 14. "EFC_SELF_TEST_ERROR,Internal" "0,1"
|
|
bitfld.long 0x2C 13. "SYS_ECC_SELF_TEST_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 12. "EFC_INSTRUCTION_INFO,Internal" "0,1"
|
|
bitfld.long 0x2C 11. "EFC_INSTRUCTION_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 10. "EFC_AUTOLOAD_ERROR,Internal" "0,1"
|
|
bitfld.long 0x2C 9. "SYS_ECC_OVERRIDE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "EFC_READY,Internal" "0,1"
|
|
bitfld.long 0x2C 7. "EFC_FCLRZ,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 6. "SYS_DIEID_AUTOLOAD_EN,Internal" "0,1"
|
|
bitfld.long 0x2C 4.--5. "SYS_REPAIR_EN,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 0.--3. "SYS_WS_READ_STATES,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "EFUSECRA,Internal"
|
|
hexmask.long 0x30 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x30 0.--5. "DATA,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x34 "EFUSEREAD,Internal"
|
|
hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED10,Internal"
|
|
bitfld.long 0x34 8.--9. "DATABIT,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x34 4.--7. "READCLOCK,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 3. "DEBUG,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "SPARE,Internal" "0,1"
|
|
bitfld.long 0x34 0.--1. "MARGIN,Internal" "0,1,2,3"
|
|
line.long 0x38 "EFUSEPROGRAM,Internal"
|
|
rbitfld.long 0x38 31. "RESERVED31,Internal" "0,1"
|
|
bitfld.long 0x38 30. "COMPAREDISABLE,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x38 14.--29. 1. "CLOCKSTALL,Internal"
|
|
bitfld.long 0x38 13. "VPPTOVDD,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x38 9.--12. "ITERATIONS,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x38 0.--8. 1. "WRITECLOCK,Internal"
|
|
line.long 0x3C "EFUSEERROR,Internal"
|
|
hexmask.long 0x3C 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x3C 5. "DONE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 0.--4. "CODE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x40 "SINGLEBIT,Internal"
|
|
hexmask.long 0x40 1.--31. 1. "FROMN,Internal"
|
|
bitfld.long 0x40 0. "FROM0,Internal" "0,1"
|
|
line.long 0x44 "TWOBIT,Internal"
|
|
hexmask.long 0x44 1.--31. 1. "FROMN,Internal"
|
|
bitfld.long 0x44 0. "FROM0,Internal" "0,1"
|
|
line.long 0x48 "SELFTESTCYC,Internal"
|
|
line.long 0x4C "SELFTESTSIGN,Internal"
|
|
tree.end
|
|
tree "GPIO"
|
|
base ad:0x40022000
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "DOUT3_0,Data Out 0 to 3Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 24. "DIO3,Sets the state of the pin that is configured as DIO#3 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "DIO2,Sets the state of the pin that is configured as DIO#2 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "DIO1,Sets the state of the pin that is configured as DIO#1 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "DIO0,Sets the state of the pin that is configured as DIO#0 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x04 "DOUT7_4,Data Out 4 to 7Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x04 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 24. "DIO7,Sets the state of the pin that is configured as DIO#7 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 16. "DIO6,Sets the state of the pin that is configured as DIO#6 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "DIO5,Sets the state of the pin that is configured as DIO#5 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "DIO4,Sets the state of the pin that is configured as DIO#4 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x08 "DOUT11_8,Data Out 8 to 11Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 24. "DIO11,Sets the state of the pin that is configured as DIO#11 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 16. "DIO10,Sets the state of the pin that is configured as DIO#10 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 8. "DIO9,Sets the state of the pin that is configured as DIO#9 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "DIO8,Sets the state of the pin that is configured as DIO#8 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x0C "DOUT15_12,Data Out 12 to 15Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x0C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 24. "DIO15,Sets the state of the pin that is configured as DIO#15 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 16. "DIO14,Sets the state of the pin that is configured as DIO#14 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 8. "DIO13,Sets the state of the pin that is configured as DIO#13 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "DIO12,Sets the state of the pin that is configured as DIO#12 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x10 "DOUT19_16,Data Out 16 to 19Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x10 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 24. "DIO19,Sets the state of the pin that is configured as DIO#19 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 16. "DIO18,Sets the state of the pin that is configured as DIO#18 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 8. "DIO17,Sets the state of the pin that is configured as DIO#17 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "DIO16,Sets the state of the pin that is configured as DIO#16 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x14 "DOUT23_20,Data Out 20 to 23Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x14 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 24. "DIO23,Sets the state of the pin that is configured as DIO#23 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 16. "DIO22,Sets the state of the pin that is configured as DIO#22 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 8. "DIO21,Sets the state of the pin that is configured as DIO#21 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "DIO20,Sets the state of the pin that is configured as DIO#20 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x18 "DOUT27_24,Data Out 24 to 27Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x18 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 24. "DIO27,Sets the state of the pin that is configured as DIO#27 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 16. "DIO26,Sets the state of the pin that is configured as DIO#26 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 8. "DIO25,Sets the state of the pin that is configured as DIO#25 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "DIO24,Sets the state of the pin that is configured as DIO#24 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x1C "DOUT31_28,Data Out 28 to 31Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x1C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 24. "DIO31,Sets the state of the pin that is configured as DIO#31 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 16. "DIO30,Sets the state of the pin that is configured as DIO#30 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 8. "DIO29,Sets the state of the pin that is configured as DIO#29 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "DIO28,Sets the state of the pin that is configured as DIO#28 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x20 "DOUT35_32,Data Out 35 to 32Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x20 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 24. "DIO35,Sets the state of the pin that is configured as DIO#35 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 16. "DIO34,Sets the state of the pin that is configured as DIO#34 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 8. "DIO33,Sets the state of the pin that is configured as DIO#33 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "DIO32,Sets the state of the pin that is configured as DIO#32 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x24 "DOUT39_36,Data Out 39 to 36Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x24 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 24. "DIO39,Sets the state of the pin that is configured as DIO#39 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 16. "DIO38,Sets the state of the pin that is configured as DIO#38 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 8. "DIO37,Sets the state of the pin that is configured as DIO#37 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0. "DIO36,Sets the state of the pin that is configured as DIO#36 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x28 "DOUT43_40,Data Out 43 to 40Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x28 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 24. "DIO43,Sets the state of the pin that is configured as DIO#43 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 16. "DIO42,Sets the state of the pin that is configured as DIO#42 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 8. "DIO41,Sets the state of the pin that is configured as DIO#41 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "DIO40,Sets the state of the pin that is configured as DIO#40 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x2C "DOUT47_44,Data Out 47 to 44Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x2C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 24. "DIO47,Sets the state of the pin that is configured as DIO#47 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 16. "DIO46,Sets the state of the pin that is configured as DIO#46 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 8. "DIO45,Sets the state of the pin that is configured as DIO#45 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "DIO44,Sets the state of the pin that is configured as DIO#44 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "DOUT31_0,Data Output for DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data output for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data output for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data output for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data output for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data output for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data output for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data output for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data output for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data output for DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data output for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data output for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data output for DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data output for DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data output for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data output for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data output for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data output for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data output for DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data output for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data output for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data output for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data output for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data output for DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data output for DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data output for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data output for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Data output for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Data output for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data output for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data output for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data output for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data output for DIO 0" "0,1"
|
|
line.long 0x04 "DOUT47_32,Data Output for DIO 0 to 31"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data output for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data output for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data output for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data output for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data output for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data output for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data output for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data output for DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Data output for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data output for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data output for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data output for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data output for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data output for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data output for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data output for DIO 32" "0,1"
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "DOUTSET31_0,Data Out SetWriting 1 to a bit position sets the corresponding bit in the DOUT47_0 register"
|
|
bitfld.long 0x00 31. "DIO31,Set bit 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Set bit 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Set bit 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Set bit 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Set bit 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Set bit 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Set bit 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Set bit 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Set bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Set bit 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Set bit 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Set bit 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Set bit 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Set bit 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Set bit 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Set bit 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Set bit 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Set bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Set bit 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Set bit 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Set bit 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Set bit 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Set bit 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Set bit 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Set bit 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Set bit 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Set bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Set bit 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Set bit 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Set bit 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Set bit 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Set bit 0" "0,1"
|
|
line.long 0x04 "DOUTSET47_32,Data Out SetWriting 1 to a bit position sets the corresponding bit in the DOUT47_0 register"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Set bit 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Set bit 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Set bit 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Set bit 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Set bit 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Set bit 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Set bit 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Set bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Set bit 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Set bit 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Set bit 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Set bit 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Set bit 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Set bit 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Set bit 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Set bit 32" "0,1"
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "DOUTCLR31_0,Data Out ClearWriting 1 to a bit position clears the corresponding bit in the DOUT47_0 register"
|
|
bitfld.long 0x00 31. "DIO31,Clears bit 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Clears bit 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Clears bit 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Clears bit 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Clears bit 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Clears bit 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Clears bit 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Clears bit 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Clears bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Clears bit 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Clears bit 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Clears bit 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Clears bit 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Clears bit 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Clears bit 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Clears bit 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Clears bit 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Clears bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Clears bit 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Clears bit 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Clears bit 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Clears bit 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Clears bit 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Clears bit 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Clears bit 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Clears bit 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Clears bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Clears bit 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Clears bit 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Clears bit 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Clears bit 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Clears bit 0" "0,1"
|
|
line.long 0x04 "DOUTCLR47_32,Data Out ClearWriting 1 to a bit position clears the corresponding bit in the DOUT47_0 register"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Clears bit 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Clears bit 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Clears bit 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Clears bit 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Clears bit 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Clears bit 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Clears bit 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Clears bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Clears bit 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Clears bit 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Clears bit 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Clears bit 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Clears bit 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Clears bit 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Clears bit 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Clears bit 32" "0,1"
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "DOUTTGL31_0,Data Out ToggleWriting 1 to a bit position will invert the corresponding DIO output"
|
|
bitfld.long 0x00 31. "DIO31,Toggles bit 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Toggles bit 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Toggles bit 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Toggles bit 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Toggles bit 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Toggles bit 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Toggles bit 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Toggles bit 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Toggles bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Toggles bit 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Toggles bit 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Toggles bit 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Toggles bit 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Toggles bit 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Toggles bit 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Toggles bit 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Toggles bit 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Toggles bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Toggles bit 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Toggles bit 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Toggles bit 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Toggles bit 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Toggles bit 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Toggles bit 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Toggles bit 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Toggles bit 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Toggles bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Toggles bit 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Toggles bit 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Toggles bit 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Toggles bit 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Toggles bit 0" "0,1"
|
|
line.long 0x04 "DOUTTGL47_32,Data Out ToggleWriting 1 to a bit position will invert the corresponding DIO output"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Toggles bit 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Toggles bit 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Toggles bit 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Toggles bit 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Toggles bit 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Toggles bit 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Toggles bit 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Toggles bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Toggles bit 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Toggles bit 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Toggles bit 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Toggles bit 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Toggles bit 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Toggles bit 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Toggles bit 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Toggles bit 32" "0,1"
|
|
rgroup.long 0xC0++0x07
|
|
line.long 0x00 "DIN31_0,Data Input from DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data input from DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data input from DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data input from DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data input from DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data input from DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data input from DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data input from DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data input from DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data input from DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data input from DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data input from DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data input from DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data input from DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data input from DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data input from DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data input from DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data input from DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data input from DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data input from DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data input from DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data input from DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data input from DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data input from DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data input from DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data input from DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data input from DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Data input from DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Data input from DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data input from DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data input from DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data input from DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data input from DIO 0" "0,1"
|
|
line.long 0x04 "DIN47_32,Data Input from DIO 32 to 47"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data input from DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data input from DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data input from DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data input from DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data input from DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data input from DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data input from DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data input from DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Data input from DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data input from DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data input from DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data input from DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data input from DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data input from DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data input from DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data input from DIO 32" "0,1"
|
|
group.long 0xD0++0x07
|
|
line.long 0x00 "DOE31_0,Data Output Enable for DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data output enable for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data output enable for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data output enable for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data output enable for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data output enable for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data output enable for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data output enable for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data output enable for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data output enable for DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data output enable for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data output enable for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data output enable for DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data output enable for DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data output enable for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data output enable for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data output enable for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data output enable for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data output enable for DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data output enable for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data output enable for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data output enable for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data output enable for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data output enable for DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data output enable for DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data output enable for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data output enable for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Data output enable for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Data output enable for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data output enable for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data output enable for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data output enable for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data output enable for DIO 0" "0,1"
|
|
line.long 0x04 "DOE47_32,Data Output Enable for DIO 32 to 47"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data output enable for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data output enable for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data output enable for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data output enable for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data output enable for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data output enable for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data output enable for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data output enable for DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Data output enable for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data output enable for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data output enable for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data output enable for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data output enable for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data output enable for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data output enable for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data output enable for DIO 32" "0,1"
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "EVFLAGS31_0,Event Register for DIO 0 to 31Reading this registers will return 1 for triggered event and 0 for non-triggered events"
|
|
bitfld.long 0x00 31. "DIO31,Event for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Event for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Event for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Event for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Event for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Event for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Event for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Event for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Event for DIO 23" "0,1"
|
|
newline
|
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bitfld.long 0x00 22. "DIO22,Event for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Event for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Event for DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Event for DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Event for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Event for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Event for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Event for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Event for DIO 14" "0,1"
|
|
newline
|
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bitfld.long 0x00 13. "DIO13,Event for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Event for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Event for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Event for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Event for DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Event for DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Event for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Event for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Event for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Event for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Event for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Event for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Event for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Event for DIO 0" "0,1"
|
|
line.long 0x04 "EVFLAGS47_32,Event Register for DIO 32 to 47Reading this registers will return 1 for triggered event and 0 for non-triggered events"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Event for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Event for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Event for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Event for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Event for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Event for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Event for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Event for DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Event for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Event for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Event for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Event for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Event for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Event for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Event for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Event for DIO 32" "0,1"
|
|
tree.end
|
|
tree "GPT"
|
|
repeat 4. (list 0. 1. 2. 3. )(list ad:0x40010000 ad:0x40011000 ad:0x40012000 ad:0x40013000 )
|
|
tree "GPT$1"
|
|
base $2
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CFG,Configuration"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CFG,GPT Configuration0x2" "32-bit timer configuration,?,?,?,16-bit timer configuration. Configure for two..,?,?,?"
|
|
line.long 0x04 "TAMR,Timer A Mode"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 13.--15. "TCACT,Timer Compare Action Select " "Disable compare operations,Toggle State on Time-Out,Clear CCP output pin on Time-Out,Set CCP output pin on Time-Out ,Set CCP output pin immediately and toggle on..,Clear CCP output pin immediately and toggle on..,Set CCP output pin immediately and clear on..,Clear CCP output pin immediately and set on.."
|
|
newline
|
|
bitfld.long 0x04 12. "TACINTD,One-Shot/Periodic Interrupt Disable" "Time-out interrupt function as normal,Time-out interrupt are disabled"
|
|
newline
|
|
bitfld.long 0x04 11. "TAPLO,GPTM Timer A PWM Legacy Operation0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0.1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0.This bit is only valid in.." "Legacy operation,CCP output pin is set to 1 on time-out"
|
|
newline
|
|
bitfld.long 0x04 10. "TAMRSU,Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated.If the timer is disabled (CTL.TAEN = 0) when this bit is set TAMATCHR and TAPR are updated when the timer is enabled.If the timer is stalled.." "Update TAMATCHR and TAPR if used on the next..,Update TAMATCHR and TAPR if used on the next.."
|
|
newline
|
|
bitfld.long 0x04 9. "TAPWMIE,GPTM Timer A PWM Interrupt EnableThis bit enables interrupts in PWM mode on rising falling or both edges of the CCP output as defined by the CTL.TAEVENTIn addition when this bit is set and a capture event occurs Timer Aautomatically generates.." "Interrupt is disabled. ,Interrupt is enabled. This bit is only valid in.."
|
|
newline
|
|
bitfld.long 0x04 8. "TAILD,GPT Timer A PWM Interval Load" "Update the TAR register with the value in the..,Update the TAR register with the value in the.."
|
|
newline
|
|
bitfld.long 0x04 7. "TASNAPS,GPT Timer A Snap-Shot Mode" "Snap-shot mode is disabled. ,If Timer A is configured in the periodic mode .."
|
|
newline
|
|
bitfld.long 0x04 6. "TAWOT,GPT Timer A Wait-On-Trigger" "Timer A begins counting as soon as it is enabled.,If Timer A is enabled (CTL.TAEN = 1) Timer A.."
|
|
newline
|
|
bitfld.long 0x04 5. "TAMIE,GPT Timer A Match Interrupt Enable" "The match interrupt is disabled for match..,An interrupt is generated when the match value.."
|
|
newline
|
|
bitfld.long 0x04 4. "TACDIR,GPT Timer A Count Direction" "The timer counts down. ,The timer counts up. When counting up the timer.."
|
|
newline
|
|
bitfld.long 0x04 3. "TAAMS,GPT Timer A Alternate Mode Note: To enable PWM mode you must also clear TACM and then configure TAMR field to 0x2" "Capture/Compare mode is enabled.,PWM mode is enabled"
|
|
newline
|
|
bitfld.long 0x04 2. "TACM,GPT Timer A Capture Mode" "Edge-Count mode,Edge-Time mode"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "TAMR,GPT Timer A Mode0x0 Reserved0x1 One-Shot Timer mode0x2 Periodic Timer mode0x3 Capture modeThe Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register" "?,One-Shot Timer mode,Periodic Timer mode ,Capture mode"
|
|
line.long 0x08 "TBMR,Timer B Mode"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 13.--15. "TCACT,Timer Compare Action Select" "Disable compare operations,Toggle State on Time-Out,Clear CCP output pin on Time-Out,Set CCP output pin on Time-Out ,Set CCP output pin immediately and toggle on..,Clear CCP output pin immediately and toggle on..,Set CCP output pin immediately and clear on..,Clear CCP output pin immediately and set on.."
|
|
newline
|
|
bitfld.long 0x08 12. "TBCINTD,One-Shot/Periodic Interrupt Mode" "Normal Time-Out Interrupt ,Mask Time-Out Interrupt"
|
|
newline
|
|
bitfld.long 0x08 11. "TBPLO,GPTM Timer B PWM Legacy Operation0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0.1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0.This bit is only valid in.." "Legacy operation,CCP output pin is set to 1 on time-out"
|
|
newline
|
|
bitfld.long 0x08 10. "TBMRSU,Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updatedIf the timer is disabled (CTL.TBEN is clear) when this bit is set TBMATCHR and TBPR are updated when the timer is enabled.If the timer is stalled.." "Update TBMATCHR and TBPR if used on the next..,Update TBMATCHR and TBPR if used on the next.."
|
|
newline
|
|
bitfld.long 0x08 9. "TBPWMIE,GPTM Timer B PWM Interrupt EnableThis bit enables interrupts in PWM mode on rising falling or both edges of the CCP output as defined by the CTL.TBEVENTIn addition when this bit is set and a capture event occurs Timer Aautomatically generates.." "Interrupt is disabled. ,Interrupt is enabled. This bit is only valid in.."
|
|
newline
|
|
bitfld.long 0x08 8. "TBILD,GPT Timer B PWM Interval Load" "Update the TBR register with the value in the..,Update the TBR register with the value in the.."
|
|
newline
|
|
bitfld.long 0x08 7. "TBSNAPS,GPT Timer B Snap-Shot Mode" "Snap-shot mode is disabled. ,If Timer B is configured in the periodic mode"
|
|
newline
|
|
bitfld.long 0x08 6. "TBWOT,GPT Timer B Wait-On-Trigger" "Timer B begins counting as soon as it is enabled. ,If Timer B is enabled (CTL.TBEN is set) Timer B.."
|
|
newline
|
|
bitfld.long 0x08 5. "TBMIE,GPT Timer B Match Interrupt Enable" "The match interrupt is disabled for match..,An interrupt is generated when the match value.."
|
|
newline
|
|
bitfld.long 0x08 4. "TBCDIR,GPT Timer B Count Direction" "The timer counts down. ,The timer counts up. When counting up the timer.."
|
|
newline
|
|
bitfld.long 0x08 3. "TBAMS,GPT Timer B Alternate Mode Note: To enable PWM mode you must also clear TBCM bit and configure TBMR field to 0x2" "Capture/Compare mode is enabled.,PWM mode is enabled"
|
|
newline
|
|
bitfld.long 0x08 2. "TBCM,GPT Timer B Capture Mode" "Edge-Count mode,Edge-Time mode"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "TBMR,GPT Timer B Mode0x0 Reserved0x1 One-Shot Timer mode0x2 Periodic Timer mode0x3 Capture modeThe Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register" "?,One-Shot Timer mode,Periodic Timer mode ,Capture mode"
|
|
line.long 0x0C "CTL,Control"
|
|
hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 14. "TBPWML,GPT Timer B PWM Output Level0: Output is unaffected" "Output is unaffected,Output is inverted"
|
|
newline
|
|
bitfld.long 0x0C 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 10.--11. "TBEVENT,GPT Timer B Event ModeThe values in this register are defined as follows:Value Description0x0 Positive edge0x1 Negative edge0x2 Reserved0x3 Both edgesNote: If PWM output inversion is enabled edge detection interruptbehavior is reversed" "Positive edge,Negative edge ,?,Both edges"
|
|
newline
|
|
bitfld.long 0x0C 9. "TBSTALL,GPT Timer B Stall Enable" "Timer B continues counting while the processor..,Timer B freezes counting while the processor is.."
|
|
newline
|
|
bitfld.long 0x0C 8. "TBEN,GPT Timer B Enable" "Timer B is disabled. ,Timer B is enabled and begins counting or the.."
|
|
newline
|
|
rbitfld.long 0x0C 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "TAPWML,GPT Timer A PWM Output Level" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x0C 4.--5. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 2.--3. "TAEVENT,GPT Timer A Event ModeThe values in this register are defined as follows:Value Description0x0 Positive edge0x1 Negative edge0x2 Reserved0x3 Both edgesNote: If PWM output inversion is enabled edge detection interruptbehavior is reversed" "Positive edge,Negative edge ,?,Both edges"
|
|
newline
|
|
bitfld.long 0x0C 1. "TASTALL,GPT Timer A Stall Enable" "Timer A continues counting while the processor..,Timer A freezes counting while the processor is.."
|
|
newline
|
|
bitfld.long 0x0C 0. "TAEN,GPT Timer A Enable" "Timer A is disabled. ,Timer A is enabled and begins counting or the.."
|
|
line.long 0x10 "SYNC,Synch Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "SYNC3,Synchronize GPT Timer 3" "No Sync. GPT3 is not affected. ,A timeout event for Timer A of GPT3 is triggered,A timeout event for Timer B of GPT3 is triggered,A timeout event for both Timer A and Timer B of.."
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|
newline
|
|
bitfld.long 0x10 4.--5. "SYNC2,Synchronize GPT Timer 2" "No Sync. GPT2 is not affected. ,A timeout event for Timer A of GPT2 is triggered,A timeout event for Timer B of GPT2 is triggered,A timeout event for both Timer A and Timer B of.."
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|
newline
|
|
bitfld.long 0x10 2.--3. "SYNC1,Synchronize GPT Timer 1" "No Sync. GPT1 is not affected. ,A timeout event for Timer A of GPT1 is triggered,A timeout event for Timer B of GPT1 is triggered,A timeout event for both Timer A and Timer B of.."
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|
newline
|
|
bitfld.long 0x10 0.--1. "SYNC0,Synchronize GPT Timer 0" "No Sync. GPT0 is not affected. ,A timeout event for Timer A of GPT0 is triggered,A timeout event for Timer B of GPT0 is triggered,A timeout event for both Timer A and Timer B of.."
|
|
group.long 0x18++0x3F
|
|
line.long 0x00 "IMR,Interrupt MaskThis register is used to enable the interrupts.Associated registers:RIS. MIS. ICLR"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 13. "DMABIM,Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
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rbitfld.long 0x00 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
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bitfld.long 0x00 11. "TBMIM,Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS" "Disable Interrupt,Enable Interrupt"
|
|
newline
|
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bitfld.long 0x00 10. "CBEIM,Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
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bitfld.long 0x00 9. "CBMIM,Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
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bitfld.long 0x00 8. "TBTOIM,Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
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rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "DMAAIM,Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS" "Disable Interrupt,Enable Interrupt"
|
|
newline
|
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bitfld.long 0x00 4. "TAMIM,Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
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bitfld.long 0x00 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "CAEIM,Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS" "Disable Interrupt,Enable Interrupt"
|
|
newline
|
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bitfld.long 0x00 1. "CAMIM,Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
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bitfld.long 0x00 0. "TATOIM,Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS" "Disable Interrupt,Enable Interrupt"
|
|
line.long 0x04 "RIS,Raw Interrupt StatusAssociated registers:IMR. MIS. ICLR"
|
|
hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 13. "DMABRIS,GPT Timer B DMA Done Raw Interrupt Status0: Transfer has not completed1: Transfer has completed" "Transfer has not completed,Transfer has completed"
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|
newline
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bitfld.long 0x04 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
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bitfld.long 0x04 11. "TBMRIS,GPT Timer B Match Raw Interrupt0: The match value has not been reached1: The match value is reached.TBMR.TBMIE is set and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode" "The match value has not been reached,The match value is reached.TBMR.TBMIE is set and.."
|
|
newline
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bitfld.long 0x04 10. "CBERIS,GPT Timer B Capture Mode Event Raw Interrupt0: The event has not occured.1: The event has occured.This interrupt asserts when the subtimer is configured in Input Edge-Time mode" "The event has not occured,The event has occured.This interrupt asserts.."
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newline
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bitfld.long 0x04 9. "CBMRIS,GPT Timer B Capture Mode Match Raw Interrupt0: The capture mode match for Timer B has not occurred.1: A capture mode match has occurred for Timer B" "The capture mode match for Timer B has not..,A capture mode match has occurred for Timer B"
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newline
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bitfld.long 0x04 8. "TBTORIS,GPT Timer B Time-out Raw Interrupt0: Timer B has not timed out1: Timer B has timed out" "Timer B has not timed out,Timer B has timed out"
|
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newline
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bitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x04 5. "DMAARIS,GPT Timer A DMA Done Raw Interrupt Status0: Transfer has not completed1: Transfer has completed" "Transfer has not completed,Transfer has completed"
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|
newline
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bitfld.long 0x04 4. "TAMRIS,GPT Timer A Match Raw Interrupt0: The match value has not been reached1: The match value is reached.TAMR.TAMIE is set and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode" "The match value has not been reached,The match value is reached.TAMR.TAMIE is set and.."
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newline
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bitfld.long 0x04 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
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bitfld.long 0x04 2. "CAERIS,GPT Timer A Capture Mode Event Raw Interrupt0: The event has not occured.1: The event has occured.This interrupt asserts when the subtimer is configured in Input Edge-Time mode" "The event has not occured,The event has occured.This interrupt asserts.."
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newline
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bitfld.long 0x04 1. "CAMRIS,GPT Timer A Capture Mode Match Raw Interrupt0: The capture mode match for Timer A has not occurred.1: A capture mode match has occurred for Timer A" "The capture mode match for Timer A has not..,A capture mode match has occurred for Timer A"
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newline
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bitfld.long 0x04 0. "TATORIS,GPT Timer A Time-out Raw Interrupt0: Timer A has not timed out1: Timer A has timed out" "Timer A has not timed out,Timer A has timed out"
|
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line.long 0x08 "MIS,Masked Interrupt StatusValues are result of bitwise AND operation between RIS and IMRAssosciated clear register: ICLR"
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hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
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newline
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bitfld.long 0x08 13. "DMABMIS," "0,1"
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|
newline
|
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bitfld.long 0x08 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
|
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newline
|
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bitfld.long 0x08 11. "TBMMIS," "0,1"
|
|
newline
|
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bitfld.long 0x08 10. "CBEMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. "CBMMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "TBTOMIS," "0,1"
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newline
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bitfld.long 0x08 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x08 5. "DMAAMIS," "0,1"
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newline
|
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bitfld.long 0x08 4. "TAMMIS," "0,1"
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newline
|
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bitfld.long 0x08 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "CAEMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "CAMMIS," "0,1"
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newline
|
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bitfld.long 0x08 0. "TATOMIS," "0,1"
|
|
line.long 0x0C "ICLR,Interrupt ClearThis register is used to clear status bits in the RIS and MIS registers"
|
|
hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 13. "DMABINT," "0,1"
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newline
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bitfld.long 0x0C 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
|
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bitfld.long 0x0C 11. "TBMCINT," "0,1"
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newline
|
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bitfld.long 0x0C 10. "CBECINT," "0,1"
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newline
|
|
bitfld.long 0x0C 9. "CBMCINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "TBTOCINT," "0,1"
|
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newline
|
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rbitfld.long 0x0C 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0C 5. "DMAAINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "TAMCINT," "0,1"
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newline
|
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bitfld.long 0x0C 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
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bitfld.long 0x0C 2. "CAECINT," "0,1"
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newline
|
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bitfld.long 0x0C 1. "CAMCINT," "0,1"
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newline
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bitfld.long 0x0C 0. "TATOCINT," "0,1"
|
|
line.long 0x10 "TAILR,Timer A Interval Load Register"
|
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line.long 0x14 "TBILR,Timer B Interval Load Register"
|
|
line.long 0x18 "TAMATCHR,Timer A Match RegisterInterrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode.In Edge-Count mode. this register along with TAILR. determines how many edge events are counted.The total.."
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|
line.long 0x1C "TBMATCHR,Timer B Match Register When a GPT is configured to one of the 32-bit modes. the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR.Reads from this register return the current match value of Timer B and writes.."
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
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hexmask.long.word 0x1C 0.--15. 1. "TBMATCHR,GPT Timer B Match Register"
|
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line.long 0x20 "TAPR,Timer A Pre-scaleThis register allows software to extend the range of the timers when they are used individually.When in one-shot or periodic down count modes. this register acts as a true prescaler for the timer counter.When acting as a true.."
|
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
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abitfld.long 0x20 0.--7. "TAPSR,Timer A Pre-scale.Prescaler ratio in one-shot and periodic count mode is TAPSR + 1 that is:0: Prescaler ratio =" "0x00=Prescaler ratio = 1,0x01=Prescaler ratio = 2,0x02=Prescaler ratio = 3,0xFF=Prescaler ratio = 256"
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line.long 0x24 "TBPR,Timer B Pre-scaleThis register allows software to extend the range of the timers when they are used individually.When in one-shot or periodic down count modes. this register acts as a true prescaler for the timer counter.When acting as a true.."
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hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
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abitfld.long 0x24 0.--7. "TBPSR,Timer B Pre-scale.Prescale ratio in one-shot and periodic count mode is TBPSR + 1 that is:0: Prescaler ratio =" "0x00=Prescaler ratio = 1,0x01=Prescaler ratio = 2,0x02=Prescaler ratio = 3,0xFF=Prescaler ratio = 256"
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line.long 0x28 "TAPMR,Timer A Pre-scale MatchThis register allows software to extend the range of the TAMATCHR when used individually"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x28 0.--7. 1. "TAPSMR,GPT Timer A Pre-scale Match"
|
|
line.long 0x2C "TBPMR,Timer B Pre-scale MatchThis register allows software to extend the range of the TBMATCHR when used individually"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x2C 0.--7. 1. "TBPSMR,GPT Timer B Pre-scale Match Register"
|
|
line.long 0x30 "TAR,Timer A RegisterThis register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes"
|
|
line.long 0x34 "TBR,Timer B RegisterThis register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes"
|
|
line.long 0x38 "TAV,Timer A Value When read. this register shows the current. free-running value of Timer A in all modes"
|
|
line.long 0x3C "TBV,Timer B Value When read. this register shows the current. free-running value of Timer B in all modes"
|
|
rgroup.long 0x5C++0x13
|
|
line.long 0x00 "TAPS,Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD. this register is updated with the value from TAPR register either on the next cycle or on the next timeout.This register shows the current value of the Timer A.."
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSS,GPT Timer A Pre-scaler"
|
|
line.long 0x04 "TBPS,Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD. this register is updated with the value from TBPR register either on the next cycle or on the next timeout.This register shows the current value of the Timer B.."
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "PSS,GPT Timer B Pre-scaler"
|
|
line.long 0x08 "TAPV,Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "PSV,GPT Timer A Pre-scaler Value"
|
|
line.long 0x0C "TBPV,Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PSV,GPT Timer B Pre-scaler Value"
|
|
line.long 0x10 "DMAEV,DMA Event This register allows software to enable/disable GPT DMA trigger events"
|
|
hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved field"
|
|
newline
|
|
bitfld.long 0x10 11. "TBMDMAEN,GPT Timer B Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CBEDMAEN,GPT Timer B Capture Event DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CBMDMAEN,GPT Timer B Capture Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "TBTODMAEN,GPT Timer B Time-Out DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5.--7. "RESERVED5,Software should not rely on the value of a reserved field" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 4. "TAMDMAEN,GPT Timer A Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "CAEDMAEN,GPT Timer A Capture Event DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CAMDMAEN,GPT Timer A Capture Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "TATODMAEN,GPT Timer A Time-Out DMA Trigger Enable" "0,1"
|
|
rgroup.long 0xFB0++0x07
|
|
line.long 0x00 "VERSION,Peripheral VersionThis register provides information regarding the GPT version"
|
|
line.long 0x04 "ANDCCP,Combined CCP OutputThis register is used to logically AND CCP output pairs for each timer"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 1. "LD_TO_EN,PWM assertion would happen at timeout0: PWM assertion happens when counter matches load value1: PWM assertion happens at timeout of the counter" "PWM assertion happens when counter matches load..,PWM assertion happens at timeout of the counter"
|
|
newline
|
|
bitfld.long 0x04 0. "CCP_AND_EN,Enables AND operation of the CCP outputs for timers A and B.0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers.1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals.." "PWM outputs of Timer A and Timer B are the..,PWM output of Timer A is ANDed version of Timer.."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "Hidden"
|
|
base ad:0x00
|
|
rgroup.quad 0x00++0x07
|
|
line.quad 0x00 "JSTATE4,Digital JTAG State Register"
|
|
bitfld.quad 0x00 62. "MODACT10,CLK.I2C0" "0,1"
|
|
bitfld.quad 0x00 61. "MODACT11,CLK.I2S0" "0,1"
|
|
bitfld.quad 0x00 60. "MODACT12,CLK.DMA" "0,1"
|
|
bitfld.quad 0x00 59. "MODACT13,CLK.TRNG" "0,1"
|
|
bitfld.quad 0x00 58. "MODACT14,CLK.SEC" "0,1"
|
|
bitfld.quad 0x00 57. "MODACT15,CLK.PKA" "0,1"
|
|
bitfld.quad 0x00 56. "MODACT16,CLK.SSI0" "0,1"
|
|
bitfld.quad 0x00 55. "MODACT17,CLK.SSI1" "0,1"
|
|
bitfld.quad 0x00 54. "MODACT18,CLK.UART0" "0,1"
|
|
bitfld.quad 0x00 53. "MODACT19,CLK.UART1" "0,1"
|
|
newline
|
|
bitfld.quad 0x00 51.--52. "PWRSTATE0,CPU%CORTEXM_PM" "0,1,2,3"
|
|
bitfld.quad 0x00 49. "MODACT5,MCU.CPU_PD" "0,1"
|
|
bitfld.quad 0x00 48. "MODACT4,MCU.SERIAL_PD" "0,1"
|
|
bitfld.quad 0x00 47. "MODACT3,MCU.PERIPH_PD" "0,1"
|
|
bitfld.quad 0x00 46. "MODACT2,MCU.RFCORE_PD" "0,1"
|
|
bitfld.quad 0x00 45. "MODACT1,MCU.VIMS_PD" "0,1"
|
|
bitfld.quad 0x00 44. "MODACT0,MCU.MCU_CTL" "0,1"
|
|
bitfld.quad 0x00 43. "MODACT9,CLK.XOSC_EN" "0,1"
|
|
bitfld.quad 0x00 42. "MODACT8,CLK.SCLK_HF_SRC" "0,1"
|
|
bitfld.quad 0x00 36.--39. "PWRSTATE1,RF%LPRF_PM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 28.--35. 1. "MODACT7,PRCM:PWRPROFSTAT"
|
|
bitfld.quad 0x00 27. "MODACT20,PC_Error" "0,1"
|
|
hexmask.quad.tbyte 0x00 6.--26. 1. "PC,PC"
|
|
bitfld.quad 0x00 0.--5. "MODACT6,Interrupts%HWI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "I2C0"
|
|
base ad:0x40002000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SOAR,Slave Own AddressThis register consists of seven address bits that identify this I2C device on the I2C bus"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--6. 1. "OAR,I2C slave own addressThis field specifies bits a6 through a0 of the slave address"
|
|
line.long 0x04 "SSTAT,Slave Status Note: This register shares address with SCTL. meaning that this register functions as a control register when written. and a status register when"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 2. "FBR,First byte received0: The first byte has not been received.1: The first byte following the slave's own address has been received.This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR.." "The first byte has not been received,The first byte following the slave's own address.."
|
|
newline
|
|
bitfld.long 0x04 1. "TREQ,Transmit request0: No outstanding transmit request.1: The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the SDR register" "No outstanding transmit request,The I2C controller has been addressed as a slave.."
|
|
bitfld.long 0x04 0. "RREQ,Receive request0: No outstanding receive data1: The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until data has been read from the SDR register." "No outstanding receive data,The I2C controller has outstanding receive data.."
|
|
wgroup.long 0x04++0x17
|
|
line.long 0x00 "SCTL,Slave ControlNote: This register shares address with SSTAT. meaning that this register functions as a control register when written. and a status register when"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved field"
|
|
bitfld.long 0x00 0. "DA,Device active0: Disables the I2C slave operation1: Enables the I2C slave operation" "Disables the I2C slave operation,Enables the I2C slave operation"
|
|
line.long 0x04 "SDR,Slave DataThis register contains the data to be transmitted when in the Slave Transmit state. and the data received when in the Slave Receive state"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "DATA,Data for transferThis field contains the data for transfer during a slave receive or transmit operation"
|
|
line.long 0x08 "SIMR,Slave Interrupt MaskThis register controls whether a raw interrupt is promoted to a controller interrupt"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 2. "STOPIM,Stop condition interrupt mask0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt controller." "The SRIS.STOPRIS interrupt is suppressed and not..,The SRIS.STOPRIS interrupt is enabled and sent.."
|
|
newline
|
|
bitfld.long 0x08 1. "STARTIM,Start condition interrupt mask0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt controller." "The SRIS.STARTRIS interrupt is suppressed and..,The SRIS.STARTRIS interrupt is enabled and sent.."
|
|
bitfld.long 0x08 0. "DATAIM,Data interrupt mask0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt controller" "The SRIS.DATARIS interrupt is suppressed and not..,The SRIS.DATARIS interrupt is enabled and sent.."
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|
line.long 0x0C "SRIS,Slave Raw Interrupt StatusThis register shows the unmasked interrupt status"
|
|
hexmask.long 0x0C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 2. "STOPRIS,Stop condition raw interrupt status0: No interrupt1: A Stop condition interrupt is pending.This bit is cleared by writing a 1 to SICR.STOPIC" "No interrupt,A Stop condition interrupt is.."
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|
newline
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bitfld.long 0x0C 1. "STARTRIS,Start condition raw interrupt status0: No interrupt1: A Start condition interrupt is pending.This bit is cleared by writing a 1 to SICR.STARTIC" "No interrupt,A Start condition interrupt is.."
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|
bitfld.long 0x0C 0. "DATARIS,Data raw interrupt status0: No interrupt1: A data received or data requested interrupt is pending.This bit is cleared by writing a 1 to the SICR.DATAIC" "No interrupt,A data received or data requested.."
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|
line.long 0x10 "SMIS,Slave Masked Interrupt StatusThis register show which interrupt is active (based on result from SRIS and SIMR)"
|
|
hexmask.long 0x10 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 2. "STOPMIS,Stop condition masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked Stop condition interrupt is pending.This bit is cleared by writing a 1 to the SICR.STOPIC" "An interrupt has not occurred or is..,An unmasked Stop condition interrupt is.."
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|
newline
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bitfld.long 0x10 1. "STARTMIS,Start condition masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked Start condition interrupt is pending.This bit is cleared by writing a 1 to the SICR.STARTIC" "An interrupt has not occurred or is..,An unmasked Start condition interrupt is.."
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|
bitfld.long 0x10 0. "DATAMIS,Data masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked data received or data requested interrupt is pending.This bit is cleared by writing a 1 to the SICR.DATAIC" "An interrupt has not occurred or is..,An unmasked data received or data requested.."
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|
line.long 0x14 "SICR,Slave Interrupt ClearThis register clears the raw interrupt SRIS"
|
|
hexmask.long 0x14 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 2. "STOPIC,Stop condition interrupt clearWriting 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS" "0,1"
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|
newline
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bitfld.long 0x14 1. "STARTIC,Start condition interrupt clearWriting 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS" "0,1"
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|
bitfld.long 0x14 0. "DATAIC,Data interrupt clearWriting 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS" "0,1"
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "MSA,Master Salve AddressThis register contains seven address bits of the slave to be accessed by the master (a6-a0). and an RS bit determining if the next operation is a receive or transmit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,I2C master slave addressDefines which slave is addressed for the transaction in master mode"
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newline
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bitfld.long 0x00 0. "RS,Receive or SendThis bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA" "Transmit/send data to slave,Receive data from slave"
|
|
line.long 0x04 "MSTAT,Master Status"
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hexmask.long 0x04 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 6. "BUSBSY,Bus busy0: The I2C bus is idle.1: The I2C bus is busy.The bit changes based on the MCTRL.START and MCTRL.STOP conditions" "The I2C bus is idle,The I2C bus is busy.The bit changes based on the.."
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|
newline
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bitfld.long 0x04 5. "IDLE,I2C idle0: The I2C controller is not idle.1: The I2C controller is idle" "The I2C controller is not idle,The I2C controller is idle"
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bitfld.long 0x04 4. "ARBLST,Arbitration lost0: The I2C controller won arbitration.1: The I2C controller lost arbitration" "The I2C controller won arbitration,The I2C controller lost arbitration"
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|
newline
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bitfld.long 0x04 3. "DATACK_N,Data Was Not Acknowledge0: The transmitted data was acknowledged.1: The transmitted data was not acknowledged" "The transmitted data was acknowledged,The transmitted data was not acknowledged"
|
|
bitfld.long 0x04 2. "ADRACK_N,Address Was Not Acknowledge0: The transmitted address was acknowledged.1: The transmitted address was not acknowledged" "The transmitted address was acknowledged,The transmitted address was not acknowledged"
|
|
newline
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bitfld.long 0x04 1. "ERR,Error0: No error was detected on the last operation.1: An error occurred on the last operation" "No error was detected on the last operation,An error occurred on the last operation"
|
|
bitfld.long 0x04 0. "BUSY,I2C busy0: The controller is idle.1: The controller is busy.When this bit-field is set the other status bits are not valid.Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been.." "The controller is idle,The controller is busy.When this bit-field is.."
|
|
wgroup.long 0x804++0x1F
|
|
line.long 0x00 "MCTRL,Master ControlThis register accesses status bits when read and control bits when written"
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|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
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bitfld.long 0x00 3. "ACK,Data acknowledge enable0: The received data byte is not acknowledged automatically by the master.1: The received data byte is acknowledged automatically by the master.This bit-field must be cleared when the I2C bus controller requires no further.." "The received data byte is not acknowledged..,The received data byte is acknowledged.."
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|
newline
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bitfld.long 0x00 2. "STOP,This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.0: The controller does not generate the Stop condition.1: The controller generates the Stop condition" "The controller does not generate the Stop..,The controller generates the Stop condition"
|
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bitfld.long 0x00 1. "START,This bit-field generates the Start or Repeated Start condition" "The controller does not generate the Start..,The controller generates the Start condition"
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|
newline
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bitfld.long 0x00 0. "RUN,I2C master enable0: The master is disabled.1: The master is enabled to transmit or receive data." "The master is disabled,The master is enabled to transmit or receive data"
|
|
line.long 0x04 "MDR,Master DataThis register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state"
|
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "DATA,When Read: Last RX Data is returnedWhen Written: Data is transferred during TX transaction"
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|
line.long 0x08 "MTPR,I2C Master Timer PeriodThis register specifies the period of the SCL clock"
|
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hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 7. "TPR_7,Must be set to 0 to set TPR" "0,1"
|
|
newline
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hexmask.long.byte 0x08 0.--6. 1. "TPR,SCL clock periodThis field specifies the period of the SCL clock.SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRDwhere:SCL_PRD is the SCL line period (I2C clock).TPR is the timer period register value (range of 1 to 127)SCL_LP is the SCL low period.."
|
|
line.long 0x0C "MIMR,Master Interrupt MaskThis register controls whether a raw interrupt is promoted to a controller interrupt"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 0. "IM,Interrupt mask0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt controller.1: The master interrupt is sent to the interrupt controller when the MRIS.RIS is set." "The MRIS.RIS interrupt is suppressed and not..,The master interrupt is sent to the interrupt.."
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line.long 0x10 "MRIS,Master Raw Interrupt StatusThis register show the unmasked interrupt status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
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bitfld.long 0x10 0. "RIS,Raw interrupt status0: No interrupt1: A master interrupt is pending.This bit is cleared by writing 1 to the MICR.IC bit" "No interrupt,A master interrupt is pending.This.."
|
|
line.long 0x14 "MMIS,Master Masked Interrupt StatusThis register show which interrupt is active (based on result from MRIS and MIMR)"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "MIS,Masked interrupt status0: An interrupt has not occurred or is masked.1: A master interrupt is pending.This bit is cleared by writing 1 to the MICR.IC bit" "An interrupt has not occurred or is masked,A master interrupt is pending.This bit is.."
|
|
line.long 0x18 "MICR,Master Interrupt ClearThis register clears the raw and masked interrupt"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "IC,Interrupt clearWriting 1 to this bit clears MRIS.RIS and MMIS.MIS .Reading this register returns no meaningful data" "0,1"
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line.long 0x1C "MCR,Master ConfigurationThis register configures the mode (Master or Slave) and sets the interface for test mode loopback"
|
|
hexmask.long 0x1C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 5. "SFE,I2C slave function enable" "Slave mode is disabled.,Slave mode is enabled."
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|
newline
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bitfld.long 0x1C 4. "MFE,I2C master function enable" "Master mode is disabled.,Master mode is enabled."
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|
rbitfld.long 0x1C 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x1C 0. "LPBK,I2C loopback0: Normal operation1: Loopback operation (test mode)" "Normal operation,Loopback operation (test mode)"
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|
tree.end
|
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tree "I2S0"
|
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base ad:0x40021000
|
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group.long 0x00++0x2F
|
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line.long 0x00 "AIFWCLKSRC,WCLK Source Selection"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
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newline
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bitfld.long 0x00 2. "WCLK_INV,Inverts WCLK source (pad or internal) when set.0: Not inverted1: Inverted" "Not inverted,Inverted"
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newline
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bitfld.long 0x00 0.--1. "WCLK_SRC,Selects WCLK source for AIF (should be the same as the BCLK source)" "None ('0'),External WCLK generator from pad,Internal WCLK generator from module PRCM,Not supported. Will give same WCLK as 'NONE'.."
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line.long 0x04 "AIFDMACFG,DMA Buffer Size Configuration"
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x04 0.--7. 1. "END_FRAME_IDX,Defines the length of the DMA buffer"
|
|
line.long 0x08 "AIFDIRCFG,Pin Direction"
|
|
hexmask.long 0x08 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 4.--5. "AD1,Configures the AD1 audio data pin usage:0x3: Reserved" "Not in use (disabled),Input mode,Output mode,?"
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|
newline
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rbitfld.long 0x08 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x08 0.--1. "AD0,Configures the AD0 audio data pin usage:0x3: Reserved" "Not in use (disabled),Input mode,Output mode,?"
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line.long 0x0C "AIFFMTCFG,Serial Interface Format Configuration"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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abitfld.long 0x0C 8.--15. "DATA_DELAY,The number of BCLK periods between a WCLK edge and MSB of the first word in a phase:0x00: LJF and DSP" "0x00=LJF and DSP format,0x01=I2S and DSP format,0x02=RJF format,0xFF=RJF format"
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newline
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bitfld.long 0x0C 7. "MEM_LEN_24,The size of each word stored to or loaded from memory" "16-bit (one 16 bit access per sample),24-bit (one 8 bit and one 16 bit locked access.."
|
|
newline
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bitfld.long 0x0C 6. "SMPL_EDGE,On the serial audio interface data (and wclk) is sampled and clocked out on opposite edges of BCLK" "Data is sampled on the negative edge and clocked..,Data is sampled on the positive edge and clocked.."
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newline
|
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bitfld.long 0x0C 5. "DUAL_PHASE,Selects dual- or single-phase format.0: Single-phase: DSP format1" "Single-phase,Dual-phase"
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|
newline
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bitfld.long 0x0C 0.--4. "WORD_LEN,Number of bits per word (8-24):In single-phase format this is the exact number of bits per word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x10 "AIFWMASK0,Word Selection Bit Mask for Pin 0"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x10 0.--7. 1. "MASK,Bit-mask indicating valid channels in a frame on AD0.In single-phase mode each bit represents one channel starting with LSB for the first word in the frame"
|
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line.long 0x14 "AIFWMASK1,Word Selection Bit Mask for Pin 1"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x14 0.--7. 1. "MASK,Bit-mask indicating valid channels in a frame on AD1.In single-phase mode each bit represents one channel starting with LSB for the first word in the frame"
|
|
line.long 0x18 "AIFWMASK2,Internal"
|
|
line.long 0x1C "AIFPWMVALUE,Audio Interface PWM Debug Value"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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abitfld.long 0x1C 0.--15. "PULSE_WIDTH,The value written to this register determines the width of the active high PWM pulse (pwm_debug) which starts together with MSB of the first output word in a DMA" "0x0000=Constant low,0x0001=Width of the pulse (number of BCLK cycles..,0xFFFE=Width of the pulse (number of BCLK cycles..,0xFFFF=Constant high"
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line.long 0x20 "AIFINPTRNEXT,DMA Input Buffer Next Pointer"
|
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line.long 0x24 "AIFINPTR,DMA Input Buffer Current Pointer"
|
|
line.long 0x28 "AIFOUTPTRNEXT,DMA Output Buffer Next Pointer"
|
|
line.long 0x2C "AIFOUTPTR,DMA Output Buffer Current Pointer"
|
|
group.long 0x34++0x37
|
|
line.long 0x00 "STMPCTL,Samplestamp Generator Control Register"
|
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 2. "OUT_RDY,Low until the output pins are ready to be started by the samplestamp generator" "0,1"
|
|
newline
|
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rbitfld.long 0x00 1. "IN_RDY,Low until the input pins are ready to be started by the samplestamp generator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STMP_EN,Enables the samplestamp generator" "0,1"
|
|
line.long 0x04 "STMPXCNTCAPT0,Captured XOSC Counter Value. Capture Channel 0"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x04 0.--15. 1. "CAPT_VALUE,The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0)"
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line.long 0x08 "STMPXPER,XOSC Period Value"
|
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x08 0.--15. 1. "VALUE,The number of 24 MHz clock cycles in the previous WCLK period (that is - the next value of the XOSC counter at the positive WCLK edge had it not been reset to 0).The value is cleared when STMPCTL.STMP_EN = 0."
|
|
line.long 0x0C "STMPWCNTCAPT0,Captured WCLK Counter Value. Capture Channel 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x0C 0.--15. 1. "CAPT_VALUE,The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel 0)"
|
|
line.long 0x10 "STMPWPER,WCLK Counter Period Value"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x10 0.--15. 1. "VALUE,Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer"
|
|
line.long 0x14 "STMPINTRIG,WCLK Counter Trigger Value for Input Pins"
|
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hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
newline
|
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hexmask.long.word 0x14 0.--15. 1. "IN_START_WCNT,Compare value used to start the incoming audio streams.This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very.."
|
|
line.long 0x18 "STMPOUTTRIG,WCLK Counter Trigger Value for Output Pins"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x18 0.--15. 1. "OUT_START_WCNT,Compare value used to start the outgoing audio streams.This bit field must equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very.."
|
|
line.long 0x1C "STMPWSET,WCLK Counter Set Operation"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x1C 0.--15. 1. "VALUE,WCLK counter modification: Sets the running WCLK counter equal to the written value"
|
|
line.long 0x20 "STMPWADD,WCLK Counter Add Operation"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "VALUE_INC,WCLK counter modification: Adds the written value to the running WCLK counter"
|
|
line.long 0x24 "STMPXPERMIN,XOSC Minimum Period ValueMinimum Value of STMPXPER"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "VALUE,Each time STMPXPER is updated the value is also loaded into this register provided that the value is smaller than the current value in this register.When written the register is reset to 0xFFFF (65535) regardless of the value written.The minimum.."
|
|
line.long 0x28 "STMPWCNT,Current Value of WCNT"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "CURR_VALUE,Current value of the WCLK counter"
|
|
line.long 0x2C "STMPXCNT,Current Value of XCNT"
|
|
hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x2C 0.--15. 1. "CURR_VALUE,Current value of the XOSC counter latched when reading STMPWCNT"
|
|
line.long 0x30 "STMPXCNTCAPT1,Internal"
|
|
hexmask.long.word 0x30 16.--31. 1. "RESERVED16,Internal"
|
|
newline
|
|
hexmask.long.word 0x30 0.--15. 1. "CAPT_VALUE,Internal"
|
|
line.long 0x34 "STMPWCNTCAPT1,Internal"
|
|
hexmask.long.word 0x34 16.--31. 1. "RESERVED16,Internal"
|
|
newline
|
|
hexmask.long.word 0x34 0.--15. 1. "CAPT_VALUE,Internal"
|
|
group.long 0x70++0x0F
|
|
line.long 0x00 "IRQMASK,Interrupt Mask RegisterSelects mask states of the flags in IRQFLAGS that contribute to the I2S_IRQ event"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 5. "AIF_DMA_IN,IRQFLAGS.AIF_DMA_IN interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "AIF_DMA_OUT,IRQFLAGS.AIF_DMA_OUT interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "WCLK_TIMEOUT,IRQFLAGS.WCLK_TIMEOUT interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 2. "BUS_ERR,IRQFLAGS.BUS_ERR interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
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bitfld.long 0x00 1. "WCLK_ERR,IRQFLAGS.WCLK_ERR interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 0. "PTR_ERR,IRQFLAGS.PTR_ERR interrupt mask.0: Disable1: Enable" "Disable,Enable"
|
|
line.long 0x04 "IRQFLAGS,Raw Interrupt Status Register"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "AIF_DMA_IN,Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT) see description of AIFINPTRNEXT register for details" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "AIF_DMA_OUT,Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTRNEXT) see description of AIFOUTPTRNEXT register for details" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "WCLK_TIMEOUT,Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "BUS_ERR,Set when a DMA operation is not completed in time (that is audio output buffer underflow or audio input buffer overflow)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "WCLK_ERR,Set when: - An unexpected WCLK edge occurs during the data delay period of a phase" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "PTR_ERR,Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time" "0,1"
|
|
line.long 0x08 "IRQSET,Interrupt Set Register"
|
|
hexmask.long 0x08 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 5. "AIF_DMA_IN," "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "AIF_DMA_OUT," "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "WCLK_TIMEOUT," "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "BUS_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "WCLK_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PTR_ERR," "0,1"
|
|
line.long 0x0C "IRQCLR,Interrupt Clear Register"
|
|
hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 5. "AIF_DMA_IN," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "AIF_DMA_OUT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "WCLK_TIMEOUT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "BUS_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "WCLK_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "PTR_ERR," "0,1"
|
|
tree.end
|
|
tree "IOC"
|
|
base ad:0x40081000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IOCFG0,Configuration of DIO0"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO0Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO1"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO1Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
repeat 15. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO17"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO17Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
repeat 15. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO32"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO32Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "IOCFG43,Configuration of DIO43"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "EDGE_IRQ_EN,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO43Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
tree.end
|
|
tree "PKA"
|
|
base ad:0x40025000
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "APTR,PKA Vector A AddressDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED11,Set to zero on write ignore on read"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "APTR,This register specifies the location of vector A within the PKA RAM"
|
|
line.long 0x04 "BPTR,PKA Vector B AddressDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
|
hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED11,Set to zero on write ignore on read"
|
|
newline
|
|
hexmask.long.word 0x04 0.--10. 1. "BPTR,This register specifies the location of vector B within the PKA RAM"
|
|
line.long 0x08 "CPTR,PKA Vector C AddressDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
|
hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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hexmask.long.word 0x08 0.--10. 1. "CPTR,This register specifies the location of vector C within the PKA RAM"
|
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line.long 0x0C "DPTR,PKA Vector D AddressDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
|
hexmask.long.tbyte 0x0C 11.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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hexmask.long.word 0x0C 0.--10. 1. "DPTR,This register specifies the location of vector D within the PKA RAM"
|
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line.long 0x10 "ALENGTH,PKA Vector A LengthDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
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hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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hexmask.long.word 0x10 0.--8. 1. "ALENGTH,This register specifies the length (in 32-bit words) of Vector A"
|
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line.long 0x14 "BLENGTH,PKA Vector B LengthDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
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hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED11,Set to zero on write ignore on read"
|
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hexmask.long.word 0x14 0.--8. 1. "BLENGTH,This register specifies the length (in 32-bit words) of Vector B"
|
|
line.long 0x18 "SHIFT,PKA Bit Shift ValueFor basic PKCP operations. modifying the contents of this register is made impossible while the operation is being performed"
|
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hexmask.long 0x18 5.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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bitfld.long 0x18 0.--4. "NUM_BITS_TO_SHIFT,This register specifies the number of bits to shift the input vector (in the range 0-31) during a Rshift or Lshift operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x1C "FUNCTION,PKA FunctionThis register contains the control bits to start basic PKCP as well as complex sequencer operations"
|
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hexmask.long.byte 0x1C 25.--31. 1. "RESERVED25,Set to zero on write ignore on read"
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bitfld.long 0x1C 24. "STALL_RESULT,When written with a 1b updating of the COMPARE bit MSW and DIVMSW registers as well as resetting the run bit is stalled beyond the point that a running operation is actually finished" "0,1"
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hexmask.long.byte 0x1C 16.--23. 1. "RESERVED16,Set to zero on write ignore on read"
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bitfld.long 0x1C 15. "RUN,The host sets this bit to instruct the PKA module to begin processing the basic PKCP or complex sequencer operation" "0,1"
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bitfld.long 0x1C 12.--14. "SEQUENCER_OPERATIONS,These bits select the complex sequencer operation to perform" "None,ExpMod-CRT,ECmontMUL,ECC-ADD (if available in firmware otherwise..,ExpMod-ACT2,ECC-MUL (if available in firmware otherwise..,ExpMod-variable,ModInv (if available in firmware otherwise.."
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bitfld.long 0x1C 11. "COPY,Perform copy operation" "0,1"
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bitfld.long 0x1C 10. "COMPARE,Perform compare operation" "0,1"
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bitfld.long 0x1C 9. "MODULO,Perform modulo operation" "0,1"
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bitfld.long 0x1C 8. "DIVIDE,Perform divide operation" "0,1"
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bitfld.long 0x1C 7. "LSHIFT,Perform left shift operation" "0,1"
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bitfld.long 0x1C 6. "RSHIFT,Perform right shift operation" "0,1"
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bitfld.long 0x1C 5. "SUBTRACT,Perform subtract operation" "0,1"
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bitfld.long 0x1C 4. "ADD,Perform add operation" "0,1"
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bitfld.long 0x1C 3. "MS_ONE,Loads the location of the Most Significant one bit within the result word indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS register - can only be used with basic PKCP operations except for Divide Modulo and Compare" "0,1"
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bitfld.long 0x1C 2. "RESERVED2,Set to zero on write ignore on read" "0,1"
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bitfld.long 0x1C 1. "ADDSUB,Perform combined add/subtract operation" "0,1"
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bitfld.long 0x1C 0. "MULTIPLY,Perform multiply operation" "0,1"
|
|
line.long 0x20 "COMPARE,PKA compare resultThis register provides the result of a basic PKCP compare operation"
|
|
hexmask.long 0x20 3.--31. 1. "RESERVED3,Ignore on read"
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bitfld.long 0x20 2. "A_GREATER_THAN_B,Vector_A is greater than Vector_B" "0,1"
|
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bitfld.long 0x20 1. "A_LESS_THAN_B,Vector_A is less than Vector_B" "0,1"
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bitfld.long 0x20 0. "A_EQUALS_B,Vector_A is equal to Vector_B" "0,1"
|
|
line.long 0x24 "MSW,PKA most-significant-word of result vectorThis register indicates the (word) address in the PKA RAM where the most significant nonzero 32-bit word of the result is stored"
|
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Ignore on read"
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bitfld.long 0x24 15. "RESULT_IS_ZERO,The result vector is all zeroes ignore the address returned in bits [10:0]" "0,1"
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bitfld.long 0x24 11.--14. "RESERVED11,Ignore on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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hexmask.long.word 0x24 0.--10. 1. "MSW_ADDRESS,Address of the most-significant nonzero 32-bit word of the result vector in PKA RAM"
|
|
line.long 0x28 "DIVMSW,PKA most-significant-word of divide remainderThis register indicates the (32-bit word) address in the PKA RAM where the most significant nonzero 32-bit word of the remainder result for the basic divide and modulo operations is stored"
|
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hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Ignore on read"
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bitfld.long 0x28 15. "RESULT_IS_ZERO,The result vector is all zeroes ignore the address returned in bits [10:0]" "0,1"
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bitfld.long 0x28 11.--14. "RESERVED11,Ignore on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x28 0.--10. 1. "MSW_ADDRESS,Address of the most significant nonzero 32-bit word of the remainder result vector in PKA RAM"
|
|
group.long 0xC8++0x03
|
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line.long 0x00 "SEQCTRL,PKA sequencer control and status registerThe sequencer is interfaced with the outside world through a single control and status register"
|
|
bitfld.long 0x00 31. "RESET,Option program ROM: Reset value = 0" "0,1"
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hexmask.long.word 0x00 16.--30. 1. "RESERVED16,Set to zero on write ignore on read"
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hexmask.long.byte 0x00 8.--15. 1. "SEQUENCER_STAT,These read-only bits can be used by the sequencer to communicate status to the outside world"
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hexmask.long.byte 0x00 0.--7. 1. "SW_CONTROL_STAT,These bits can be used by software to trigger sequencer operations"
|
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rgroup.long 0xF4++0x0B
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line.long 0x00 "OPTIONS,PKA hardware options registerThis register provides the host with a means to determine the hardware configuration implemented in this PKA engine. focused on options that have an effect on software interacting with the module."
|
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Ignore on read"
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|
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bitfld.long 0x00 11. "INT_MASKING,Interrupt Masking" "indicates that the main interrupt output (bit..,indicates that interrupt masking logic is.."
|
|
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bitfld.long 0x00 8.--10. "PROTECTION_OPTION,Protection Option" "indicates no additional protection against side..,indicates the SCAP option,Reserved,indicates the PROT option;,?..."
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bitfld.long 0x00 7. "PROGRAM_RAM,Program RAM" "indicates sequencer program storage in ROM,indicates sequencer program storage in RAM"
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bitfld.long 0x00 5.--6. "SEQUENCER_CONFIGURATION,Sequencer Configuration" "Reserved,Indicates a standard..,Reserved,Reserved"
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bitfld.long 0x00 2.--4. "RESERVED2,Ignore on read" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--1. "PKCP_CONFIGURATION,PKCP Configuration" "Reserved,Indicates a PKCP with a 16x16 multiplier,indicates a PKCP with a 32x32 multiplier,Reserved"
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line.long 0x04 "FWREV,PKA firmware revision and capabilities registerThis register allows the host access to the internal firmware revision number of the PKA Engine for software driver matching and diagnostic purposes"
|
|
bitfld.long 0x04 28.--31. "FW_CAPABILITIES,Firmware Capabilities 4-bit binary encoding for the functionality implemented in the firmware" "indicates basic ModExp with/without CRT,adds Modular Inversion,value 2 adds Modular Inversion and ECC operations,?..."
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bitfld.long 0x04 24.--27. "MAJOR_FW_REVISION,4-bit binary encoding of the major firmware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 20.--23. "MINOR_FW_REVISION,4-bit binary encoding of the minor firmware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "FW_PATCH_LEVEL,4-bit binary encoding of the firmware patch level initial release will carry value zeroPatches are used to remove bugs without changing the functionality or interface of a module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x04 0.--15. 1. "RESERVED0,Ignore on read"
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|
line.long 0x08 "HWREV,PKA hardware revision registerThis register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes"
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bitfld.long 0x08 28.--31. "RESERVED28,Ignore on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 24.--27. "MAJOR_HW_REVISION,4-bit binary encoding of the major hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x08 20.--23. "MINOR_HW_REVISION,4-bit binary encoding of the minor hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "HW_PATCH_LEVEL,4-bit binary encoding of the hardware patch level initial release will carry value zeroPatches are used to remove bugs without changing the functionality or interface of a module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "COMPLEMENT_OF_BASIC_EIP_NUMBER,Bit-by-bit logic complement of bits [7:0] EIP-28 gives 0xE3"
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|
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hexmask.long.byte 0x08 0.--7. 1. "BASIC_EIP_NUMBER,8-bit binary encoding of the EIP number EIP-28 gives 0x1C"
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tree.end
|
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tree "PKA_INT"
|
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base ad:0x40027000
|
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group.long 0x00++0x03
|
|
line.long 0x00 "RESERVED_0,Software should not rely on the value of a reserved"
|
|
group.long 0xFF8++0x07
|
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line.long 0x00 "OPTIONS,PKA Options register"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED11,Ignore on read"
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rbitfld.long 0x00 10. "AIC_PRESENT,When set to '1' indicates that an EIP201 AIC is included in the EIP150" "0,1"
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rbitfld.long 0x00 9. "EIP76_PRESENT,When set to '1' indicates that the EIP76 TRNG is included in the EIP150" "0,1"
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rbitfld.long 0x00 8. "EIP28_PRESENT,When set to '1' indicates that the EIP28 PKA is included in the EIP150" "0,1"
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|
rbitfld.long 0x00 4.--7. "RESERVED4,Ignore on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rbitfld.long 0x00 3. "AXI_INTERFACE,When set to '1' indicates that the EIP150 is equipped with a AXI interface" "0,1"
|
|
rbitfld.long 0x00 2. "AHB_IS_ASYNC,When set to '1' indicates that AHB interface is asynchronous Only applicable when AHB_INTERFACE is 1" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AHB_INTERFACE,When set to '1' indicates that the EIP150 is equipped with a AHB interface" "0,1"
|
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bitfld.long 0x00 0. "PLB_INTERFACE,When set to '1' indicates that the EIP150 is equipped with a PLB interface" "0,1"
|
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line.long 0x04 "REVISION,PKA hardware revision registerThis register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes"
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bitfld.long 0x04 28.--31. "RESERVED28,These bits should be ignored on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 24.--27. "MAJOR_REVISION,These bits encode the major version number for this module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 20.--23. "MINOR_REVISION,These bits encode the minor version number for this module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "PATCH_LEVEL,These bits encode the hardware patch level for this module they start at value 0 on the first release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x04 8.--15. 1. "COMP_EIP_NUM,These bits simply contain the complement of bits [7:0] used by a driver to ascertain that the EIP150 revision register is indeed"
|
|
hexmask.long.byte 0x04 0.--7. 1. "EIP_NUM,These bits encode the AuthenTec EIP number for the EIP150"
|
|
tree.end
|
|
tree "PRCM"
|
|
base ad:0x40082000
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "INFRCLKDIVR,Infrastructure Clock Division Factor For Run Mode"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
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line.long 0x04 "INFRCLKDIVS,Infrastructure Clock Division Factor For Sleep Mode"
|
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hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
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line.long 0x08 "INFRCLKDIVDS,Infrastructure Clock Division Factor For DeepSleep Mode"
|
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
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line.long 0x0C "VDCTL,MCU Voltage Domain Control"
|
|
hexmask.long 0x0C 1.--31. 1. "SPARE1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x0C 0. "ULDO,Request PMCTL to switch to uLDO.0: No request1: Assert request when possibleThe bit will have no effect before the following requirements are met:1" "No request,Assert request when.."
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "CLKLOADCTL,Load PRCM Settings To CLKCTRL Power Domain"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 1. "LOAD_DONE,Status of LOAD" "One or more registers have been write accessed..,No registers are write accessed after last LOAD"
|
|
newline
|
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bitfld.long 0x00 0. "LOAD," "No action,Load settings to CLKCTRL"
|
|
line.long 0x04 "RFCCLKG,RFC Clock Gate"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 0. "CLK_EN," "Disable Clock,Enable clock if RFC power domain is.."
|
|
line.long 0x08 "VIMSCLKG,VIMS Clock Gate"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 0.--1. "CLK_EN," "0,1,2,3"
|
|
group.long 0x3C++0x53
|
|
line.long 0x00 "SECDMACLKGR,SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 24. "DMA_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
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rbitfld.long 0x00 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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newline
|
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bitfld.long 0x00 19. "PKA_ZERIOZE_RESET_N,Zeroization logic hardware reset.0: pka_zeroize logic inactive.1: pka_zeroize of memory is enabled" "pka_zeroize logic inactive,pka_zeroize of memory is enabled"
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newline
|
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bitfld.long 0x00 18. "PKA_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
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bitfld.long 0x00 17. "TRNG_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
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bitfld.long 0x00 16. "CRYPTO_AM_CLK_EN," "No force,Force clock on for all.."
|
|
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|
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hexmask.long.byte 0x00 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
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rbitfld.long 0x00 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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newline
|
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bitfld.long 0x00 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
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bitfld.long 0x00 1. "TRNG_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
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bitfld.long 0x00 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x04 "SECDMACLKGS,SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode"
|
|
hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
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rbitfld.long 0x04 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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newline
|
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bitfld.long 0x04 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x04 1. "TRNG_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
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bitfld.long 0x04 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x08 "SECDMACLKGDS,SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode"
|
|
hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x08 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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newline
|
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bitfld.long 0x08 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x08 1. "TRNG_CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
newline
|
|
bitfld.long 0x08 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
line.long 0x0C "GPIOCLKGR,GPIO Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 8. "AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x10 "GPIOCLKGS,GPIO Clock Gate For Sleep Mode"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x14 "GPIOCLKGDS,GPIO Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x18 "GPTCLKGR,GPT Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "AM_CLK_EN,Each bit below has the following meaning:0: No force1: Force clock on for all modes (Run Sleep and Deep Sleep)Overrides CLK_EN GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled.ENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD.." "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x18 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clock Can be forced on by AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clock Can be forced on by..,?..."
|
|
line.long 0x1C "GPTCLKGS,GPT Clock Gate For Sleep Mode"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clockCan be forced on by GPTCLKGR.AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x20 "GPTCLKGDS,GPT Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x20 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clockCan be forced on by GPTCLKGR.AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x24 "I2CCLKGR,I2C Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 8.--9. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x24 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x24 0.--1. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x28 "I2CCLKGS,I2C Clock Gate For Sleep Mode"
|
|
hexmask.long 0x28 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0.--1. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x2C "I2CCLKGDS,I2C Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x2C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x2C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x30 "UARTCLKGR,UART Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x30 8.--11. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x30 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x30 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x34 "UARTCLKGS,UART Clock Gate For Sleep Mode"
|
|
hexmask.long 0x34 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x34 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x38 "UARTCLKGDS,UART Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x38 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x38 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x3C "SSICLKGR,SSI Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x3C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x3C 8.--11. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x3C 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x3C 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x40 "SSICLKGS,SSI Clock Gate For Sleep Mode"
|
|
hexmask.long 0x40 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x40 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x44 "SSICLKGDS,SSI Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x44 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x44 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x48 "I2SCLKGR,I2S Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x48 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x48 8. "AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x48 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x48 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x4C "I2SCLKGS,I2S Clock Gate For Sleep Mode"
|
|
hexmask.long 0x4C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x4C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x50 "I2SCLKGDS,I2S Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x50 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x50 0. "CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
group.long 0xB4++0x2B
|
|
line.long 0x00 "SYSBUSCLKDIV,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?"
|
|
line.long 0x04 "CPUCLKDIV,Internal"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Internal"
|
|
newline
|
|
bitfld.long 0x04 0. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
line.long 0x08 "PERBUSCPUCLKDIV,Internal"
|
|
hexmask.long 0x08 4.--31. 1. "RESERVED4,Internal"
|
|
newline
|
|
bitfld.long 0x08 0.--3. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.long 0x0C "PERBUSDMACLKDIV,Internal"
|
|
line.long 0x10 "PERDMACLKDIV,Internal"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Internal"
|
|
newline
|
|
bitfld.long 0x10 0.--3. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.long 0x14 "I2SBCLKSEL,I2S Clock Control"
|
|
hexmask.long 0x14 1.--31. 1. "SPARE1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "SRC,BCLK source selector0: Use external BCLK1: Use internally generated clockFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Use external BCLK,Use internally generated clockFor changes to.."
|
|
line.long 0x18 "GPTCLKDIV,GPT Scalar"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "RATIO,Scalar used for GPTs" "Divide by 1,Divide by 2,Divide by 4,Divide by 8,Divide by 16,Divide by 32,Divide by 64,Divide by 128,Divide by 256,?,?,?,?,?,?,?"
|
|
line.long 0x1C "I2SCLKCTL,I2S Clock Control"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 3. "SMPL_ON_POSEDGE,On the I2S serial interface data and WCLK is sampled and clocked out on opposite edges of BCLK" "data and WCLK are sampled on the negative edge..,data and WCLK are sampled on the positive edge.."
|
|
newline
|
|
bitfld.long 0x1C 1.--2. "WCLK_PHASE,Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV)" "Single phase,Dual phase,User Defined,Reserved/UndefinedFor changes to.."
|
|
newline
|
|
bitfld.long 0x1C 0. "EN," "MCLK BCLK and WCLK will be static low,Enables the generation of MCLK BCLK and WCLKFor.."
|
|
line.long 0x20 "I2SMCLKDIV,MCLK Division Ratio"
|
|
hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--9. 1. "MDIV,An unsigned factor of the division ratio used to generate MCLK [2-1024]:MCLK = MCUCLK/MDIV[Hz]MCUCLK is 48MHz.A value of 0 is interpreted as 1024.A value of 1 is invalid.If MDIV is odd the low phase of the clock is one MCUCLK period longer than the.."
|
|
line.long 0x24 "I2SBCLKDIV,BCLK Division Ratio"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--9. 1. "BDIV,An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]:BCLK = MCUCLK/BDIV[Hz]MCUCLK is 48MHz.A value of 0 is interpreted as 1024.A value of 1 is invalid.If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0 the low phase of the.."
|
|
line.long 0x28 "I2SWCLKDIV,WCLK Division Ratio"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "WDIV,If I2SCLKCTL.WCLK_PHASE = 0 Single phase.WCLK is high one BCLK period and low WDIV[9:0] (unsigned [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]MCUCLK is 48MHz.If I2SCLKCTL.WCLK_PHASE = 1 Dual phase.Each phase on WCLK (50% duty.."
|
|
group.long 0xF0++0x1B
|
|
line.long 0x00 "RESETSECDMA,RESET For SEC (PKA And TRNG And CRYPTO) And UDMA"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA,Write 1 to reset" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "PKA,Write 1 to reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRNG,Write 1 to reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CRYPTO,Write 1 to reset" "0,1"
|
|
line.long 0x04 "RESETGPIO,RESET For GPIO IPs"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "GPIO," "No action,Reset GPIO"
|
|
line.long 0x08 "RESETGPT,RESET For GPT Ips"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "GPT," "No action,Reset all GPTs"
|
|
line.long 0x0C "RESETI2C,RESET For I2C IPs"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "I2C1," "No action,Reset I2C1"
|
|
newline
|
|
bitfld.long 0x0C 0. "I2C0," "No action,Reset I2C0"
|
|
line.long 0x10 "RESETUART,RESET For UART IPs"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 3. "UART3," "No action,Reset UART3"
|
|
newline
|
|
bitfld.long 0x10 2. "UART2," "No action,Reset UART2"
|
|
newline
|
|
bitfld.long 0x10 1. "UART1," "No action,Reset UART1"
|
|
newline
|
|
bitfld.long 0x10 0. "UART0," "No action,Reset UART0"
|
|
line.long 0x14 "RESETSSI,RESET For SSI IPs"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3. "SSI3," "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "SSI2," "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "SSI1," "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SSI0," "0,1"
|
|
line.long 0x18 "RESETI2S,RESET For I2S IP"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 0. "I2S," "No action,Reset module"
|
|
group.long 0x12C++0x0F
|
|
line.long 0x00 "PDCTL0,Power Domain Control"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "PERIPH_ON,PERIPH Power domain.0: PERIPH power domain is powered down1: PERIPH power domain is powered up" "PERIPH power domain is powered down,PERIPH power domain is powered up"
|
|
newline
|
|
bitfld.long 0x00 1. "SERIAL_ON,SERIAL Power domain.0: SERIAL power domain is powered down1: SERIAL power domain is powered up" "SERIAL power domain is powered down,SERIAL power domain is powered up"
|
|
newline
|
|
bitfld.long 0x00 0. "RFC_ON," "RFC power domain powered off if also..,RFC power domain powered on"
|
|
line.long 0x04 "PDCTL0RFC,RFC Power Domain Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,Alias for PDCTL0.RFC_ON" "0,1"
|
|
line.long 0x08 "PDCTL0SERIAL,SERIAL Power Domain Control"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,Alias for PDCTL0.SERIAL_ON" "0,1"
|
|
line.long 0x0C "PDCTL0PERIPH,PERIPH Power Domain Control"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,Alias for PDCTL0.PERIPH_ON" "0,1"
|
|
rgroup.long 0x140++0x0F
|
|
line.long 0x00 "PDSTAT0,Power Domain Status"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "PERIPH_ON,PERIPH Power domain.0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
newline
|
|
bitfld.long 0x00 1. "SERIAL_ON,SERIAL Power domain.0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
newline
|
|
bitfld.long 0x00 0. "RFC_ON,RFC Power domain0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
line.long 0x04 "PDSTAT0RFC,RFC Power Domain Status"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,Alias for PDSTAT0.RFC_ON" "0,1"
|
|
line.long 0x08 "PDSTAT0SERIAL,SERIAL Power Domain Status"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,Alias for PDSTAT0.SERIAL_ON" "0,1"
|
|
line.long 0x0C "PDSTAT0PERIPH,PERIPH Power Domain Status"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,Alias for PDSTAT0.PERIPH_ON" "0,1"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "PDCTL1,Power Domain Control"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "VIMS_MODE," "VIMS power domain is only powered when CPU power..,VIMS power domain is powered whenever the BUS..,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "RFC_ON," "RFC power domain powered off if also..,RFC power domain powered on Bit shall be used by.."
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_ON," "Causes a power down of the CPU power domain when..,Initiates power-on of the CPU power domain.This.."
|
|
newline
|
|
rbitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
group.long 0x184++0x0B
|
|
line.long 0x00 "PDCTL1CPU,CPU Power Domain Direct Control"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "ON,This is an alias for PDCTL1.CPU_ON" "0,1"
|
|
line.long 0x04 "PDCTL1RFC,RFC Power Domain Direct Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,This is an alias for PDCTL1.RFC_ON" "0,1"
|
|
line.long 0x08 "PDCTL1VIMS,VIMS Mode Direct Control"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "MODE,This is an alias for PDCTL1.VIMS_MODE" "0,1,2,3"
|
|
rgroup.long 0x194++0x13
|
|
line.long 0x00 "PDSTAT1,Power Manager Status"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4. "BUS_ON," "BUS domain not accessible,BUS domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 3. "VIMS_ON," "VIMS domain not accessible,VIMS domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 2. "RFC_ON," "RFC domain not accessible,RFC domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_ON," "CPU and BUS domain not accessible,CPU and BUS domains are both currently accessible"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x04 "PDSTAT1BUS,BUS Power Domain Direct Read Status"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,This is an alias for PDSTAT1.BUS_ON" "0,1"
|
|
line.long 0x08 "PDSTAT1RFC,RFC Power Domain Direct Read Status"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,This is an alias for PDSTAT1.RFC_ON" "0,1"
|
|
line.long 0x0C "PDSTAT1CPU,CPU Power Domain Direct Read Status"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,This is an alias for PDSTAT1.CPU_ON" "0,1"
|
|
line.long 0x10 "PDSTAT1VIMS,VIMS Mode Direct Read Status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "ON,This is an alias for PDSTAT1.VIMS_ON" "0,1"
|
|
group.long 0x1CC++0x0B
|
|
line.long 0x00 "RFCBITS,Control To RFC"
|
|
line.long 0x04 "RFCMODESEL,Selected RFC Mode"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "CURR,Selects the set of commands that the RFC will accept" "Select Mode 0,Select Mode 1,Select Mode 2,Select Mode 3,Select Mode 4,Select Mode 5,Select Mode 6,Select Mode 7"
|
|
line.long 0x08 "RFCMODEHWOPT,Allowed RFC Modes"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "AVAIL,Permitted RFC modes"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "PWRPROFSTAT,Power Profiler Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VALUE,SW can use these bits to timestamp the application"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "MCUSRAMCFG,MCU SRAM configuration"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "PARITY_EN,Parity enable0: Parity disabled Parity section available as GPRAM1: Parity enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BM_OFF,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PAGE,Page Mode select0: Page Mode disabled" "Page Mode disabled,Page Mode enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "PGS,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BM,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PCH_F,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PCH_L,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "RAMRETEN,Memory Retention Control"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3. "RFCULL," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RFC," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "VIMS," "VIMS,VIMS,?..."
|
|
group.long 0x290++0x0B
|
|
line.long 0x00 "OSCIMSC,Oscillator Interrupt Mask Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "HFSRCPENDIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LFSRCDONEIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "XOSCDLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "XOSCLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RCOSCDLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RCOSCLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "XOSCHFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RCOSCHFIM," "0,1"
|
|
line.long 0x04 "OSCRIS,Oscillator Raw Interrupt Status"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 7. "HFSRCPENDRIS,SCLK_HF source switch pending interrupt.After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source change request then the requested SCLK_HF source will be enabled and qualified" "Indicates SCLK_HF source is not ready to be..,Indicates SCLK_HF source is ready to be.."
|
|
newline
|
|
bitfld.long 0x04 6. "LFSRCDONERIS,SCLK_LF source switch done.The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that the SCLK_LF source shall be changed" "Indicates SCLK_LF source switch has not completed,Indicates SCLK_LF source switch has completed.."
|
|
newline
|
|
bitfld.long 0x04 5. "XOSCDLFRIS,The XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF" "XOSCDLF has not been qualified,XOSCDLF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 4. "XOSCLFRIS,The XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator has been qualified with respect to frequency" "XOSCLF has not been qualified,XOSCLF has been qualified Interrupt is qualified.."
|
|
newline
|
|
bitfld.long 0x04 3. "RCOSCDLFRIS,The RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF" "RCOSCDLF has not been qualified,RCOSCDLF has been qualifiedInterrupt is.."
|
|
newline
|
|
bitfld.long 0x04 2. "RCOSCLFRIS,The RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF oscillator has been qualified with respect to frequency" "RCOSCLF has not been qualified,RCOSCLF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 1. "XOSCHFRIS,The XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been qualified for use as a clock source" "XOSC_HF has not been qualified,XOSC_HF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 0. "RCOSCHFRIS,The RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been qualified for use as a clock source When the RCOSCHFRIS interrupt is high the oscillator is qualified and will be used as a clock source when selected" "RCOSC_HF has not been qualified,RCOSC_HF has been qualifiedInterrupt is.."
|
|
line.long 0x08 "OSCICR,Oscillator Raw Interrupt Clear"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 7. "HFSRCPENDC,Writing 1 to this field clears the HFSRCPEND raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. "LFSRCDONEC,Writing 1 to this field clears the LFSRCDONE raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "XOSCDLFC,Writing 1 to this field clears the XOSCDLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "XOSCLFC,Writing 1 to this field clears the XOSCLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "RCOSCDLFC,Writing 1 to this field clears the RCOSCDLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "RCOSCLFC,Writing 1 to this field clears the RCOSCLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "XOSCHFC,Writing 1 to this field clears the XOSCHF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "RCOSCHFC,Writing 1 to this field clears the RCOSCHF raw interrupt status" "0,1"
|
|
group.long 0x2B0++0x17
|
|
line.long 0x00 "NVMNSCADDR,NVM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x00 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "BOUNDARY,Non-Secure callable boundary address"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "NVMNSADDR,NVM Non-Secure boundary Address"
|
|
rbitfld.long 0x04 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 21.--30. 1. "RESERVED21,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x04 20. "BOUNDARY_MSB,Non-Secure boundary address MSBHW controlled." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 13.--19. 1. "BOUNDARY,Non-Secure boundary address.Writing this field when BUSSECCFG.VALID is set may result in undefined behavior."
|
|
newline
|
|
hexmask.long.word 0x04 0.--12. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x08 "SRAMNSCADDR,SRAM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x08 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x08 19.--30. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 10.--18. 1. "BOUNDARY,Non-Secure callable boundary address"
|
|
newline
|
|
hexmask.long.word 0x08 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "SRAMNSADDR,SRAM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x0C 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0C 19.--30. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x0C 10.--18. 1. "BOUNDARY,Non-Secure boundary address.Writing this field when BUSSECCFG.VALID is set may result in undefined behavior."
|
|
newline
|
|
hexmask.long.word 0x0C 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x10 "BUSSECCFG,BUS Secuirty Configuration Register"
|
|
bitfld.long 0x10 31. "VALID,Security configuration validRegisters that needs to be followed by VALID before settings being applied are:- NVMNSCADDR- NVMNSADDR- SRAMNSCADDR- SRAMNSADDR- BUSSECCFG- CPULOCK" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x10 8.--30. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "BUS_CFG,Bus interconnect security and firewall configuration"
|
|
line.long 0x14 "CPULOCK,CPU Lock Register"
|
|
rbitfld.long 0x14 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long 0x14 5.--30. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 4. "LOCKNSVTOR,When set will lock non-secure vector table base addressWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LOCKSVTAIRCR,When set will lock- Secure vector table base address- Secure interrupt priority- Busfault- Hardfault NMI security targetWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "LOCKSAU,When set will lock SAU regionsWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LOCKNSMPU,When set will lock non-secure MPUWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "LOCKSMPU,When set will lock secure MPUWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
tree.end
|
|
tree "RFC"
|
|
tree "RFC_DBELL"
|
|
base ad:0x40041000
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "CMDR,Doorbell Command Register"
|
|
line.long 0x04 "CMDSTA,Doorbell Command Status Register"
|
|
line.long 0x08 "RFHWIFG,Interrupt Flags From RF Hardware Modules"
|
|
hexmask.long.word 0x08 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 19. "RATCH7,Radio timer channel 7 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 18. "RATCH6,Radio timer channel 6 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 17. "RATCH5,Radio timer channel 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. "RATCH4,Radio timer channel 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 15. "RATCH3,Radio timer channel 3 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 14. "RATCH2,Radio timer channel 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 13. "RATCH1,Radio timer channel 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "RATCH0,Radio timer channel 0 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 11. "RFESOFT2,RF engine software defined interrupt 2 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. "RFESOFT1,RF engine software defined interrupt 1 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. "RFESOFT0,RF engine software defined interrupt 0 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "RFEDONE,RF engine command done interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. "TRCTK,Debug tracer system tick interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "MDMSOFT,Modem software defined interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "MDMOUT,Modem FIFO output interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "MDMIN,Modem FIFO input interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "MDMDONE,Modem command done interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "FSCA,Frequency synthesizer calibration accelerator interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x0C "RFHWIEN,Interrupt Enable For RF Hardware Modules"
|
|
hexmask.long.word 0x0C 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 19. "RATCH7,Interrupt enable for RFHWIFG.RATCH7" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 18. "RATCH6,Interrupt enable for RFHWIFG.RATCH6" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 17. "RATCH5,Interrupt enable for RFHWIFG.RATCH5" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. "RATCH4,Interrupt enable for RFHWIFG.RATCH4" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 15. "RATCH3,Interrupt enable for RFHWIFG.RATCH3" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 14. "RATCH2,Interrupt enable for RFHWIFG.RATCH2" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 13. "RATCH1,Interrupt enable for RFHWIFG.RATCH1" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 12. "RATCH0,Interrupt enable for RFHWIFG.RATCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 11. "RFESOFT2,Interrupt enable for RFHWIFG.RFESOFT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 10. "RFESOFT1,Interrupt enable for RFHWIFG.RFESOFT1" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RFESOFT0,Interrupt enable for RFHWIFG.RFESOFT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "RFEDONE,Interrupt enable for RFHWIFG.RFEDONE" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "TRCTK,Interrupt enable for RFHWIFG.TRCTK" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "MDMSOFT,Interrupt enable for RFHWIFG.MDMSOFT" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "MDMOUT,Interrupt enable for RFHWIFG.MDMOUT" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "MDMIN,Interrupt enable for RFHWIFG.MDMIN" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "MDMDONE,Interrupt enable for RFHWIFG.MDMDONE" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "FSCA,Interrupt enable for RFHWIFG.FSCA" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x10 "RFCPEIFG,Interrupt Flags For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x10 31. "INTERNAL_ERROR,Interrupt flag 31" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "BOOT_DONE,Interrupt flag 30" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "MODULES_UNLOCKED,Interrupt flag 29" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. "SYNTH_NO_LOCK,Interrupt flag 28" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "IRQ27,Interrupt flag 27" "0,1"
|
|
newline
|
|
bitfld.long 0x10 26. "RX_ABORTED,Interrupt flag 26" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "RX_N_DATA_WRITTEN,Interrupt flag 25" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "RX_DATA_WRITTEN,Interrupt flag 24" "0,1"
|
|
newline
|
|
bitfld.long 0x10 23. "RX_ENTRY_DONE,Interrupt flag 23" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "RX_BUF_FULL,Interrupt flag 22" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "RX_CTRL_ACK,Interrupt flag 21" "0,1"
|
|
newline
|
|
bitfld.long 0x10 20. "RX_CTRL,Interrupt flag 20" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "RX_EMPTY,Interrupt flag 19" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "RX_IGNORED,Interrupt flag 18" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "RX_NOK,Interrupt flag 17" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "RX_OK,Interrupt flag 16" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "IRQ15,Interrupt flag 15" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "IRQ14,Interrupt flag 14" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FG_COMMAND_STARTED,Interrupt flag 13" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "COMMAND_STARTED,Interrupt flag 12" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "TX_BUFFER_CHANGED,Interrupt flag 11" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "TX_ENTRY_DONE,Interrupt flag 10" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "TX_RETRANS,Interrupt flag 9" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "TX_CTRL_ACK_ACK,Interrupt flag 8" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "TX_CTRL_ACK,Interrupt flag 7" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "TX_CTRL,Interrupt flag 6" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "TX_ACK,Interrupt flag 5" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "TX_DONE,Interrupt flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "LAST_FG_COMMAND_DONE,Interrupt flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "FG_COMMAND_DONE,Interrupt flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "LAST_COMMAND_DONE,Interrupt flag 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "COMMAND_DONE,Interrupt flag 0" "0,1"
|
|
line.long 0x14 "RFCPEIEN,Interrupt Enable For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x14 31. "INTERNAL_ERROR,Interrupt enable for RFCPEIFG.INTERNAL_ERROR" "0,1"
|
|
newline
|
|
bitfld.long 0x14 30. "BOOT_DONE,Interrupt enable for RFCPEIFG.BOOT_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "MODULES_UNLOCKED,Interrupt enable for RFCPEIFG.MODULES_UNLOCKED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. "SYNTH_NO_LOCK,Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "IRQ27,Interrupt enable for RFCPEIFG.IRQ27" "0,1"
|
|
newline
|
|
bitfld.long 0x14 26. "RX_ABORTED,Interrupt enable for RFCPEIFG.RX_ABORTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "RX_N_DATA_WRITTEN,Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24. "RX_DATA_WRITTEN,Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN" "0,1"
|
|
newline
|
|
bitfld.long 0x14 23. "RX_ENTRY_DONE,Interrupt enable for RFCPEIFG.RX_ENTRY_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. "RX_BUF_FULL,Interrupt enable for RFCPEIFG.RX_BUF_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "RX_CTRL_ACK,Interrupt enable for RFCPEIFG.RX_CTRL_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 20. "RX_CTRL,Interrupt enable for RFCPEIFG.RX_CTRL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "RX_EMPTY,Interrupt enable for RFCPEIFG.RX_EMPTY" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "RX_IGNORED,Interrupt enable for RFCPEIFG.RX_IGNORED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 17. "RX_NOK,Interrupt enable for RFCPEIFG.RX_NOK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. "RX_OK,Interrupt enable for RFCPEIFG.RX_OK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "IRQ15,Interrupt enable for RFCPEIFG.IRQ15" "0,1"
|
|
newline
|
|
bitfld.long 0x14 14. "IRQ14,Interrupt enable for RFCPEIFG.IRQ14" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "FG_COMMAND_STARTED,Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "COMMAND_STARTED,Interrupt enable for RFCPEIFG.COMMAND_STARTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "TX_BUFFER_CHANGED,Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "TX_ENTRY_DONE,Interrupt enable for RFCPEIFG.TX_ENTRY_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "TX_RETRANS,Interrupt enable for RFCPEIFG.TX_RETRANS" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "TX_CTRL_ACK_ACK,Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "TX_CTRL_ACK,Interrupt enable for RFCPEIFG.TX_CTRL_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "TX_CTRL,Interrupt enable for RFCPEIFG.TX_CTRL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "TX_ACK,Interrupt enable for RFCPEIFG.TX_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "TX_DONE,Interrupt enable for RFCPEIFG.TX_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LAST_FG_COMMAND_DONE,Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "FG_COMMAND_DONE,Interrupt enable for RFCPEIFG.FG_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LAST_COMMAND_DONE,Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "COMMAND_DONE,Interrupt enable for RFCPEIFG.COMMAND_DONE" "0,1"
|
|
line.long 0x18 "RFCPEISL,Interrupt Vector Selection For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x18 31. "INTERNAL_ERROR,Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 30. "BOOT_DONE,Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 29. "MODULES_UNLOCKED,Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 28. "SYNTH_NO_LOCK,Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 27. "IRQ27,Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 26. "RX_ABORTED,Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 25. "RX_N_DATA_WRITTEN,Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 24. "RX_DATA_WRITTEN,Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 23. "RX_ENTRY_DONE,Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 22. "RX_BUF_FULL,Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 21. "RX_CTRL_ACK,Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 20. "RX_CTRL,Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 19. "RX_EMPTY,Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 18. "RX_IGNORED,Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 17. "RX_NOK,Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 16. "RX_OK,Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 15. "IRQ15,Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 14. "IRQ14,Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 13. "FG_COMMAND_STARTED,Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 12. "COMMAND_STARTED,Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 11. "TX_BUFFER_CHANGED,Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 10. "TX_ENTRY_DONE,Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 9. "TX_RETRANS,Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 8. "TX_CTRL_ACK_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 7. "TX_CTRL_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 6. "TX_CTRL,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 5. "TX_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 4. "TX_DONE,Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 3. "LAST_FG_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 2. "FG_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 1. "LAST_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 0. "COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
line.long 0x1C "RFACKIFG,Doorbell Command Acknowledgement Interrupt Flag"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0. "ACKFLAG,Interrupt flag for Command ACK" "0,1"
|
|
line.long 0x20 "SYSGPOCTL,RF Core General Purpose Output Control"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 12.--15. "GPOCTL3,RF Core GPO control bit 3" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 8.--11. "GPOCTL2,RF Core GPO control bit 2" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 4.--7. "GPOCTL1,RF Core GPO control bit 1" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 0.--3. "GPOCTL0,RF Core GPO control bit 0" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
tree.end
|
|
tree "RFC_PWR"
|
|
base ad:0x40040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCLKEN,RF Core Power Management and Clock Enable"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 13. "DEMOD,Enable clock to the Demodulator" "0,1"
|
|
bitfld.long 0x00 12. "MOD,Enable clock to the Modulator" "0,1"
|
|
bitfld.long 0x00 11. "IQRAM,Enable clock to IQ RAM in coherent demodulator" "0,1"
|
|
bitfld.long 0x00 10. "RFCTRC,Enable clock to the RF Core Tracer (RFCTRC) module" "0,1"
|
|
bitfld.long 0x00 9. "FSCA,Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) module" "0,1"
|
|
bitfld.long 0x00 8. "PHA,Enable clock to the Packet Handling Accelerator (PHA) module" "0,1"
|
|
bitfld.long 0x00 7. "RAT,Enable clock to the Radio Timer (RAT) module" "0,1"
|
|
bitfld.long 0x00 6. "RFERAM,Enable clock to the RF Engine RAM module" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RFE,Enable clock to the RF Engine (RFE) module" "0,1"
|
|
bitfld.long 0x00 4. "MDMRAM,Enable clock to the Modem RAM module" "0,1"
|
|
bitfld.long 0x00 3. "MDM,Enable clock to the Modem (MDM) module" "0,1"
|
|
bitfld.long 0x00 2. "CPERAM,Enable clock to the Command and Packet Engine (CPE) RAM module" "0,1"
|
|
bitfld.long 0x00 1. "CPE,Enable processor clock (hclk) to the Command and Packet Engine (CPE)" "0,1"
|
|
rbitfld.long 0x00 0. "RFC,Enable essential clocks for the RF Core interface" "0,1"
|
|
tree.end
|
|
tree "RFC_RAT"
|
|
base ad:0x40043000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RATCNT,Radio Timer Counter Value"
|
|
group.long 0x80++0x1F
|
|
line.long 0x00 "RATCH0VAL,Timer Channel 0 Capture/Compare Register"
|
|
line.long 0x04 "RATCH1VAL,Timer Channel 1 Capture/Compare Register"
|
|
line.long 0x08 "RATCH2VAL,Timer Channel 2 Capture/Compare Register"
|
|
line.long 0x0C "RATCH3VAL,Timer Channel 3 Capture/Compare Register"
|
|
line.long 0x10 "RATCH4VAL,Timer Channel 4 Capture/Compare Register"
|
|
line.long 0x14 "RATCH5VAL,Timer Channel 5 Capture/Compare Register"
|
|
line.long 0x18 "RATCH6VAL,Timer Channel 6 Capture/Compare Register"
|
|
line.long 0x1C "RATCH7VAL,Timer Channel 7 Capture/Compare Register"
|
|
tree.end
|
|
tree.end
|
|
tree "SMPH"
|
|
base ad:0x40084000
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SMPH$1,MCU SEMAPHORE 0"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is availableReading the register causes it to change value to 0" "Semaphore is taken,Semaphore is availableReading the register.."
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "SMPH$1,MCU SEMAPHORE 16"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is availableReading the register causes it to change value to 0" "Semaphore is taken,Semaphore is availableReading the register.."
|
|
repeat.end
|
|
rgroup.long 0x800++0x7F
|
|
line.long 0x00 "PEEK0,MCU SEMAPHORE 0 ALIAS"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x04 "PEEK1,MCU SEMAPHORE 1 ALIAS"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x08 "PEEK2,MCU SEMAPHORE 2 ALIAS"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x0C "PEEK3,MCU SEMAPHORE 3 ALIAS"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x10 "PEEK4,MCU SEMAPHORE 4 ALIAS"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x14 "PEEK5,MCU SEMAPHORE 5 ALIAS"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x18 "PEEK6,MCU SEMAPHORE 6 ALIAS"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x1C "PEEK7,MCU SEMAPHORE 7 ALIAS"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x20 "PEEK8,MCU SEMAPHORE 8 ALIAS"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x24 "PEEK9,MCU SEMAPHORE 9 ALIAS"
|
|
hexmask.long 0x24 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x28 "PEEK10,MCU SEMAPHORE 10 ALIAS"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x2C "PEEK11,MCU SEMAPHORE 11 ALIAS"
|
|
hexmask.long 0x2C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x30 "PEEK12,MCU SEMAPHORE 12 ALIAS"
|
|
hexmask.long 0x30 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x30 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x34 "PEEK13,MCU SEMAPHORE 13 ALIAS"
|
|
hexmask.long 0x34 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x34 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x38 "PEEK14,MCU SEMAPHORE 14 ALIAS"
|
|
hexmask.long 0x38 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x38 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x3C "PEEK15,MCU SEMAPHORE 15 ALIAS"
|
|
hexmask.long 0x3C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x3C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x40 "PEEK16,MCU SEMAPHORE 16 ALIAS"
|
|
hexmask.long 0x40 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x40 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x44 "PEEK17,MCU SEMAPHORE 17 ALIAS"
|
|
hexmask.long 0x44 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x44 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x48 "PEEK18,MCU SEMAPHORE 18 ALIAS"
|
|
hexmask.long 0x48 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x48 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x4C "PEEK19,MCU SEMAPHORE 19 ALIAS"
|
|
hexmask.long 0x4C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x4C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x50 "PEEK20,MCU SEMAPHORE 20 ALIAS"
|
|
hexmask.long 0x50 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x50 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x54 "PEEK21,MCU SEMAPHORE 21 ALIAS"
|
|
hexmask.long 0x54 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x54 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x58 "PEEK22,MCU SEMAPHORE 22 ALIAS"
|
|
hexmask.long 0x58 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x58 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x5C "PEEK23,MCU SEMAPHORE 23 ALIAS"
|
|
hexmask.long 0x5C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x5C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x60 "PEEK24,MCU SEMAPHORE 24 ALIAS"
|
|
hexmask.long 0x60 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x60 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x64 "PEEK25,MCU SEMAPHORE 25 ALIAS"
|
|
hexmask.long 0x64 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x64 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x68 "PEEK26,MCU SEMAPHORE 26 ALIAS"
|
|
hexmask.long 0x68 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x68 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x6C "PEEK27,MCU SEMAPHORE 27 ALIAS"
|
|
hexmask.long 0x6C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x6C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x70 "PEEK28,MCU SEMAPHORE 28 ALIAS"
|
|
hexmask.long 0x70 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x70 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x74 "PEEK29,MCU SEMAPHORE 29 ALIAS"
|
|
hexmask.long 0x74 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x74 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x78 "PEEK30,MCU SEMAPHORE 30 ALIAS"
|
|
hexmask.long 0x78 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x78 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x7C "PEEK31,MCU SEMAPHORE 31 ALIAS"
|
|
hexmask.long 0x7C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x7C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
tree.end
|
|
tree "SRAM_MMR"
|
|
base ad:0x40035000
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PER_CTL,Parity Error Control Parity error check controls"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "PER_DISABLE,Parity Status Disable0: A parity error will update PER_CHK.PER_ADDR field1: Parity error does not update PER_CHK.PER_ADDR field" "A parity error will update PER_CHK.PER_ADDR field,Parity error does not update PER_CHK.PER_ADDR.."
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "PER_DEBUG_ENABLE,Parity Error Debug Enable0: Normal operation1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity errors will be generated on reads from within this offset" "Normal operation,An address offset can be written to.."
|
|
line.long 0x04 "PER_CHK,Parity Error CheckParity error check results"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. "PER_ADDR,Parity Error Address OffsetReturns the last address offset which resulted in a parity error during an SRAM"
|
|
line.long 0x08 "PER_DBG,Parity Error DebugParity error check debug address setting"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "PER_DEBUG_ADDR,Debug Parity Error Address OffsetWhen PER_CTL.PER_DEBUG is 1 this field is used to set a parity debug address offset"
|
|
line.long 0x0C "MEM_CTL,Memory ControlControls memory initialization"
|
|
abitfld.long 0x0C 8.--31. "MEM_SEL,Memory Instance SelectThis field is used to enable/disable initialization of each SRAM instance when triggered using MEM_CTL.MEM_CLR_EN" "0x000000=Initialization of instance x is disabled,0x000001=Initialization of instance x is enabled"
|
|
rbitfld.long 0x0C 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 1. "MEM_BUSY,Memory Busy status0: Memory accepts transfers1: Memory controller is busy during initialization" "Memory accepts transfers,Memory controller is busy during initialization"
|
|
bitfld.long 0x0C 0. "MEM_CLR_EN,Memory Contents Initialization enableWriting 1 to MEM_CLR_EN will start memory initialization" "0,1"
|
|
line.long 0x10 "MEM_STA,Memory StatusControls memory initialization"
|
|
abitfld.long 0x10 8.--31. "MEM_STA,Memory Instance StatusThis field gives the current status of each SRAM instance" "0x000000=Instance x is in normal mode,0x000001=Instance x is getting initialized"
|
|
hexmask.long.byte 0x10 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
tree.end
|
|
tree "SSI"
|
|
repeat 2. (list 0. 1. )(list ad:0x40000000 ad:0x40008000 )
|
|
tree "SSI$1"
|
|
base $2
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CR0,Control 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "SCR,Serial clock rate:This is used to generate the transmit and receive bit rate of the SSI"
|
|
newline
|
|
bitfld.long 0x00 7. "SPH,CLKOUT phase (Motorola SPI frame format only)This bit selects the clock edge that captures data and enables it to change state" "Data is captured on the first clock edge..,Data is captured on the second clock edge.."
|
|
newline
|
|
bitfld.long 0x00 6. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "SSI produces a steady state LOW value on..,SSI produces a steady state HIGH value on the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "FRF,Frame format" "Motorola SPI frame format,TI synchronous serial frame format,National Microwire frame format,?"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DSS,Data Size Select" "?,?,?,4-bit data,5-bit data,6-bit data,7-bit data,8-bit data,9-bit data,10-bit data,11-bit data,12-bit data,13-bit data,14-bit data,15-bit data,16-bit data"
|
|
line.long 0x04 "CR1,Control 1"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 3. "SOD,Slave-mode output disabledThis bit is relevant only in the slave mode MS=1" "SSI can drive the TXD output in slave mode,SSI cannot drive the TXD output in slave mode"
|
|
newline
|
|
bitfld.long 0x04 2. "MS,Master or slave mode select" "Device configured as master,Device configured as slave"
|
|
newline
|
|
bitfld.long 0x04 1. "SSE,Synchronous serial interface enable" "Operation disabled,Operation enabled"
|
|
newline
|
|
bitfld.long 0x04 0. "LBM,Loop back mode:0: Normal serial port operation enabled.1: Output of transmit serial shifter is connected to input of receive serial shifter internally" "Normal serial port operation enabled,Output of transmit serial shifter is connected.."
|
|
line.long 0x08 "DR,Data16-bits wide data register:When read. the entry in the receive FIFO. pointed to by the current FIFO read pointer. is accessed"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "DATA,Transmit/receive dataThe values read from this field or written to this field must be right-justified when SSI is programmed for a data size that is less than 16 bits (CR0.DSS != 0b1111)"
|
|
line.long 0x0C "SR,Status"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 4. "BSY,Serial interface busy:0: SSI is idle1: SSI is currently transmitting and/or receiving a frame or the transmit FIFO is not empty" "SSI is idle,SSI is currently transmitting.."
|
|
newline
|
|
bitfld.long 0x0C 3. "RFF,Receive FIFO full:0: Receive FIFO is not full.1: Receive FIFO is full" "Receive FIFO is not full,Receive FIFO is full"
|
|
newline
|
|
bitfld.long 0x0C 2. "RNE,Receive FIFO not empty0: Receive FIFO is empty.1: Receive FIFO is not empty" "Receive FIFO is empty,Receive FIFO is not empty"
|
|
newline
|
|
bitfld.long 0x0C 1. "TNF,Transmit FIFO not full:0: Transmit FIFO is full.1: Transmit FIFO is not full" "Transmit FIFO is full,Transmit FIFO is not full"
|
|
newline
|
|
bitfld.long 0x0C 0. "TFE,Transmit FIFO empty:0: Transmit FIFO is not empty.1: Transmit FIFO is empty" "Transmit FIFO is not empty,Transmit FIFO is empty"
|
|
line.long 0x10 "CPSR,Clock Prescale"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "CPSDVSR,Clock prescale divisor:This field specifies the division factor by which the input system clock to SSI must be internally divided before further use.The value programmed into this field must be an even non-zero number (2-254)"
|
|
line.long 0x14 "IMSC,Interrupt Mask Set and Clear"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3. "TXIM,Transmit FIFO interrupt mask:A read returns the current mask for transmit FIFO interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "RXIM,Receive FIFO interrupt mask:A read returns the current mask for receive FIFO interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "RTIM,Receive timeout interrupt mask:A read returns the current mask for receive timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "RORIM,Receive overrun interrupt mask:A read returns the current mask for receive overrun interrupt" "0,1"
|
|
line.long 0x18 "RIS,Raw Interrupt Status"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 3. "TXRIS,Raw transmit FIFO interrupt status:The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "RXRIS,Raw interrupt state of receive FIFO interrupt:The receive interrupt is asserted when there are four or more valid entries in the receive FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "RTRIS,Raw interrupt state of receive timeout interrupt:The receive timeout interrupt is asserted when the receive FIFO is not empty and SSI has remained idle for a fixed 32 bit period" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "RORRIS,Raw interrupt state of receive overrun interrupt:The receive overrun interrupt is asserted when the FIFO is already full and an additional data frame is received causing an overrun of the FIFO" "0,1"
|
|
line.long 0x1C "MIS,Masked Interrupt Status"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 3. "TXMIS,Masked interrupt state of transmit FIFO interrupt:This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "RXMIS,Masked interrupt state of receive FIFO interrupt:This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "RTMIS,Masked interrupt state of receive timeout interrupt:This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "RORMIS,Masked interrupt state of receive overrun interrupt:This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM" "0,1"
|
|
line.long 0x20 "ICR,Interrupt ClearOn a write of 1. the corresponding interrupt is cleared"
|
|
hexmask.long 0x20 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 1. "RTIC,Clear the receive timeout interrupt:Writing 1 to this field clears the timeout interrupt (RIS.RTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "RORIC,Clear the receive overrun interrupt:Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS)" "0,1"
|
|
line.long 0x24 "DMACR,DMA Control"
|
|
hexmask.long 0x24 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 1. "TXDMAE,Transmit DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "RXDMAE,Receive DMA enable" "0,1"
|
|
repeat 2. (list 1. 2. )(list 0x00 0x68 )
|
|
rgroup.long ($2+0x28)++0x03
|
|
line.long 0x00 "RESERVED$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "TRNG"
|
|
base ad:0x40028000
|
|
rgroup.long 0x00++0x3B
|
|
line.long 0x00 "OUT0,Random Number Lower Word Readout Value"
|
|
line.long 0x04 "OUT1,Random Number Upper Word Readout Value"
|
|
line.long 0x08 "IRQFLAGSTAT,Interrupt Status"
|
|
bitfld.long 0x08 31. "NEED_CLOCK," "0,1"
|
|
hexmask.long 0x08 2.--30. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "SHUTDOWN_OVF," "0,1"
|
|
bitfld.long 0x08 0. "RDY," "0,1"
|
|
line.long 0x0C "IRQFLAGMASK,Interrupt Mask"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 1. "SHUTDOWN_OVF," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "RDY," "0,1"
|
|
line.long 0x10 "IRQFLAGCLR,Interrupt Flag Clear"
|
|
hexmask.long 0x10 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 1. "SHUTDOWN_OVF," "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "RDY," "0,1"
|
|
line.long 0x14 "CTL,Control"
|
|
abitfld.long 0x14 16.--31. "STARTUP_CYCLES,This field determines the number of samples (between 2^8 and 2^24) taken to gather entropy from the FROs during startup" "0x0000=2^24 samples,0x0001=1*2^8 samples,0x0002=2*2^8 samples,0x0003=3*2^8 samples,0x8000=32768*2^8 samples,0xC000=49152*2^8 samples,0xFFFF=65535*2^8 samplesThis field can only be.."
|
|
rbitfld.long 0x14 11.--15. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x14 10. "TRNG_EN," "0,1"
|
|
hexmask.long.byte 0x14 3.--9. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 2. "NO_LFSR_FB," "0,1"
|
|
bitfld.long 0x14 1. "TEST_MODE," "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x18 "CFG0,Configuration 0"
|
|
abitfld.long 0x18 16.--31. "MAX_REFILL_CYCLES,This field determines the maximum number of samples (between 2^8 and 2^24) taken to re-generate entropy from the FROs after reading out a 64 bits random number" "0x0000=2^24 samples,0x0001=1*2^8 samples,0x0002=2*2^8 samples,0x0003=3*2^8 samples,0x8000=32768*2^8 samples,0xC000=49152*2^8 samples,0xFFFF=65535*2^8 samplesThis field can only be.."
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|
rbitfld.long 0x18 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "SMPL_DIV,This field directly controls the number of clock cycles between samples taken from the FROs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
abitfld.long 0x18 0.--7. "MIN_REFILL_CYCLES,This field determines the minimum number of samples (between 2^6 and 2^14) taken to re-generate entropy from the FROs after reading out a 64 bits random number" "0x00=Minimum samples = MAX_REFILL_CYCLES (all..,0x01=1*2^6 samples,0x02=2*2^6 samples,0xFF=255*2^6 samples"
|
|
line.long 0x1C "ALARMCNT,Alarm Control"
|
|
rbitfld.long 0x1C 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x1C 24.--29. "SHUTDOWN_CNT,Read-only indicates the number of '1' bits in ALARMSTOP register.The maximum value equals the number of FROs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
rbitfld.long 0x1C 21.--23. "RESERVED21,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 16.--20. "SHUTDOWN_THR,Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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hexmask.long.byte 0x1C 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "ALARM_THR,Alarm detection threshold for the repeating pattern detectors on each FRO"
|
|
line.long 0x20 "FROEN,FRO Enable"
|
|
hexmask.long.byte 0x20 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "FRO_MASK,Enable bits for the individual FROs"
|
|
line.long 0x24 "FRODETUNE,FRO De-tune Bit"
|
|
hexmask.long.byte 0x24 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "FRO_MASK,De-tune bits for the individual FROs"
|
|
line.long 0x28 "ALARMMASK,Alarm Event"
|
|
hexmask.long.byte 0x28 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "FRO_MASK,Logging bits for the 'alarm events' of individual FROs"
|
|
line.long 0x2C "ALARMSTOP,Alarm Shutdown"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "FRO_FLAGS,Logging bits for the 'alarm events' of individual FROs"
|
|
line.long 0x30 "LFSR0,LFSR Readout Value"
|
|
line.long 0x34 "LFSR1,LFSR Readout Value"
|
|
line.long 0x38 "LFSR2,LFSR Readout Value"
|
|
hexmask.long.word 0x38 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x38 0.--16. 1. "LFSR_80_64,Bits [80:64] of the main entropy accumulation LFSR"
|
|
rgroup.long 0x78++0x07
|
|
line.long 0x00 "HWOPT,TRNG Engine Options Information"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 6.--11. "NR_OF_FROS,Number of FROs implemented in this TRNG value 24 (decimal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "HWVER0,HW Version 0EIP Number And Core Revision"
|
|
bitfld.long 0x04 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. "HW_MAJOR_VER,4 bits binary encoding of the major hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 20.--23. "HW_MINOR_VER,4 bits binary encoding of the minor hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. "HW_PATCH_LVL,4 bits binary encoding of the hardware patch level initial release will carry value zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "EIP_NUM_COMPL,Bit-by-bit logic complement of bits [7:0]"
|
|
hexmask.long.byte 0x04 0.--7. 1. "EIP_NUM,8 bits binary encoding of the module number"
|
|
rgroup.long 0x1FD8++0x03
|
|
line.long 0x00 "IRQSTATMASK,Interrupt Status After Masking"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "SHUTDOWN_OVF,Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with IRQFLAGMASK.SHUTDOWN_OVF)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RDY,New random value available (result of IRQFLAGSTAT.RDY AND'ed with IRQFLAGMASK.RDY)" "0,1"
|
|
rgroup.long 0x1FE0++0x03
|
|
line.long 0x00 "HWVER1,HW Version 1TRNG Revision Number"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,The revision number of this module is Rev 2.0"
|
|
group.long 0x1FEC++0x07
|
|
line.long 0x00 "IRQSET,Interrupt Set"
|
|
line.long 0x04 "SWRESET,SW Reset Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "RESET,Write '1' to soft reset reset will be low for 4-5 clock cycles" "0,1"
|
|
rgroup.long 0x1FF8++0x03
|
|
line.long 0x00 "IRQSTAT,Interrupt Status"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,TRNG Interrupt status" "0,1"
|
|
tree.end
|
|
tree "UART"
|
|
repeat 2. (list 0. 1. )(list ad:0x40001000 ad:0x4000B000 )
|
|
tree "UART$1"
|
|
base $2
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,DataFor words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1). data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0). data is stored in the transmitter holding register (the bottom.."
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 11. "OE,UART Overrun Error:This bit is set to 1 if data is received and the receive FIFO is already full" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "BE,UART Break Error:This bit is set to 1 if a break condition was detected indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits).In FIFO mode.." "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "PE,UART Parity Error:When set to 1 it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select.In FIFO mode this error is associated with the character at the top of the FIFO (that is the.." "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "FE,UART Framing Error:When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).In FIFO mode this error is associated with the character at the top of the FIFO (that is. the oldest received data.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Data transmitted or received:On writes the transmit data character is pushed into the FIFO.On reads the oldest received data character since the last read is returned"
|
|
line.long 0x04 "RSR,StatusThis register is mapped to the same address as ECR register"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 3. "OE,UART Overrun Error:This bit is set to 1 if data is received and the receive FIFO is already full" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "BE,UART Break Error:This bit is set to 1 if a break condition was detected indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits).When a break.." "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "PE,UART Parity Error:When set to 1 it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "FE,UART Framing Error:When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1)" "0,1"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "ECR,Error ClearThis register is mapped to the same address as RSR register"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3. "OE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "FE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
|
|
repeat 5. (list 0. 2. 1. 3. 4. )(list 0x00 0x14 0x44 0x88 0xFC8 )
|
|
rgroup.long ($2+0x08)++0x03
|
|
line.long 0x00 "RESERVED$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "FR,FlagReads from this register return the UART flags"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "TXFE,UART Transmit FIFO Empty:The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled this bit is set when the transmit holding register is empty. - If the FIFO is enabled this bit is set when the transmit FIFO is empty.This.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "RXFF,UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled this bit is set when the receive holding register is full. - If the FIFO is enabled this bit is set when the receive FIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TXFF,UART Transmit FIFO Full:Transmit FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXFE,UART Receive FIFO Empty:Receive FIFO empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BUSY,UART Busy: If this bit is set to 1 the UART is busy transmitting data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "CTS,Clear To Send: This bit is the complement of the active-low UART CTS input pin.That is the bit is 1 when CTS input pin is LOW" "0,1"
|
|
group.long 0x24++0x27
|
|
line.long 0x00 "IBRD,Integer Baud-Rate DivisorIf this register is modified while transmission or reception is on-going. the baud rate will not be updated until transmission or reception of the current character is complete"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DIVINT,The integer baud rate divisor:The baud rate divisor is calculated using the formula below:Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)Baud rate divisor must be minimum 1 and maximum 65535"
|
|
line.long 0x04 "FBRD,Fractional Baud-Rate DivisorIf this register is modified while trasmission or reception is on-going. the baudrate will not be updated until transmission or reception of the current character is complete"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "DIVFRAC,Fractional Baud-Rate Divisor:The baud rate divisor is calculated using the formula below:Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)Baud rate divisor must be minimum 1 and maximum 65535" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "LCRH,Line Control"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 7. "SPS,UART Stick Parity Select:0: Stick parity is disabled1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0).This bit has no effect when PEN disables parity checking and.." "Stick parity is disabled,The parity bit is transmitted and checked as.."
|
|
newline
|
|
bitfld.long 0x08 5.--6. "WLEN,UART Word Length:These bits indicate the number of data bits transmitted or received in a frame" "Word Length 5 bits,Word Length 6 bits,Word Length 7 bits,Word Length 8 bits"
|
|
newline
|
|
bitfld.long 0x08 4. "FEN,UART Enable FIFOs" "FIFOs are disabled (character mode) that is the..,Transmit and receive FIFO buffers are enabled.."
|
|
newline
|
|
bitfld.long 0x08 3. "STP2,UART Two Stop Bits Select:If this bit is set to 1 two stop bits are transmitted at the end of the frame" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "EPS,UART Even Parity Select" "Odd parity: The UART generates or checks for an..,Even parity: The UART generates or checks for an.."
|
|
newline
|
|
bitfld.long 0x08 1. "PEN,UART Parity EnableThis bit controls generation and checking of parity bit" "Parity is disabled and no parity bit is added to..,Parity checking and generation is enabled."
|
|
newline
|
|
bitfld.long 0x08 0. "BRK,UART Send BreakIf this bit is set to 1 a low-level is continually output on the UARTTXD output pin after completing transmission of the current character" "0,1"
|
|
line.long 0x0C "CTL,Control"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 15. "CTSEN,CTS hardware flow control enable" "CTS hardware flow control disabled,CTS hardware flow control enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. "RTSEN,RTS hardware flow control enable" "RTS hardware flow control disabled,RTS hardware flow control enabled"
|
|
newline
|
|
bitfld.long 0x0C 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 11. "RTS,Request to SendThis bit is the complement of the active-low UART RTS output" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 10. "RESERVED10,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RXE,UART Receive EnableIf the UART is disabled in the middle of reception it completes the current character before stopping" "UART Receive disabled,UART Receive enabled"
|
|
newline
|
|
bitfld.long 0x0C 8. "TXE,UART Transmit EnableIf the UART is disabled in the middle of transmission it completes the current character before stopping" "UART Transmit disabled,UART Transmit enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. "LBE,UART Loop Back Enable:Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART" "Loop Back disabled,Loop Back enabled"
|
|
newline
|
|
bitfld.long 0x0C 1.--6. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 0. "UARTEN,UART Enable" "UART disabled,UART enabled"
|
|
line.long 0x10 "IFLS,Interrupt FIFO Level Select"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 3.--5. "RXSEL,Receive interrupt FIFO level select:This field sets the trigger points for the receive interrupt" "Receive FIFO becomes >= 1/8 full,Receive FIFO becomes >= 1/4 full,Receive FIFO becomes >= 1/2 full,Receive FIFO becomes >= 3/4 full,Receive FIFO becomes >= 7/8 full,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 0.--2. "TXSEL,Transmit interrupt FIFO level select:This field sets the trigger points for the transmit interrupt" "Transmit FIFO becomes <= 1/8 full,Transmit FIFO becomes <= 1/4 full,Transmit FIFO becomes <= 1/2 full,Transmit FIFO becomes <= 3/4 full,Transmit FIFO becomes <= 7/8 full,?,?,?"
|
|
line.long 0x14 "IMSC,Interrupt Mask Set/Clear"
|
|
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 11. "EOTIM,End of Transmission interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "OEIM,Overrun error interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "BEIM,Break error interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "PEIM,Parity error interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "FEIM,Framing error interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "RTIM,Receive timeout interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "TXIM,Transmit interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "RXIM,Receive interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 1. "CTSMIM,Clear to Send (CTS) modem interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x18 "RIS,Raw Interrupt Status"
|
|
hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 11. "EOTRIS,End of Transmission interrupt status: This field returns the raw interrupt state of UART's end of transmission interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 10. "OERIS,Overrun error interrupt status: This field returns the raw interrupt state of UART's overrun error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "BERIS,Break error interrupt status:This field returns the raw interrupt state of UART's break error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "PERIS,Parity error interrupt status:This field returns the raw interrupt state of UART's parity error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "FERIS,Framing error interrupt status:This field returns the raw interrupt state of UART's framing error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "RTRIS,Receive timeout interrupt status:This field returns the raw interrupt state of UART's receive timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "TXRIS,Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt.When FIFOs are enabled (LCRH.FEN = 1) the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the.." "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "RXRIS,Receive interrupt status:This field returns the raw interrupt state of UART's receive interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 1. "CTSRMIS,Clear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of UART's clear to send interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x1C "MIS,Masked Interrupt Status"
|
|
hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 11. "EOTMIS,End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 10. "OEMIS,Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 9. "BEMIS,Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PEMIS,Parity error masked interrupt status:This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "FEMIS,Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTMIS,Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt.The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "TXMIS,Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXMIS,Receive masked interrupt status:This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 1. "CTSMMIS,Clear to Send (CTS) modem masked interrupt status:This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x20 "ICR,Interrupt ClearOn a write of 1. the corresponding interrupt is cleared"
|
|
hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 11. "EOTIC,End of Transmission interrupt clear:Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 10. "OEIC,Overrun error interrupt clear:Writing 1 to this field clears the overrun error interrupt (RIS.OERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 9. "BEIC,Break error interrupt clear:Writing 1 to this field clears the break error interrupt (RIS.BERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEIC,Parity error interrupt clear:Writing 1 to this field clears the parity error interrupt (RIS.PERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "FEIC,Framing error interrupt clear:Writing 1 to this field clears the framing error interrupt (RIS.FERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTIC,Receive timeout interrupt clear:Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 5. "TXIC,Transmit interrupt clear:Writing 1 to this field clears the transmit interrupt (RIS.TXRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXIC,Receive interrupt clear:Writing 1 to this field clears the receive interrupt (RIS.RXRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 1. "CTSMIC,Clear to Send (CTS) modem interrupt clear:Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x24 "DMACTL,DMA Control"
|
|
hexmask.long 0x24 3.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 2. "DMAONERR,DMA on error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "TXDMAE,Transmit DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "RXDMAE,Receive DMA enable" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "UDMA0"
|
|
base ad:0x40020000
|
|
rgroup.long 0x00++0x3F
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 28.--31. "TEST," "Controller does not include the integration test..,Controller includes the integration test logic,Undefined,?,?,?,?,?,?,?,?,?,?,?,?,Undefined"
|
|
hexmask.long.byte 0x00 21.--27. 1. "RESERVED21,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TOTALCHANNELS,Register value returns number of available uDMA channels minus one" "Show that the controller is configured to use 1..,Shows that the controller is configured to use 2..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Shows that the controller is configured to use.."
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "STATE,Current state of the control state machine" "Idle,Reading channel controller data,Reading source data end pointer,Reading destination data end pointer,Reading source data,Writing destination data,Waiting for uDMA request to clear,Writing channel controller data,Stalled,Done,Peripheral scatter-gather transition,Undefined,?,?,?,Undefined"
|
|
bitfld.long 0x00 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTERENABLE,Shows the enable status of the controller as configured by CFG.MASTERENABLE:0: Controller is disabled1: Controller is enabled" "Controller is disabled,Controller is enabled"
|
|
line.long 0x04 "CFG,Configuration"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5.--7. "PRTOCTRL,Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows:Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring.Bit [6] Controls HProt[2] to indicate if a bufferable access is.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 1.--4. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0. "MASTERENABLE,Enables the controller:0: Disables the controller1: Enables the controller" "Disables the controller,Enables the controller"
|
|
line.long 0x08 "CTRL,Channel Control Data Base Pointer"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "BASEPTR,This register point to the base address for the primary data structures of each DMA channel"
|
|
hexmask.long.word 0x08 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "ALTCTRL,Channel Alternate Control Data Base Pointer"
|
|
line.long 0x10 "WAITONREQ,Channel Wait On Request Status"
|
|
line.long 0x14 "SOFTREQ,Channel Software Request"
|
|
line.long 0x18 "SETBURST,Channel Set UseBurst"
|
|
line.long 0x1C "CLEARBURST,Channel Clear UseBurst"
|
|
line.long 0x20 "SETREQMASK,Channel Set Request Mask"
|
|
line.long 0x24 "CLEARREQMASK,Clear Channel Request Mask"
|
|
line.long 0x28 "SETCHANNELEN,Set Channel Enable"
|
|
line.long 0x2C "CLEARCHANNELEN,Clear Channel Enable"
|
|
line.long 0x30 "SETCHNLPRIALT,Channel Set Primary-Alternate"
|
|
line.long 0x34 "CLEARCHNLPRIALT,Channel Clear Primary-Alternate"
|
|
line.long 0x38 "SETCHNLPRIORITY,Set Channel Priority"
|
|
line.long 0x3C "CLEARCHNLPRIORITY,Clear Channel Priority"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ERROR,Error Status and Clear"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STATUS,Returns the status of bus error flag in uDMA or clears this bit Read as:0: No bus error detected1: Bus error detectedWrite as:0: No effect status of bus error flag is unchanged.1: Clears the bus error flag" "No effect status of bus error flag is unchanged,Clears the bus error flag"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "REQDONE,Channel Request Done"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "DONEMASK,Channel Request Done Mask"
|
|
tree.end
|
|
tree "VIMS"
|
|
base ad:0x40034000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "STAT,StatusDisplays current VIMS mode and line buffer status"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 5. "IDCODE_LB_DIS,Icode/Dcode flash line buffer status0: Enabled or in transition to disabled1: Disabled and flushed" "Enabled or in transition to disabled,Disabled and flushed"
|
|
newline
|
|
bitfld.long 0x00 4. "SYSBUS_LB_DIS,Sysbus flash line buffer control0: Enabled or in transition to disabled1: Disabled and flushed" "Enabled or in transition to disabled,Disabled and flushed"
|
|
bitfld.long 0x00 3. "MODE_CHANGING,VIMS mode change status0: VIMS is in the mode defined by MODE1: VIMS is in the process of changing to the mode given in CTL.MODE" "VIMS is in the mode defined by MODE,VIMS is in the process of changing to the mode.."
|
|
newline
|
|
bitfld.long 0x00 2. "INV,This bit is set when invalidation of the cache memory is active / ongoing" "0,1"
|
|
bitfld.long 0x00 0.--1. "MODE,Current VIMS mode" "VIMS GPRAM mode,VIMS Cache mode,?,VIMS Off mode"
|
|
line.long 0x04 "CTL,ControlConfigure VIMS mode and line buffer settings"
|
|
bitfld.long 0x04 31. "STATS_CLR,Set this bit to clear statistic counters" "0,1"
|
|
bitfld.long 0x04 30. "STATS_EN,Set this bit to enable statistic counters" "0,1"
|
|
newline
|
|
bitfld.long 0x04 29. "DYN_CG_EN," "0,1"
|
|
hexmask.long.tbyte 0x04 6.--28. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "IDCODE_LB_DIS,Icode/Dcode flash line buffer control0: Enable1: Disable" "Enable,Disable"
|
|
bitfld.long 0x04 4. "SYSBUS_LB_DIS,Sysbus flash line buffer control0: Enable1: Disable" "Enable,Disable"
|
|
newline
|
|
bitfld.long 0x04 3. "ARB_CFG,Icode/Dcode and sysbus arbitation scheme0: Static arbitration (icode/docde > sysbus)1: Round-robin arbitration" "Static arbitration (icode/docde > sysbus),Round-robin arbitration"
|
|
bitfld.long 0x04 2. "PREF_EN,Tag prefetch control0: Disabled1: Enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "MODE,VIMS mode request.Write accesses to this field will be blocked while STAT.MODE_CHANGING is set to 1" "VIMS GPRAM mode,VIMS Cache mode,?,VIMS Off mode"
|
|
tree.end
|
|
tree "WDT"
|
|
base ad:0x40080000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "LOAD,Configuration"
|
|
line.long 0x04 "VALUE,Current Count Value"
|
|
line.long 0x08 "CTL,Control"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 2. "INTTYPE,WDT Interrupt Type0: WDT interrupt is a standard interrupt" "WDT interrupt is a standard interrupt,WDT interrupt is a non-maskable interrupt"
|
|
newline
|
|
bitfld.long 0x08 1. "RESEN,WDT Reset Enable" "Disabled,Enable the Watchdog.."
|
|
bitfld.long 0x08 0. "INTEN,WDT Interrupt Enable0: Interrupt event disabled" "Interrupt event disabled,Interrupt event enabled"
|
|
line.long 0x0C "ICR,Interrupt Clear"
|
|
line.long 0x10 "RIS,Raw Interrupt Status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "WDTRIS,This register is the raw interrupt status register" "The WDT has not timed out,A WDT time-out event has occurred"
|
|
line.long 0x14 "MIS,Masked Interrupt Status"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "WDTMIS,This register is the masked interrupt status register" "The WDT has not timed out or is masked,An unmasked WDT time-out event has occurred"
|
|
group.long 0x418++0x07
|
|
line.long 0x00 "TEST,Test Mode"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "STALL,WDT Stall Enable0: The WDT timer continues counting if the CPU is stopped with a debugger.1: If the CPU is stopped with a debugger the WDT stops counting" "The WDT timer continues counting if the CPU is..,If the CPU is stopped with a debugger the WDT.."
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "TEST_EN,The test enable bit" "Enable external reset,Disables the generation of an external reset"
|
|
line.long 0x04 "INT_CAUS,Interrupt Cause Test Mode"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 1. "CAUSE_RESET,Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "CAUSE_INTR,Replica of RIS.WDTRIS" "0,1"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "LOCK,Lock"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CC2651P3")||cpuis("CC2651R3"))
|
|
tree "AON"
|
|
tree "AON_BATMON"
|
|
base ad:0x40095000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTL,Internal"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Internal"
|
|
bitfld.long 0x00 1. "CALC_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MEAS_EN,Internal" "0,1"
|
|
line.long 0x04 "MEASCFG,Internal"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Internal"
|
|
bitfld.long 0x04 0.--1. "PER,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
group.long 0x0C++0x2B
|
|
line.long 0x00 "TEMPP0,Internal"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Internal"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CFG,Internal"
|
|
line.long 0x04 "TEMPP1,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x04 0.--5. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "TEMPP2,Internal"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED5,Internal"
|
|
bitfld.long 0x08 0.--4. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "BATMONP0,Internal"
|
|
hexmask.long 0x0C 7.--31. 1. "RESERVED6,Internal"
|
|
hexmask.long.byte 0x0C 0.--6. 1. "CFG,Internal"
|
|
line.long 0x10 "BATMONP1,Internal"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x10 0.--5. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "IOSTRP0,Internal"
|
|
hexmask.long 0x14 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x14 4.--5. "CFG2,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--3. "CFG1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "FLASHPUMPP0,Internal"
|
|
hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x18 9. "DIS_NOISE_FILTER,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "FALLB,Internal" "0,1"
|
|
bitfld.long 0x18 6.--7. "HIGHLIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 5. "LOWLIM,Internal" "0,1"
|
|
bitfld.long 0x18 4. "OVR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "BAT,Last Measured Battery VoltageThis register may be read while BATUPD.STAT = 1"
|
|
hexmask.long.tbyte 0x1C 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x1C 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x20 "BATUPD,Battery UpdateIndicates BAT Updates"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT," "No update since last clear,New battery voltage is present.Write 1 to clear.."
|
|
line.long 0x24 "TEMP,TemperatureLast Measured Temperature in Degrees CelsiusThis register may be read while TEMPUPD.STAT = 1."
|
|
hexmask.long.word 0x24 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x24 8.--16. "INT,Integer part (signed) of temperature value" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x28 "TEMPUPD,Temperature UpdateIndicates TEMP Updates"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "STAT," "No update since last clear,New temperature is present.Write 1 to clear the.."
|
|
group.long 0x48++0x17
|
|
line.long 0x00 "EVENTMASK,Event Mask"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 5. "TEMP_UPDATE_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "BATT_UPDATE_MASK," "0,1"
|
|
bitfld.long 0x00 3. "TEMP_BELOW_LL_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TEMP_OVER_UL_MASK," "0,1"
|
|
bitfld.long 0x00 1. "BATT_BELOW_LL_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BATT_OVER_UL_MASK," "0,1"
|
|
line.long 0x04 "EVENT,Event"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5. "TEMP_UPDATE,Alias to TEMPUPD.STAT" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "BATT_UPDATE,Alias to BATUPD.STAT" "0,1"
|
|
bitfld.long 0x04 3. "TEMP_BELOW_LL,Read:1: Temperature level is below the lower limit set by TEMPLL.0: Temperature level is not below the lower limit set by TEMPLL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
newline
|
|
bitfld.long 0x04 2. "TEMP_OVER_UL,Read:1: Temperature level is above the upper limit set by TEMPUL.0: Temperature level is not above the upper limit set by TEMPUL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
bitfld.long 0x04 1. "BATT_BELOW_LL,Read:1: Battery level is below the lower limit set by BATTLL.0: Battery level is not below the lower limit set by BATTLL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
newline
|
|
bitfld.long 0x04 0. "BATT_OVER_UL,Read:1: Battery level is above the upper limit set by BATTUL.0: Battery level is not above the upper limit set by BATTUL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
line.long 0x08 "BATTUL,Battery Upper Limit"
|
|
hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x08 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x0C "BATTLL,Battery Lower Limit"
|
|
hexmask.long.tbyte 0x0C 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x0C 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x10 "TEMPUL,Temperature Upper Limit"
|
|
hexmask.long.word 0x10 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x10 8.--16. "INT,Integer part (signed) of temperature upper limit" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "FRAC,Fractional part of temperature upper limit.Total value = INTEGER + FRACTIONALThe encoding is an extension of the 2's complement encoding.00" "0.0C,0.25C,?..."
|
|
rbitfld.long 0x10 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "TEMPLL,Temperature Lower Limit"
|
|
hexmask.long.word 0x14 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x14 8.--16. "INT,Integer part (signed) of temperature lower limit" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
bitfld.long 0x14 6.--7. "FRAC,Fractional part of temperature lower limit.Total value = INTEGER + FRACTIONALThe encoding is an extension of the 2's complement encoding.00" "0.0C,0.25C,?..."
|
|
rbitfld.long 0x14 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "AON_EVENT"
|
|
base ad:0x40093000
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MCUWUSEL,Wake-up Selector For MCUThis register contains pointers to 4 of 8 events (events 0 to 3) which are routed to AON_PMCTRL as wakeup sources for MCU"
|
|
rbitfld.long 0x00 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "WU3_EV,MCU Wakeup Source #3AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "WU2_EV,MCU Wakeup Source #2AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "WU1_EV,MCU Wakeup Source #1AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "WU0_EV,MCU Wakeup Source #0AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
line.long 0x04 "MCUWUSEL1,Wake-up Selector For MCUThis register contains pointers to 4 of 8 events (events 4 to 7) which are routed to AON_PMCTRL as wakeup sources for MCU"
|
|
rbitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 24.--29. "WU7_EV,MCU Wakeup Source #7AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 16.--21. "WU6_EV,MCU Wakeup Source #6AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 8.--13. "WU5_EV,MCU Wakeup Source #5AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "WU4_EV,MCU Wakeup Source #4AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
line.long 0x08 "EVTOMCUSEL,Event Selector For MCU Event Fabric This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT"
|
|
hexmask.long.word 0x08 22.--31. 1. "RESERVED22,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 16.--21. "AON_PROG2_EV,Event selector for AON_PROG2 event.AON Event Source id# selecting event routed to EVENT as AON_PROG2 event." "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x08 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 8.--13. "AON_PROG1_EV,Event selector for AON_PROG1 event.AON Event Source id# selecting event routed to EVENT as AON_PROG1 event." "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
|
|
newline
|
|
rbitfld.long 0x08 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "AON_PROG0_EV,Event selector for AON_PROG0 event.AON Event Source id# selecting event routed to EVENT as AON_PROG0 event." "Edge detect IO event from the DIO(s) which have..,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,0,?,?,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
|
|
line.long 0x0C "RTCSEL,RTC Capture Event Selector For AON_RTCThis register contains a pointer to select an AON event for RTC capture"
|
|
hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0.--5. "RTC_CH1_CAPT_EV,AON Event Source id# for RTCSEL event which is fed to AON_RTC" "Edge detect IO event from the DIO(s) which have..,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,0,?,?,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
|
|
tree.end
|
|
tree "AON_IOC"
|
|
base ad:0x40094000
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "IOSTRMIN,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x00 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "IOSTRMED,Internal"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x04 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "IOSTRMAX,Internal"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x08 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CLK32KCTL,SCLK_LF External Output Control"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "OE_N," "0,1"
|
|
line.long 0x04 "TCKCTL,TCK IO Pin Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "EN," "0,1"
|
|
tree.end
|
|
tree "AON_PMCTL"
|
|
base ad:0x40090000
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "AUXSCECLK,AUX SCE Clock ManagementThis register contains bitfields that are relevant for setting up the clock to the AUX domain"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "PD_SRC,Selects the clock source for the AUX domain when AUX is in powerdown mode.Note: Switching the clock source is guaranteed to be glitch-free" "No clock,LF clock (SCLK_LF )"
|
|
newline
|
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hexmask.long.byte 0x00 1.--7. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "SRC,Selects the clock source for the AUX domain when AUX is in active mode.Note: Switching the clock source is guaranteed to be glitch-free" "HF Clock divided by 2 (SCLK_HFDIV2),MF Clock (SCLK_MF)"
|
|
line.long 0x04 "RAMCFG,RAM ConfigurationThis register contains power management related configuration for the SRAM in the MCU and AUX domain"
|
|
hexmask.long.word 0x04 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 17. "AUX_SRAM_PWR_OFF,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "AUX_SRAM_RET_EN,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 4.--15. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--3. "BUS_SRAM_RET_EN,MCU SRAM is partitioned into 8 banks" "Retention is disabled,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,?,?,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,?,?,?,?,?,?,Retention on for all banks BANK[0]: BANK[1]:.."
|
|
group.long 0x10++0x1F
|
|
line.long 0x00 "PWRCTL,Power Management ControlThis register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDC_ACTIVE,Select to use DCDC regulator for VDDR in active mode" "Use GLDO for regulation of VDDR in active mode,Use DCDC for regulation of VDDR in active mode"
|
|
newline
|
|
bitfld.long 0x00 1. "EXT_REG_MODE,Status of source for VDDRsupply:0: DCDC or GLDO are generating VDDR1: DCDC and GLDO are bypassed and an external regulator supplies VDDR" "DCDC or GLDO are generating VDDR,DCDC and GLDO are bypassed and an external.."
|
|
newline
|
|
bitfld.long 0x00 0. "DCDC_EN,Select to use DCDC regulator during recharge of VDDR0: Use GLDO for recharge of VDDR1: Use DCDC for recharge of VDDRNote: This bitfield should be set to the same as DCDC_ACTIVE" "Use GLDO for recharge of VDDR,Use DCDC for recharge of VDDR"
|
|
line.long 0x04 "PWRSTAT,AON Power and Reset StatusThis register is used to monitor various power management related signals in AON"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 2. "JTAG_PD_ON,Indicates JTAG power state:0: JTAG is powered off1: JTAG is powered on" "JTAG is powered off,JTAG is powered on"
|
|
newline
|
|
bitfld.long 0x04 1. "AUX_BUS_RESET_DONE,Indicates Reset Done from AUX Bus:0: AUX Bus is being reset1: AUX Bus reset is released" "AUX Bus is being reset,AUX Bus reset is released"
|
|
newline
|
|
bitfld.long 0x04 0. "AUX_RESET_DONE,Indicates Reset Done from AUX:0: AUX is being reset1: AUX reset is released" "AUX is being reset,AUX reset is released"
|
|
line.long 0x08 "SHUTDOWN,Shutdown ControlThis register contains bitfields required for entering shutdown mode"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "EN,Shutdown control.0: Do not write 0 to this bit" "Do not write 0 to this bit,Immediately start the process to enter shutdown.."
|
|
line.long 0x0C "RECHARGECFG,Recharge Controller ConfigurationThis register sets all relevant parameters for controlling the recharge algorithm"
|
|
bitfld.long 0x0C 30.--31. "MODE,Selects recharge algorithm for VDDR when the system is running on the uLDO" "Recharge disabled,Static timer,Adaptive timer,External recharge comparator. Note that the.."
|
|
newline
|
|
rbitfld.long 0x0C 24.--29. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 20.--23. "C2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 16.--19. "C1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 11.--15. "MAX_PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 8.--10. "MAX_PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0C 3.--7. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x0C 0.--2. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "RECHARGESTAT,Recharge Controller StatusThis register controls various status registers which are updated during recharge"
|
|
hexmask.long.word 0x10 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 16.--19. "VDDR_SMPLS,The last 4 VDDR samples.For each bit:0: VDDR was below VDDR_OK threshold when recharge started1: VDDR was above VDDR_OK threshold when recharge startedThe register is updated prior to every recharge period with a shift left and bit 0 is.." "VDDR was below VDDR_OK threshold when recharge..,VDDR was above VDDR_OK threshold when recharge..,?..."
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "MAX_USED_PER,Shows the maximum number of 32kHz periods that have separated two recharge cycles and VDDR still was above VDDR_OK threshold when the latter recharge started"
|
|
line.long 0x14 "OSCCFG,Oscillator ConfigurationThis register sets the period for Amplitude compensation requests sent to the oscillator control system"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3.--7. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "RESETCTL,Reset ManagementThis register contains bitfields related to system reset such as reset source and reset request and control of brown out resets"
|
|
bitfld.long 0x18 31. "SYSRESET,Cold reset register" "No effect,Generate system reset"
|
|
newline
|
|
rbitfld.long 0x18 26.--30. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x18 25. "BOOT_DET_1_CLR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "BOOT_DET_0_CLR,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 18.--23. "RESERVED18,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x18 17. "BOOT_DET_1_SET,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 16. "BOOT_DET_0_SET,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "WU_FROM_SD,A Wakeup from SHUTDOWN on an IO event has occurred or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached" "Wakeup occurred from cold reset or brown out as..,A wakeup has occurred from SHUTDOWN"
|
|
newline
|
|
bitfld.long 0x18 14. "GPIO_WU_FROM_SD,A wakeup from SHUTDOWN on an IO event has occurred Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources.0: The wakeup did not occur from SHUTDOWN on an IO event1: A wakeup from SHUTDOWN occurred from an IO.." "The wakeup did not occur from SHUTDOWN on an IO..,A wakeup from SHUTDOWN occurred from an IO.."
|
|
newline
|
|
rbitfld.long 0x18 13. "BOOT_DET_1,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "BOOT_DET_0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--11. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 8. "VDDS_LOSS_EN,Controls reset generation in case VDDS is lost0: Brown out detect of VDDS is ignored unless VDDS_LOSS_EN_OVR=11: Brown out detect of VDDS generates system reset " "Brown out detect of VDDS is ignored unless..,Brown out detect of VDDS generates system reset"
|
|
newline
|
|
bitfld.long 0x18 7. "VDDR_LOSS_EN,Controls reset generation in case VDDR is lost0: Brown out detect of VDDR is ignored unless VDDR_LOSS_EN_OVR=11: Brown out detect of VDDR generates system reset" "Brown out detect of VDDR is ignored unless..,Brown out detect of VDDR generates system reset"
|
|
newline
|
|
bitfld.long 0x18 6. "VDD_LOSS_EN,Controls reset generation in case VDD is lost0: Brown out detect of VDD is ignored unless VDD_LOSS_EN_OVR=11: Brown out detect of VDD generates system reset" "Brown out detect of VDD is ignored unless..,Brown out detect of VDD generates system reset"
|
|
newline
|
|
bitfld.long 0x18 5. "CLK_LOSS_EN,Controls reset generation in case SCLK_LF SCLK_MF or SCLK_HF is lost when clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]0: Clock loss is ignored1: Clock loss generates system resetNote: Clock loss reset.." "Clock loss is ignored,Clock loss generates system reset"
|
|
newline
|
|
bitfld.long 0x18 4. "MCU_WARM_RESET,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 1.--3. "RESET_SRC,Shows the root cause of the last system reset" "Power on reset,Reset pin,Brown out detect on VDDS,?,Brown out detect on VDDR,SCLK_LF SCLK_MF or SCLK_HF clock loss detect,Software reset via SYSRESET or hardware power..,Software reset via PRCM warm reset request"
|
|
newline
|
|
rbitfld.long 0x18 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x1C "SLEEPCTL,Sleep ControlThis register is used to unfreeze the IO pad ring after waking up from SHUTDOWN"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0. "IO_PAD_SLEEP_DIS,Controls the I/O pad sleep mode" "I/O pad sleep mode is enabled meaning all..,I/O pad sleep mode is disabledApplication.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "JTAGCFG,JTAG ConfigurationThis register contains control for configuration of the JTAG domain"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "JTAG_PD_FORCE_ON,Controls JTAG Power domain power state:0: Controlled exclusively by debug subsystem" "Controlled exclusively by debug subsystem,JTAG Power Domain is forced on independent of.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "JTAGUSERCODE,JTAG USERCODEBoot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem"
|
|
group.long 0xC4++0x07
|
|
line.long 0x00 "WDTLOAD,ConfigurationLoad Value register"
|
|
line.long 0x04 "WDTTEST,Test Mode"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "STALLEN,WDT Stall Enable0: The WDT timer continues counting if the CPU is stopped with a debugger.1: If the CPU is stopped with a debugger the WDT stops counting" "The WDT timer continues counting if the CPU is..,If the CPU is stopped with a debugger the WDT.."
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "WDTLOCK,Lock"
|
|
tree.end
|
|
tree "AON_RTC"
|
|
base ad:0x40092000
|
|
group.long 0x00++0x37
|
|
line.long 0x00 "CTL,ControlThis register contains various bitfields for configuration of RTCRTL Name = CONFIG"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16.--18. "COMB_EV_MASK,Eventmask selecting which delayed events that form the combined event." "No event is selected for combined event.,Use Channel 0 delayed event in combined event,Use Channel 1 delayed event in combined event,?,Use Channel 2 delayed event in combined event,?,?,?"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "EV_DELAY,Number of SCLK_LF clock cycles waited before generating delayed events" "No delay on delayed event,Delay by 1 clock cycles,Delay by 2 clock cycles,Delay by 4 clock cycles,Delay by 8 clock cycles,Delay by 16 clock cycles,Delay by 32 clock cycles,Delay by 48 clock cycles,Delay by 64 clock cycles,Delay by 80 clock cycles,Delay by 96 clock cycles,Delay by 112 clock cycles,Delay by 128 clock cycles,Delay by 144 clock cycles,?,?"
|
|
newline
|
|
bitfld.long 0x00 7. "RESET,RTC Counter reset.Writing 1 to this bit will reset the RTC counter.This bit is cleared when reset takes effect" "0,1"
|
|
rbitfld.long 0x00 3.--6. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "RTC_4KHZ_EN,RTC_4KHZ is a 4 KHz reference output tapped from SUBSEC.VALUE bit 19 which is used by AUX timer" "RTC_4KHZ signal is forced to 0,RTC_4KHZ is enabled ( provied that RTC is.."
|
|
bitfld.long 0x00 1. "RTC_UPD_EN,RTC_UPD is a 16 KHz signal used to sync up the radio timer" "RTC_UPD signal is forced to 0,RTC_UPD signal is toggling @16 kHz"
|
|
newline
|
|
bitfld.long 0x00 0. "EN,Enable RTC counter0: Halted (frozen)1: Running" "Halted (frozen),Running"
|
|
line.long 0x04 "EVFLAGS,Event Flags. RTC StatusThis register contains event flags from the 3 RTC channels"
|
|
hexmask.long.word 0x04 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 16. "CH2,Channel 2 event flag set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value.An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "CH1,Channel 1 event flag set when CHCTL.CH1_EN = 1 and one of the following:- CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value.- CHCTL.CH1_CAPT_EN = 1 and capture occurs.An event will be scheduled to occur as soon as possible.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "CH0,Channel 0 event flag set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value.An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any.." "0,1"
|
|
line.long 0x08 "SEC,Second Counter Value. Integer Part"
|
|
line.long 0x0C "SUBSEC,Second Counter Value. Fractional Part"
|
|
line.long 0x10 "SUBSECINC,Subseconds IncrementValue added to SUBSEC.VALUE on every SCLK_LFclock cycle"
|
|
hexmask.long.byte 0x10 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "VALUEINC,This value compensates for a SCLK_LF clock which has an offset from 32768 Hz.The compensation value can be found as 2^38 / freq where freq is SCLK_LF clock frequency in HertzThis value is added to SUBSEC.VALUE on every cycle and carry of this.."
|
|
line.long 0x14 "CHCTL,Channel Configuration"
|
|
hexmask.long.word 0x14 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 18. "CH2_CONT_EN,Set to enable continuous operation of Channel 2" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 17. "RESERVED17,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x14 16. "CH2_EN,RTC Channel 2 Enable0: Disable RTC Channel 21: Enable RTC Channel 2" "Disable RTC Channel 2,Enable RTC Channel 2"
|
|
newline
|
|
rbitfld.long 0x14 10.--15. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 9. "CH1_CAPT_EN,Set Channel 1 mode0: Compare mode (default)1: Capture mode" "Compare mode (default),Capture mode"
|
|
newline
|
|
bitfld.long 0x14 8. "CH1_EN,RTC Channel 1 Enable0: Disable RTC Channel 11: Enable RTC Channel 1" "Disable RTC Channel 1,Enable RTC Channel 1"
|
|
hexmask.long.byte 0x14 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "CH0_EN,RTC Channel 0 Enable0: Disable RTC Channel 01: Enable RTC Channel 0" "Disable RTC Channel 0,Enable RTC Channel 0"
|
|
line.long 0x18 "CH0CMP,Channel 0 Compare Value"
|
|
line.long 0x1C "CH1CMP,Channel 1 Compare Value"
|
|
line.long 0x20 "CH2CMP,Channel 2 Compare Value"
|
|
line.long 0x24 "CH2CMPINC,Channel 2 Compare Value Auto-incrementThis register is primarily used to generate periodical wake-up for the AUX_SCE module. through the [AUX_EVCTL.EVSTAT0.AON_RTC] event."
|
|
line.long 0x28 "CH1CAPT,Channel 1 Capture ValueIf CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1. capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL."
|
|
hexmask.long.word 0x28 16.--31. 1. "SEC,Value of SEC.VALUE bits 15:0 at capture time"
|
|
hexmask.long.word 0x28 0.--15. 1. "SUBSEC,Value of SUBSEC.VALUE bits 31:16 at capture time"
|
|
line.long 0x2C "SYNC,AON SynchronizationThis register is used for synchronizing between MCU and entire AON domain"
|
|
hexmask.long 0x2C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "WBUSY,This register will always return 0 - however it will not return the value until there are no outstanding write requests between MCU and AONNote: Writing to this register prior to reading will force a wait until next SCLK_MF edge" "0,1"
|
|
line.long 0x30 "TIME,Current Counter Value"
|
|
hexmask.long.word 0x30 16.--31. 1. "SEC_L,Returns the lower halfword of SEC register"
|
|
hexmask.long.word 0x30 0.--15. 1. "SUBSEC_H,Returns the upper halfword of SUBSEC register"
|
|
line.long 0x34 "SYNCLF,Synchronization to SCLK_LFThis register is used for synchronizing MCU to positive or negative edge of SCLK_LF"
|
|
hexmask.long 0x34 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x34 0. "PHASE,This bit will always return the SCLK_LF phase" "Falling edge of SCLK_LF,Rising edge of SCLK_LF"
|
|
tree.end
|
|
tree.end
|
|
tree "AUX"
|
|
tree "AUX_ADI4"
|
|
base ad:0x400CB000
|
|
group.byte 0x00++0x05
|
|
line.byte 0x00 "MUX0,Internal"
|
|
bitfld.byte 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x00 6. "ADCCOMPB_IN,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
newline
|
|
bitfld.byte 0x00 4.--5. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "COMPA_REF,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.byte 0x01 "MUX1,Internal"
|
|
line.byte 0x02 "MUX2,Internal"
|
|
bitfld.byte 0x02 3.--7. "ADCCOMPB_IN,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x02 0.--2. "DAC_VREF_SEL,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?"
|
|
line.byte 0x03 "MUX3,Internal"
|
|
line.byte 0x04 "ISRC,Current SourceStrength and trim control for current source"
|
|
bitfld.byte 0x04 2.--7. "TRIM,Adjust current from current source.Output currents may be combined to get desired total current" "No current connected,0.25 uA,0.5 uA,?,1.0 uA,?,?,?,2.0 uA,?,?,?,?,?,?,?,4.5 uA,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,11.75 uA,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x04 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.byte 0x04 0. "EN,Current source enable" "0,1"
|
|
line.byte 0x05 "COMP,ComparatorControl COMPA and COMPB comparators"
|
|
bitfld.byte 0x05 7. "COMPA_REF_RES_EN,Enables 400kohm resistance from COMPA reference node to ground" "0,1"
|
|
bitfld.byte 0x05 6. "COMPA_REF_CURR_EN,Enables 2uA IPTAT current from ISRC to COMPA reference node" "0,1"
|
|
newline
|
|
bitfld.byte 0x05 3.--5. "LPM_BIAS_WIDTH_TRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x05 2. "COMPB_EN,COMPB enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x05 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x05 0. "COMPA_EN,COMPA enable" "0,1"
|
|
group.byte 0x07++0x04
|
|
line.byte 0x00 "MUX4,Internal"
|
|
line.byte 0x01 "ADC0,ADC Control 0ADC Sample Control"
|
|
bitfld.byte 0x01 7. "SMPL_MODE,ADC Sampling mode:0: Synchronous mode1: Asynchronous modeThe ADC does a sample-and-hold before conversion" "Synchronous mode,Asynchronous modeThe ADC does a.."
|
|
bitfld.byte 0x01 3.--6. "SMPL_CYCLE_EXP,Controls the sampling duration before conversion when the ADC is operated in synchronous mode (SMPL_MODE = 0)" "?,?,?,16x 6 MHz clock periods = 2.7us,32x 6 MHz clock periods = 5.3us,64x 6 MHz clock periods = 10.6us,128x 6 MHz clock periods = 21.3us,256x 6 MHz clock periods = 42.6us,512x 6 MHz clock periods = 85.3us,1024x 6 MHz clock periods = 170us,2048x 6 MHz clock periods = 341us,4096x 6 MHz clock periods = 682us,8192x 6 MHz clock periods = 1.37ms,16384x 6 MHz clock periods = 2.73ms,32768x 6 MHz clock periods = 5.46ms,65536x 6 MHz clock periods = 10.9ms"
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|
newline
|
|
bitfld.byte 0x01 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x01 1. "RESET_N,Reset ADC digital subchip active low" "Reset,Normal.."
|
|
newline
|
|
bitfld.byte 0x01 0. "EN,ADC Enable0: Disable1: Enable" "Disable,Enable"
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|
line.byte 0x02 "ADC1,ADC Control 1ADC Comparator Control"
|
|
hexmask.byte 0x02 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.byte 0x02 0. "SCALE_DIS,Internal" "0,1"
|
|
line.byte 0x03 "ADCREF0,ADC Reference 0Control reference used by the ADC"
|
|
bitfld.byte 0x03 7. "SPARE7,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x03 6. "REF_ON_IDLE,Enable ADCREF in IDLE state.0: Disabled in IDLE state1: Enabled in IDLE stateKeep ADCREF enabled when ADC0.SMPL_MODE =" "Disabled in IDLE state,Enabled in IDLE stateKeep ADCREF enabled when.."
|
|
newline
|
|
bitfld.byte 0x03 5. "IOMUX,Internal" "0,1"
|
|
bitfld.byte 0x03 4. "EXT,Internal" "0,1"
|
|
newline
|
|
bitfld.byte 0x03 3. "SRC,ADC reference source:0: Fixed reference =" "Fixed reference = 4.3V,Relative reference = VDDS"
|
|
bitfld.byte 0x03 1.--2. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x03 0. "EN,ADC reference module enable:0: ADC reference module powered down1: ADC reference module enabled" "ADC reference module powered down,ADC reference module enabled"
|
|
line.byte 0x04 "ADCREF1,ADC Reference 1Control reference used by the ADC"
|
|
bitfld.byte 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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|
bitfld.byte 0x04 0.--5. "VTRIM,Trim output voltage of ADC fixed reference (64 steps 2's complement)" "nominal voltage 1.43V,nominal + 0.4% 1.435V,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,maximum voltage 1.6V,minimum voltage 1.3V,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,nominal - 0.4% 1.425V"
|
|
group.byte 0x0E++0x01
|
|
line.byte 0x00 "LPMBIAS,Internal"
|
|
bitfld.byte 0x00 6.--7. "SPARE6,Internal" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. "LPM_TRIM_IOUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "STAT,Software should not rely on the value of a reserved"
|
|
tree.end
|
|
repeat 4. (list 0. 1. 2. 3. )(list ad:0x400CC000 ad:0x400CD000 ad:0x400CE000 ad:0x400CF000 )
|
|
tree "AUX_AIODIO$1"
|
|
base $2
|
|
group.long 0x00++0x47
|
|
line.long 0x00 "IOMODE,Input Output ModeThis register controls pull-up. pull-down. and output mode for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
newline
|
|
bitfld.long 0x00 14.--15. "IO7,Selects mode for AUXIO[8i+7]" "Output Mode:When IOPOE bit 7 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 7 is 0:..,Open-Drain Mode: When IOPOE bit 7 is 0: - If..,Open-Source Mode: When IOPOE bit 7 is 0: - If.."
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|
newline
|
|
bitfld.long 0x00 12.--13. "IO6,Selects mode for AUXIO[8i+6]" "Output Mode:When IOPOE bit 6 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 6 is 0:..,Open-Drain Mode: When IOPOE bit 6 is 0: - If..,Open-Source Mode: When IOPOE bit 6 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "IO5,Selects mode for AUXIO[8i+5]" "Output Mode:When IOPOE bit 5 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 5 is 0:..,Open-Drain Mode: When IOPOE bit 5 is 0: - If..,Open-Source Mode: When IOPOE bit 5 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 8.--9. "IO4,Selects mode for AUXIO[8i+4]" "Output Mode:When IOPOE bit 4 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 4 is 0:..,Open-Drain Mode: When IOPOE bit 4 is 0: - If..,Open-Source Mode: When IOPOE bit 4 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "IO3,Selects mode for AUXIO[8i+3]" "Output Mode:When IOPOE bit 3 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 3 is 0:..,Open-Drain Mode: When IOPOE bit 3 is 0: - If..,Open-Source Mode: When IOPOE bit 3 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "IO2,Select mode for AUXIO[8i+2]" "Output Mode:When IOPOE bit 2 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 2 is 0:..,Open-Drain Mode: When IOPOE bit 2 is 0: - If..,Open-Source Mode: When IOPOE bit 2 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IO1,Select mode for AUXIO[8i+1]" "Output Mode:When IOPOE bit 1 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 1 is 0:..,Open-Drain Mode: When IOPOE bit 1 is 0: - If..,Open-Source Mode: When IOPOE bit 1 is 0: - If.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "IO0,Select mode for AUXIO[8i+0]" "Output Mode:When IOPOE bit 0 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 0 is 0:..,Open-Drain Mode: When IOPOE bit 0 is 0: - If..,Open-Source Mode: When IOPOE bit 0 is 0: - If.."
|
|
line.long 0x04 "GPIODIE,General Purpose Input Output Digital Input EnableThis register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]"
|
|
line.long 0x08 "IOPOE,Input Output Peripheral Output EnableThis register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*].Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT"
|
|
line.long 0x0C "GPIODOUT,General Purpose Input Output Data OutThe output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to set AUXIO[8i+n].Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]"
|
|
line.long 0x10 "GPIODIN,General Purpose Input Output Data InThis register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "IO7_0,Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set"
|
|
line.long 0x14 "GPIODOUTSET,General Purpose Input Output Data Out SetSet bits in GPIODOUT in instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to set GPIODOUT bit n"
|
|
line.long 0x18 "GPIODOUTCLR,General Purpose Input Output Data Out ClearClear bits in GPIODOUT instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to clear GPIODOUT bit n.Read value is 0"
|
|
line.long 0x1C "GPIODOUTTGL,General Purpose Input Output Data Out ToggleToggle bits in GPIODOUT in instance i of AUX_AIODIO"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n"
|
|
line.long 0x20 "IO0PSEL,Input Output 0 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1"
|
|
hexmask.long 0x20 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x24 "IO1PSEL,Input Output 1 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1"
|
|
hexmask.long 0x24 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x28 "IO2PSEL,Input Output 2 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1"
|
|
hexmask.long 0x28 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x2C "IO3PSEL,Input Output 3 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1"
|
|
hexmask.long 0x2C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x2C 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x30 "IO4PSEL,Input Output 4 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1"
|
|
hexmask.long 0x30 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x30 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x34 "IO5PSEL,Input Output 5 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1"
|
|
hexmask.long 0x34 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x34 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x38 "IO6PSEL,Input Output 6 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1"
|
|
hexmask.long 0x38 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x38 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x3C "IO7PSEL,Input Output 7 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1"
|
|
hexmask.long 0x3C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x3C 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
|
|
line.long 0x40 "IOMODEL,Input Output Mode LowThis is an alias register for IOMODE.IO0 thru IOMODE.IO3"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x40 6.--7. "IO3,See IOMODE.IO3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x40 4.--5. "IO2,See IOMODE.IO2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x40 2.--3. "IO1,See IOMODE.IO1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x40 0.--1. "IO0,See IOMODE.IO0" "0,1,2,3"
|
|
line.long 0x44 "IOMODEH,Input Output Mode HighThis is an alias register for IOMODE.IO4 thru IOMODE.IO7"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x44 6.--7. "IO7,See IOMODE.IO7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x44 4.--5. "IO6,See IOMODE.IO6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x44 2.--3. "IO5,See IOMODE.IO5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x44 0.--1. "IO4,See IOMODE.IO4" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
tree "AUX_ANAIF"
|
|
base ad:0x400C9000
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "ADCCTL,ADC ControlConfiguration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 14. "START_POL,Select active polarity for START_SRC event" "Set ADC trigger on rising edge of event source.,Set ADC trigger on falling edge of event source."
|
|
newline
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bitfld.long 0x00 8.--13. "START_SRC,Select ADC trigger event source from the asynchronous AUX event bus.Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10,AUX_EVCTL:EVSTAT0.AUXIO11,AUX_EVCTL:EVSTAT0.AUXIO12,AUX_EVCTL:EVSTAT0.AUXIO13,AUX_EVCTL:EVSTAT0.AUXIO14,AUX_EVCTL:EVSTAT0.AUXIO15,AUX_EVCTL:EVSTAT1.AUXIO16,AUX_EVCTL:EVSTAT1.AUXIO17,AUX_EVCTL:EVSTAT1.AUXIO18,AUX_EVCTL:EVSTAT1.AUXIO19,AUX_EVCTL:EVSTAT1.AUXIO20,AUX_EVCTL:EVSTAT1.AUXIO21,AUX_EVCTL:EVSTAT1.AUXIO22,AUX_EVCTL:EVSTAT1.AUXIO23,AUX_EVCTL:EVSTAT1.AUXIO24,AUX_EVCTL:EVSTAT1.AUXIO25,AUX_EVCTL:EVSTAT1.AUXIO26,AUX_EVCTL:EVSTAT1.AUXIO27,AUX_EVCTL:EVSTAT1.AUXIO28,AUX_EVCTL:EVSTAT1.AUXIO29,AUX_EVCTL:EVSTAT1.AUXIO30,AUX_EVCTL:EVSTAT1.AUXIO31,AUX_EVCTL:EVSTAT2.MANUAL_EV ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,?,?,AUX_EVCTL:EVSTAT2.AUX_COMPA,AUX_EVCTL:EVSTAT2.AUX_COMPB,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,?,?,?,?,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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rbitfld.long 0x00 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--1. "CMD,ADC interface command.Non-enumerated values are not supported" "Disable ADC interface.,Enable ADC interface.,?,Flush ADC FIFO.You must set CMD to EN or DIS.."
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line.long 0x04 "ADCFIFOSTAT,ADC FIFO StatusFIFO can hold up to four ADC samples"
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hexmask.long 0x04 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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bitfld.long 0x04 4. "OVERFLOW,FIFO overflow flag.0: FIFO has not overflowed.1: FIFO has overflowed this flag is sticky until you flush the FIFO.When the flag is set the ADC FIFO write pointer is static" "FIFO has not overflowed,FIFO has overflowed this flag is sticky until.."
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bitfld.long 0x04 3. "UNDERFLOW,FIFO underflow flag.0: FIFO has not underflowed.1: FIFO has underflowed this flag is sticky until you flush the FIFO.When the flag is set the ADC FIFO read pointer is static" "FIFO has not underflowed,FIFO has underflowed this flag is sticky until.."
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bitfld.long 0x04 2. "FULL,FIFO full flag.0: FIFO is not full there is less than 4 samples in the FIFO" "FIFO is not full there is less than 4 samples in..,FIFO is full there are 4 samples in the.."
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bitfld.long 0x04 1. "ALMOST_FULL,FIFO almost full flag.0: There are less than 3 samples in the FIFO or the FIFO is full" "There are less than 3 samples in the FIFO or the..,There are 3 samples in the FIFO there is room.."
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bitfld.long 0x04 0. "EMPTY,FIFO empty flag.0: FIFO contains one or more samples.1: FIFO is empty.When the flag is set read returns the previous sample that was read and sets the UNDERFLOW flag" "FIFO contains one or more samples,FIFO is empty.When the flag is set read returns.."
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line.long 0x08 "ADCFIFO,ADC FIFO"
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hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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hexmask.long.word 0x08 0.--11. 1. "DATA,FIFO data.Read:Get oldest ADC sample from FIFO.Write:Write dummy sample to FIFO"
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line.long 0x0C "ADCTRIG,ADC Trigger"
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hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 0. "START,Manual ADC trigger" "0,1"
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line.long 0x10 "ISRCCTL,Current Source Control"
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hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x10 0. "RESET_N,ISRC reset control.0: ISRC drives 0 uA.1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN" "ISRC drives 0 uA,ISRC drives current ADI_4_AUX"
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group.long 0x30++0x1B
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line.long 0x00 "DACCTL,DAC ControlThis register controls the analog part of the DAC."
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hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x00 5. "DAC_EN,DAC module enable.0: Disable DAC.1: Enable DAC.The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA.The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA in Standby TI-RTOS power mode" "Disable DAC,Enable DAC.The Sensor.."
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bitfld.long 0x00 4. "DAC_BUFFER_EN,DAC buffer enable.DAC buffer reduces the time required to produce the programmed voltage at the expense of increased current consumption.0: Disable DAC buffer.1: Enable DAC buffer.Enable buffer when DAC_VOUT_SEL equals COMPA_IN.Do not.." "Disable DAC buffer,Enable DAC buffer.Enable buffer when.."
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bitfld.long 0x00 3. "DAC_PRECHARGE_EN,DAC precharge enable.Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and VDDS is higher than 2.65 V" "0 V to 1.28 V,1.28 V to 2.56 V"
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bitfld.long 0x00 0.--2. "DAC_VOUT_SEL,DAC output connection.An analog node must only have one driver" "Connect to nothingIt is recommended to use NC..,Connect to COMPB_REF analog node.Required..,Connect to COMPA_REF analog node.It is not..,?,Connect to COMPA_IN analog node.Required..,?,?,?"
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line.long 0x04 "LPMBIASCTL,Low Power Mode Bias ControlThe low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x04 0. "EN,Module enable.0: Disable low power mode bias module.1: Enable low power mode bias module.Set EN to 1 15 us before you enable the DAC or Comparator A" "Disable low power mode bias module,Enable low power mode bias module.Set EN to 1 15.."
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line.long 0x08 "DACSMPLCTL,DAC Sample ControlThe DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor"
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hexmask.long 0x08 1.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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bitfld.long 0x08 0. "EN,DAC sample clock enable.0: Disable sample clock" "Disable sample clock,Enable DAC sample clock"
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line.long 0x0C "DACSMPLCFG0,DAC Sample Configuration 0"
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hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 0.--5. "CLKDIV,Clock division.AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the sample clock base frequency" "Divide by 1,Divide by 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 64"
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line.long 0x10 "DACSMPLCFG1,DAC Sample Configuration 1The sample clock period equals (high time + low time) * base period"
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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bitfld.long 0x10 14. "H_PER,High time.The sample clock period is high for this many base periods.0: 2 periods1: 4 periods" "2 periods,4 periods"
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bitfld.long 0x10 12.--13. "L_PER,Low time.The sample clock period is low for this many base periods.0: 1 period1: 2 periods2: 3 periods3: 4 periods" "1 period,2 periods,3 periods,4 periods"
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bitfld.long 0x10 8.--11. "SETUP_CNT,Setup count.Number of active sample clock periods during the setup phase.0: 1 sample clock period" "1 sample clock period,2 sample clock periods,?,?,?,?,?,?,?,?,?,?,?,?,?,16 sample clock periods"
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hexmask.long.byte 0x10 0.--7. 1. "HOLD_INTERVAL,Hold interval.Number of inactive sample clock periods between each active sample clock period during hold phase"
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line.long 0x14 "DACVALUE,DAC Value"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x14 0.--7. 1. "VALUE,DAC value.Digital data word for the DAC.Only change VALUE when DACCTL.DAC_EN is 0"
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line.long 0x18 "DACSTAT,DAC Status"
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hexmask.long 0x18 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x18 1. "SETUP_ACTIVE,DAC setup phase status.0: Sample clock is disabled or setup phase is complete.1: Setup phase in progress" "Sample clock is disabled or setup phase is..,Setup phase in progress"
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bitfld.long 0x18 0. "HOLD_ACTIVE,DAC hold phase status.0: Sample clock is disabled or DAC is not in hold phase.1: Hold phase in progress" "Sample clock is disabled or DAC is not in hold..,Hold phase in progress"
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tree.end
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tree "AUX_DDI0_OSC"
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base ad:0x400CA000
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group.long 0x00++0x37
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line.long 0x00 "CTL0,Control 0Controls clock source selects"
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bitfld.long 0x00 31. "XTAL_IS_24M,Set based on the accurate high frequency XTAL" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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bitfld.long 0x00 30. "RESERVED30,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 29. "BYPASS_XOSC_LF_CLK_QUAL,Internal" "0,1"
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bitfld.long 0x00 28. "BYPASS_RCOSC_LF_CLK_QUAL,Internal" "0,1"
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bitfld.long 0x00 26.--27. "DOUBLER_START_DURATION,Internal" "0,1,2,3"
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bitfld.long 0x00 25. "DOUBLER_RESET_DURATION,Internal" "0,1"
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bitfld.long 0x00 24. "CLK_DCDC_SRC_SEL,Select DCDC clock source.0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC1: CLK_DCDC is always 48 MHz clock from RCOSC" "CLK_DCDC is 48 MHz clock from RCOSC or XOSC /..,CLK_DCDC is always 48 MHz clock from RCOSC"
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hexmask.long.word 0x00 15.--23. 1. "RESERVED15,Software should not rely on the value of a reserved"
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bitfld.long 0x00 14. "HPOSC_MODE_EN," "0,1"
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bitfld.long 0x00 13. "RESERVED13,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 12. "RCOSC_LF_TRIMMED,Internal" "0,1"
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bitfld.long 0x00 11. "XOSC_HF_POWER_MODE,Internal" "0,1"
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bitfld.long 0x00 10. "XOSC_LF_DIG_BYPASS,Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock.0: Use 32kHz XOSC as xosc_lf clock source1: Use digital input (from AON) as xosc_lf clock source.This bit will only have effect when SCLK_LF_SRC_SEL is.." "Use 32kHz XOSC as xosc_lf clock source,Use digital input (from AON) as xosc_lf clock.."
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bitfld.long 0x00 9. "CLK_LOSS_EN,Enable clock loss detection and hence the indicators to the system controller" "Disable,EnableClock loss.."
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bitfld.long 0x00 7.--8. "ACLK_TDC_SRC_SEL,Source select for aclk_tdc.00: RCOSC_HF (48MHz)01: RCOSC_HF (24MHz)10: XOSC_HF (24MHz)11: Not used" "RCOSC_HF (48MHz),RCOSC_HF (24MHz),?..."
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bitfld.long 0x00 4.--6. "ACLK_REF_SRC_SEL,Source select for aclk_ref000: RCOSC_HF derived (31.25kHz)001: XOSC_HF derived (31.25kHz)010: RCOSC_LF (32kHz)011: XOSC_LF (32.768kHz)100: RCOSC_MF (2MHz)101-111: Not used" "RCOSC_HF derived (31.25kHz),XOSC_HF derived (31.25kHz),?..."
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bitfld.long 0x00 2.--3. "SCLK_LF_SRC_SEL,Source select for sclk_lf" "Low frequency clock derived from High Frequency..,Low frequency clock derived from High Frequency..,Low frequency RCOSC,Low frequency XOSC"
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bitfld.long 0x00 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x00 0. "SCLK_HF_SRC_SEL,Source select for sclk_hf" "High frequency RCOSC clock,High frequency XOSC or HPOSC clk (use HPOSC when.."
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line.long 0x04 "CTL1,Control 1This register contains OSC_DIG configuration"
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hexmask.long.word 0x04 23.--31. 1. "RESERVED23,Software should not rely on the value of a reserved"
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bitfld.long 0x04 18.--22. "RCOSCHFCTRIMFRACT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 17. "RCOSCHFCTRIMFRACT_EN,Internal" "0,1"
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hexmask.long.byte 0x04 10.--16. 1. "SPARE10,Software should not rely on the value of a reserved"
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bitfld.long 0x04 9. "FORCE_RCOSC_LF,Force rcosc_lf to be enabled0: Disabled1: Enabled" "Disabled,Enabled"
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bitfld.long 0x04 8. "CLK_LF_LOSS_EN,Enable LF clock loss detection and hence the indicators to the system controller" "Disable,EnableClock loss.."
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bitfld.long 0x04 2.--7. "SPARE2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 0.--1. "XOSC_HF_FAST_START,Internal" "0,1,2,3"
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line.long 0x08 "RADCEXTCFG,RADC External Configuration"
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hexmask.long.word 0x08 22.--31. 1. "HPM_IBIAS_WAIT_CNT,Internal"
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bitfld.long 0x08 16.--21. "LPM_IBIAS_WAIT_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 12.--15. "IDAC_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 6.--11. "RADC_DAC_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 5. "RADC_MODE_IS_SAR,Internal" "0,1"
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bitfld.long 0x08 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x0C "AMPCOMPCTL,Amplitude Compensation Control"
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bitfld.long 0x0C 31. "SPARE31,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x0C 30. "AMPCOMP_REQ_MODE,Internal" "0,1"
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bitfld.long 0x0C 28.--29. "AMPCOMP_FSM_UPDATE_RATE,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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bitfld.long 0x0C 27. "AMPCOMP_SW_CTRL,Internal" "0,1"
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bitfld.long 0x0C 26. "AMPCOMP_SW_EN,Internal" "0,1"
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bitfld.long 0x0C 24.--25. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x0C 20.--23. "IBIAS_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "IBIAS_INIT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "LPM_IBIAS_WAIT_CNT_FINAL,Internal"
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bitfld.long 0x0C 4.--7. "CAP_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "IBIASCAP_HPTOLP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x10 "AMPCOMPTH1,Amplitude Compensation Threshold 1This register contains threshold values for amplitude compensation algorithm"
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hexmask.long.byte 0x10 24.--31. 1. "SPARE24,Software should not rely on the value of a reserved"
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bitfld.long 0x10 18.--23. "HPMRAMP3_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 16.--17. "SPARE16,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x10 10.--15. "HPMRAMP3_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 6.--9. "IBIASCAP_LPTOHP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0.--5. "HPMRAMP1_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x14 "AMPCOMPTH2,Amplitude Compensation Threshold 2This register contains threshold values for amplitude compensation algorithm."
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bitfld.long 0x14 26.--31. "LPMUPDATE_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 24.--25. "SPARE24,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x14 18.--23. "LPMUPDATE_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x14 16.--17. "SPARE16,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x14 10.--15. "ADC_COMP_AMPTH_LPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x14 8.--9. "SPARE8,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x14 2.--7. "ADC_COMP_AMPTH_HPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x14 0.--1. "SPARE0,Software should not rely on the value of a reserved" "0,1,2,3"
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line.long 0x18 "ANABYPASSVAL1,Analog Bypass Values 1"
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hexmask.long.word 0x18 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 16.--19. "XOSC_HF_ROW_Q12,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.word 0x18 0.--15. 1. "XOSC_HF_COLUMN_Q12,Internal"
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line.long 0x1C "ANABYPASSVAL2,Internal"
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hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--13. 1. "XOSC_HF_IBIASTHERM,Internal"
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line.long 0x20 "ATESTCTL,Analog Test Control"
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bitfld.long 0x20 31. "SCLK_LF_AUX_EN,Enable 32 kHz clock to AUX_COMPB." "0,1"
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newline
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hexmask.long.word 0x20 16.--30. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 14.--15. "TEST_RCOSCMF,Test mode control for RCOSC_MF0x0: test modes" "test modes disabled,boosted bias current into self biased inverter,clock qualification disabled,boosted bias current into self biased inverter +.."
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newline
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bitfld.long 0x20 12.--13. "ATEST_RCOSCMF,ATEST control for RCOSC_MF0x0: ATEST" "ATEST disabled,ATEST enabled VDD_LOCAL connected ATEST internal..,ATEST disabled,ATEST enabled bias current connected ATEST.."
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newline
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hexmask.long.word 0x20 0.--11. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x24 "ADCDOUBLERNANOAMPCTL,ADC Doubler Nanoamp Control"
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hexmask.long.byte 0x24 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 24. "NANOAMP_BIAS_ENABLE,Internal" "0,1"
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newline
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bitfld.long 0x24 23. "SPARE23,Software should not rely on the value of a reserved" "0,1"
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newline
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hexmask.long.tbyte 0x24 6.--22. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 5. "ADC_SH_MODE_EN,Internal" "0,1"
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newline
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bitfld.long 0x24 4. "ADC_SH_VBUF_EN,Internal" "0,1"
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newline
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bitfld.long 0x24 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x24 0.--1. "ADC_IREF_CTRL,Internal" "0,1,2,3"
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line.long 0x28 "XOSCHFCTL,XOSCHF Control"
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hexmask.long.tbyte 0x28 14.--31. 1. "SPARE14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x28 13. "TCXO_MODE_XOSC_HF_EN,If this register is 1 when TCXO_MODE is 1 then the XOSC_HF is enabled turning on the XOSC_HF bias current allowing a DC bias point to be provided to the clipped-sine wave clock signal on external input" "0,1"
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newline
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bitfld.long 0x28 12. "TCXO_MODE,If this register is 1 when BYPASS is 1 this will enable clock qualification on the TCXO clock on external input" "0,1"
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newline
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bitfld.long 0x28 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x28 8.--9. "PEAK_DET_ITRIM,Internal" "0,1,2,3"
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newline
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bitfld.long 0x28 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x28 6. "BYPASS,Internal" "0,1"
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newline
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bitfld.long 0x28 5. "RESERVED5,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x28 2.--4. "HP_BUF_ITRIM,Internal" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x28 0.--1. "LP_BUF_ITRIM,Internal" "0,1,2,3"
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line.long 0x2C "LFOSCCTL,Low Frequency Oscillator Control"
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hexmask.long.byte 0x2C 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 22.--23. "XOSCLF_REGULATOR_TRIM,Internal" "0,1,2,3"
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newline
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bitfld.long 0x2C 18.--21. "XOSCLF_CMIRRWR_RATIO,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x2C 10.--17. 1. "RESERVED10,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 8.--9. "RCOSCLF_RTUNE_TRIM,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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newline
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hexmask.long.byte 0x2C 0.--7. 1. "RCOSCLF_CTUNE_TRIM,Internal"
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line.long 0x30 "RCOSCHFCTL,RCOSCHF Control"
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hexmask.long.word 0x30 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x30 8.--15. 1. "RCOSCHF_CTRIM,Internal"
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newline
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hexmask.long.byte 0x30 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x34 "RCOSCMFCTL,RCOSC_MF Control"
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hexmask.long.word 0x34 16.--31. 1. "SPARE16,Software should not rely on the value of a reserved"
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newline
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abitfld.long 0x34 9.--15. "RCOSC_MF_CAP_ARRAY,Adjust RCOSC_MF capacitor" "0x00=nominal frequency 0.625pF,0x3F=lowest frequency 1.125pF,0x40=highest frequency 0.125pF"
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newline
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bitfld.long 0x34 8. "RCOSC_MF_REG_SEL,Choose regulator type.0: default1: alternate" "default,alternate"
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newline
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bitfld.long 0x34 6.--7. "RCOSC_MF_RES_COARSE,Select coarse resistor for frequency" "400kohms default,300kohms min,600kohms max,500kohms"
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newline
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bitfld.long 0x34 4.--5. "RCOSC_MF_RES_FINE,Select fine resistor for frequency" "11kohms minimum resistance max freq,13kohms,16kohms,20kohms max resistance min freq"
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newline
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bitfld.long 0x34 0.--3. "RCOSC_MF_BIAS_ADJ,Adjusts bias current to RCOSC_MF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x3C++0x0B
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line.long 0x00 "STAT0,Status 0This register contains status signals from OSC_DIG"
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bitfld.long 0x00 31. "RCOSC_LF_GOOD,RCOSC_LF_GOOD" "0,1"
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newline
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bitfld.long 0x00 29.--30. "SCLK_LF_SRC,Indicates source for the sclk_lf" "Low frequency clock derived from High Frequency..,Low frequency clock derived from High Frequency..,Low frequency RCOSC,Low frequency XOSC"
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newline
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bitfld.long 0x00 28. "SCLK_HF_SRC,Indicates source for the sclk_hf" "High frequency RCOSC clock,High frequency XOSC"
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newline
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bitfld.long 0x00 23.--27. "RESERVED23,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 22. "RCOSC_HF_EN,RCOSC_HF_EN" "0,1"
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newline
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bitfld.long 0x00 21. "RCOSC_LF_EN,RCOSC_LF_EN" "0,1"
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newline
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bitfld.long 0x00 20. "XOSC_LF_EN,XOSC_LF_EN" "0,1"
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newline
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bitfld.long 0x00 19. "CLK_DCDC_RDY,CLK_DCDC_RDY" "0,1"
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newline
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bitfld.long 0x00 18. "CLK_DCDC_RDY_ACK,CLK_DCDC_RDY_ACK" "0,1"
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newline
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bitfld.long 0x00 17. "SCLK_HF_LOSS,Indicates sclk_hf is lost" "0,1"
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newline
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bitfld.long 0x00 16. "SCLK_LF_LOSS,Indicates sclk_lf is lost" "0,1"
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newline
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bitfld.long 0x00 15. "XOSC_HF_EN,Indicates that XOSC_HF is enabled" "0,1"
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newline
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bitfld.long 0x00 14. "RESERVED14,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 13. "XB_48M_CLK_EN,Indicates that the 48MHz clock from the DOUBLER is enabled.It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal)" "0,1"
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newline
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bitfld.long 0x00 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 11. "XOSC_HF_LP_BUF_EN,XOSC_HF_LP_BUF_EN" "0,1"
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newline
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bitfld.long 0x00 10. "XOSC_HF_HP_BUF_EN,XOSC_HF_HP_BUF_EN" "0,1"
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newline
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bitfld.long 0x00 9. "RESERVED9,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 8. "ADC_THMET,ADC_THMET" "0,1"
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newline
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bitfld.long 0x00 7. "ADC_DATA_READY,indicates when adc_data is ready" "0,1"
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newline
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bitfld.long 0x00 1.--6. "ADC_DATA,adc_data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0. "PENDINGSCLKHFSWITCHING,Indicates when SCLK_HF clock source is ready to be switched" "0,1"
|
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line.long 0x04 "STAT1,Status 1This register contains status signals from OSC_DIG"
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bitfld.long 0x04 28.--31. "RAMPSTATE,AMPCOMP FSM State" "RESET,INITIALIZATION,HPM_RAMP1,HPM_RAMP2,HPM_RAMP3,HPM_UPDATE,IDAC_INCREMENT,IBIAS_CAP_UPDATE,IBIAS_DECREMENT_WITH_MEASURE,LPM_UPDATE,IBIAS_INCREMENT,IDAC_DECREMENT_WITH_MEASURE,DUMMY_TO_INIT_1,FAST_START,FAST_START_SETTLE,?"
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newline
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bitfld.long 0x04 22.--27. "HPM_UPDATE_AMP,XOSC_HF amplitude during HPM_UPDATE state.When amplitude compensation of XOSC_HF is enabled in high performance mode this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC divided by 15 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x04 16.--21. "LPM_UPDATE_AMP,XOSC_HF amplitude during LPM_UPDATE stateWhen amplitude compensation of XOSC_HF is enabled in low power mode this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC divided by 15 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x04 15. "FORCE_RCOSC_HF,force_rcosc_hf" "0,1"
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newline
|
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bitfld.long 0x04 14. "SCLK_HF_EN,SCLK_HF_EN" "0,1"
|
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newline
|
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bitfld.long 0x04 13. "SCLK_MF_EN,SCLK_MF_EN" "0,1"
|
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newline
|
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bitfld.long 0x04 12. "ACLK_ADC_EN,ACLK_ADC_EN" "0,1"
|
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newline
|
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bitfld.long 0x04 11. "ACLK_TDC_EN,ACLK_TDC_EN" "0,1"
|
|
newline
|
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bitfld.long 0x04 10. "ACLK_REF_EN,ACLK_REF_EN" "0,1"
|
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newline
|
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bitfld.long 0x04 9. "CLK_CHP_EN,CLK_CHP_EN" "0,1"
|
|
newline
|
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bitfld.long 0x04 8. "CLK_DCDC_EN,CLK_DCDC_EN" "0,1"
|
|
newline
|
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bitfld.long 0x04 7. "SCLK_HF_GOOD,SCLK_HF_GOOD" "0,1"
|
|
newline
|
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bitfld.long 0x04 6. "SCLK_MF_GOOD,SCLK_MF_GOOD" "0,1"
|
|
newline
|
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bitfld.long 0x04 5. "SCLK_LF_GOOD,SCLK_LF_GOOD" "0,1"
|
|
newline
|
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bitfld.long 0x04 4. "ACLK_ADC_GOOD,ACLK_ADC_GOOD" "0,1"
|
|
newline
|
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bitfld.long 0x04 3. "ACLK_TDC_GOOD,ACLK_TDC_GOOD" "0,1"
|
|
newline
|
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bitfld.long 0x04 2. "ACLK_REF_GOOD,ACLK_REF_GOOD" "0,1"
|
|
newline
|
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bitfld.long 0x04 1. "CLK_CHP_GOOD,CLK_CHP_GOOD" "0,1"
|
|
newline
|
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bitfld.long 0x04 0. "CLK_DCDC_GOOD,CLK_DCDC_GOOD" "0,1"
|
|
line.long 0x08 "STAT2,Status 2This register contains status signals from AMPCOMP FSM"
|
|
bitfld.long 0x08 26.--31. "ADC_DCBIAS,DC Bias read by RADC during SAR modeThe value is an unsigned integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x08 25. "HPM_RAMP1_THMET,Indication of threshold is met for hpm_ramp1" "0,1"
|
|
newline
|
|
bitfld.long 0x08 24. "HPM_RAMP2_THMET,Indication of threshold is met for hpm_ramp2" "0,1"
|
|
newline
|
|
bitfld.long 0x08 23. "HPM_RAMP3_THMET,Indication of threshold is met for hpm_ramp3" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x08 16.--22. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 12.--15. "RAMPSTATE,xosc_hf amplitude compensation FSMThis is identical to STAT1.RAMPSTATE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x08 4.--11. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 3. "AMPCOMP_REQ,ampcomp_req" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "XOSC_HF_AMPGOOD,amplitude of xosc_hf is within the required threshold (set by DDI)" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "XOSC_HF_FREQGOOD,frequency of xosc_hf is good to use for the digital clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "XOSC_HF_RF_FREQGOOD,frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations" "0,1"
|
|
tree.end
|
|
tree "AUX_EVCTL"
|
|
base ad:0x400C5000
|
|
rgroup.long 0x00++0x1B
|
|
line.long 0x00 "EVSTAT0,Event Status 0Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 15. "AUXIO15,AUXIO15 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "AUXIO14,AUXIO14 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "AUXIO13,AUXIO13 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "AUXIO12,AUXIO12 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "AUXIO11,AUXIO11 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "AUXIO10,AUXIO10 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "AUXIO9,AUXIO9 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "AUXIO8,AUXIO8 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "AUXIO7,AUXIO7 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "AUXIO6,AUXIO6 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "AUXIO5,AUXIO5 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "AUXIO4,AUXIO4 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AUXIO3,AUXIO3 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "AUXIO2,AUXIO2 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AUXIO1,AUXIO1 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "AUXIO0,AUXIO0 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 0" "0,1"
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line.long 0x04 "EVSTAT1,Event Status 1Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "AUXIO31,AUXIO31 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 7" "0,1"
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bitfld.long 0x04 14. "AUXIO30,AUXIO30 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 6" "0,1"
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bitfld.long 0x04 13. "AUXIO29,AUXIO29 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 5" "0,1"
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bitfld.long 0x04 12. "AUXIO28,AUXIO28 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 4" "0,1"
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bitfld.long 0x04 11. "AUXIO27,AUXIO27 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 3" "0,1"
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bitfld.long 0x04 10. "AUXIO26,AUXIO26 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 2" "0,1"
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bitfld.long 0x04 9. "AUXIO25,AUXIO25 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 1" "0,1"
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bitfld.long 0x04 8. "AUXIO24,AUXIO24 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 0" "0,1"
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bitfld.long 0x04 7. "AUXIO23,AUXIO23 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 7" "0,1"
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bitfld.long 0x04 6. "AUXIO22,AUXIO22 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 6" "0,1"
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bitfld.long 0x04 5. "AUXIO21,AUXIO21 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 5" "0,1"
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bitfld.long 0x04 4. "AUXIO20,AUXIO20 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 4" "0,1"
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bitfld.long 0x04 3. "AUXIO19,AUXIO19 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 3" "0,1"
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bitfld.long 0x04 2. "AUXIO18,AUXIO18 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 2" "0,1"
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bitfld.long 0x04 1. "AUXIO17,AUXIO17 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 1" "0,1"
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bitfld.long 0x04 0. "AUXIO16,AUXIO16 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 0" "0,1"
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line.long 0x08 "EVSTAT2,Event Status 2Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x08 15. "AUX_COMPB,Comparator B output" "0,1"
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bitfld.long 0x08 14. "AUX_COMPA,Comparator A output" "0,1"
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bitfld.long 0x08 13. "MCU_OBSMUX1,Observation input 1 from IOC" "0,1"
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bitfld.long 0x08 12. "MCU_OBSMUX0,Observation input 0 from IOC" "0,1"
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bitfld.long 0x08 11. "MCU_EV,Event from EVENT configured by EVENT:AUXSEL0" "0,1"
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bitfld.long 0x08 10. "ACLK_REF,TDC reference clock.It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ" "0,1"
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bitfld.long 0x08 9. "VDDR_RECHARGE,Event is high during VDDR recharge" "0,1"
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bitfld.long 0x08 8. "MCU_ACTIVE,Event is high while system(MCU AUX or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state)" "0,1"
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bitfld.long 0x08 7. "PWR_DWN,Event is high while system(MCU AUX or JTAG domains) is in powerdown (uLDO power supply)" "0,1"
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bitfld.long 0x08 6. "SCLK_LF,SCLK_LF clock" "0,1"
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bitfld.long 0x08 5. "AON_BATMON_TEMP_UPD,Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP" "0,1"
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bitfld.long 0x08 4. "AON_BATMON_BAT_UPD,Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT" "0,1"
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bitfld.long 0x08 3. "AON_RTC_4KHZ,AON_RTC:SUBSEC.VALUE bit" "0,1"
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bitfld.long 0x08 2. "AON_RTC_CH2_DLY,AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration" "0,1"
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bitfld.long 0x08 1. "AON_RTC_CH2,AON_RTC:EVFLAGS.CH2" "0,1"
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bitfld.long 0x08 0. "MANUAL_EV,Programmable event" "0,1"
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line.long 0x0C "EVSTAT3,Event Status 3Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 15. "AUX_TIMER2_CLKSWITCH_RDY,AUX_SYSIF:TIMER2CLKSWITCH.RDY" "0,1"
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bitfld.long 0x0C 14. "AUX_DAC_HOLD_ACTIVE,AUX_ANAIF:DACSTAT.HOLD_ACTIVE" "0,1"
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bitfld.long 0x0C 13. "AUX_SMPH_AUTOTAKE_DONE,See AUX_SMPH:AUTOTAKE.SMPH_ID for description" "0,1"
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bitfld.long 0x0C 12. "AUX_ADC_FIFO_NOT_EMPTY,AUX_ANAIF:ADCFIFOSTAT.EMPTY negated" "0,1"
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bitfld.long 0x0C 11. "AUX_ADC_FIFO_ALMOST_FULL,AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL" "0,1"
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bitfld.long 0x0C 10. "AUX_ADC_IRQ,The logical function for this event is configurable.When DMACTL.EN =" "0,1"
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bitfld.long 0x0C 9. "AUX_ADC_DONE,AUX_ANAIF ADC conversion done event" "0,1"
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bitfld.long 0x0C 8. "AUX_ISRC_RESET_N,AUX_ANAIF:ISRCCTL.RESET_N" "0,1"
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bitfld.long 0x0C 7. "AUX_TDC_DONE,AUX_TDC:STAT.DONE" "0,1"
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bitfld.long 0x0C 6. "AUX_TIMER0_EV,AUX_TIMER0_EV event see AUX_TIMER01:T0TARGET for description" "0,1"
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bitfld.long 0x0C 5. "AUX_TIMER1_EV,AUX_TIMER1_EV event see AUX_TIMER01:T1TARGET for description" "0,1"
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bitfld.long 0x0C 4. "AUX_TIMER2_PULSE,AUX_TIMER2 pulse event" "0,1"
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bitfld.long 0x0C 3. "AUX_TIMER2_EV3,AUX_TIMER2 event output 3" "0,1"
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bitfld.long 0x0C 2. "AUX_TIMER2_EV2,AUX_TIMER2 event output 2" "0,1"
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bitfld.long 0x0C 1. "AUX_TIMER2_EV1,AUX_TIMER2 event output 1" "0,1"
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bitfld.long 0x0C 0. "AUX_TIMER2_EV0,AUX_TIMER2 event output 0" "0,1"
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line.long 0x10 "SCEWEVCFG0,Sensor Controller Engine Wait Event Configuration 0Configuration of this register and SCEWEVCFG1 controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS"
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hexmask.long 0x10 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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bitfld.long 0x10 6. "COMB_EV_EN,Event combination control:0: Disable event combination.1: Enable event combination" "Disable event combination,Enable event combination"
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bitfld.long 0x10 0.--5. "EV0_SEL,Select the event source from the synchronous event bus to be used in event equation" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10 ,EVSTAT0.AUXIO11 ,EVSTAT0.AUXIO12 ,EVSTAT0.AUXIO13 ,EVSTAT0.AUXIO14 ,EVSTAT0.AUXIO15 ,EVSTAT1.AUXIO16 ,EVSTAT1.AUXIO17 ,EVSTAT1.AUXIO18 ,EVSTAT1.AUXIO19 ,EVSTAT1.AUXIO20 ,EVSTAT1.AUXIO21 ,EVSTAT1.AUXIO22 ,EVSTAT1.AUXIO23 ,EVSTAT1.AUXIO24 ,EVSTAT1.AUXIO25 ,EVSTAT1.AUXIO26 ,EVSTAT1.AUXIO27 ,EVSTAT1.AUXIO28 ,EVSTAT1.AUXIO29 ,EVSTAT1.AUXIO30 ,EVSTAT1.AUXIO31 ,Programmable delay event as described in PROGDLY,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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line.long 0x14 "SCEWEVCFG1,Sensor Controller Engine Wait Event Configuration 1See SCEWEVCFG0 for description"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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bitfld.long 0x14 7. "EV0_POL,Polarity of SCEWEVCFG0.EV0_SEL event.When SCEWEVCFG0.COMB_EV_EN is" "Non-inverted,Inverted"
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bitfld.long 0x14 6. "EV1_POL,Polarity of EV1_SEL event.When SCEWEVCFG0.COMB_EV_EN is" "Non-inverted,Inverted"
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bitfld.long 0x14 0.--5. "EV1_SEL,Select the event source from the synchronous event bus to be used in event equation" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10 ,EVSTAT0.AUXIO11 ,EVSTAT0.AUXIO12 ,EVSTAT0.AUXIO13 ,EVSTAT0.AUXIO14 ,EVSTAT0.AUXIO15 ,EVSTAT1.AUXIO16 ,EVSTAT1.AUXIO17 ,EVSTAT1.AUXIO18 ,EVSTAT1.AUXIO19 ,EVSTAT1.AUXIO20 ,EVSTAT1.AUXIO21 ,EVSTAT1.AUXIO22 ,EVSTAT1.AUXIO23 ,EVSTAT1.AUXIO24 ,EVSTAT1.AUXIO25 ,EVSTAT1.AUXIO26 ,EVSTAT1.AUXIO27 ,EVSTAT1.AUXIO28 ,EVSTAT1.AUXIO29 ,EVSTAT1.AUXIO30 ,EVSTAT1.AUXIO31 ,Programmable delay event as described in PROGDLY,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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line.long 0x18 "DMACTL,Direct Memory Access Control"
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hexmask.long 0x18 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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bitfld.long 0x18 2. "REQ_MODE,UDMA0 Request mode" "Burst requests are generated on UDMA0 channel 7..,Single requests are generated on UDMA0 channel 7.."
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bitfld.long 0x18 1. "EN,uDMA ADC interface enable.0: Disable UDMA0 interface to ADC.1: Enable UDMA0 interface to ADC" "Disable UDMA0 interface to ADC,Enable UDMA0 interface to ADC"
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bitfld.long 0x18 0. "SEL,Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data" "UDMA0 trigger event will be generated when there..,UDMA0 trigger event will be generated when the.."
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group.long 0x20++0x4B
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line.long 0x00 "SWEVSET,Software Event SetSet software event flags from AUX domain to AON and MCU domains"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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bitfld.long 0x00 2. "SWEV2,Software event flag" "No effect,Set software event flag 2"
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bitfld.long 0x00 1. "SWEV1,Software event flag" "No effect,Set software event flag 1"
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bitfld.long 0x00 0. "SWEV0,Software event flag" "No effect,Set software event flag 0"
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line.long 0x04 "EVTOAONFLAGS,Events To AON FlagsThis register contains a collection of event flags routed to AON_EVENT"
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hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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bitfld.long 0x04 8. "AUX_TIMER1_EV,This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV" "0,1"
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bitfld.long 0x04 7. "AUX_TIMER0_EV,This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV" "0,1"
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bitfld.long 0x04 6. "AUX_TDC_DONE,This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE" "0,1"
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bitfld.long 0x04 5. "AUX_ADC_DONE,This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE" "0,1"
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bitfld.long 0x04 4. "AUX_COMPB,This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB" "0,1"
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bitfld.long 0x04 3. "AUX_COMPA,This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA" "0,1"
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bitfld.long 0x04 2. "SWEV2,This event flag is set when software writes a 1 to SWEVSET.SWEV2" "0,1"
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bitfld.long 0x04 1. "SWEV1,This event flag is set when software writes a 1 to SWEVSET.SWEV1" "0,1"
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bitfld.long 0x04 0. "SWEV0,This event flag is set when software writes a 1 to SWEVSET.SWEV0" "0,1"
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line.long 0x08 "EVTOAONPOL,Events To AON PolarityEvent source polarity configuration for EVTOAONFLAGS"
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hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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bitfld.long 0x08 8. "AUX_TIMER1_EV,Select the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV" "High level,Low level"
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bitfld.long 0x08 7. "AUX_TIMER0_EV,Select the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV" "High level,Low level"
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bitfld.long 0x08 6. "AUX_TDC_DONE,Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE" "High level,Low level"
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bitfld.long 0x08 5. "AUX_ADC_DONE,Select the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE" "High level,Low level"
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bitfld.long 0x08 4. "AUX_COMPB,Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB" "Rising edge,Falling edge"
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bitfld.long 0x08 3. "AUX_COMPA,Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA" "Rising edge,Falling edge"
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rbitfld.long 0x08 0.--2. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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line.long 0x0C "EVTOAONFLAGSCLR,Events To AON ClearClear event flags in EVTOAONFLAGS"
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hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 8. "AUX_TIMER1_EV,Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV.Read value is 0" "0,1"
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bitfld.long 0x0C 7. "AUX_TIMER0_EV,Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV.Read value is 0" "0,1"
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bitfld.long 0x0C 6. "AUX_TDC_DONE,Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 5. "AUX_ADC_DONE,Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE.Read value is 0" "0,1"
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bitfld.long 0x0C 4. "AUX_COMPB,Write 1 to clear EVTOAONFLAGS.AUX_COMPB.Read value is 0" "0,1"
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bitfld.long 0x0C 3. "AUX_COMPA,Write 1 to clear EVTOAONFLAGS.AUX_COMPA.Read value is 0" "0,1"
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bitfld.long 0x0C 2. "SWEV2,Write 1 to clear EVTOAONFLAGS.SWEV2.Read value is 0" "0,1"
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bitfld.long 0x0C 1. "SWEV1,Write 1 to clear EVTOAONFLAGS.SWEV1.Read value is 0" "0,1"
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bitfld.long 0x0C 0. "SWEV0,Write 1 to clear EVTOAONFLAGS.SWEV0.Read value is 0" "0,1"
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line.long 0x10 "EVTOMCUFLAGS,Events to MCU FlagsThis register contains a collection of event flags routed to MCU domain"
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hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x10 15. "AUX_TIMER2_PULSE,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE occurs on EVSTAT3.AUX_TIMER2_PULSE" "0,1"
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bitfld.long 0x10 14. "AUX_TIMER2_EV3,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 occurs on EVSTAT3.AUX_TIMER2_EV3" "0,1"
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bitfld.long 0x10 13. "AUX_TIMER2_EV2,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 occurs on EVSTAT3.AUX_TIMER2_EV2" "0,1"
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bitfld.long 0x10 12. "AUX_TIMER2_EV1,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 occurs on EVSTAT3.AUX_TIMER2_EV1" "0,1"
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bitfld.long 0x10 11. "AUX_TIMER2_EV0,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 occurs on EVSTAT3.AUX_TIMER2_EV0" "0,1"
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bitfld.long 0x10 10. "AUX_ADC_IRQ,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ" "0,1"
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bitfld.long 0x10 9. "MCU_OBSMUX0,This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0" "0,1"
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bitfld.long 0x10 8. "AUX_ADC_FIFO_ALMOST_FULL,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL" "0,1"
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bitfld.long 0x10 7. "AUX_ADC_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE" "0,1"
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bitfld.long 0x10 6. "AUX_SMPH_AUTOTAKE_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE" "0,1"
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|
newline
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bitfld.long 0x10 5. "AUX_TIMER1_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV" "0,1"
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|
newline
|
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bitfld.long 0x10 4. "AUX_TIMER0_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV" "0,1"
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|
newline
|
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bitfld.long 0x10 3. "AUX_TDC_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE" "0,1"
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|
newline
|
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bitfld.long 0x10 2. "AUX_COMPB,This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB" "0,1"
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|
newline
|
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bitfld.long 0x10 1. "AUX_COMPA,This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA" "0,1"
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|
newline
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|
bitfld.long 0x10 0. "AUX_WU_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on reduction-OR of the AUX_SYSIF:WUFLAGS register" "0,1"
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|
line.long 0x14 "EVTOMCUPOL,Event To MCU PolarityEvent source polarity configuration for EVTOMCUFLAGS"
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|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x14 15. "AUX_TIMER2_PULSE,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE" "High level,Low level"
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newline
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bitfld.long 0x14 14. "AUX_TIMER2_EV3,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3" "High level,Low level"
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|
newline
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bitfld.long 0x14 13. "AUX_TIMER2_EV2,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2" "High level,Low level"
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|
newline
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bitfld.long 0x14 12. "AUX_TIMER2_EV1,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1" "High level,Low level"
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newline
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bitfld.long 0x14 11. "AUX_TIMER2_EV0,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0" "High level,Low level"
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newline
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bitfld.long 0x14 10. "AUX_ADC_IRQ,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ" "High level,Low level"
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newline
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bitfld.long 0x14 9. "MCU_OBSMUX0,Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0" "High level,Low level"
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newline
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bitfld.long 0x14 8. "AUX_ADC_FIFO_ALMOST_FULL,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL" "High level,Low level"
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newline
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bitfld.long 0x14 7. "AUX_ADC_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE" "High level,Low level"
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newline
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bitfld.long 0x14 6. "AUX_SMPH_AUTOTAKE_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE" "High level,Low level"
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newline
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bitfld.long 0x14 5. "AUX_TIMER1_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV" "High level,Low level"
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|
newline
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bitfld.long 0x14 4. "AUX_TIMER0_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV" "High level,Low level"
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newline
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bitfld.long 0x14 3. "AUX_TDC_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE" "High level,Low level"
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|
newline
|
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bitfld.long 0x14 2. "AUX_COMPB,Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB" "Rising edge,Falling edge"
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|
newline
|
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bitfld.long 0x14 1. "AUX_COMPA,Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA" "Rising edge,Falling edge"
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|
newline
|
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bitfld.long 0x14 0. "AUX_WU_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV" "High level,Low level"
|
|
line.long 0x18 "EVTOMCUFLAGSCLR,Events To MCU Flags ClearClear event flags in EVTOMCUFLAGS"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x18 15. "AUX_TIMER2_PULSE,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE.Read value is 0" "0,1"
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|
newline
|
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bitfld.long 0x18 14. "AUX_TIMER2_EV3,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3.Read value is 0" "0,1"
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|
newline
|
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bitfld.long 0x18 13. "AUX_TIMER2_EV2,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2.Read value is 0" "0,1"
|
|
newline
|
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bitfld.long 0x18 12. "AUX_TIMER2_EV1,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1.Read value is 0" "0,1"
|
|
newline
|
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bitfld.long 0x18 11. "AUX_TIMER2_EV0,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0.Read value is 0" "0,1"
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|
newline
|
|
bitfld.long 0x18 10. "AUX_ADC_IRQ,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ.Read value is 0" "0,1"
|
|
newline
|
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bitfld.long 0x18 9. "MCU_OBSMUX0,Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0.Read value is 0" "0,1"
|
|
newline
|
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bitfld.long 0x18 8. "AUX_ADC_FIFO_ALMOST_FULL,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.Read value is 0" "0,1"
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|
newline
|
|
bitfld.long 0x18 7. "AUX_ADC_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "AUX_SMPH_AUTOTAKE_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "AUX_TIMER1_EV,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV.Read value is 0" "0,1"
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|
newline
|
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bitfld.long 0x18 4. "AUX_TIMER0_EV,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV.Read value is 0" "0,1"
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|
newline
|
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bitfld.long 0x18 3. "AUX_TDC_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "AUX_COMPB,Write 1 to clear EVTOMCUFLAGS.AUX_COMPB.Read value is 0" "0,1"
|
|
newline
|
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bitfld.long 0x18 1. "AUX_COMPA,Write 1 to clear EVTOMCUFLAGS.AUX_COMPA.Read value is 0" "0,1"
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|
newline
|
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bitfld.long 0x18 0. "AUX_WU_EV,Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV.Read value is 0" "0,1"
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|
line.long 0x1C "COMBEVTOMCUMASK,Combined Event To MCU MaskSelect event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU.The AUX_COMB event is high as long as one or more of the included event flags are set"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x1C 15. "AUX_TIMER2_PULSE,EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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newline
|
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bitfld.long 0x1C 14. "AUX_TIMER2_EV3,EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
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bitfld.long 0x1C 13. "AUX_TIMER2_EV2,EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
|
bitfld.long 0x1C 12. "AUX_TIMER2_EV1,EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
|
bitfld.long 0x1C 11. "AUX_TIMER2_EV0,EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
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bitfld.long 0x1C 10. "AUX_ADC_IRQ,EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 9. "MCU_OBSMUX0,EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
|
bitfld.long 0x1C 8. "AUX_ADC_FIFO_ALMOST_FULL,EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
|
bitfld.long 0x1C 7. "AUX_ADC_DONE,EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 6. "AUX_SMPH_AUTOTAKE_DONE,EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 5. "AUX_TIMER1_EV,EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 4. "AUX_TIMER0_EV,EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
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|
newline
|
|
bitfld.long 0x1C 3. "AUX_TDC_DONE,EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 2. "AUX_COMPB,EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event.0: Exclude1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 1. "AUX_COMPA,EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 0. "AUX_WU_EV,EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
line.long 0x20 "EVOBSCFG,Event Observation Configuration"
|
|
hexmask.long 0x20 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--5. "EVOBS_SEL,Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIOn" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10,EVSTAT0.AUXIO11,EVSTAT0.AUXIO12,EVSTAT0.AUXIO13,EVSTAT0.AUXIO14,EVSTAT0.AUXIO15,EVSTAT1.AUXIO16,EVSTAT1.AUXIO17,EVSTAT1.AUXIO18,EVSTAT1.AUXIO19,EVSTAT1.AUXIO20,EVSTAT1.AUXIO21,EVSTAT1.AUXIO22,EVSTAT1.AUXIO23,EVSTAT1.AUXIO24,EVSTAT1.AUXIO25,EVSTAT1.AUXIO26,EVSTAT1.AUXIO27,EVSTAT1.AUXIO28,EVSTAT1.AUXIO29,EVSTAT1.AUXIO30,EVSTAT1.AUXIO31,EVSTAT2.MANUAL_EV,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
|
|
line.long 0x24 "PROGDLY,Programmable Delay"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "VALUE,VALUE decrements to 0 at a rate of 1 MHz.The event AUX_PROG_DLY_IDLE is high when VALUE is 0 otherwise it is low"
|
|
line.long 0x28 "MANUAL,ManualProgrammable event"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0. "EV,This bit field sets the value of EVSTAT2.MANUAL_EV" "0,1"
|
|
line.long 0x2C "EVSTAT0L,Event Status 0 Low"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "ALIAS_EV,Alias of EVSTAT0 event 7 down to 0"
|
|
line.long 0x30 "EVSTAT0H,Event Status 0 High"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "ALIAS_EV,Alias of EVSTAT0 event 15 down to 8"
|
|
line.long 0x34 "EVSTAT1L,Event Status 1 Low"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "ALIAS_EV,Alias of EVSTAT1 event 7 down to 0"
|
|
line.long 0x38 "EVSTAT1H,Event Status 1 High"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "ALIAS_EV,Alias of EVSTAT1 event 15 down to 8"
|
|
line.long 0x3C "EVSTAT2L,Event Status 2 Low"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "ALIAS_EV,Alias of EVSTAT2 event 7 down to 0"
|
|
line.long 0x40 "EVSTAT2H,Event Status 2 High"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "ALIAS_EV,Alias of EVSTAT2 event 15 down to 8"
|
|
line.long 0x44 "EVSTAT3L,Event Status 3 Low"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "ALIAS_EV,Alias of EVSTAT3 event 7 down to 0"
|
|
line.long 0x48 "EVSTAT3H,Event Status 3 High"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "ALIAS_EV,Alias of EVSTAT3 event 15 down to 8"
|
|
tree.end
|
|
tree "AUX_SMPH"
|
|
base ad:0x400C8000
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SMPH$1,Semaphore 0"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Request or release of semaphore.Request by read:0: Semaphore not available.1: Semaphore granted.Release by write:0: Do not use.1: Release semaphore" "Do not use,Release semaphore"
|
|
repeat.end
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AUTOTAKE,Auto TakeSticky Request for Single Semaphore"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--2. "SMPH_ID,Write the semaphore ID 0x0-0x7 to SMPH_ID to request this semaphore until it is granted" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "AUX_SYSIF"
|
|
base ad:0x400C6000
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "OPMODEREQ,Operational Mode RequestAUX can operate in three operational modes"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "REQ,AUX operational mode request" "Active operational mode characterized by:-..,Lowpower operational mode characterized by:-..,Powerdown operational mode with wakeup to active..,Powerdown operational mode with wakeup to.."
|
|
line.long 0x04 "OPMODEACK,Operational Mode AcknowledgementAUX_SCE program must assume that the current operational mode is the one acknowledged"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "ACK,AUX operational mode acknowledgement" "Active operational mode is acknowledged.,Lowpower operational mode is acknowledged.,Powerdown operational mode with wakeup to active..,Powerdown operational mode with wakeup to.."
|
|
line.long 0x08 "PROGWU0CFG,Programmable Wakeup 0 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
|
|
newline
|
|
bitfld.long 0x08 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
|
|
newline
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bitfld.long 0x08 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x0C "PROGWU1CFG,Programmable Wakeup 1 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x0C 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x0C 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x10 "PROGWU2CFG,Programmable Wakeup 2 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x10 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x10 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x14 "PROGWU3CFG,Programmable Wakeup 3 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x14 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x14 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x18 "SWWUTRIG,Software Wakeup Triggers System CPU uses these wakeup flags to perform handshaking with AUX_SCE"
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hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 3. "SW_WU3,Software wakeup 3 trigger.0: No effect.1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU3 and.."
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newline
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bitfld.long 0x18 2. "SW_WU2,Software wakeup 2 trigger.0: No effect.1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU2 and.."
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newline
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bitfld.long 0x18 1. "SW_WU1,Software wakeup 1 trigger.0: No effect.1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU1 and.."
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newline
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bitfld.long 0x18 0. "SW_WU0,Software wakeup 0 trigger.0: No effect.1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU0 and.."
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line.long 0x1C "WUFLAGS,Wakeup FlagsThis register holds the eight AUX wakeup flags"
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hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 7. "SW_WU3,Software wakeup 3 flag.0: Software wakeup 3 not triggered.1: Software wakeup 3 triggered" "Software wakeup 3 not triggered,Software wakeup 3 triggered"
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newline
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bitfld.long 0x1C 6. "SW_WU2,Software wakeup 2 flag.0: Software wakeup 2 not triggered.1: Software wakeup 2 triggered" "Software wakeup 2 not triggered,Software wakeup 2 triggered"
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newline
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bitfld.long 0x1C 5. "SW_WU1,Software wakeup 1 flag.0: Software wakeup 1 not triggered.1: Software wakeup 1 triggered" "Software wakeup 1 not triggered,Software wakeup 1 triggered"
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newline
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bitfld.long 0x1C 4. "SW_WU0,Software wakeup 0 flag.0: Software wakeup 0 not triggered.1: Software wakeup 0 triggered" "Software wakeup 0 not triggered,Software wakeup 0 triggered"
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newline
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bitfld.long 0x1C 3. "PROG_WU3,Programmable wakeup" "Programmable wakeup 3 not triggered,Programmable wakeup 3 triggered"
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newline
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bitfld.long 0x1C 2. "PROG_WU2,Programmable wakeup" "Programmable wakeup 2 not triggered,Programmable wakeup 2 triggered"
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newline
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bitfld.long 0x1C 1. "PROG_WU1,Programmable wakeup" "Programmable wakeup 1 not triggered,Programmable wakeup 1 triggered"
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newline
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bitfld.long 0x1C 0. "PROG_WU0,Programmable wakeup" "Programmable wakeup 0 not triggered,Programmable wakeup 0 triggered"
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line.long 0x20 "WUFLAGSCLR,Wakeup Flags ClearThis register clears AUX wakeup flags WUFLAGS"
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 7. "SW_WU3,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU3"
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newline
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bitfld.long 0x20 6. "SW_WU2,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU2"
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newline
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bitfld.long 0x20 5. "SW_WU1,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU1"
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newline
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bitfld.long 0x20 4. "SW_WU0,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU0"
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newline
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bitfld.long 0x20 3. "PROG_WU3,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU3"
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newline
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bitfld.long 0x20 2. "PROG_WU2,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU2"
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newline
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bitfld.long 0x20 1. "PROG_WU1,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU1"
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newline
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bitfld.long 0x20 0. "PROG_WU0,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU0"
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line.long 0x24 "WUGATE,Wakeup GateYou must disable the AUX wakeup output:- Before you clear a programmable wakeup flag.- Before you change the value of [PROGWUnCFG.EN] or [PROGWUnCFG.WU_SRC].The AUX wakeup output must be re-enabled after clear operation or programmable.."
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hexmask.long 0x24 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 0. "EN,Wakeup output enable.0: Disable AUX wakeup output.1: Enable AUX wakeup output" "Disable AUX wakeup output,Enable AUX wakeup output"
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repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
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group.long ($2+0x28)++0x03
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line.long 0x00 "VECCFG$1,Vector Configuration 0AUX_SCE wakeup vector 0 configuration"
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hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--3. "VEC_EV,Select trigger event for vector 0.Non-enumerated values are treated as NONE" "Vector is disabled.,WUFLAGS.PROG_WU0,WUFLAGS.PROG_WU1,WUFLAGS.PROG_WU2,WUFLAGS.PROG_WU3,WUFLAGS.SW_WU0 ,WUFLAGS.SW_WU1 ,WUFLAGS.SW_WU2 ,WUFLAGS.SW_WU3 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY,?,?,?,?,?,?"
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repeat.end
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group.long 0x48++0x23
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line.long 0x00 "EVSYNCRATE,Event Synchronization Rate Configure synchronization rate for certain events to the synchronous AUX event bus.You must select SCE rate when AUX_SCE uses the event"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 2. "AUX_COMPA_SYNC_RATE,Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x00 1. "AUX_COMPB_SYNC_RATE,Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x00 0. "AUX_TIMER2_SYNC_RATE,Select synchronization rate for:- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3- AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE" "SCE rate,AUX bus rate"
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line.long 0x04 "PEROPRATE,Peripheral Operational Rate Some AUX peripherals are operated at either SCE or at AUX bus rate"
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hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 3. "ANAIF_DAC_OP_RATE,Select operational rate for AUX_ANAIF DAC sample clock state machine" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 2. "TIMER01_OP_RATE,Select operational rate for AUX_TIMER01" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 1. "SPIM_OP_RATE,Select operational rate for AUX_SPIM" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 0. "MAC_OP_RATE,Select operational rate for AUX_MAC" "SCE rate,AUX bus rate"
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line.long 0x08 "ADCCLKCTL,ADC Clock Control"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 1. "ACK,Clock acknowledgement.0: ADC clock is disabled.1: ADC clock is enabled" "ADC clock is disabled,ADC clock is enabled"
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newline
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bitfld.long 0x08 0. "REQ,ADC clock request.0: Disable ADC clock.1: Enable ADC clock.Only modify REQ when equal to ACK." "Disable ADC clock,Enable ADC clock.Only modify REQ when equal to ACK"
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line.long 0x0C "TDCCLKCTL,TDC Counter Clock ControlControls if the AUX_TDC counter clock source is enabled"
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hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 1. "ACK,TDC counter clock acknowledgement.0: TDC counter clock is disabled.1: TDC counter clock is enabled" "TDC counter clock is disabled,TDC counter clock is enabled"
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newline
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bitfld.long 0x0C 0. "REQ,TDC counter clock request.0: Disable TDC counter clock.1: Enable TDC counter clock.Only modify REQ when equal to ACK." "Disable TDC counter clock,Enable TDC counter clock.Only modify REQ when.."
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line.long 0x10 "TDCREFCLKCTL,TDC Reference Clock ControlControls if the AUX_TDC reference clock source is enabled"
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hexmask.long 0x10 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 1. "ACK,TDC reference clock acknowledgement.0: TDC reference clock is disabled.1: TDC reference clock is enabled" "TDC reference clock is disabled,TDC reference clock is enabled"
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newline
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bitfld.long 0x10 0. "REQ,TDC reference clock request.0: Disable TDC reference clock.1: Enable TDC reference clock.Only modify REQ when equal to ACK." "Disable TDC reference clock,Enable TDC reference clock.Only modify REQ when.."
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line.long 0x14 "TIMER2CLKCTL,AUX_TIMER2 Clock ControlAccess to AUX_TIMER2 is only possible when TIMER2CLKSTAT.STAT is different from NONE"
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hexmask.long 0x14 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 0.--2. "SRC,Select clock source for AUX_TIMER2.Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or TIMER2CLKSWITCH.RDY is 1.It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0" "no clock,SCLK_LF,SCLK_MF,?,SCLK_HF / 2,?,?,?"
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line.long 0x18 "TIMER2CLKSTAT,AUX_TIMER2 Clock Status"
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hexmask.long 0x18 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 0.--2. "STAT,AUX_TIMER2 clock source status" "No clock ,SCLK_LF,SCLK_MF,?,SCLK_HF / 2,?,?,?"
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line.long 0x1C "TIMER2CLKSWITCH,AUX_TIMER2 Clock Switch"
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hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 0. "RDY,Status of clock switcher.0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT.1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT.RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY" "TIMER2CLKCTL.SRC is different from..,TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT.RDY.."
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line.long 0x20 "TIMER2DBGCTL,AUX_TIMER2 Debug Control"
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hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 0. "DBG_FREEZE_EN,Debug freeze enable.0: AUX_TIMER2 does not halt when the system CPU halts in debug mode.1: Halt AUX_TIMER2 when the system CPU halts in debug mode" "AUX_TIMER2 does not halt when the system CPU..,Halt AUX_TIMER2 when the system CPU halts in.."
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group.long 0x70++0x27
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line.long 0x00 "CLKSHIFTDET,Clock Shift DetectionA transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF:- A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when.."
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "STAT,Clock shift detection.Write:0: Restart clock shift detection.1: Do not use.Read:0: MCU domain did not enter or exit active state since you wrote 0 to STAT" "MCU domain did not enter or exit active state..,MCU domain entered or exited active state since.."
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line.long 0x04 "RECHARGETRIG,VDDR Recharge Trigger"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "TRIG,Recharge trigger.0: No effect.1: Request VDDR recharge" "No effect,Request VDDR recharge"
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line.long 0x08 "RECHARGEDET,VDDR Recharge DetectionSome applications can be sensitive to power noise caused by recharge of VDDR"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 1. "STAT,VDDR recharge detector status.0: No recharge of VDDR has occurred since EN was set.1: Recharge of VDDR has occurred since EN was set" "No recharge of VDDR has occurred since EN was set,Recharge of VDDR has occurred since EN was set"
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newline
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bitfld.long 0x08 0. "EN,VDDR recharge detector enable.0: Disable recharge detection" "Disable recharge detection,Enable recharge detection"
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line.long 0x0C "RTCSUBSECINC0,Real Time Counter Sub Second Increment 0INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.AUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "INC15_0,New value for bits 15:0 in AON_RTC:SUBSECINC"
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line.long 0x10 "RTCSUBSECINC1,Real Time Counter Sub Second Increment 1INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.AUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "INC23_16,New value for bits 23:16 in AON_RTC:SUBSECINC"
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line.long 0x14 "RTCSUBSECINCCTL,Real Time Counter Sub Second Increment ControlAUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long 0x14 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 1. "UPD_ACK,Update acknowledgement.0: AON_RTC has not acknowledged UPD_REQ" "AON_RTC has not acknowledged UPD_REQ,AON_RTC has acknowledged UPD_REQ"
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newline
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bitfld.long 0x14 0. "UPD_REQ,Request AON_RTC to update AON_RTC:SUBSECINC.0: Clear request to update.1: Set request to update.Only change UPD_REQ when it equals UPD_ACK" "Clear request to update,Set request to update.Only change UPD_REQ when.."
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line.long 0x18 "RTCSEC,Real Time Counter Second System CPU must not access this register"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "SEC,Bits 15:0 in AON_RTC:SEC.VALUE"
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line.long 0x1C "RTCSUBSEC,Real Time Counter Sub-Second System CPU must not access this register"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "SUBSEC,Bits 31:16 in AON_RTC:SUBSEC.VALUE"
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line.long 0x20 "RTCEVCLR,AON_RTC Event ClearRequest to clear events:- AON_RTC:EVFLAGS.CH2.- AON_RTC:EVFLAGS.CH2 delayed version.- AUX_EVCTL:EVSTAT2.AON_RTC_CH2.- AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY"
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hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 0. "RTC_CH2_EV_CLR,Clear events from AON_RTC channel 2.0: No effect" "No effect,Clear events from AON_RTC.."
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line.long 0x24 "BATMONBAT,AON_BATMON Battery Voltage ValueRead access to AON_BATMON:BAT"
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hexmask.long.tbyte 0x24 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 8.--10. "INT,See AON_BATMON:BAT.INT" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x24 0.--7. 1. "FRAC,See AON_BATMON:BAT.FRAC"
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rgroup.long 0x9C++0x07
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line.long 0x00 "BATMONTEMP,AON_BATMON Temperature ValueRead access to AON_BATMON:TEMP"
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hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 11.--15. "SIGN,Sign extension of INT.Follow this procedure to get the correct value:- Do two dummy reads of SIGN.- Then read SIGN until two consecutive reads are equal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.word 0x00 2.--10. 1. "INT,See AON_BATMON:TEMP.INT"
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newline
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bitfld.long 0x00 0.--1. "FRAC,See AON_BATMON:TEMP.FRAC" "0,1,2,3"
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line.long 0x04 "TIMERHALT,Timer HaltDebug register"
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hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 3. "PROGDLY,Halt programmable delay.0: AUX_EVCTL:PROGDLY.VALUE decrements as normal.1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation" "AUX_EVCTL,Halt AUX_EVCTL"
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newline
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bitfld.long 0x04 2. "AUX_TIMER2,Halt AUX_TIMER2.0: AUX_TIMER2 operates as normal.1: Halt AUX_TIMER2 operation" "AUX_TIMER2 operates as normal,Halt AUX_TIMER2 operation"
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newline
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bitfld.long 0x04 1. "AUX_TIMER1,Halt AUX_TIMER01 Timer" "AUX_TIMER01 Timer 1 operates as normal,Halt AUX_TIMER01 Timer 1 operation"
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newline
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bitfld.long 0x04 0. "AUX_TIMER0,Halt AUX_TIMER01 Timer" "AUX_TIMER01 Timer 0 operates as normal,Halt AUX_TIMER01 Timer 0 operation"
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rgroup.long 0xB0++0x07
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line.long 0x00 "TIMER2BRIDGE,AUX_TIMER2 Bridge"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "BUSY,Status of bus transactions to AUX_TIMER2.0: No unfinished bus transactions.1: A bus transaction is ongoing" "No unfinished bus transactions,A bus transaction is ongoing"
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line.long 0x04 "SWPWRPROF,Software Power Profiler"
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hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0.--2. "STAT,Software status bits that can be read by the power profiler" "0,1,2,3,4,5,6,7"
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tree.end
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tree "AUX_TDC"
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base ad:0x400C4000
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group.long 0x00++0x27
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line.long 0x00 "CTL,Control"
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hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--1. "CMD,TDC commands" "Clear STAT.SAT STAT.DONE and RESULT.VALUE..,Synchronous counter start.The counter looks..,Asynchronous counter start.The counter starts..,Force TDC state machine back to IDLE.."
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line.long 0x04 "STAT,Status"
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 7. "SAT,TDC measurement saturation flag.0: Conversion has not saturated.1: Conversion stopped due to saturation.This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD" "Conversion has not saturated,Conversion stopped due to saturation.This field.."
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newline
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bitfld.long 0x04 6. "DONE,TDC measurement complete flag.0: TDC measurement has not yet completed.1: TDC measurement has completed.This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD" "TDC measurement has not yet completed,TDC measurement has completed.This field clears.."
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newline
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bitfld.long 0x04 0.--5. "STATE,TDC state machine status" "Current state is TDC_STATE_WAIT_START. The..,?,?,?,Current state is..,?,Current state is TDC_STATE_IDLE. This is the..,Current state is TDC_STATE_CLRCNT. The..,Current state is TDC_STATE_WAIT_STOP.The state..,?,?,?,Current state is TDC_STATE_WAIT_STOPCNTDOWN.The..,?,Current state is TDC_STATE_GETRESULTS.The state..,Current state is TDC_STATE_POR. This is the..,?,?,?,?,?,?,Current state is TDC_STATE_WAIT_CLRCNT_DONE..,?,?,?,?,?,?,?,Current state is TDC_WAIT_STARTFALL. The..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Current state is TDC_FORCESTOP.You wrote ABORT..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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line.long 0x08 "RESULT,ResultResult of last TDC conversion"
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hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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newline
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hexmask.long 0x08 0.--24. 1. "VALUE,TDC conversion result.The result of the TDC conversion is given in number of clock edges of the clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL"
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line.long 0x0C "SATCFG,Saturation Configuration"
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hexmask.long 0x0C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 0.--3. "LIMIT,Saturation limit.The flag STAT.SAT is set when the TDC counter saturates.Values not enumerated are not supported" "?,?,?,Result bit 12: TDC conversion saturates and..,Result bit 13: TDC conversion saturates and..,Result bit 14: TDC conversion saturates and..,Result bit 15: TDC conversion saturates and..,Result bit 16: TDC conversion saturates and..,Result bit 17: TDC conversion saturates and..,Result bit 18: TDC conversion saturates and..,Result bit 19: TDC conversion saturates and..,Result bit 20: TDC conversion saturates and..,Result bit 21: TDC conversion saturates and..,Result bit 22: TDC conversion saturates and..,Result bit 23: TDC conversion saturates and..,Result bit 24: TDC conversion saturates and.."
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line.long 0x10 "TRIGSRC,Trigger SourceSelect source and polarity for TDC start and stop events"
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 14. "STOP_POL,Polarity of stop source.Change only while STAT.STATE is IDLE" "TDC conversion stops when high level is detected.,TDC conversion stops when low level is detected."
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newline
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bitfld.long 0x10 8.--13. "STOP_SRC,Select stop source from the asynchronous AUX event bus.Change only while STAT.STATE is IDLE" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,Select TDC Prescaler event which is generated by..,No event."
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newline
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rbitfld.long 0x10 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x10 6. "START_POL,Polarity of start source.Change only while STAT.STATE is IDLE" "TDC conversion starts when high level is detected.,TDC conversion starts when low level is detected."
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newline
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bitfld.long 0x10 0.--5. "START_SRC,Select start source from the asynchronous AUX event bus.Change only while STAT.STATE is IDLE" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,Select TDC Prescaler event which is generated by..,No event."
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line.long 0x14 "TRIGCNT,Trigger CounterStop-counter control and status"
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hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x14 0.--15. 1. "CNT,Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.Read CNT to get the remaining number of stop events to ignore during a TDC measurement"
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line.long 0x18 "TRIGCNTLOAD,Trigger Counter LoadStop-counter load"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "CNT,Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.To measure frequency of an event source: - Set start event equal to stop event.- Set CNT to number of periods to measure"
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line.long 0x1C "TRIGCNTCFG,Trigger Counter ConfigurationStop-counter configuration"
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hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 0. "EN,Enable stop-counter.0: Disable stop-counter.1: Enable stop-counter.Change only while STAT.STATE is IDLE" "Disable stop-counter,Enable stop-counter.Change only while STAT.STATE.."
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line.long 0x20 "PRECTL,Prescaler ControlThe prescaler can be used to count events that are faster than the AUX bus rate"
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 7. "RESET_N,Prescaler reset.0: Reset prescaler.1: Release reset of prescaler.AUX_TDC_PRE event becomes 0 when you reset the prescaler" "Reset prescaler,Release reset of prescaler.AUX_TDC_PRE.."
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newline
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bitfld.long 0x20 6. "RATIO,Prescaler ratio" "Prescaler divides input by 16. AUX_TDC_PRE..,Prescaler divides input by 64. AUX_TDC_PRE.."
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newline
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bitfld.long 0x20 0.--5. "SRC,Prescaler event source" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x24 "PRECNTR,Prescaler Counter"
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x24 0.--15. 1. "CNT,Prescaler counter value.Write a value to CNT to capture the value of the 16-bit prescaler counter into CNT"
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tree.end
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tree "AUX_TIMER01"
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base ad:0x400C7000
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group.long 0x00++0x1F
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line.long 0x00 "T0CFG,Timer 0 Configuration"
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hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 14. "TICK_SRC_POL,Tick source polarity for Timer 0" "Count on rising edges of TICK_SRC.,Count on falling edges of TICK_SRC."
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newline
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bitfld.long 0x00 8.--13. "TICK_SRC,Select Timer 0 tick source from the synchronous event bus" "AUX_EVCTL:EVSTAT0.AUXIO0..,AUX_EVCTL:EVSTAT0.AUXIO1..,AUX_EVCTL:EVSTAT0.AUXIO2..,AUX_EVCTL:EVSTAT0.AUXIO3..,AUX_EVCTL:EVSTAT0.AUXIO4..,AUX_EVCTL:EVSTAT0.AUXIO5..,AUX_EVCTL:EVSTAT0.AUXIO6..,AUX_EVCTL:EVSTAT0.AUXIO7..,AUX_EVCTL:EVSTAT0.AUXIO8..,AUX_EVCTL:EVSTAT0.AUXIO9..,AUX_EVCTL:EVSTAT0.AUXIO10..,AUX_EVCTL:EVSTAT0.AUXIO11..,AUX_EVCTL:EVSTAT0.AUXIO12..,AUX_EVCTL:EVSTAT0.AUXIO13..,AUX_EVCTL:EVSTAT0.AUXIO14..,AUX_EVCTL:EVSTAT0.AUXIO15..,AUX_EVCTL:EVSTAT1.AUXIO16..,AUX_EVCTL:EVSTAT1.AUXIO17..,AUX_EVCTL:EVSTAT1.AUXIO18..,AUX_EVCTL:EVSTAT1.AUXIO19..,AUX_EVCTL:EVSTAT1.AUXIO20..,AUX_EVCTL:EVSTAT1.AUXIO21..,AUX_EVCTL:EVSTAT1.AUXIO22..,AUX_EVCTL:EVSTAT1.AUXIO23..,AUX_EVCTL:EVSTAT1.AUXIO24..,AUX_EVCTL:EVSTAT1.AUXIO25..,AUX_EVCTL:EVSTAT1.AUXIO26..,AUX_EVCTL:EVSTAT1.AUXIO27..,AUX_EVCTL:EVSTAT1.AUXIO28..,AUX_EVCTL:EVSTAT1.AUXIO29..,AUX_EVCTL:EVSTAT1.AUXIO30..,AUX_EVCTL:EVSTAT1.AUXIO31..,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2..,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY..,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ..,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD..,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD..,AUX_EVCTL:EVSTAT2.SCLK_LF..,AUX_EVCTL:EVSTAT2.PWR_DWN..,AUX_EVCTL:EVSTAT2.MCU_ACTIVE..,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE..,AUX_EVCTL:EVSTAT2.ACLK_REF..,AUX_EVCTL:EVSTAT2.MCU_EV..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1..,AUX_EVCTL:EVSTAT2.AUX_COMPA..,AUX_EVCTL:EVSTAT2.AUX_COMPB..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE..,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV..,No event.,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N..,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE..,AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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newline
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bitfld.long 0x00 4.--7. "PRE,Prescaler division ratio is" "Divide by 1,Divide by 2,Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 32 768"
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newline
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rbitfld.long 0x00 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 1. "MODE,Timer 0 mode.Configure source for Timer 0 prescaler" "Use clock as source for prescaler. Note that..,Use event set by TICK_SRC as source for.."
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newline
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bitfld.long 0x00 0. "RELOAD,Timer 0 reload mode" "Manual mode.Timer 0 stops and T0CTL.EN becomes..,Continuous mode.Timer 0 restarts when the.."
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line.long 0x04 "T0CTL,Timer 0 Control"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "EN,Timer 0 enable.0: Disable Timer" "Disable Timer 0,Enable Timer 0.The counter restarts from 0.."
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line.long 0x08 "T0TARGET,Timer 0 Target"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x08 0.--15. 1. "VALUE,Timer 0 target value.Manual Reload Mode:- Timer 0 increments until the counter value becomes equal to or greater than VALUE"
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line.long 0x0C "T0CNTR,Timer 0 Counter"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.word 0x0C 0.--15. 1. "VALUE,Timer 0 counter value"
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line.long 0x10 "T1CFG,Timer 1 Configuration"
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 14. "TICK_SRC_POL,Tick source polarity for Timer 1" "Count on rising edges of TICK_SRC.,Count on falling edges of TICK_SRC."
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newline
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bitfld.long 0x10 8.--13. "TICK_SRC,Select Timer 1 tick source from the synchronous event bus" "AUX_EVCTL:EVSTAT0.AUXIO0..,AUX_EVCTL:EVSTAT0.AUXIO1..,AUX_EVCTL:EVSTAT0.AUXIO2..,AUX_EVCTL:EVSTAT0.AUXIO3..,AUX_EVCTL:EVSTAT0.AUXIO4..,AUX_EVCTL:EVSTAT0.AUXIO5..,AUX_EVCTL:EVSTAT0.AUXIO6..,AUX_EVCTL:EVSTAT0.AUXIO7..,AUX_EVCTL:EVSTAT0.AUXIO8..,AUX_EVCTL:EVSTAT0.AUXIO9..,AUX_EVCTL:EVSTAT0.AUXIO10..,AUX_EVCTL:EVSTAT0.AUXIO11..,AUX_EVCTL:EVSTAT0.AUXIO12..,AUX_EVCTL:EVSTAT0.AUXIO13..,AUX_EVCTL:EVSTAT0.AUXIO14..,AUX_EVCTL:EVSTAT0.AUXIO15..,AUX_EVCTL:EVSTAT1.AUXIO16..,AUX_EVCTL:EVSTAT1.AUXIO17..,AUX_EVCTL:EVSTAT1.AUXIO18..,AUX_EVCTL:EVSTAT1.AUXIO19..,AUX_EVCTL:EVSTAT1.AUXIO20..,AUX_EVCTL:EVSTAT1.AUXIO21..,AUX_EVCTL:EVSTAT1.AUXIO22..,AUX_EVCTL:EVSTAT1.AUXIO23..,AUX_EVCTL:EVSTAT1.AUXIO24..,AUX_EVCTL:EVSTAT1.AUXIO25..,AUX_EVCTL:EVSTAT1.AUXIO26..,AUX_EVCTL:EVSTAT1.AUXIO27..,AUX_EVCTL:EVSTAT1.AUXIO28..,AUX_EVCTL:EVSTAT1.AUXIO29..,AUX_EVCTL:EVSTAT1.AUXIO30..,AUX_EVCTL:EVSTAT1.AUXIO31..,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2..,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY..,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ..,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD..,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD..,AUX_EVCTL:EVSTAT2.SCLK_LF..,AUX_EVCTL:EVSTAT2.PWR_DWN..,AUX_EVCTL:EVSTAT2.MCU_ACTIVE..,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE..,AUX_EVCTL:EVSTAT2.ACLK_REF..,AUX_EVCTL:EVSTAT2.MCU_EV..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1..,AUX_EVCTL:EVSTAT2.AUX_COMPA..,AUX_EVCTL:EVSTAT2.AUX_COMPB..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE..,No event.,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV..,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N..,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE..,AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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newline
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bitfld.long 0x10 4.--7. "PRE,Prescaler division ratio is" "Divide by 1,Divide by 2,Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 32 768"
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newline
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rbitfld.long 0x10 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x10 1. "MODE,Timer 1 mode.Configure source for Timer 1 prescaler" "Use clock as source for prescaler. Note that..,Use event set by TICK_SRC as source for.."
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newline
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bitfld.long 0x10 0. "RELOAD,Timer 1 reload mode" "Manual mode.Timer 1 stops and T1CTL.EN becomes..,Continuous mode.Timer 1 restarts when the.."
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line.long 0x14 "T1CTL,Timer 1 Control"
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hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 0. "EN,Timer 1 enable.0: Disable Timer" "Disable Timer 1,Enable Timer 1.The counter restarts from 0.."
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line.long 0x18 "T1TARGET,Timer 1 TargetTimer 1 counter target value"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "VALUE,Timer 1 target value.Manual Reload Mode:- Timer 1 increments until the counter value becomes equal to or greater than VALUE"
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line.long 0x1C "T1CNTR,Timer 1 Counter"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "VALUE,Timer 1 counter value"
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tree.end
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tree.end
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tree "CCFG"
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base ad:0x50003000
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rgroup.long 0x00++0x47
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line.long 0x00 "SIZE_AND_DIS_FLAGS,CCFG Size and Disable Flags"
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hexmask.long.word 0x00 16.--31. 1. "SIZE_OF_CCFG,Total size of CCFG in bytes"
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newline
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hexmask.long.word 0x00 4.--15. 1. "DISABLE_FLAGS,Reserved for future use"
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newline
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bitfld.long 0x00 3. "DIS_TCXO,Deprecated" "0,1"
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newline
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bitfld.long 0x00 2. "DIS_GPRAM,Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).0: GPRAM is enabled and hence CACHE disabled.1: GPRAM is disabled and instead CACHE is enabled (default).Notes:- Disabling CACHE will reduce CPU execution speed (up to 60%).- GPRAM is 8.." "GPRAM is enabled and hence CACHE disabled,GPRAM is disabled and instead CACHE is enabled.."
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newline
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bitfld.long 0x00 1. "DIS_ALT_DCDC_SETTING,Disable alternate DC/DC settings" "Enable alternate DC/DC settings,Disable alternate DC/DC settings.See"
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newline
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bitfld.long 0x00 0. "DIS_XOSC_OVR,Disable XOSC override functionality.0: Enable XOSC override functionality.1: Disable XOSC override functionality.See:MODE_CONF_1.DELTA_IBIAS_INITMODE_CONF_1.DELTA_IBIAS_OFFSETMODE_CONF_1.XOSC_MAX_START" "Enable XOSC override functionality,Disable XOSC override functionality.See"
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line.long 0x04 "MODE_CONF,Mode Configuration 0"
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bitfld.long 0x04 28.--31. "VDDR_TRIM_SLEEP_DELTA,Signed delta value to apply to theVDDR_TRIM_SLEEP target minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 27. "DCDC_RECHARGE,DC/DC during recharge in powerdown.0: Use the DC/DC during recharge in powerdown.1: Do not use the DC/DC during recharge in powerdown (default).NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly.." "Use the DC/DC during recharge in powerdown,Do not use the DC/DC during recharge in.."
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newline
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bitfld.long 0x04 26. "DCDC_ACTIVE,DC/DC in active mode.0: Use the DC/DC during active mode.1: Do not use the DC/DC during active mode (default).NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled.." "Use the DC/DC during active mode,Do not use the DC/DC during active mode.."
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newline
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bitfld.long 0x04 25. "VDDR_EXT_LOAD,Reserved for future use" "0,1"
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newline
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bitfld.long 0x04 24. "VDDS_BOD_LEVEL,VDDS BOD level.0: VDDS BOD level is 2.0V (necessary for external load mode or for maximum PA output power on CC13xx).1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default)." "VDDS BOD level is 2.0V (necessary for external..,VDDS BOD level is 1.8V (or 1.65V for external.."
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newline
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bitfld.long 0x04 22.--23. "SCLK_LF_OPTION,Select source for SCLK_LF" "31.25kHz clock derived from 48MHz XOSC or HPOSC..,External low frequency clock on DIO defined by..,32.768kHz low frequency XOSC,Low frequency RCOSC (default)"
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newline
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bitfld.long 0x04 21. "VDDR_TRIM_SLEEP_TC," "0,1"
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newline
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bitfld.long 0x04 20. "RTC_COMP,Reserved for future use" "0,1"
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newline
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bitfld.long 0x04 18.--19. "XOSC_FREQ,Selects which high frequency oscillator is used (required for radio usage)" "External 48Mhz TCXO.Refer to..,Internal high precision oscillator.,48 MHz XOSC_HF,24 MHz XOSC_HF. Not supported."
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newline
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bitfld.long 0x04 17. "XOSC_CAP_MOD,Enable modification (delta) to XOSC cap-array" "Apply cap-array delta,Do not apply cap-array delta (default)"
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newline
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bitfld.long 0x04 16. "HF_COMP,Reserved for future use" "0,1"
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newline
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hexmask.long.byte 0x04 8.--15. 1. "XOSC_CAPARRAY_DELTA,Signed 8-bit value directly modifying trimmed XOSC cap-array step value"
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newline
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hexmask.long.byte 0x04 0.--7. 1. "VDDR_CAP,Unsigned 8-bit integer representing the minimum decoupling capacitance (worst case) on VDDR in units of 100nF"
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line.long 0x08 "MODE_CONF_1,Mode Configuration 1"
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bitfld.long 0x08 31. "TCXO_TYPE,Selects the TCXO type.0: CMOS type" "CMOS type,Clipped-sine type"
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newline
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hexmask.long.byte 0x08 24.--30. 1. "TCXO_MAX_START,Maximum TCXO startup time in units of 100us.Bit field value is only valid if MODE_CONF.XOSC_FREQ=0"
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newline
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bitfld.long 0x08 20.--23. "ALT_DCDC_VMIN,Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).Voltage = (28 + ALT_DCDC_VMIN) /" "1.75V,1.8125V,?,?,?,?,?,?,?,?,?,?,?,?,2.625V,2.6875VNOTE! The.."
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newline
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bitfld.long 0x08 19. "ALT_DCDC_DITHER_EN,Enable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).0: Dither disable1: Dither enable" "Dither disable,Dither enable"
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newline
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bitfld.long 0x08 16.--18. "ALT_DCDC_IPEAK,Inductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x08 12.--15. "DELTA_IBIAS_INIT,Signed delta value for IBIAS_INIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x08 8.--11. "DELTA_IBIAS_OFFSET,Signed delta value for IBIAS_OFFSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x08 0.--7. 1. "XOSC_MAX_START,Unsigned value of maximum XOSC startup time (worst case) in units of 100us"
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line.long 0x0C "VOLT_LOAD_0,Voltage Load 0Enabled by MODE_CONF.VDDR_EXT_LOAD"
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hexmask.long.byte 0x0C 24.--31. 1. "VDDR_EXT_TP45,Reserved for future use"
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newline
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hexmask.long.byte 0x0C 16.--23. 1. "VDDR_EXT_TP25,Reserved for future use"
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newline
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hexmask.long.byte 0x0C 8.--15. 1. "VDDR_EXT_TP5,Reserved for future use"
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newline
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hexmask.long.byte 0x0C 0.--7. 1. "VDDR_EXT_TM15,Reserved for future use"
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line.long 0x10 "VOLT_LOAD_1,Voltage Load 1Enabled by MODE_CONF.VDDR_EXT_LOAD"
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hexmask.long.byte 0x10 24.--31. 1. "VDDR_EXT_TP125,Reserved for future use"
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newline
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hexmask.long.byte 0x10 16.--23. 1. "VDDR_EXT_TP105,Reserved for future use"
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newline
|
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hexmask.long.byte 0x10 8.--15. 1. "VDDR_EXT_TP85,Reserved for future use"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "VDDR_EXT_TP65,Reserved for future use"
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line.long 0x14 "EXT_LF_CLK,Extern LF clock configuration"
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hexmask.long.byte 0x14 24.--31. 1. "DIO,Unsigned integer selecting the DIO to supply external 32kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL"
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newline
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hexmask.long.tbyte 0x14 0.--23. 1. "RTC_INCREMENT,Unsigned integer defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC"
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line.long 0x18 "IEEE_MAC_0,IEEE MAC Address 0"
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line.long 0x1C "IEEE_MAC_1,IEEE MAC Address 1"
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line.long 0x20 "IEEE_BLE_0,IEEE BLE Address 0"
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line.long 0x24 "IEEE_BLE_1,IEEE BLE Address 1"
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line.long 0x28 "BL_CONFIG,Bootloader ConfigurationConfigures the functionality of the ROM boot loader.If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the.."
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hexmask.long.byte 0x28 24.--31. 1. "BOOTLOADER_ENABLE,Bootloader enable"
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newline
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hexmask.long.byte 0x28 17.--23. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x28 16. "BL_LEVEL,Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field.0: Active low.1: Active high" "Active low,Active high"
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newline
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hexmask.long.byte 0x28 8.--15. 1. "BL_PIN_NUMBER,DIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field"
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newline
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hexmask.long.byte 0x28 0.--7. 1. "BL_ENABLE,Enables the boot loader"
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|
line.long 0x2C "ERASE_CONF,Erase Configuration"
|
|
hexmask.long.tbyte 0x2C 9.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x2C 8. "CHIP_ERASE_DIS_N,Chip erase.This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD.A successful chip erase operation will force the content of the flash main bank back to.." "Disable,Enable"
|
|
newline
|
|
hexmask.long.byte 0x2C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x2C 0. "BANK_ERASE_DIS_N,Bank erase.This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE).A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration.." "Disable the boot loader bank erase function,Enable the boot loader bank erase function"
|
|
line.long 0x30 "ERASE_CONF_1,Erase Configuration 1"
|
|
hexmask.long 0x30 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x30 0. "WEPROT_CCFG_N,WriteErase protect the CCFG sectorSetting this bit = 0 will set FLASH:WEPROT_AUX_BY1.WEPROT_B0_CCFG_BY1 = 1 during boot and hence WriteErase protect the CCFG" "0,1"
|
|
line.long 0x34 "CCFG_TI_OPTIONS,TI Options"
|
|
hexmask.long.word 0x34 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--15. 1. "IDAU_CFG_ENABLE,IDAU"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "TI_FA_ENABLE,TI Failure"
|
|
line.long 0x38 "CCFG_TAP_DAP_0,Test Access Points Enable 0"
|
|
hexmask.long.byte 0x38 24.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 16.--23. 1. "CPU_DAP_ENABLE,Enable CPU"
|
|
newline
|
|
hexmask.long.byte 0x38 8.--15. 1. "PWRPROF_TAP_ENABLE,Enable PWRPROF TAP.0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PWRPROF TAP access will remain disabled out of.."
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "TEST_TAP_ENABLE,Enable Test TAP.0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: TEST TAP access will remain disabled out of.."
|
|
line.long 0x3C "CCFG_TAP_DAP_1,Test Access Points Enable 1"
|
|
hexmask.long.byte 0x3C 24.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PBIST2_TAP_ENABLE,Enable PBIST2 TAP.0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PBIST2 TAP access will remain disabled out of.."
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--15. 1. "PBIST1_TAP_ENABLE,Enable PBIST1 TAP.0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PBIST1 TAP access will remain disabled out of.."
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "AON_TAP_ENABLE,Enable AON TAP0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: AON TAP access will remain disabled out of.."
|
|
line.long 0x40 "IMAGE_VALID_CONF,Image Valid"
|
|
line.long 0x44 "CCFG_WEPROT_31_0_BY2K,Protect Sectors 0-31Each bit write protects one 2KB flash sector from being both programmed and erased"
|
|
bitfld.long 0x44 31. "WEPROT_SEC_31_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 30. "WEPROT_SEC_30_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 29. "WEPROT_SEC_29_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 28. "WEPROT_SEC_28_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 27. "WEPROT_SEC_27_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 26. "WEPROT_SEC_26_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 25. "WEPROT_SEC_25_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 24. "WEPROT_SEC_24_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 23. "WEPROT_SEC_23_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 22. "WEPROT_SEC_22_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 21. "WEPROT_SEC_21_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 20. "WEPROT_SEC_20_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 19. "WEPROT_SEC_19_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 18. "WEPROT_SEC_18_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 17. "WEPROT_SEC_17_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 16. "WEPROT_SEC_16_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 15. "WEPROT_SEC_15_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 14. "WEPROT_SEC_14_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 13. "WEPROT_SEC_13_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 12. "WEPROT_SEC_12_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 11. "WEPROT_SEC_11_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 10. "WEPROT_SEC_10_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 9. "WEPROT_SEC_9_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 8. "WEPROT_SEC_8_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 7. "WEPROT_SEC_7_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "WEPROT_SEC_6_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 5. "WEPROT_SEC_5_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 4. "WEPROT_SEC_4_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 3. "WEPROT_SEC_3_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 2. "WEPROT_SEC_2_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 1. "WEPROT_SEC_1_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 0. "WEPROT_SEC_0_N," "0,1"
|
|
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x48)++0x03
|
|
line.long 0x00 "CCFG_WEPROT_SPARE_$1,Spare register for WriteErase configuration"
|
|
repeat.end
|
|
rgroup.long 0x54++0x0B
|
|
line.long 0x00 "TRUSTZONE_FLASH_CFG,Trustzone configuration register for flash"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--16. 1. "NSADDR_BOUNDARY,Value will be written to PRCM:NVMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "NSCADDR_BOUNDARY,Value will be written to PRCM:NVMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
line.long 0x04 "TRUSTZONE_SRAM_CFG,Trustzone configuration register for MCU SRAM"
|
|
hexmask.long.word 0x04 18.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 9.--17. 1. "NSADDR_BOUNDARY,Value will be written to PRCM:SRAMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
newline
|
|
hexmask.long.word 0x04 0.--8. 1. "NSCADDR_BOUNDARY,Value will be written to PRCM:SRAMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
line.long 0x08 "SRAM_CFG,Configuration register for MCU SRAM"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "MEM_SEL,Value will be written to SRAM_MMR:MEM_CTL.MEM_SEL by ROM boot FW"
|
|
newline
|
|
hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "PARITY_DIS,Value will be inverted and then written to PRCM:MCUSRAMCFG.PARITY_EN by ROM boot FW" "0,1"
|
|
rgroup.long 0x64++0x07
|
|
line.long 0x00 "CPU_LOCK_CFG,Configuration register for MCU CPU lock options"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4. "LOCKNSVTOR_N,Value will be inverted and written to PRCM:CPULOCK.LOCKNSVTOR by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "LOCKSVTAIRCR_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSVTAIRCR by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "LOCKSAU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSAU by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKNSMPU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKNSMPU by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LOCKSMPU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSMPU by ROM boot FW" "0,1"
|
|
line.long 0x04 "DEB_AUTH_CFG,Configuration register for debug authentication"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 3. "INTSPNIDEN,Value will be written to CPU_DCB:DAUTHCTRL.INTSPNIDEN by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "SPNIDENSEL,Value will be written to CPU_DCB:DAUTHCTRL.SPNIDENSEL by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "INTSPIDEN,Value will be written to CPU_DCB:DAUTHCTRL.INTSPIDEN by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "SPIDENSEL,Value will be written to CPU_DCB:DAUTHCTRL.SPIDENSEL by ROM boot FW" "0,1"
|
|
tree.end
|
|
tree "CPU"
|
|
tree "CPU_DWT"
|
|
base ad:0xE0001000
|
|
rgroup.long 0x00++0x1F
|
|
line.long 0x00 "CTRL,Provides configuration and status information for the DWT unit. and used to control features of the unit"
|
|
bitfld.long 0x00 28.--31. "NUMCOMP,Number of DWT comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "NOTRCPKT,Indicates whether the implementation does not support trace" "0,1"
|
|
bitfld.long 0x00 26. "NOEXTTRIG,Reserved RAZ" "0,1"
|
|
bitfld.long 0x00 25. "NOCYCCNT,Indicates whether the implementation does not include a cycle counter" "0,1"
|
|
bitfld.long 0x00 24. "NOPRFCNT,Indicates whether the implementation does not include the profiling counters" "0,1"
|
|
bitfld.long 0x00 23. "CYCDISS,Controls whether the cycle counter is disabled in Secure state" "0,1"
|
|
bitfld.long 0x00 22. "CYCEVTENA,Enables Event Counter packet generation on POSTCNT underflow" "0,1"
|
|
bitfld.long 0x00 21. "FOLDEVTENA,Enables DWT_FOLDCNT counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LSUEVTENA,Enables DWT_LSUCNT counter" "0,1"
|
|
bitfld.long 0x00 19. "SLEEPEVTENA,Enable DWT_SLEEPCNT counter" "0,1"
|
|
bitfld.long 0x00 18. "EXCEVTENA,Enables DWT_EXCCNT counter" "0,1"
|
|
bitfld.long 0x00 17. "CPIEVTENA,Enables DWT_CPICNT counter" "0,1"
|
|
bitfld.long 0x00 16. "EXTTRCENA,Enables generation of Exception Trace packets" "0,1"
|
|
bitfld.long 0x00 13.--15. "RESERVED13,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "PCSAMPLENA,Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation" "0,1"
|
|
bitfld.long 0x00 10.--11. "SYNCTAP,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "CYCTAP,Selects the position of the POSTCNT tap on the CYCCNT counter" "0,1"
|
|
bitfld.long 0x00 5.--8. "POSTINIT,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "POSTPRESET,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "CYCCNTENA,Enables CYCCNT" "0,1"
|
|
line.long 0x04 "CYCCNT,Shows or sets the value of the processor cycle counter. CYCCNT"
|
|
line.long 0x08 "CPICNT,CPI Count Register"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x08 0.--7. 1. "CPICNT,Counts one on each cycle when all of the following are true:- DWT_CTRL.CPIEVTENA == 1 and DEMCR.TRCENA == 1.- No instruction is executed.- No load-store operation is in progress see DWT_LSUCNT.- No exception-entry or exception-exit operation is.."
|
|
line.long 0x0C "EXCCNT,Counts the total cycles spent in exception processing"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EXCCNT,Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x10 "SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SLEEPCNT,Counts one on each cycle when all of the following are true:- DWT_CTRL.SLEEPEVTENA == 1 and DEMCR.TRCENA == 1.- No instruction is executed see DWT_CPICNT.- No load-store operation is in progress see DWT_LSUCNT.- No exception-entry or.."
|
|
line.long 0x14 "LSUCNT,Increments on the additional cycles required to execute all load or store instructions"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x14 0.--7. 1. "LSUCNT,Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x18 "FOLDCNT,Increments on the additional cycles required to execute all load or store instructions"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FOLDCNT,Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x1C "PCSR,Program Counter Sample Register"
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x10 0x20 0x30 )
|
|
hgroup.long ($2+0x20)++0x03
|
|
hide.long 0x00 "COMP$1,Provides a reference value for use by watchpoint comparator 0"
|
|
repeat.end
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x10 0x20 0x30 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "FUNCTION$1,Controls the operation of watchpoint comparator 0"
|
|
rbitfld.long 0x00 27.--31. "ID,Identifies the capabilities for MATCH for comparator *n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 25.--26. "RESERVED25,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 24. "MATCHED,Set to 1 when the comparator matches" "0,1"
|
|
hexmask.long.word 0x00 12.--23. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,Defines the size of the object being watched for by Data Value and Data Address comparators" "0,1,2,3"
|
|
rbitfld.long 0x00 6.--9. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "ACTION,Defines the action on a match" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "MATCH,Controls the type of match generated by this comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the DWT"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_FPB"
|
|
base ad:0xE0002000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Provides FPB implementation information. and the global enable for the FPB unit"
|
|
rbitfld.long 0x00 28.--31. "REV,Flash Patch and Breakpoint Unit architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 15.--27. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 12.--14. "NUM_CODE_14_12_,Indicates the number of implemented instruction address comparators" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--11. "NUM_LIT,Indicates the number of implemented literal address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "NUM_CODE_7_4_,Indicates the number of implemented instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "KEY,Writes to the FP_CTRL are ignored unless KEY is concurrently written to one" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the FPB" "0,1"
|
|
line.long 0x04 "REMAP,Indicates whether the implementation supports Flash Patch remap and. if it does. holds the target address for remap"
|
|
bitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x04 29. "RMPSPT,Indicates whether the FPB unit supports the Flash Patch remap function" "0,1"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. "REMAP,Holds the bits[28:5] of the Flash Patch remap address"
|
|
bitfld.long 0x04 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "COMP$1,Holds an address for comparison"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "BE,Selects between flashpatch and breakpoint functionality" "0,1"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the FPB"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the FPB"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the FP"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_ITM"
|
|
base ad:0xE0000000
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "STIM$1,Provides the interface for generating Instrumentation packets"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "DISABLED,Indicates whether the Stimulus Port is enabled or disabled" "0,1"
|
|
bitfld.long 0x00 0. "FIFOREADY,Indicates whether the Stimulus Port can accept data" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "STIM$1,Provides the interface for generating Instrumentation packets"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "DISABLED,Indicates whether the Stimulus Port is enabled or disabled" "0,1"
|
|
bitfld.long 0x00 0. "FIFOREADY,Indicates whether the Stimulus Port can accept data" "0,1"
|
|
repeat.end
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "TER0,Provide an individual enable bit for each ITM_STIM register"
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "TPR,Controls which stimulus ports can be accessed by unprivileged code"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "TCR,Configures and controls transfers through the ITM interface"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 23. "BUSY,Indicates whether the ITM is currently processing events" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "TraceBusID,Identifier for multi-source trace stream formatting"
|
|
rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "GTSFREQ,Defines how often the ITM generates a global timestamp based on the global timestamp clock frequency or disables generation of global timestamps" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "TSPrescale,Local timestamp prescaler used with the trace packet reference clock" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x00 5. "STALLENA,Stall the PE to guarantee delivery of Data Trace packets" "0,1"
|
|
bitfld.long 0x00 4. "SWOENA,Enables asynchronous clocking of the timestamp counter" "0,1"
|
|
bitfld.long 0x00 3. "TXENA,Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU" "0,1"
|
|
bitfld.long 0x00 2. "SYNCENA,Enables Synchronization packet transmission for a synchronous TPIU" "0,1"
|
|
bitfld.long 0x00 1. "TSENA,Enables Local timestamp generation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ITMENA,Enables the ITM" "0,1"
|
|
rgroup.long 0xEF0++0x03
|
|
line.long 0x00 "INT_ATREADY,Integration Mode: Read ATB Ready"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFVALID,A read of this bit returns the value of AFVALID" "0,1"
|
|
bitfld.long 0x00 0. "ATREADY,A read of this bit returns the value of ATREADY" "0,1"
|
|
group.long 0xEF8++0x03
|
|
line.long 0x00 "INT_ATVALID,Integration Mode: Write ATB Valid"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFREADY,A write to this bit gives the value of AFREADY" "0,1"
|
|
bitfld.long 0x00 0. "ATREADY,A write to this bit gives the value of ATVALID" "0,1"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ITCTRL,Integration Mode Control Register"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "IME,Integration mode enable bit - The possible values are" "The trace unit is not in integration mode,The trace unit is in integration mode"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the ITM"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_SCS"
|
|
base ad:0xE000E000
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "RESERVED000,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "ICTR,Interrupt Control TypeRead this register to see the number of interrupt lines that the NVIC supports"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "INTLINESNUM,Total number of interrupt lines in groups of" "0...32,33...64,65...96,97...128,129...160,161...192,193...224,225...256"
|
|
line.long 0x08 "ACTLR,Auxiliary ControlThis register is used to disable certain aspects of functionality within the processor"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 9. "DISOOFP,Disables floating point instructions completing out of order with respect to integer instructions" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "DISFPCA,Disable automatic update of CONTROL.FPCA" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "DISFOLD,Disables folding of IT instruction" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "DISDEFWBUF,Disables write buffer use during default memory map accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "DISMCYCINT,Disables interruption of multi-cycle instructions" "0,1"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "STCSR,SysTick Control and StatusThis register enables the SysTick features and returns status flags related to SysTick"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 16. "COUNTFLAG,Returns 1 if timer counted to 0 since last time this was" "0,1"
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newline
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hexmask.long.word 0x00 3.--15. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 2. "CLKSOURCE,Clock source:0: External reference clock.1: Core clockExternal clock is not available in this device" "External reference clock,Core clockExternal clock is not available in.."
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newline
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bitfld.long 0x00 1. "TICKINT," "0,1"
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newline
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bitfld.long 0x00 0. "ENABLE,Enable SysTick counter0: Counter disabled1: Counter operates in a multi-shot way" "Counter disabled,Counter operates in a multi-shot way"
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line.long 0x04 "STRVR,SysTick Reload ValueThis register is used to specify the start value to load into the current value register STCVR.CURRENT when the counter reaches 0"
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hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.tbyte 0x04 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current ValueRead from this register returns the current value of SysTick counter"
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hexmask.long.byte 0x08 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.tbyte 0x08 0.--23. 1. "CURRENT,Current value at the time the register is accessed"
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line.long 0x0C "STCR,SysTick Calibration ValueUsed to enable software to scale to any required speed using divide and multiply"
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bitfld.long 0x0C 31. "NOREF,Reads as one" "0,1"
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bitfld.long 0x0C 30. "SKEW,Reads as one" "0,1"
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bitfld.long 0x0C 24.--29. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.tbyte 0x0C 0.--23. 1. "TENMS,An optional Reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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group.long 0x100++0x07
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line.long 0x00 "NVIC_ISER0,Irq 0 to 31 Set EnableThis register is used to enable interrupts and determine which interrupts are currently enabled"
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bitfld.long 0x00 31. "SETENA31,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
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bitfld.long 0x00 30. "SETENA30,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
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bitfld.long 0x00 29. "SETENA29,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
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bitfld.long 0x00 28. "SETENA28,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
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bitfld.long 0x00 27. "SETENA27,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
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bitfld.long 0x00 26. "SETENA26,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
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bitfld.long 0x00 25. "SETENA25,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
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bitfld.long 0x00 24. "SETENA24,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
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bitfld.long 0x00 23. "SETENA23,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
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bitfld.long 0x00 22. "SETENA22,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
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bitfld.long 0x00 21. "SETENA21,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
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bitfld.long 0x00 20. "SETENA20,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
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bitfld.long 0x00 19. "SETENA19,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
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bitfld.long 0x00 18. "SETENA18,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
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bitfld.long 0x00 17. "SETENA17,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
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bitfld.long 0x00 16. "SETENA16,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
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bitfld.long 0x00 15. "SETENA15,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
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bitfld.long 0x00 14. "SETENA14,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
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bitfld.long 0x00 13. "SETENA13,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
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bitfld.long 0x00 12. "SETENA12,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
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bitfld.long 0x00 11. "SETENA11,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
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bitfld.long 0x00 10. "SETENA10,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
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bitfld.long 0x00 9. "SETENA9,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
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bitfld.long 0x00 8. "SETENA8,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
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bitfld.long 0x00 7. "SETENA7,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "SETENA6,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "SETENA5,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "SETENA4,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "SETENA3,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "SETENA2,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "SETENA1,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "SETENA0,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
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line.long 0x04 "NVIC_ISER1,Irq 32 to 63 Set EnableThis register is used to enable interrupts and determine which interrupts are currently enabled"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 5. "SETENA37,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "SETENA36,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "SETENA35,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "SETENA34,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "SETENA33,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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newline
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bitfld.long 0x04 0. "SETENA32,Writing 0 to this bit has no effect writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
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group.long 0x180++0x07
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line.long 0x00 "NVIC_ICER0,Irq 0 to 31 Clear EnableThis register is used to disable interrupts and determine which interrupts are currently enabled"
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bitfld.long 0x00 31. "CLRENA31,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
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bitfld.long 0x00 30. "CLRENA30,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
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newline
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bitfld.long 0x00 29. "CLRENA29,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
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bitfld.long 0x00 28. "CLRENA28,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
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newline
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bitfld.long 0x00 27. "CLRENA27,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
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bitfld.long 0x00 26. "CLRENA26,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
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bitfld.long 0x00 25. "CLRENA25,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
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bitfld.long 0x00 24. "CLRENA24,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
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newline
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bitfld.long 0x00 23. "CLRENA23,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
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bitfld.long 0x00 22. "CLRENA22,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
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bitfld.long 0x00 21. "CLRENA21,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
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bitfld.long 0x00 20. "CLRENA20,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
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newline
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bitfld.long 0x00 19. "CLRENA19,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
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bitfld.long 0x00 18. "CLRENA18,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
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bitfld.long 0x00 17. "CLRENA17,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
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bitfld.long 0x00 16. "CLRENA16,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
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newline
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bitfld.long 0x00 15. "CLRENA15,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
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bitfld.long 0x00 14. "CLRENA14,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
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newline
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bitfld.long 0x00 13. "CLRENA13,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
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bitfld.long 0x00 12. "CLRENA12,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
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newline
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bitfld.long 0x00 11. "CLRENA11,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
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newline
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bitfld.long 0x00 10. "CLRENA10,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
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newline
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bitfld.long 0x00 9. "CLRENA9,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
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bitfld.long 0x00 8. "CLRENA8,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
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bitfld.long 0x00 7. "CLRENA7,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "CLRENA6,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "CLRENA5,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "CLRENA4,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "CLRENA3,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "CLRENA2,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "CLRENA1,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "CLRENA0,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
|
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line.long 0x04 "NVIC_ICER1,Irq 32 to 63 Clear EnableThis register is used to disable interrupts and determine which interrupts are currently enabled"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 5. "CLRENA37,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "CLRENA36,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "CLRENA35,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "CLRENA34,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "CLRENA33,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "CLRENA32,Writing 0 to this bit has no effect writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
|
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group.long 0x200++0x07
|
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line.long 0x00 "NVIC_ISPR0,Irq 0 to 31 Set PendingThis register is used to force interrupts into the pending state and determine which interrupts are currently pending"
|
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bitfld.long 0x00 31. "SETPEND31,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
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bitfld.long 0x00 30. "SETPEND30,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
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bitfld.long 0x00 29. "SETPEND29,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
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bitfld.long 0x00 28. "SETPEND28,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
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bitfld.long 0x00 27. "SETPEND27,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
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bitfld.long 0x00 26. "SETPEND26,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
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bitfld.long 0x00 25. "SETPEND25,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
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bitfld.long 0x00 24. "SETPEND24,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
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bitfld.long 0x00 23. "SETPEND23,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
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bitfld.long 0x00 22. "SETPEND22,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
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bitfld.long 0x00 21. "SETPEND21,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
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bitfld.long 0x00 20. "SETPEND20,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
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bitfld.long 0x00 19. "SETPEND19,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
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bitfld.long 0x00 18. "SETPEND18,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
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bitfld.long 0x00 17. "SETPEND17,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
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bitfld.long 0x00 16. "SETPEND16,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
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bitfld.long 0x00 15. "SETPEND15,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
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bitfld.long 0x00 14. "SETPEND14,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
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bitfld.long 0x00 13. "SETPEND13,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
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bitfld.long 0x00 12. "SETPEND12,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
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bitfld.long 0x00 11. "SETPEND11,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
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bitfld.long 0x00 10. "SETPEND10,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
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bitfld.long 0x00 9. "SETPEND9,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
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bitfld.long 0x00 8. "SETPEND8,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
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bitfld.long 0x00 7. "SETPEND7,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "SETPEND6,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "SETPEND5,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "SETPEND4,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "SETPEND3,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "SETPEND2,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "SETPEND1,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "SETPEND0,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
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line.long 0x04 "NVIC_ISPR1,Irq 32 to 63 Set PendingThis register is used to force interrupts into the pending state and determine which interrupts are currently pending"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 5. "SETPEND37,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "SETPEND36,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "SETPEND35,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "SETPEND34,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "SETPEND33,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "SETPEND32,Writing 0 to this bit has no effect writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
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group.long 0x280++0x07
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line.long 0x00 "NVIC_ICPR0,Irq 0 to 31 Clear PendingThis register is used to clear pending interrupts and determine which interrupts are currently pending"
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bitfld.long 0x00 31. "CLRPEND31,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details)" "0,1"
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bitfld.long 0x00 30. "CLRPEND30,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details)" "0,1"
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bitfld.long 0x00 29. "CLRPEND29,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details)" "0,1"
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bitfld.long 0x00 28. "CLRPEND28,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details)" "0,1"
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bitfld.long 0x00 27. "CLRPEND27,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details)" "0,1"
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bitfld.long 0x00 26. "CLRPEND26,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details)" "0,1"
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bitfld.long 0x00 25. "CLRPEND25,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details)" "0,1"
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bitfld.long 0x00 24. "CLRPEND24,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details)" "0,1"
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bitfld.long 0x00 23. "CLRPEND23,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details)" "0,1"
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bitfld.long 0x00 22. "CLRPEND22,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details)" "0,1"
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bitfld.long 0x00 21. "CLRPEND21,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details)" "0,1"
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bitfld.long 0x00 20. "CLRPEND20,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details)" "0,1"
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bitfld.long 0x00 19. "CLRPEND19,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details)" "0,1"
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bitfld.long 0x00 18. "CLRPEND18,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details)" "0,1"
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bitfld.long 0x00 17. "CLRPEND17,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details)" "0,1"
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bitfld.long 0x00 16. "CLRPEND16,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details)" "0,1"
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bitfld.long 0x00 15. "CLRPEND15,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details)" "0,1"
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bitfld.long 0x00 14. "CLRPEND14,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details)" "0,1"
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bitfld.long 0x00 13. "CLRPEND13,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details)" "0,1"
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bitfld.long 0x00 12. "CLRPEND12,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details)" "0,1"
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bitfld.long 0x00 11. "CLRPEND11,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details)" "0,1"
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bitfld.long 0x00 10. "CLRPEND10,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details)" "0,1"
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bitfld.long 0x00 9. "CLRPEND9,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details)" "0,1"
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bitfld.long 0x00 8. "CLRPEND8,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details)" "0,1"
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bitfld.long 0x00 7. "CLRPEND7,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details)" "0,1"
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bitfld.long 0x00 6. "CLRPEND6,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details)" "0,1"
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bitfld.long 0x00 5. "CLRPEND5,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details)" "0,1"
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bitfld.long 0x00 4. "CLRPEND4,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details)" "0,1"
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bitfld.long 0x00 3. "CLRPEND3,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details)" "0,1"
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bitfld.long 0x00 2. "CLRPEND2,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details)" "0,1"
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bitfld.long 0x00 1. "CLRPEND1,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details)" "0,1"
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bitfld.long 0x00 0. "CLRPEND0,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details)" "0,1"
|
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line.long 0x04 "NVIC_ICPR1,Irq 32 to 63 Clear PendingThis register is used to clear pending interrupts and determine which interrupts are currently pending"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 5. "CLRPEND37,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details)" "0,1"
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bitfld.long 0x04 4. "CLRPEND36,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details)" "0,1"
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bitfld.long 0x04 3. "CLRPEND35,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details)" "0,1"
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bitfld.long 0x04 2. "CLRPEND34,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details)" "0,1"
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bitfld.long 0x04 1. "CLRPEND33,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details)" "0,1"
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bitfld.long 0x04 0. "CLRPEND32,Writing 0 to this bit has no effect writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details)" "0,1"
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rgroup.long 0x300++0x07
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line.long 0x00 "NVIC_IABR0,Irq 0 to 31 Active BitThis register is used to determine which interrupts are active"
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bitfld.long 0x00 31. "ACTIVE31,Reading 0 from this bit implies that interrupt line 31 is not active" "0,1"
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bitfld.long 0x00 30. "ACTIVE30,Reading 0 from this bit implies that interrupt line 30 is not active" "0,1"
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newline
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bitfld.long 0x00 29. "ACTIVE29,Reading 0 from this bit implies that interrupt line 29 is not active" "0,1"
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newline
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bitfld.long 0x00 28. "ACTIVE28,Reading 0 from this bit implies that interrupt line 28 is not active" "0,1"
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newline
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bitfld.long 0x00 27. "ACTIVE27,Reading 0 from this bit implies that interrupt line 27 is not active" "0,1"
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bitfld.long 0x00 26. "ACTIVE26,Reading 0 from this bit implies that interrupt line 26 is not active" "0,1"
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newline
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bitfld.long 0x00 25. "ACTIVE25,Reading 0 from this bit implies that interrupt line 25 is not active" "0,1"
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newline
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bitfld.long 0x00 24. "ACTIVE24,Reading 0 from this bit implies that interrupt line 24 is not active" "0,1"
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newline
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bitfld.long 0x00 23. "ACTIVE23,Reading 0 from this bit implies that interrupt line 23 is not active" "0,1"
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newline
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bitfld.long 0x00 22. "ACTIVE22,Reading 0 from this bit implies that interrupt line 22 is not active" "0,1"
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newline
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bitfld.long 0x00 21. "ACTIVE21,Reading 0 from this bit implies that interrupt line 21 is not active" "0,1"
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newline
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bitfld.long 0x00 20. "ACTIVE20,Reading 0 from this bit implies that interrupt line 20 is not active" "0,1"
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newline
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bitfld.long 0x00 19. "ACTIVE19,Reading 0 from this bit implies that interrupt line 19 is not active" "0,1"
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newline
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bitfld.long 0x00 18. "ACTIVE18,Reading 0 from this bit implies that interrupt line 18 is not active" "0,1"
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newline
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bitfld.long 0x00 17. "ACTIVE17,Reading 0 from this bit implies that interrupt line 17 is not active" "0,1"
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newline
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bitfld.long 0x00 16. "ACTIVE16,Reading 0 from this bit implies that interrupt line 16 is not active" "0,1"
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newline
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bitfld.long 0x00 15. "ACTIVE15,Reading 0 from this bit implies that interrupt line 15 is not active" "0,1"
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newline
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bitfld.long 0x00 14. "ACTIVE14,Reading 0 from this bit implies that interrupt line 14 is not active" "0,1"
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newline
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bitfld.long 0x00 13. "ACTIVE13,Reading 0 from this bit implies that interrupt line 13 is not active" "0,1"
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newline
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bitfld.long 0x00 12. "ACTIVE12,Reading 0 from this bit implies that interrupt line 12 is not active" "0,1"
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newline
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bitfld.long 0x00 11. "ACTIVE11,Reading 0 from this bit implies that interrupt line 11 is not active" "0,1"
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newline
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bitfld.long 0x00 10. "ACTIVE10,Reading 0 from this bit implies that interrupt line 10 is not active" "0,1"
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newline
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bitfld.long 0x00 9. "ACTIVE9,Reading 0 from this bit implies that interrupt line 9 is not active" "0,1"
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newline
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bitfld.long 0x00 8. "ACTIVE8,Reading 0 from this bit implies that interrupt line 8 is not active" "0,1"
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newline
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bitfld.long 0x00 7. "ACTIVE7,Reading 0 from this bit implies that interrupt line 7 is not active" "0,1"
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newline
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bitfld.long 0x00 6. "ACTIVE6,Reading 0 from this bit implies that interrupt line 6 is not active" "0,1"
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newline
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bitfld.long 0x00 5. "ACTIVE5,Reading 0 from this bit implies that interrupt line 5 is not active" "0,1"
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newline
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bitfld.long 0x00 4. "ACTIVE4,Reading 0 from this bit implies that interrupt line 4 is not active" "0,1"
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newline
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bitfld.long 0x00 3. "ACTIVE3,Reading 0 from this bit implies that interrupt line 3 is not active" "0,1"
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newline
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bitfld.long 0x00 2. "ACTIVE2,Reading 0 from this bit implies that interrupt line 2 is not active" "0,1"
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newline
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bitfld.long 0x00 1. "ACTIVE1,Reading 0 from this bit implies that interrupt line 1 is not active" "0,1"
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newline
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bitfld.long 0x00 0. "ACTIVE0,Reading 0 from this bit implies that interrupt line 0 is not active" "0,1"
|
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line.long 0x04 "NVIC_IABR1,Irq 32 to 63 Active BitThis register is used to determine which interrupts are active"
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hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 5. "ACTIVE37,Reading 0 from this bit implies that interrupt line 37 is not active" "0,1"
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newline
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bitfld.long 0x04 4. "ACTIVE36,Reading 0 from this bit implies that interrupt line 36 is not active" "0,1"
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newline
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bitfld.long 0x04 3. "ACTIVE35,Reading 0 from this bit implies that interrupt line 35 is not active" "0,1"
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newline
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bitfld.long 0x04 2. "ACTIVE34,Reading 0 from this bit implies that interrupt line 34 is not active" "0,1"
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newline
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bitfld.long 0x04 1. "ACTIVE33,Reading 0 from this bit implies that interrupt line 33 is not active" "0,1"
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newline
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bitfld.long 0x04 0. "ACTIVE32,Reading 0 from this bit implies that interrupt line 32 is not active" "0,1"
|
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group.long 0x400++0x27
|
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line.long 0x00 "NVIC_IPR0,Irq 0 to 3 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details)"
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hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details)"
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hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details)"
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hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details)"
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line.long 0x04 "NVIC_IPR1,Irq 4 to 7 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x04 24.--31. 1. "PRI_7,Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details)"
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hexmask.long.byte 0x04 16.--23. 1. "PRI_6,Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details)"
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hexmask.long.byte 0x04 8.--15. 1. "PRI_5,Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details)"
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hexmask.long.byte 0x04 0.--7. 1. "PRI_4,Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details)"
|
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line.long 0x08 "NVIC_IPR2,Irq 8 to 11 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
|
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hexmask.long.byte 0x08 24.--31. 1. "PRI_11,Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details)"
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hexmask.long.byte 0x08 16.--23. 1. "PRI_10,Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details)"
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hexmask.long.byte 0x08 8.--15. 1. "PRI_9,Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details)"
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hexmask.long.byte 0x08 0.--7. 1. "PRI_8,Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details)"
|
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line.long 0x0C "NVIC_IPR3,Irq 12 to 15 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
|
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hexmask.long.byte 0x0C 24.--31. 1. "PRI_15,Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details)"
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hexmask.long.byte 0x0C 16.--23. 1. "PRI_14,Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details)"
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hexmask.long.byte 0x0C 8.--15. 1. "PRI_13,Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details)"
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hexmask.long.byte 0x0C 0.--7. 1. "PRI_12,Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details)"
|
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line.long 0x10 "NVIC_IPR4,Irq 16 to 19 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
|
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hexmask.long.byte 0x10 24.--31. 1. "PRI_19,Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details)"
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hexmask.long.byte 0x10 16.--23. 1. "PRI_18,Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details)"
|
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hexmask.long.byte 0x10 8.--15. 1. "PRI_17,Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details)"
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hexmask.long.byte 0x10 0.--7. 1. "PRI_16,Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details)"
|
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line.long 0x14 "NVIC_IPR5,Irq 20 to 23 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
|
|
hexmask.long.byte 0x14 24.--31. 1. "PRI_23,Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details)"
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hexmask.long.byte 0x14 16.--23. 1. "PRI_22,Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details)"
|
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hexmask.long.byte 0x14 8.--15. 1. "PRI_21,Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details)"
|
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|
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hexmask.long.byte 0x14 0.--7. 1. "PRI_20,Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details)"
|
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line.long 0x18 "NVIC_IPR6,Irq 24 to 27 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
|
|
hexmask.long.byte 0x18 24.--31. 1. "PRI_27,Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details)"
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hexmask.long.byte 0x18 16.--23. 1. "PRI_26,Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details)"
|
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hexmask.long.byte 0x18 8.--15. 1. "PRI_25,Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details)"
|
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|
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hexmask.long.byte 0x18 0.--7. 1. "PRI_24,Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details)"
|
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line.long 0x1C "NVIC_IPR7,Irq 28 to 31 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "PRI_31,Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details)"
|
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newline
|
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hexmask.long.byte 0x1C 16.--23. 1. "PRI_30,Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details)"
|
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newline
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hexmask.long.byte 0x1C 8.--15. 1. "PRI_29,Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details)"
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hexmask.long.byte 0x1C 0.--7. 1. "PRI_28,Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details)"
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line.long 0x20 "NVIC_IPR8,Irq 32 to 35 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.byte 0x20 24.--31. 1. "PRI_35,Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details)"
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hexmask.long.byte 0x20 16.--23. 1. "PRI_34,Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details)"
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hexmask.long.byte 0x20 8.--15. 1. "PRI_33,Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details)"
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hexmask.long.byte 0x20 0.--7. 1. "PRI_32,Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details)"
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line.long 0x24 "NVIC_IPR9,Irq 32 to 35 PriorityThis register is used to assign a priority from 0 to 255 to each of the available interrupts"
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x24 8.--15. 1. "PRI_37,Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details)"
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hexmask.long.byte 0x24 0.--7. 1. "PRI_36,Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details)"
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rgroup.long 0xD00++0x4F
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line.long 0x00 "CPUID,CPUID BaseThis register determines the ID number of the processor core. the version number of the processor core and the implementation details of the processor core"
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hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementor code"
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bitfld.long 0x00 20.--23. "VARIANT,Implementation defined variant number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "CONSTANT,Reads as 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "PARTNO,Number of processor within family"
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bitfld.long 0x00 0.--3. "REVISION,Implementation defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "ICSR,Interrupt Control StateThis register is used to set a pending Non-Maskable Interrupt (NMI). set or clear a pending SVC. set or clear a pending SysTick. check for pending exceptions. check the vector number of the highest priority pended exception.."
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bitfld.long 0x04 31. "NMIPENDSET,Set pending NMI bit" "No action,Set pending NMI"
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bitfld.long 0x04 29.--30. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x04 28. "PENDSVSET,Set pending pendSV bit.0: No action1: Set pending PendSV" "No action,Set pending PendSV"
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bitfld.long 0x04 27. "PENDSVCLR,Clear pending pendSV bit0: No action1: Clear pending pendSV" "No action,Clear pending pendSV"
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bitfld.long 0x04 26. "PENDSTSET,Set a pending SysTick bit.0: No action1: Set pending SysTick" "No action,Set pending SysTick"
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bitfld.long 0x04 25. "PENDSTCLR,Clear pending SysTick bit0: No action1: Clear pending SysTick" "No action,Clear pending SysTick"
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rbitfld.long 0x04 24. "RESERVED24,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x04 23. "ISRPREEMPT,This field can only be used at debug time" "A pending exception is not serviced,A pending exception is serviced on exit from the.."
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bitfld.long 0x04 22. "ISRPENDING,Interrupt pending flag" "Interrupt not pending,Interrupt pending"
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rbitfld.long 0x04 18.--21. "RESERVED18,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x04 12.--17. "VECTPENDING,Pending ISR number field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 11. "RETTOBASE,Indicates whether there are preempted active exceptions:0: There are preempted active exceptions to execute1: There are no active exceptions or the currently-executing exception is the only active exception" "There are preempted active exceptions to execute,There are no active exceptions or the.."
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rbitfld.long 0x04 9.--10. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3"
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hexmask.long.word 0x04 0.--8. 1. "VECTACTIVE,Active ISR number field"
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line.long 0x08 "VTOR,Vector Table OffsetThis register is used to relocated the vector table base address"
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bitfld.long 0x08 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
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hexmask.long.tbyte 0x08 7.--29. 1. "TBLOFF,Bits 29 down to 7 of the vector table base offset"
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hexmask.long.byte 0x08 0.--6. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x0C "AIRCR,Application Interrupt/Reset ControlThis register is used to determine data endianness. clear all active state information for debug or to recover from a hard failure. execute a system reset. alter the priority grouping position (binary point)"
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hexmask.long.word 0x0C 16.--31. 1. "VECTKEY,Register key"
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rbitfld.long 0x0C 15. "ENDIANESS,Data endianness bit" "Little endian,Big endian"
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rbitfld.long 0x0C 11.--14. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--10. "PRIGROUP,Interrupt priority grouping field" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 2. "SYSRESETREQ,Requests a warm reset" "0,1"
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bitfld.long 0x0C 1. "VECTCLRACTIVE,Clears all active state information for active NMI fault and interrupts" "0,1"
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bitfld.long 0x0C 0. "VECTRESET,System Reset bit" "0,1"
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line.long 0x10 "SCR,System ControlThis register is used for power-management functions. i.e.. signaling to the system when the processor can enter a low power state. controlling how the processor enters and exits low power states"
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hexmask.long 0x10 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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bitfld.long 0x10 4. "SEVONPEND,Send Event on Pending bit:0: Only enabled interrupts or events can wakeup the processor disabled interrupts are excluded1: Enabled events and all interrupts including disabled interrupts can wakeup the processor.When an event or interrupt.." "Only enabled interrupts or events can wakeup the..,Enabled events and all interrupts including.."
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bitfld.long 0x10 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x10 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low power mode" "Sleep,Deep sleep"
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bitfld.long 0x10 1. "SLEEPONEXIT,Sleep on exit when returning from Handler mode to Thread mode" "Do not sleep when returning to thread mode,Sleep on ISR exit"
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bitfld.long 0x10 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x14 "CCR,Configuration ControlThis register is used to enable NMI. HardFault and FAULTMASK to ignore bus fault. trap divide by zero and unaligned accesses. enable user access to the Software Trigger Interrupt Register (STIR). control entry to Thread Mode"
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hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
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bitfld.long 0x14 9. "STKALIGN,Stack alignment bit.0: Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.1: On exception entry the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved" "Only 4-byte alignment is guaranteed for the SP..,On exception entry the SP used prior to the.."
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bitfld.long 0x14 8. "BFHFNMIGN,Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions" "Data BusFaults caused by load and store..,Data BusFaults caused by load and store.."
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bitfld.long 0x14 5.--7. "RESERVED5,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4. "DIV_0_TRP,Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of" "Do not trap divide by 0,Trap divide by 0"
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bitfld.long 0x14 3. "UNALIGN_TRP,Enables unaligned access traps:0: Do not trap unaligned halfword and word accesses1: Trap unaligned halfword and word accesses" "Do not trap unaligned halfword and word accesses,Trap unaligned halfword and word accesses"
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bitfld.long 0x14 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x14 1. "USERSETMPEND,Enables unprivileged software access to STIR:0: User code is not allowed to write to the Software Trigger Interrupt register (STIR).1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception.." "User code is not allowed to write to the..,User code can write the Software Trigger.."
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bitfld.long 0x14 0. "NONBASETHREDENA,Indicates how the processor enters Thread mode:0: Processor can enter Thread mode only when no exception is active.1: Processor can enter Thread mode from any level using the appropriate return value (EXC_RETURN).Exception returns occur.." "Processor can enter Thread mode only when no..,Processor can enter Thread mode from any level.."
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line.long 0x18 "SHPR1,System Handlers 4-7 PriorityThis register is used to prioritize the following system handlers: Memory manage. Bus fault. and Usage fault"
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hexmask.long.byte 0x18 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x18 16.--23. 1. "PRI_6,Priority of system handler 6"
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hexmask.long.byte 0x18 8.--15. 1. "PRI_5,Priority of system handler"
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hexmask.long.byte 0x18 0.--7. 1. "PRI_4,Priority of system handler"
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line.long 0x1C "SHPR2,System Handlers 8-11 PriorityThis register is used to prioritize the SVC handler"
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hexmask.long.byte 0x1C 24.--31. 1. "PRI_11,Priority of system handler 11"
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hexmask.long.tbyte 0x1C 0.--23. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x20 "SHPR3,System Handlers 12-15 PriorityThis register is used to prioritize the following system handlers: SysTick. PendSV and Debug Monitor"
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hexmask.long.byte 0x20 24.--31. 1. "PRI_15,Priority of system handler 15"
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hexmask.long.byte 0x20 16.--23. 1. "PRI_14,Priority of system handler 14"
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hexmask.long.byte 0x20 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x20 0.--7. 1. "PRI_12,Priority of system handler 12"
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line.long 0x24 "SHCSR,System Handler Control and StateThis register is used to enable or disable the system handlers. determine the pending status of bus fault. mem manage fault. and SVC. determine the active status of the system handlers"
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hexmask.long.word 0x24 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
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bitfld.long 0x24 18. "USGFAULTENA,Usage fault system handler enable" "Exception disabled,Exception enabled"
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bitfld.long 0x24 17. "BUSFAULTENA,Bus fault system handler enable" "Exception disabled,Exception enabled"
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bitfld.long 0x24 16. "MEMFAULTENA,MemManage fault system handler enable" "Exception disabled,Exception enabled"
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rbitfld.long 0x24 15. "SVCALLPENDED,SVCall pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 14. "BUSFAULTPENDED,BusFault pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 13. "MEMFAULTPENDED,MemManage exception pending" "Exception is not active,Exception is pending."
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rbitfld.long 0x24 12. "USGFAULTPENDED,Usage fault pending" "Exception is not active,Exception is pending."
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bitfld.long 0x24 11. "SYSTICKACT,SysTick active" "Not active,Active"
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bitfld.long 0x24 10. "PENDSVACT,PendSV" "Not active,Active"
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rbitfld.long 0x24 9. "RESERVED9,Software should not rely on the value of a reserved" "0,1"
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rbitfld.long 0x24 8. "MONITORACT,Debug monitor active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 7. "SVCALLACT,SVCall active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 4.--6. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 3. "USGFAULTACT,UsageFault exception active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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rbitfld.long 0x24 1. "BUSFAULTACT,BusFault exception active" "Exception is not active,Exception is active"
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rbitfld.long 0x24 0. "MEMFAULTACT,MemManage exception active" "Exception is not active,Exception is active"
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line.long 0x28 "CFSR,Configurable Fault StatusThis register is used to obtain information about local faults"
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bitfld.long 0x28 26.--31. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 25. "DIVBYZERO,When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0 this fault occurs The instruction is executed and the return PC points to it" "0,1"
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bitfld.long 0x28 24. "UNALIGNED,When CCR.UNALIGN_TRP is enabled and there is an attempt to make an unaligned memory access then this fault occurs" "0,1"
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bitfld.long 0x28 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 19. "NOCP,Attempt to use a coprocessor instruction" "0,1"
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bitfld.long 0x28 18. "INVPC,Attempt to load EXC_RETURN into PC illegally" "0,1"
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bitfld.long 0x28 17. "INVSTATE,Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state)" "0,1"
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bitfld.long 0x28 16. "UNDEFINSTR,This bit is set when the processor attempts to execute an undefined instruction" "0,1"
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bitfld.long 0x28 15. "BFARVALID,This bit is set if the Bus Fault Address Register (BFAR) contains a valid address" "0,1"
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bitfld.long 0x28 13.--14. "RESERVED13,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x28 12. "STKERR,Stacking from exception has caused one or more bus faults" "0,1"
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bitfld.long 0x28 11. "UNSTKERR,Unstack from exception return has caused one or more bus faults" "0,1"
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bitfld.long 0x28 10. "IMPRECISERR,Imprecise data bus error" "0,1"
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bitfld.long 0x28 9. "PRECISERR,Precise data bus error return" "0,1"
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bitfld.long 0x28 8. "IBUSERR,Instruction bus error flag" "0,1"
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bitfld.long 0x28 7. "MMARVALID,Memory Manage Address Register (MMFAR) address valid flag" "0,1"
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bitfld.long 0x28 5.--6. "RESERVED5,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x28 4. "MSTKERR,Stacking from exception has caused one or more access violations" "0,1"
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bitfld.long 0x28 3. "MUNSTKERR,Unstack from exception return has caused one or more access violations" "0,1"
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bitfld.long 0x28 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x28 1. "DACCVIOL,Data access violation flag" "0,1"
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bitfld.long 0x28 0. "IACCVIOL,Instruction access violation flag" "0,1"
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line.long 0x2C "HFSR,Hard Fault StatusThis register is used to obtain information about events that activate the Hard Fault handler"
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bitfld.long 0x2C 31. "DEBUGEVT,This bit is set if there is a fault related to debug" "0,1"
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bitfld.long 0x2C 30. "FORCED,Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled" "0,1"
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hexmask.long 0x2C 2.--29. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x2C 1. "VECTTBL,This bit is set if there is a fault because of vector table read on exception processing (Bus Fault)" "0,1"
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bitfld.long 0x2C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
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line.long 0x30 "DFSR,Debug Fault StatusThis register is used to monitor external debug requests. vector catches. data watchpoint match. BKPT instruction execution. halt requests"
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hexmask.long 0x30 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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bitfld.long 0x30 4. "EXTERNAL,External debug request flag" "External debug request signal not asserted,External debug request signal asserted"
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bitfld.long 0x30 3. "VCATCH,Vector catch flag" "No vector catch occurred,Vector catch occurred"
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bitfld.long 0x30 2. "DWTTRAP,Data Watchpoint and Trace (DWT) flag" "No DWT match,DWT match"
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bitfld.long 0x30 1. "BKPT,BKPT flag" "No BKPT instruction execution,BKPT instruction execution"
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bitfld.long 0x30 0. "HALTED,Halt request flag" "No halt request,Halt requested by NVIC including step"
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line.long 0x34 "MMFAR,Mem Manage Fault AddressThis register is used to read the address of the location that caused a Memory Manage Fault"
|
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line.long 0x38 "BFAR,Bus Fault AddressThis register is used to read the address of the location that generated a Bus Fault"
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line.long 0x3C "AFSR,Auxiliary Fault StatusThis register is used to determine additional system fault information to software"
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line.long 0x40 "ID_PFR0,Processor Feature 0"
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hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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bitfld.long 0x40 4.--7. "STATE1,State1 (T-bit ==" "N/A,N/A,Thumb-2 encoding with the 16-bit basic..,Thumb-2 encoding with all Thumb-2 basic..,?..."
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bitfld.long 0x40 0.--3. "STATE0,State0 (T-bit ==" "No ARM..,N/A,?..."
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line.long 0x44 "ID_PFR1,Processor Feature 1"
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hexmask.long.tbyte 0x44 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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bitfld.long 0x44 8.--11. "MICROCONTROLLER_PROGRAMMERS_MODEL,Microcontroller programmer's model0x0: Not supported0x2: Two-stack support" "Not supported,?,Two-stack support,?..."
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hexmask.long.byte 0x44 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
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line.long 0x48 "ID_DFR0,Debug Feature 0This register provides a high level view of the debug system"
|
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hexmask.long.byte 0x48 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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bitfld.long 0x48 20.--23. "MICROCONTROLLER_DEBUG_MODEL,Microcontroller Debug Model - memory mapped0x0: Not supported0x1: Microcontroller debug v1 (ITMv1 and DWTv1)" "Not supported,Microcontroller debug v1 (ITMv1 and..,?..."
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hexmask.long.tbyte 0x48 0.--19. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x4C "ID_AFR0,Auxiliary Feature 0This register provides some freedom for implementation defined features to be registered"
|
|
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
|
|
rgroup.long ($2+0xD50)++0x03
|
|
line.long 0x00 "ID_MMFR$1,Memory Model Feature 0General information on the memory model and memory management support"
|
|
repeat.end
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature 2General information on the memory model and memory management support"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED28,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 24. "WAIT_FOR_INTERRUPT_STALLING,wait for interrupt stalling0x0: Not supported0x1: Wait for interrupt supported" "Not supported,Wait for interrupt supported"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
repeat 5. (list 0. 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0xD60)++0x03
|
|
line.long 0x00 "ID_ISAR$1,ISA Feature 0Information on the instruction set attributes register"
|
|
repeat.end
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access ControlThis register specifies the access privileges for coprocessors"
|
|
rgroup.long 0xD90++0x2B
|
|
line.long 0x00 "MPU_TYPE,MPU TypeThis register indicates many regions the MPU supports"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Reads 0"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "IREGION,The processor core uses only a unified MPU this field always reads 0x0"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DREGION,Number of supported MPU regions field"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Reads 0"
|
|
newline
|
|
bitfld.long 0x00 0. "SEPARATE,The processor core uses only a unified MPU thus this field is always 0" "0,1"
|
|
line.long 0x04 "MPU_CTRL,MPU ControlThis register is used to enable the MPU. enable the default memory map (background region). and enable the MPU when in Hard Fault. Non-maskable Interrupt (NMI). and FAULTMASK escalated handlers"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 2. "PRIVDEFENA,This bit enables the default memory map for privileged access as a background region when the MPU is enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "HFNMIENA,This bit enables the MPU when in Hard Fault NMI and FAULTMASK escalated handlers" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "ENABLE,Enable MPU0: MPU disabled1: MPU enabled" "MPU disabled,MPU enabled"
|
|
line.long 0x08 "MPU_RNR,MPU Region NumberThis register is used to select which protection region is accessed"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "REGION,Region select field"
|
|
line.long 0x0C "MPU_RBAR,MPU Region Base AddressThis register writes the base address of a region"
|
|
hexmask.long 0x0C 5.--31. 1. "ADDR,Region base address field"
|
|
newline
|
|
bitfld.long 0x0C 4. "VALID,MPU region number valid:0: MPU_RNR remains unchanged and is interpreted.1: MPU_RNR is overwritten by REGION" "MPU_RNR remains unchanged and is interpreted,MPU_RNR is overwritten by REGION"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "REGION,MPU region override field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "MPU_RASR,MPU Region Attribute and SizeThis register controls the MPU access permissions"
|
|
bitfld.long 0x10 29.--31. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 28. "XN,Instruction access disable:0: Enable instruction" "Enable instruction fetches,Disable instruction fetches"
|
|
newline
|
|
bitfld.long 0x10 27. "RESERVED27,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24.--26. "AP,Data access permission:0x0: Priviliged permissions: No access" "Priviliged permissions,Priviliged permissions,Priviliged permissions,Priviliged permissions,Reserved,Priviliged permissions,Priviliged permissions,Priviliged permissions"
|
|
newline
|
|
bitfld.long 0x10 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 19.--21. "TEX,Type extension" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 18. "S,Shareable bit:0: Not shareable1: Shareable" "Not shareable,Shareable"
|
|
newline
|
|
bitfld.long 0x10 17. "C,Cacheable bit:0: Not" "Not cacheable,Cacheable"
|
|
newline
|
|
bitfld.long 0x10 16. "B,Bufferable bit:0: Not bufferable1: Bufferable" "Not bufferable,Bufferable"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "SRD,Sub-Region Disable field:Setting a bit in this field disables the corresponding sub-region"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 1.--5. "SIZE,MPU Protection Region Size" "?,?,?,?,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
newline
|
|
bitfld.long 0x10 0. "ENABLE,Region enable bit:0: Disable region" "Disable region,Enable region"
|
|
line.long 0x14 "MPU_RBAR_A1,MPU Alias 1 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x18 "MPU_RASR_A1,MPU Alias 1 Region Attribute and SizeAlias for MPU_RASR"
|
|
line.long 0x1C "MPU_RBAR_A2,MPU Alias 2 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x20 "MPU_RASR_A2,MPU Alias 2 Region Attribute and SizeAlias for MPU_RASR"
|
|
line.long 0x24 "MPU_RBAR_A3,MPU Alias 3 Region Base AddressAlias for MPU_RBAR"
|
|
line.long 0x28 "MPU_RASR_A3,MPU Alias 3 Region Attribute and SizeAlias for MPU_RASR"
|
|
group.long 0xDF0++0x0F
|
|
line.long 0x00 "DHCSR,Debug Halting Control and StatusThe purpose of this register is to provide status information about the state of the processor. enable core debug. halt and step the processor"
|
|
bitfld.long 0x00 26.--31. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 25. "S_RESET_ST,Indicates that the core has been reset or is now being reset since the last time this bit was" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "S_RETIRE_ST,Indicates that an instruction has completed since last" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "S_LOCKUP,Reads as one if the core is running (not halted) and a lockup condition is present.When writing to this register 1 must be written this bit-field otherwise the write operation is ignored and no bits are written into the register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "S_SLEEP,Indicates that the core is sleeping (WFI WFE or **SLEEP-ON-EXIT**)" "0,1"
|
|
newline
|
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bitfld.long 0x00 17. "S_HALT,The core is in debug state when this bit is set.When writing to this register 1 must be written this bit-field otherwise the write operation is ignored and no bits are written into the register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "S_REGRDY,Register Read/Write on the Debug Core Register Selector register is available" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 6.--15. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 5. "C_SNAPSTALL,If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED4,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "C_MASKINTS,Mask interrupts when stepping or running in halted debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "C_STEP,Steps the core in halted debug" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "C_HALT,Halts the core" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "C_DEBUGEN,Enables debug" "0,1"
|
|
line.long 0x04 "DCRSR,Deubg Core Register SelectorThe purpose of this register is to select the processor register to transfer data to or from"
|
|
hexmask.long.word 0x04 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 16. "REGWNR," "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 5.--15. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "REGSEL,Register select0x00: R00x01: R10x02: R20x03: R30x04: R40x05: R50x06: R60x07: R70x08: R80x09: R90x0A: R100x0B: R110x0C: R120x0D: Current SP0x0E: LR0x0F" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,XPSR/flags..,MSP (Main SP),PSP (Process SP),?,CONTROL<<24 |..,?..."
|
|
line.long 0x08 "DCRDR,Debug Core Register Data"
|
|
line.long 0x0C "DEMCR,Debug Exception and Monitor ControlThe purpose of this register is vector catching and debug monitor control"
|
|
hexmask.long.byte 0x0C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 24. "TRCENA,This bit must be set to 1 to enable use of the trace and debug blocks: DWT ITM ETM and TPIU" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 19. "MON_REQ,This enables the monitor to identify how it wakes up" "Woken up by debug exception,Woken up by MON_PEND"
|
|
newline
|
|
bitfld.long 0x0C 18. "MON_STEP,When MON_EN = 1 this steps the core" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 17. "MON_PEND,Pend the monitor to activate when priority permits" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. "MON_EN,Enable the debug monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 11.--15. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 10. "VC_HARDERR,Debug trap on Hard Fault" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "VC_INTERR,Debug trap on a fault occurring during an exception entry or return sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "VC_BUSERR,Debug Trap on normal Bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 7. "VC_STATERR,Debug trap on Usage Fault state errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "VC_CHKERR,Debug trap on Usage Fault enabled checking errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "VC_NOCPERR,Debug trap on a UsageFault access to a Coprocessor" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "VC_MMERR,Debug trap on Memory Management faults" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0C 0. "VC_CORERESET,Reset Vector Catch" "0,1"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID field"
|
|
group.long 0xF34++0x13
|
|
line.long 0x00 "FPCCR,Floating Point Context ControlThis register holds control data for the floating-point unit"
|
|
bitfld.long 0x00 31. "ASPEN,Automatic State Preservation enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "LSPEN,Lazy State Preservation enable" "Disable automatic lazy state preservation for..,Enable automatic lazy state preservation for.."
|
|
newline
|
|
hexmask.long.tbyte 0x00 9.--29. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "MONRDY,Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending.0: DebugMonitor is disabled or priority did not permit setting DEMCR.MON_PEND when the.." "DebugMonitor is disabled or priority did not..,DebugMonitor is enabled and priority permits.."
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "BFRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending.0: BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when.." "BusFault is disabled or priority did not permit..,BusFault is enabled and priority permitted.."
|
|
newline
|
|
bitfld.long 0x00 5. "MMRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending.0: MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when.." "MemManage is disabled or priority did not permit..,MemManage is enabled and priority permitted.."
|
|
newline
|
|
bitfld.long 0x00 4. "HFRDY,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending.0: Priority did not permit setting the HardFault handler to the pending state when the floating-point stack.." "Priority did not permit setting the HardFault..,Priority permitted setting the HardFault handler.."
|
|
newline
|
|
bitfld.long 0x00 3. "THREAD,Indicates the processor mode was Thread when it allocated the FP stack frame.0: Mode was not Thread Mode when the floating-point stack frame was allocated.1: Mode was Thread Mode when the floating-point stack frame was allocated" "Mode was not Thread Mode when the floating-point..,Mode was Thread Mode when the floating-point.."
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "USER,Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame:0: Privilege level was not user when the floating-point stack frame was allocated.1: Privilege level was user when the.." "Privilege level was not user when the..,Privilege level was user when the floating-point.."
|
|
newline
|
|
bitfld.long 0x00 0. "LSPACT,Indicates whether Lazy preservation of the FP state is active:0: Lazy state preservation is not active.1: Lazy state preservation is active" "Lazy state preservation is not active,Lazy state preservation is active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address This register holds the location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
hexmask.long 0x04 2.--31. 1. "ADDRESS,Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
line.long 0x08 "FPDSCR,Floating Point Default Status ControlThis register holds the default values for the floating-point status control data that the processor assigns to the FPSCR when it creates a new floating-point context"
|
|
bitfld.long 0x08 27.--31. "RESERVED27,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 26. "AHP,Default value for Alternative Half Precision bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. "DN,Default value for Default NaN mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 24. "FZ,Default value for Flush-to-Zero mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22.--23. "RMODE,Default value for Rounding Mode control field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.tbyte 0x08 0.--21. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "MVFR0,Media and FP Feature 0Describes the features provided by the Floating-point extension"
|
|
bitfld.long 0x0C 28.--31. "FP_ROUNDING_MODES,Indicates the rounding modes supported by the FP floating-point hardware" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 24.--27. "SHORT_VECTORS,Indicates the hardware support for FP short vectors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 20.--23. "SQUARE_ROOT,Indicates the hardware support for FP square root operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 16.--19. "DIVIDE,Indicates the hardware support for FP divide operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 12.--15. "FP_EXCEPTION_TRAPPING,Indicates whether the FP hardware implementation supports exception trapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 8.--11. "DOUBLE_PRECISION,Indicates the hardware support for FP double-precision operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 4.--7. "SINGLE_PRECISION,Indicates the hardware support for FP single-precision operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "A_SIMD,Indicates the size of the FP register bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "MVFR1,Media and FP Feature 1Describes the features provided by the Floating-point extension"
|
|
bitfld.long 0x10 28.--31. "FP_FUSED_MAC,Indicates whether the FP supports fused multiply accumulate operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 24.--27. "FP_HPFP,Indicates whether the FP supports half-precision floating-point conversion operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x10 8.--23. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 4.--7. "D_NAN_MODE,Indicates whether the FP hardware implementation supports only the Default NaN mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 0.--3. "FTZ_MODE,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_TIPROP"
|
|
base ad:0xE00FE000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RESERVED000,Software should not rely on the value of a reserved"
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "TRACECLKMUX,Internal"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x00 0. "TRACECLK_N_SWV,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
tree.end
|
|
tree "CPU_TPIU"
|
|
base ad:0xE0040000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "SSPSR,Supported Sync Port SizesThis register represents a single port size that is supported on the device. that is. 4. 2 or 1"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "FOUR,4-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
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bitfld.long 0x00 2. "THREE,3-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 1. "TWO,2-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
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bitfld.long 0x00 0. "ONE,1-bit port size support0x0: Not supported0x1: Supported" "Not supported,Supported"
|
|
line.long 0x04 "CSPSR,Current Sync Port SizeThis register has the same format as SSPSR but only one bit can be set. and all others must be zero"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 3. "FOUR,4-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
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bitfld.long 0x04 2. "THREE,3-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
bitfld.long 0x04 1. "TWO,2-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
newline
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bitfld.long 0x04 0. "ONE,1-bit port enableWriting values with more than one bit set in CSPSR or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ACPR,Async Clock PrescalerThis register scales the baud rate of the asynchronous output"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x00 0.--12. 1. "PRESCALER,Divisor for input trace clock is (PRESCALER + 1)"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "SPPR,Selected Pin ProtocolThis register selects the protocol to be used for trace output"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--1. "PROTOCOL,Trace output protocol" "TracePort mode,SerialWire Output (Manchester). This is the..,SerialWire Output (NRZ),?"
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "FFSR,Formatter and Flush Status"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "FTNONSTOP," "0,1"
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|
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bitfld.long 0x00 0.--2. "RESERVED0,This field always reads as zero" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FFCR,Formatter and Flush ControlWhen one of the two single wire output (SWO) modes is selected. ENFCONT enables the formatter to be bypassed"
|
|
hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "TRIGIN,Indicates that triggers are inserted when a trigger pin is asserted" "0,1"
|
|
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bitfld.long 0x04 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 1. "ENFCONT,Enable continuous formatting:0: Continuous formatting disabled1: Continuous formatting enabled" "Continuous formatting disabled,Continuous formatting enabled"
|
|
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|
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bitfld.long 0x04 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x08 "FSCR,Formatter Synchronization Counter"
|
|
rgroup.long 0xFA0++0x03
|
|
line.long 0x00 "CLAIMMASK,Claim Tag Mask"
|
|
wgroup.long 0xFA0++0x07
|
|
line.long 0x00 "CLAIMSET,Claim Tag Set"
|
|
line.long 0x04 "CLAIMTAG,Current Claim Tag"
|
|
wgroup.long 0xFA4++0x03
|
|
line.long 0x00 "CLAIMCLR,Claim Tag Clear"
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "DEVID,Device ID"
|
|
tree.end
|
|
tree.end
|
|
tree "CRYPTO"
|
|
base ad:0x40024000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DMACH0CTL,Channel 0 ControlThis register is used for channel enabling and priority selection"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
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bitfld.long 0x00 1. "PRIO,Channel priority0: Low1: HighIf both channels have the same priority access of the channels to the external port is arbitrated using the round robin scheme" "Low,HighIf.."
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bitfld.long 0x00 0. "EN,Channel enable0: Disabled1: EnableNote: Disabling an active channel interrupts the DMA operation" "Disabled,Enable"
|
|
line.long 0x04 "DMACH0EXTADDR,Channel 0 External Address"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMACH0LEN,Channel 0 DMA Length"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "DMALEN,Channel DMA length in bytesDuring configuration this register contains the DMA transfer length in bytes"
|
|
rgroup.long 0x18++0x0F
|
|
line.long 0x00 "DMASTAT,DMAC StatusThis register provides the actual state of each DMA channel"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
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bitfld.long 0x00 17. "PORT_ERR,Reflects possible transfer errors on the AHB port" "0,1"
|
|
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hexmask.long.word 0x00 2.--16. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x00 1. "CH1_ACT,A value of 1 indicates that channel 1 is active (DMA transfer on-going)" "0,1"
|
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bitfld.long 0x00 0. "CH0_ACT,A value of 1 indicates that channel 0 is active (DMA transfer on-going)" "0,1"
|
|
line.long 0x04 "DMASWRESET,DMAC Software ResetSoftware reset is used to reset the DMAC to stop all transfers and clears the port error status register"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
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bitfld.long 0x04 0. "SWRES,Software reset enable0 : Disabled1 : Enabled (self-cleared to 0)Completion of the software reset must be checked through the DMASTAT" "Disabled,Enabled (self-cleared.."
|
|
line.long 0x08 "DMACH1CTL,Channel 1 ControlThis register is used for channel enabling and priority selection"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
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bitfld.long 0x08 1. "PRIO,Channel priority0: Low1: HighIf both channels have the same priority access of the channels to the external port is arbitrated using the round robin scheme" "Low,HighIf.."
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|
newline
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bitfld.long 0x08 0. "EN,Channel enable0: Disabled1: EnableNote: Disabling an active channel interrupts the DMA operation" "Disabled,Enable"
|
|
line.long 0x0C "DMACH1EXTADDR,Channel 1 External Address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMACH1LEN,Channel 1 DMA Length"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
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|
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hexmask.long.word 0x00 0.--15. 1. "DMALEN,Channel DMA length in bytes.During configuration this register contains the DMA transfer length in bytes"
|
|
group.long 0x78++0x07
|
|
line.long 0x00 "DMABUSCFG,DMAC Master Run-time ParametersThis register defines all the run-time parameters for the AHB master interface port"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
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bitfld.long 0x00 12.--15. "AHB_MST1_BURST_SIZE,Maximum burst size that can be performed on the AHB bus" "?,?,4 bytes,8 bytes ,16 bytes ,32 bytes ,64 bytes ,?,?,?,?,?,?,?,?,?"
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bitfld.long 0x00 11. "AHB_MST1_IDLE_EN,Idle insertion between consecutive burst transfers on AHB" "Do not insert idle transfers.,Idle transfer insertion enabled"
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|
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|
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bitfld.long 0x00 10. "AHB_MST1_INCR_EN,Burst length type of AHB transfer" "Unspecified length burst transfers,Fixed length bursts or single transfers"
|
|
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|
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bitfld.long 0x00 9. "AHB_MST1_LOCK_EN,Locked transform on AHB" "Transfers are not locked,Transfers are locked"
|
|
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|
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bitfld.long 0x00 8. "AHB_MST1_BIGEND,Endianess for the AHB master" "Little Endian,Big Endian"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "DMAPORTERR,DMAC Port Error Raw StatusThis register provides the actual status of individual port errors"
|
|
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
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bitfld.long 0x04 12. "PORT1_AHB_ERROR,A value of 1 indicates that the EIP-101 has detected an AHB bus error" "0,1"
|
|
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bitfld.long 0x04 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
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|
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bitfld.long 0x04 9. "PORT1_CHANNEL,Indicates which channel has serviced last (channel 0 or channel 1) by AHB master port" "0,1"
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|
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|
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hexmask.long.word 0x04 0.--8. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "DMAHWVER,DMAC VersionThis register contains an indication (or signature) of the EIP type of this DMAC. as well as the hardware version/patch numbers"
|
|
bitfld.long 0x00 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 24.--27. "HW_MAJOR_VERSION,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x00 20.--23. "HW_MINOR_VERSION,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 16.--19. "HW_PATCH_LEVEL,Patch levelStarts at 0 at first delivery of this version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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hexmask.long.byte 0x00 8.--15. 1. "EIP_NUMBER_COMPL,Bit-by-bit complement of the EIP_NUMBER field bits"
|
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "EIP_NUMBER,Binary encoding of the EIP-number of this DMA controller (209)"
|
|
group.long 0x400++0x0F
|
|
line.long 0x00 "KEYWRITEAREA,Key Store Write AreaThis register defines where the keys should be written in the key store RAM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
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|
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bitfld.long 0x00 7. "RAM_AREA7,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA7 is not selected to be written.1: RAM_AREA7 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA7 is not selected to be written,RAM_AREA7 is selected to be written.Writing to.."
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|
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|
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bitfld.long 0x00 6. "RAM_AREA6,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA6 is not selected to be written.1: RAM_AREA6 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA6 is not selected to be written,RAM_AREA6 is selected to be written.Writing to.."
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|
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|
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bitfld.long 0x00 5. "RAM_AREA5,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA5 is not selected to be written.1: RAM_AREA5 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA5 is not selected to be written,RAM_AREA5 is selected to be written.Writing to.."
|
|
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|
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bitfld.long 0x00 4. "RAM_AREA4,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA4 is not selected to be written.1: RAM_AREA4 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA4 is not selected to be written,RAM_AREA4 is selected to be written.Writing to.."
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|
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|
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bitfld.long 0x00 3. "RAM_AREA3,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA3 is not selected to be written.1: RAM_AREA3 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA3 is not selected to be written,RAM_AREA3 is selected to be written.Writing to.."
|
|
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|
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bitfld.long 0x00 2. "RAM_AREA2,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA2 is not selected to be written.1: RAM_AREA2 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA2 is not selected to be written,RAM_AREA2 is selected to be written.Writing to.."
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|
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|
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bitfld.long 0x00 1. "RAM_AREA1,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA1 is not selected to be written.1: RAM_AREA1 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA1 is not selected to be written,RAM_AREA1 is selected to be written.Writing to.."
|
|
newline
|
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bitfld.long 0x00 0. "RAM_AREA0,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA0 is not selected to be written.1: RAM_AREA0 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA0 is not selected to be written,RAM_AREA0 is selected to be written.Writing to.."
|
|
line.long 0x04 "KEYWRITTENAREA,Key Store Written AreaThis register shows which areas of the key store RAM contain valid written keys.When a new key needs to be written to the key store. on a location that is already occupied by a valid key. this key area must be.."
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 7. "RAM_AREA_WRITTEN7,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
|
|
newline
|
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bitfld.long 0x04 6. "RAM_AREA_WRITTEN6,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
|
|
newline
|
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bitfld.long 0x04 5. "RAM_AREA_WRITTEN5,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
|
|
newline
|
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bitfld.long 0x04 4. "RAM_AREA_WRITTEN4,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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|
newline
|
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bitfld.long 0x04 3. "RAM_AREA_WRITTEN3,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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|
newline
|
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bitfld.long 0x04 2. "RAM_AREA_WRITTEN2,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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|
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bitfld.long 0x04 1. "RAM_AREA_WRITTEN1,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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|
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|
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bitfld.long 0x04 0. "RAM_AREA_WRITTEN0,On read this bit returns the key area written status.This bit can be reset by writing a" "0,1"
|
|
line.long 0x08 "KEYSIZE,Key Store SizeThis register defines the size of the keys that are written with DMA"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 0.--1. "SIZE,Key size:00: ReservedWhen writing this to this register the KEY_STORE_WRITTEN_AREA register is reset" "?,128 bits,192 bits,256 bits"
|
|
line.long 0x0C "KEYREADAREA,Key Store Read AreaThis register selects the key store RAM area from where the key needs to be read that will be used for an AES operation"
|
|
bitfld.long 0x0C 31. "BUSY,Key store operation busy status flag (read only):0: Operation is complete.1: Operation is not completed and the key store is busy" "Operation is complete,Operation is not completed and the key store is.."
|
|
newline
|
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hexmask.long 0x0C 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "RAM_AREA,Selects the area of the key store RAM from where the key needs to be read that will be writen to the AES engineRAM_AREA:RAM areas RAM_AREA0 RAM_AREA2 RAM_AREA4 and RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes.Only RAM.." "RAM Area 0,RAM Area 1,RAM Area 2,RAM Area 3,RAM Area 4,RAM Area 5,RAM Area 6,RAM Area 7,No RAM,?,?,?,?,?,?,?"
|
|
wgroup.long 0x500++0x03
|
|
line.long 0x00 "AESKEY2,AES_KEY2_0 / AES_GHASH_H_IN_0Second Key / GHASH Key (internal. but clearable)The following registers are not accessible through the host for reading and writing"
|
|
wgroup.long 0x510++0x03
|
|
line.long 0x00 "AESKEY3,AES_KEY3_0 / AES_KEY2_4Third Key / Second Key (internal. but clearable)The following registers are not accessible through the host for reading and writing"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "AESIV,AES initialization vector registersThese registers are used to provide and read the IV from the AES engine"
|
|
group.long 0x550++0x0F
|
|
line.long 0x00 "AESCTL,AES ControlAES input/output buffer control and mode registerThis register specifies the AES mode of operation for the EIP-120t.Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0"
|
|
rbitfld.long 0x00 31. "CONTEXT_READY,If 1 this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SAVED_CONTEXT_RDY,If 1 this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the host to retrieve" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "SAVE_CONTEXT,This bit indicates that an authentication TAG or result IV needs to be stored as a result context.Typically this bit must be set for authentication modes returning a TAG (CBC-MAC GCM and CCM) or for basic encryption modes that require.." "0,1"
|
|
newline
|
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bitfld.long 0x00 28. "GCM_CCM_CONTINUE,Continue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase.Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation to continue processing from the.." "0,1"
|
|
newline
|
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bitfld.long 0x00 27. "GET_DIGEST,Interrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation.Set this write-only signal to '1b' to interrupt GCM or CCM processing at the next full block (128 bits) boundary" "0,1"
|
|
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|
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bitfld.long 0x00 26. "GCM_CCM_CONTINUE_AAD,Continue processing of an interrupted AES-GCM or AES-CCM operation in the AAD phase.Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation to continue processing from the next full.." "0,1"
|
|
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|
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bitfld.long 0x00 25. "XCBC_MAC,Set to '1' to select AES-XCBC MAC mode.The direction bit must be set to '1' for this mode.Selecting this mode requires writing the length register" "0,1"
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|
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|
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bitfld.long 0x00 22.--24. "CCM_M,Defines M which indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one).Note: The EIP-120t always returns a 128-bit authentication field of which the M.." "0,1,2,3,4,5,6,7"
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|
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bitfld.long 0x00 19.--21. "CCM_L,Defines L which indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one" "0,1,2,3,4,5,6,7"
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|
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|
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bitfld.long 0x00 18. "CCM,If set to 1 AES-CCM is selectedAES-CCM is a combined mode using AES for authentication and encryption.Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers.Note: The CTR mode bit in this register must.." "0,1"
|
|
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|
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bitfld.long 0x00 16.--17. "GCM,Set these bits to 11 to select AES-GCM mode.AES-GCM is a combined mode using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption.Note: The CTR mode bit in this register must also be set to 1 to.." "No GCM mode,Reserved do not select,?..."
|
|
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|
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bitfld.long 0x00 15. "CBC_MAC,Set to 1 to select AES-CBC MAC mode.The direction bit must be set to 1 for this mode.Selecting this mode requires writing the length register after all other registers" "0,1"
|
|
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bitfld.long 0x00 9.--14. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
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bitfld.long 0x00 7.--8. "CTR_WIDTH,Specifies the counter width for AES-CTR mode00 = 32-bit counter01 = 64-bit counter10 = 96-bit counter11 = 128-bit counter" "32-bit counter,64-bit counter,?..."
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newline
|
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bitfld.long 0x00 6. "CTR,If set to 1 AES counter mode (CTR) is selected.Note: This bit must also be set for GCM and CCM when encryption/decryption is required" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CBC,If set to 1 cipher-block-chaining (CBC) mode is selected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "KEY_SIZE,This read-only field specifies the key size.The key size is automatically configured when a new key is loaded through the key store module.00 = N/A - Reserved01 =" "N/A - Reserved,128-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "DIR,If set to 1 an encrypt operation is performed.If set to 0 a decrypt operation is performed.This bit must be written with a 1 when CBC-MAC is selected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INPUT_READY,If 1 this status bit indicates that the 16-byte AES input buffer is empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OUTPUT_READY,If 1 this status bit indicates that an AES output block is available to be retrieved by the host.Writing 0 clears the bit to 0 and indicates that output data is read by the host" "0,1"
|
|
line.long 0x04 "AESDATALEN0,AES Crypto Length 0 (LSW)These registers are used to write the Length values to the EIP-120t"
|
|
line.long 0x08 "AESDATALEN1,AES Crypto Length 1 (MSW)These registers are used to write the Length values to the EIP-120t"
|
|
bitfld.long 0x08 29.--31. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long 0x08 0.--28. 1. "C_LENGTH,C_LENGTH[60:32]Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes"
|
|
line.long 0x0C "AESAUTHLEN,AES Authentication Length"
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
|
|
rgroup.long ($2+0x560)++0x03
|
|
line.long 0x00 "AESDATAOUT$1,Data Input/Output"
|
|
repeat.end
|
|
repeat 2. (list 0. 1. )(list 0x00 0x04 )
|
|
wgroup.long ($2+0x560)++0x03
|
|
line.long 0x00 "AESDATAIN$1,AES Data Input_Output 0The data registers are typically accessed through the DMA and not with host writes and/or reads"
|
|
repeat.end
|
|
wgroup.long 0x568++0x0B
|
|
line.long 0x00 "AESDATAIN2,AES Data Input_Output 2The data registers are typically accessed via DMA and not with host writes and/or reads"
|
|
line.long 0x04 "AESDATAIN3,AES Data Input_Output 3The data registers are typically accessed via DMA and not with host writes and/or reads"
|
|
line.long 0x08 "AESTAGOUT,AES Tag Out 0The tag registers can be accessed via DMA or directly with host reads.These registers buffer the TAG from the EIP-120t"
|
|
group.long 0x5D4++0x0B
|
|
line.long 0x00 "AESCCMALNWRD,This register needs to be read and stored when an AES-CCM operation is interrupted"
|
|
line.long 0x04 "AESBLKCNT0,This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations"
|
|
line.long 0x08 "AESBLKCNT1,This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations"
|
|
hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long 0x08 0.--24. 1. "AES_BLK_CNT_56_32,[56:32] of Internal block counter for AES GCM and CCM operations.These bits read the block count value that represents the number of blocks to go"
|
|
repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
wgroup.long ($2+0x604)++0x03
|
|
line.long 0x00 "HASHDATAIN$1,HASH Data Input 1The data input registers should be used to provide input data to the hash module through the slave interface"
|
|
repeat.end
|
|
repeat 15. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
wgroup.long ($2+0x644)++0x03
|
|
line.long 0x00 "HASHDATAIN$1,HASH Data Input 17The data input registers should be used to provide input data to the hash module through the slave interface"
|
|
repeat.end
|
|
group.long 0x680++0x0F
|
|
line.long 0x00 "HASHIOBUFCTRL,HASH Input_Output Buffer ControlThis register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "PAD_DMA_MESSAGE,Note: This bit must only be used when data is supplied through the DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "GET_DIGEST,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PAD_MESSAGE,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "RESERVED3,Write 0s and ignore on reading" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "RFD_IN,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DATA_IN_AV,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OUTPUT_FULL,Indicates that the output buffer registers (HASHDIGESTn) are available for reading by the host.When this bit reads 0 the output buffer registers are released; the hash engine is allowed to write new data to it" "0,1"
|
|
line.long 0x04 "HASHMODE,HASH Mode"
|
|
hexmask.long 0x04 7.--31. 1. "RESERVED7,Write 0s and ignore on reading"
|
|
newline
|
|
bitfld.long 0x04 6. "SHA384_MODE,The host must write this bit with 1 prior to processing a SHA 384 session" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5. "SHA512_MODE,The host must write this bit with 1 prior to processing a SHA 512 session" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "SHA224_MODE,The host must write this bit with 1 prior to processing a SHA 224 session" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "SHA256_MODE,The host must write this bit with 1 prior to processing a SHA 256 session" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1.--2. "RESERVED1,Write 0s and ignore on reading" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0. "NEW_HASH,When set to 1 it indicates that the hash engine must start processing a new hash session" "0,1"
|
|
line.long 0x08 "HASHINLENL,HASH Input Length LSB"
|
|
line.long 0x0C "HASHINLENH,HASH Input Length MSB"
|
|
group.long 0x6C0++0x47
|
|
line.long 0x00 "HASHDIGESTA,HASH Digest AThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x04 "HASHDIGESTB,HASH Digest BThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x08 "HASHDIGESTC,HASH Digest CThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x0C "HASHDIGESTD,HASH Digest DThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x10 "HASHDIGESTE,HASH Digest EThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x14 "HASHDIGESTF,HASH Digest FThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x18 "HASHDIGESTG,HASH Digest GThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x1C "HASHDIGESTH,HASH Digest HThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x20 "HASHDIGESTI,HASH Digest IThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x24 "HASHDIGESTJ,HASH Digest JThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x28 "HASHDIGESTK,HASH Digest KThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x2C "HASHDIGESTL,HASH Digest LThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x30 "HASHDIGESTM,HASH Digest MThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x34 "HASHDIGESTN,HASH Digest NThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x38 "HASHDIGESTO,HASH Digest 0The hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x3C "HASHDIGESTP,HASH Digest PThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
|
|
line.long 0x40 "ALGSEL,Algorithm SelectThis algorithm selection register configures the internal destination of the DMA controller"
|
|
bitfld.long 0x40 31. "TAG,If this bit is cleared to 0 the DMA operation involves only data.If this bit is set the DMA operation includes a TAG (Authentication Result / Digest).For SHA-256 operation a DMA must be set up for both input data and TAG" "0,1"
|
|
newline
|
|
hexmask.long 0x40 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x40 3. "HASH_SHA_512,If set to one selects the hash engine in 512B mode as destination for the DMAThe maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out.." "0,1"
|
|
newline
|
|
bitfld.long 0x40 2. "HASH_SHA_256,If set to one selects the hash engine in 256B mode as destination for the DMAThe maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out.." "0,1"
|
|
newline
|
|
bitfld.long 0x40 1. "AES,If set to one selects the AES engine as source/destination for the DMAThe read and write maximum transfer size to the DMA engine is set to 16 bytes" "0,1"
|
|
newline
|
|
bitfld.long 0x40 0. "KEY_STORE,If set to one selects the Key Store as destination for the DMAThe maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16 24 and 32 bytes are allowed)" "0,1"
|
|
line.long 0x44 "DMAPROTCTL,DMA Protection ControlMaster PROT privileged access enableThis register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys.."
|
|
hexmask.long 0x44 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x44 0. "PROT_EN,Select AHB transfer protection control for DMA transfers using the key store area as destination.0 : transfers use 'USER' type access.1 : transfers use 'PRIVILEGED' type access" "transfers use 'USER' type access,transfers use 'PRIVILEGED' type access"
|
|
group.long 0x740++0x03
|
|
line.long 0x00 "SWRESET,Software Reset"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "SW_RESET,If this bit is set to 1 the following modules are reset: - Master control internal state is reset" "0,1"
|
|
group.long 0x780++0x13
|
|
line.long 0x00 "IRQTYPE,Control Interrupt Configuration"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "LEVEL,If this bit is 0 the interrupt output is a pulse.If this bit is set to 1 the interrupt is a level interrupt that must be cleared by writing the interrupt clear register.This bit is applicable for both interrupt output signals" "0,1"
|
|
line.long 0x04 "IRQEN,Control Interrupt Enable"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 1. "DMA_IN_DONE,If this bit is set to 0 the DMA input done interrupt disabledIf this bit is set to 1 the DMA input done interrupt enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "RESULT_AVAIL,If this bit is set to 0 the Result Available interrupt is disabledIf this bit is set to 1 the Result Available interrupt is enabled." "0,1"
|
|
line.long 0x08 "IRQCLR,Control Interrupt Clear"
|
|
bitfld.long 0x08 31. "DMA_BUS_ERR,If 1 is written to this bit the DMA bus error status is cleared.Writing 0 has no effect" "0,1"
|
|
newline
|
|
bitfld.long 0x08 30. "KEY_ST_WR_ERR,If 1 is written to this bit the key store write error status is cleared.Writing 0 has no effect" "0,1"
|
|
newline
|
|
bitfld.long 0x08 29. "KEY_ST_RD_ERR,If 1 is written to this bit the key store read error status is cleared.Writing 0 has no effect" "0,1"
|
|
newline
|
|
hexmask.long 0x08 2.--28. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "DMA_IN_DONE,If 1 is written to this bit the DMA in done interrupt status is cleared.Writing 0 has no effect.Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE)." "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "RESULT_AVAIL,If 1 is written to this bit the result available interrupt status is cleared.Writing 0 has no effect.Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE)." "0,1"
|
|
line.long 0x0C "IRQSET,Control Interrupt Set"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "DMA_IN_DONE,If 1 is written to this bit the DMA data in done interrupt is set.Writing 0 has no effect.If the interrupt configuration register is programmed to pulse clearing the DMA data in done interrupt is not needed" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "RESULT_AVAIL,If 1 is written to this bit the result available interrupt is setWriting 0 has no effect.If the interrupt configuration register is programmed to pulse clearing the result available interrupt is not needed" "0,1"
|
|
line.long 0x10 "IRQSTAT,Control Interrupt Status"
|
|
bitfld.long 0x10 31. "DMA_BUS_ERR,This bit is set when a DMA bus error is detected during a DMA operation" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "KEY_ST_WR_ERR,This bit is set when a write error is detected during the DMA write operation to the key store memory" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "KEY_ST_RD_ERR,This bit is set when a read error is detected during the read of a key from the key store while copying it to the AES core" "0,1"
|
|
newline
|
|
hexmask.long 0x10 2.--28. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 1. "DMA_IN_DONE,This read only bit returns the actual DMA data in done interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "RESULT_AVAIL,This read only bit returns the actual result available interrupt status" "0,1"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "HWVER,Hardware Version"
|
|
bitfld.long 0x00 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "HW_MAJOR_VER,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "HW_MINOR_VER,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HW_PATCH_LVL,Patch levelStarts at 0 at first delivery of this version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "VER_NUM_COMPL,These bits simply contain the complement of bits [7:0] (0x87) used by a driver to ascertain that the EIP-120t register is indeed"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VER_NUM,These bits encode the EIP number for the EIP-120t this field contains the value 120 (decimal) or 0x78"
|
|
tree.end
|
|
tree "EVENT"
|
|
base ad:0x40083000
|
|
rgroup.long 0x00++0xAB
|
|
line.long 0x00 "CPUIRQSEL0,Output Selection for CPU Interrupt 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x04 "CPUIRQSEL1,Output Selection for CPU Interrupt 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x08 "CPUIRQSEL2,Output Selection for CPU Interrupt 2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "CPUIRQSEL3,Output Selection for CPU Interrupt 3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "CPUIRQSEL4,Output Selection for CPU Interrupt 4"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "CPUIRQSEL5,Output Selection for CPU Interrupt 5"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "CPUIRQSEL6,Output Selection for CPU Interrupt 6"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "CPUIRQSEL7,Output Selection for CPU Interrupt 7"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "CPUIRQSEL8,Output Selection for CPU Interrupt 8"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "CPUIRQSEL9,Output Selection for CPU Interrupt 9"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x28 "CPUIRQSEL10,Output Selection for CPU Interrupt 10"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x2C "CPUIRQSEL11,Output Selection for CPU Interrupt 11"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x30 "CPUIRQSEL12,Output Selection for CPU Interrupt 12"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x34 "CPUIRQSEL13,Output Selection for CPU Interrupt 13"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x38 "CPUIRQSEL14,Output Selection for CPU Interrupt 14"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x3C "CPUIRQSEL15,Output Selection for CPU Interrupt 15"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x40 "CPUIRQSEL16,Output Selection for CPU Interrupt 16"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x44 "CPUIRQSEL17,Output Selection for CPU Interrupt 17"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x48 "CPUIRQSEL18,Output Selection for CPU Interrupt 18"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x4C "CPUIRQSEL19,Output Selection for CPU Interrupt 19"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x50 "CPUIRQSEL20,Output Selection for CPU Interrupt 20"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x54 "CPUIRQSEL21,Output Selection for CPU Interrupt 21"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x58 "CPUIRQSEL22,Output Selection for CPU Interrupt 22"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x5C "CPUIRQSEL23,Output Selection for CPU Interrupt 23"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x60 "CPUIRQSEL24,Output Selection for CPU Interrupt 24"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x64 "CPUIRQSEL25,Output Selection for CPU Interrupt 25"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x68 "CPUIRQSEL26,Output Selection for CPU Interrupt 26"
|
|
hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x68 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x6C "CPUIRQSEL27,Output Selection for CPU Interrupt 27"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x70 "CPUIRQSEL28,Output Selection for CPU Interrupt 28"
|
|
hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x70 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x74 "CPUIRQSEL29,Output Selection for CPU Interrupt 29"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x78 "CPUIRQSEL30,Output Selection for CPU Interrupt 30"
|
|
hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x78 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x7C "CPUIRQSEL31,Output Selection for CPU Interrupt 31"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x80 "CPUIRQSEL32,Output Selection for CPU Interrupt 32"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x84 "CPUIRQSEL33,Output Selection for CPU Interrupt 33"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x88 "CPUIRQSEL34,Output Selection for CPU Interrupt 34"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x8C "CPUIRQSEL35,Output Selection for CPU Interrupt 35"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x90 "CPUIRQSEL36,Output Selection for CPU Interrupt 36"
|
|
hexmask.long.tbyte 0x90 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x90 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x94 "CPUIRQSEL37,Output Selection for CPU Interrupt 37"
|
|
hexmask.long.tbyte 0x94 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x94 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x98 "CPUIRQSEL38,Output Selection for CPU Interrupt 38"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x9C "CPUIRQSEL39,Output Selection for CPU Interrupt 39"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA0 "CPUIRQSEL40,Output Selection for CPU Interrupt 40"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA4 "CPUIRQSEL41,Output Selection for CPU Interrupt 41"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA8 "CPUIRQSEL42,Output Selection for CPU Interrupt 42"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--7. 1. "EV,Read only selection value"
|
|
rgroup.long 0x100++0x27
|
|
line.long 0x00 "RFCSEL0,Output Selection for RFC Event 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x04 "RFCSEL1,Output Selection for RFC Event 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x08 "RFCSEL2,Output Selection for RFC Event 2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "RFCSEL3,Output Selection for RFC Event 3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "RFCSEL4,Output Selection for RFC Event 4"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "RFCSEL5,Output Selection for RFC Event 5"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "RFCSEL6,Output Selection for RFC Event 6"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "RFCSEL7,Output Selection for RFC Event 7"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "RFCSEL8,Output Selection for RFC Event 8"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "RFCSEL9,Output Selection for RFC Event 9"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "GPT0ACAPTSEL,Output Selection for GPT0 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT0BCAPTSEL,Output Selection for GPT0 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "GPT1ACAPTSEL,Output Selection for GPT1 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT1BCAPTSEL,Output Selection for GPT1 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "GPT2ACAPTSEL,Output Selection for GPT2 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT2BCAPTSEL,Output Selection for GPT2 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
rgroup.long 0x500++0x107
|
|
line.long 0x00 "UDMACH0SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "UDMACH0BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x08 "UDMACH1SSEL,Output Selection for DMA Channel 1 SREQ"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "UDMACH1BSEL,Output Selection for DMA Channel 1 REQ"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "UDMACH2SSEL,Output Selection for DMA Channel 2 SREQ"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "UDMACH2BSEL,Output Selection for DMA Channel 2 REQ"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "UDMACH3SSEL,Output Selection for DMA Channel 3 SREQ"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "UDMACH3BSEL,Output Selection for DMA Channel 3 REQ"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "UDMACH4SSEL,Output Selection for DMA Channel 4 SREQ"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "UDMACH4BSEL,Output Selection for DMA Channel 4 REQ"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x28 "UDMACH5SSEL,Output Selection for DMA Channel 5 SREQ"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x2C "UDMACH5BSEL,Output Selection for DMA Channel 5 REQ"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x30 "UDMACH6SSEL,Output Selection for DMA Channel 6 SREQ"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x34 "UDMACH6BSEL,Output Selection for DMA Channel 6 REQ"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x38 "UDMACH7SSEL,Output Selection for DMA Channel 7 SREQ"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x3C "UDMACH7BSEL,Output Selection for DMA Channel 7 REQ"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x40 "UDMACH8SSEL,Output Selection for DMA Channel 8 SREQSingle request is ignored for this channel"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x44 "UDMACH8BSEL,Output Selection for DMA Channel 8 REQ"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x48 "UDMACH9SSEL,Output Selection for DMA Channel 9 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x4C "UDMACH9BSEL,Output Selection for DMA Channel 9 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x50 "UDMACH10SSEL,Output Selection for DMA Channel 10 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x54 "UDMACH10BSEL,Output Selection for DMA Channel 10 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x58 "UDMACH11SSEL,Output Selection for DMA Channel 11 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x5C "UDMACH11BSEL,Output Selection for DMA Channel 11 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x60 "UDMACH12SSEL,Output Selection for DMA Channel 12 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x64 "UDMACH12BSEL,Output Selection for DMA Channel 12 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x68 "UDMACH13SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x6C "UDMACH13BSEL,Output Selection for DMA Channel 13 REQ"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x70 "UDMACH14SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x74 "UDMACH14BSEL,Output Selection for DMA Channel 14 REQ"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x78 "UDMACH15SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x7C "UDMACH15BSEL,Output Selection for DMA Channel 15 REQ"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x80 "UDMACH16SSEL,Output Selection for DMA Channel 16 SREQ"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x84 "UDMACH16BSEL,Output Selection for DMA Channel 16 REQ"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x88 "UDMACH17SSEL,Output Selection for DMA Channel 17 SREQ"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x8C "UDMACH17BSEL,Output Selection for DMA Channel 17 REQ"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x90 "UDMACH18SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x94 "UDMACH18BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x98 "UDMACH19SSEL,Output Selection for DMA Channel 19 SREQ"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x9C "UDMACH19BSEL,Output Selection for DMA Channel 19 REQ"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA0 "UDMACH20SSEL,Output Selection for DMA Channel 20 SREQ"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA4 "UDMACH20BSEL,Output Selection for DMA Channel 20 REQ"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA8 "UDMACH21SSEL,Output Selection for DMA Channel 21 SREQ"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xAC "UDMACH21BSEL,Output Selection for DMA Channel 21 REQ"
|
|
hexmask.long.tbyte 0xAC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xAC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB0 "UDMACH22SSEL,Output Selection for DMA Channel 22 SREQ"
|
|
hexmask.long.tbyte 0xB0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB4 "UDMACH22BSEL,Output Selection for DMA Channel 22 REQ"
|
|
hexmask.long.tbyte 0xB4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB8 "UDMACH23SSEL,Output Selection for DMA Channel 23 SREQ"
|
|
hexmask.long.tbyte 0xB8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xBC "UDMACH23BSEL,Output Selection for DMA Channel 23 REQ"
|
|
hexmask.long.tbyte 0xBC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC0 "UDMACH24SSEL,Output Selection for DMA Channel 24 SREQ"
|
|
hexmask.long.tbyte 0xC0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC4 "UDMACH24BSEL,Output Selection for DMA Channel 24 REQ"
|
|
hexmask.long.tbyte 0xC4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC8 "UDMACH25SSEL,Output Selection for DMA Channel 25 SREQ"
|
|
hexmask.long.tbyte 0xC8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xCC "UDMACH25BSEL,Output Selection for DMA Channel 25 REQ"
|
|
hexmask.long.tbyte 0xCC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD0 "UDMACH26SSEL,Output Selection for DMA Channel 26 SREQ"
|
|
hexmask.long.tbyte 0xD0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xD0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD4 "UDMACH26BSEL,Output Selection for DMA Channel 26 REQ"
|
|
hexmask.long.tbyte 0xD4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xD4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD8 "UDMACH27SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0xDC "UDMACH27BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0xE0 "UDMACH28SSEL,Output Selection for DMA Channel 28 SREQ"
|
|
hexmask.long.tbyte 0xE0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xE4 "UDMACH28BSEL,Output Selection for DMA Channel 28 REQ"
|
|
hexmask.long.tbyte 0xE4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xE8 "UDMACH29SSEL,Output Selection for DMA Channel 29 SREQ"
|
|
hexmask.long.tbyte 0xE8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xEC "UDMACH29BSEL,Output Selection for DMA Channel 29 REQ"
|
|
hexmask.long.tbyte 0xEC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xEC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF0 "UDMACH30SSEL,Output Selection for DMA Channel 30 SREQ"
|
|
hexmask.long.tbyte 0xF0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF4 "UDMACH30BSEL,Output Selection for DMA Channel 30 REQ"
|
|
hexmask.long.tbyte 0xF4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF8 "UDMACH31SSEL,Output Selection for DMA Channel 31 SREQ"
|
|
hexmask.long.tbyte 0xF8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xFC "UDMACH31BSEL,Output Selection for DMA Channel 31 REQ"
|
|
hexmask.long.tbyte 0xFC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xFC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x100 "GPT3ACAPTSEL,Output Selection for GPT3 0"
|
|
hexmask.long.tbyte 0x100 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x100 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x104 "GPT3BCAPTSEL,Output Selection for GPT3 1"
|
|
hexmask.long.tbyte 0x104 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x104 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "AUXSEL0,Output Selection for AUX Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "CM3NMISEL0,Output Selection for NMI Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "I2SSTMPSEL0,Output Selection for I2S Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "FRZSEL0,Output Selection for FRZ SubscriberThe halted debug signal is passed to peripherals such as the General Purpose Timer. Sensor Controller with Digital and Analog Peripherals (AUX). Radio. and RTC"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "SWEV,Set or Clear Software Events"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 24. "SWEV3,Writing '1' to this bit when the value is '0' triggers the Software 3 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "SWEV2,Writing '1' to this bit when the value is '0' triggers the Software 2 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "SWEV1,Writing '1' to this bit when the value is '0' triggers the Software 1 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "SWEV0,Writing '1' to this bit when the value is '0' triggers the Software 0 event" "0,1"
|
|
tree.end
|
|
tree "FCFG1"
|
|
base ad:0x50001000
|
|
repeat 4. (list 0. 4. 140. 324. )(list 0x00 0x04 0x150 0x324 )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "RESERVED_$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "MISC_CONF_1,Misc configurations"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DEVICE_MINOR_REV,HW minor revision number (a value of 0xFF shall be treated equally to 0x00).Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer.Value may change without warning"
|
|
line.long 0x04 "MISC_CONF_2,Internal"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "HPOSC_COMP_P3,Internal"
|
|
repeat 5. (list 5. 4. 3. 2. 1. )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0xB0)++0x03
|
|
line.long 0x00 "HPOSC_MEAS_$1,Internal"
|
|
hexmask.long.word 0x00 16.--31. 1. "HPOSC_D5,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "HPOSC_T5,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "HPOSC_DT5,Internal"
|
|
repeat.end
|
|
rgroup.long 0xC4++0x1B
|
|
line.long 0x00 "CONFIG_CC26_FE,Internal"
|
|
bitfld.long 0x00 28.--31. "IFAMP_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "LNA_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "IFAMP_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--18. "CTL_PA0_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13. "PATRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RSSITRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSSI_OFFSET,Internal"
|
|
line.long 0x04 "CONFIG_CC13_FE,Internal"
|
|
bitfld.long 0x04 28.--31. "IFAMP_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 24.--27. "LNA_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 19.--23. "IFAMP_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 14.--18. "CTL_PA0_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 13. "PATRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12. "RSSITRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8.--11. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "RSSI_OFFSET,Internal"
|
|
line.long 0x08 "CONFIG_RF_COMMON,Internal"
|
|
bitfld.long 0x08 31. "DISABLE_CORNER_CAP,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25.--30. "SLDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 22.--24. "RESERVED,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 21. "PA20DBMTRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16.--20. "CTL_PA_20DBM_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x08 9.--15. 1. "RFLDO_TRIM_OUTPUT,Internal"
|
|
newline
|
|
bitfld.long 0x08 6.--8. "QUANTCTLTHRES,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "DACTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CONFIG_SYNTH_DIV2_CC26_2G4,Internal"
|
|
bitfld.long 0x0C 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x0C 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x0C 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "CONFIG_SYNTH_DIV2_CC13_2G4,Internal"
|
|
bitfld.long 0x10 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x10 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x10 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x10 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "CONFIG_SYNTH_DIV2_CC26_1G,Internal"
|
|
bitfld.long 0x14 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x14 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x14 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x14 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "CONFIG_SYNTH_DIV2_CC13_1G,Internal"
|
|
bitfld.long 0x18 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x18 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x18 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x18 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xE0)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV4_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 4. (list 5. 10. 15. 30. )(list 0x00 0x0C 0x18 0x1C )
|
|
rgroup.long ($2+0xE8)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xEC)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV6_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xF8)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV12_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "IOCONF,IO Configuration"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "GPIO_CNT,Number of available DIOs."
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "USER_ID,User Identification.Reading this register and the FCFG1:ICEPICK_DEVICE_ID register is the only supported way of identifying a device.The value of this register will be written to AON_PMCTL:JTAGUSERCODE by boot FW while in safezone"
|
|
bitfld.long 0x00 28.--31. "PG_REV,Field used to distinguish revisions of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "VER,Version number.0x0: Bits [25:12] of this register has the stated meaning.Any other setting indicate a different encoding of these bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 25. "PA," "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED24,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CC13," "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "SEQUENCE,Sequence.Used to differentiate between marketing/orderable product where other fields of this register are the same (temp range flash size voltage range etc)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PKG,Package type.0x0: 4x4mm QFN (RHB) package0x1: 5x5mm QFN (RSM) package0x2: 7x7mm QFN (RGZ) package0x3: Wafer sale package (naked" "4x4mm QFN (RHB) package,5x5mm QFN (RSM) package,7x7mm QFN (RGZ) package,Wafer sale package (naked die),WCSP (YFV),7x7mm QFN package with Wettable FlanksOther..,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PROTOCOL,Protocols supported.0x1: BLE" "?,BLE,RF4CE,?,Zigbee/6lowpan,?,?,?,ProprietaryMore than..,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
rgroup.long 0x2B0++0x0B
|
|
line.long 0x00 "FLASH_OTP_DATA3,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FLASH_SIZE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "ANA2_TRIM,Internal"
|
|
bitfld.long 0x04 31. "RCOSCHFCTRIMFRACT_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 26.--30. "RCOSCHFCTRIMFRACT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 25. "RESERVED0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 23.--24. "SET_RCOSC_HF_FINE_RESISTOR,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 22. "ATESTLF_UDIGLDO_IBIAS_TRIM,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 15.--21. 1. "NANOAMP_RES_TRIM,Internal"
|
|
newline
|
|
bitfld.long 0x04 12.--14. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 11. "DITHER_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8.--10. "DCDC_IPEAK,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 6.--7. "DEAD_TIME_TRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 3.--5. "DCDC_LOW_EN_SEL,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "DCDC_HIGH_EN_SEL,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "LDO_TRIM,Internal"
|
|
bitfld.long 0x08 29.--31. "RESERVED4,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 24.--28. "VDDR_TRIM_SLEEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 19.--23. "RESERVED3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 16.--18. "GLDO_CURSRC,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 13.--15. "RESERVED2,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 11.--12. "ITRIM_DIGLDO_LOAD,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 8.--10. "ITRIM_UDIGLDO,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 3.--7. "RESERVED1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "VTRIM_DELTA,Internal" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2E8++0x0F
|
|
line.long 0x00 "MAC_BLE_0,MAC BLE Address 0"
|
|
line.long 0x04 "MAC_BLE_1,MAC BLE Address 1"
|
|
line.long 0x08 "MAC_15_4_0,MAC IEEE 802.15.4 Address 0"
|
|
line.long 0x0C "MAC_15_4_1,MAC IEEE 802.15.4 Address 1"
|
|
rgroup.long 0x30C++0x07
|
|
line.long 0x00 "MISC_TRIM,Miscellaneous Trim Parameters"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--16. "TRIM_RECHARGE_COMP_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TRIM_RECHARGE_COMP_REFLEVEL,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEMPVSLOPE,Signed byte value representing the TEMP slope with battery voltage in degrees C / V with four fractional bits"
|
|
line.long 0x04 "RCOSC_HF_TEMPCOMP,Internal"
|
|
hexmask.long.byte 0x04 24.--31. 1. "FINE_RESISTOR,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. "CTRIM,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "CTRIMFRACT_QUAD,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "CTRIMFRACT_SLOPE,Internal"
|
|
rgroup.long 0x318++0x0B
|
|
line.long 0x00 "ICEPICK_DEVICE_ID,IcePick Device IdentificationReading this register and the FCFG1:USER_ID register is the only supported way of identifying a device"
|
|
bitfld.long 0x00 28.--31. "PG_REV,Field used to distinguish revisions of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "WAFER_ID,Field used to identify silicon die"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "MANUFACTURER_ID,Manufacturer"
|
|
line.long 0x04 "FCFG1_REVISION,Factory Configuration (FCFG1) Revision"
|
|
line.long 0x08 "MISC_OTP_DATA,Misc OTP Data"
|
|
bitfld.long 0x08 28.--31. "RCOSC_HF_ITUNE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x08 20.--27. 1. "RCOSC_HF_CRIM,Internal"
|
|
newline
|
|
bitfld.long 0x08 15.--19. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 12.--14. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
rgroup.long 0x34C++0x07
|
|
line.long 0x00 "CONFIG_IF_ADC,Internal"
|
|
bitfld.long 0x00 28.--31. "FF2ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FF3ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "INT3ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "FF1ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "AAFCAP,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--13. "INT2ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "IFDIGLDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "IFANALDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CONFIG_OSC_TOP,Internal"
|
|
bitfld.long 0x04 30.--31. "RESERVED,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 26.--29. "XOSC_HF_ROW_Q12,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x04 10.--25. 1. "XOSC_HF_COLUMN_Q12,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 2.--9. 1. "RCOSCLF_CTUNE_TRIM,Internal"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RCOSCLF_RTUNE_TRIM,Internal" "0,1,2,3"
|
|
rgroup.long 0x35C++0x07
|
|
line.long 0x00 "SOC_ADC_ABS_GAIN,AUX_ADC Gain in Absolute Reference Mode"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "SOC_ADC_ABS_GAIN_TEMP1,SOC_ADC gain in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REL_GAIN,AUX_ADC Gain in Relative Reference Mode"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "SOC_ADC_REL_GAIN_TEMP1,SOC_ADC gain in relative reference mode at temperature 1 (30C)"
|
|
rgroup.long 0x368++0x17
|
|
line.long 0x00 "SOC_ADC_OFFSET_INT,AUX_ADC Temperature Offsets in Absolute Reference Mode"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "SOC_ADC_REL_OFFSET_TEMP1,SOC_ADC offset in relative reference mode at temperature 1 (30C)"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SOC_ADC_ABS_OFFSET_TEMP1,SOC_ADC offset in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REF_TRIM_AND_OFFSET_EXT,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "SOC_ADC_REF_VOLTAGE_TRIM_TEMP1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "AMPCOMP_TH1,Internal"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED1,Internal"
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|
newline
|
|
bitfld.long 0x08 18.--23. "HPMRAMP3_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
bitfld.long 0x08 16.--17. "RESERVED0,Internal" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x08 10.--15. "HPMRAMP3_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x08 6.--9. "IBIASCAP_LPTOHP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x08 0.--5. "HPMRAMP1_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "AMPCOMP_TH2,Internal"
|
|
bitfld.long 0x0C 26.--31. "LPMUPDATE_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 24.--25. "RESERVED3,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 18.--23. "LPMUPDATE_HTM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x0C 16.--17. "RESERVED2,Internal" "0,1,2,3"
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|
newline
|
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bitfld.long 0x0C 10.--15. "ADC_COMP_AMPTH_LPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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bitfld.long 0x0C 8.--9. "RESERVED1,Internal" "0,1,2,3"
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|
newline
|
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bitfld.long 0x0C 2.--7. "ADC_COMP_AMPTH_HPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x0C 0.--1. "RESERVED0,Internal" "0,1,2,3"
|
|
line.long 0x10 "AMPCOMP_CTRL1,Internal"
|
|
bitfld.long 0x10 31. "RESERVED1,Internal" "0,1"
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|
newline
|
|
bitfld.long 0x10 30. "AMPCOMP_REQ_MODE,Internal" "0,1"
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|
newline
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bitfld.long 0x10 24.--29. "RESERVED0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 20.--23. "IBIAS_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
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bitfld.long 0x10 16.--19. "IBIAS_INIT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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hexmask.long.byte 0x10 8.--15. 1. "LPM_IBIAS_WAIT_CNT_FINAL,Internal"
|
|
newline
|
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bitfld.long 0x10 4.--7. "CAP_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x10 0.--3. "IBIASCAP_HPTOLP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "ANABYPASS_VALUE2,Internal"
|
|
hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.word 0x14 0.--13. 1. "XOSC_HF_IBIASTHERM,Internal"
|
|
rgroup.long 0x388++0x0B
|
|
line.long 0x00 "VOLT_TRIM,Internal"
|
|
bitfld.long 0x00 29.--31. "RESERVED3,Internal" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 24.--28. "VDDR_TRIM_HH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
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bitfld.long 0x00 21.--23. "RESERVED2,Internal" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 16.--20. "VDDR_TRIM_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
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bitfld.long 0x00 13.--15. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 8.--12. "VDDR_TRIM_SLEEP_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x00 5.--7. "RESERVED0,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 0.--4. "TRIMBOD_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "OSC_CONF,OSC Configuration"
|
|
bitfld.long 0x04 30.--31. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 29. "ADC_SH_VBUF_EN,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x04 28. "ADC_SH_MODE_EN,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x04 27. "ATESTLF_RCOSCLF_IBIAS_TRIM,Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM" "0,1"
|
|
newline
|
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bitfld.long 0x04 25.--26. "XOSCLF_REGULATOR_TRIM,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x04 21.--24. "XOSCLF_CMIRRWR_RATIO,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 19.--20. "XOSC_HF_FAST_START,Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 18. "XOSC_OPTION," "0,1"
|
|
newline
|
|
bitfld.long 0x04 17. "HPOSC_OPTION,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "HPOSC_BIAS_HOLD_MODE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12.--15. "HPOSC_CURRMIRR_RATIO,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x04 8.--11. "HPOSC_BIAS_RES_SET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. "HPOSC_FILTER_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5.--6. "HPOSC_BIAS_RECHARGE_DELAY,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 3.--4. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 1.--2. "HPOSC_SERIES_CAP,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0. "HPOSC_DIV3_BYPASS,Internal" "0,1"
|
|
line.long 0x08 "FREQ_OFFSET,Internal"
|
|
hexmask.long.word 0x08 16.--31. 1. "HPOSC_COMP_P0,Internal"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. "HPOSC_COMP_P1,Internal"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "HPOSC_COMP_P2,Internal"
|
|
rgroup.long 0x398++0x03
|
|
line.long 0x00 "MISC_OTP_DATA_1,Internal"
|
|
bitfld.long 0x00 29.--31. "RESERVED,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "PEAK_DET_ITRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "HP_BUF_ITRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "LP_BUF_ITRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DBLR_LOOP_FILTER_RESET_VOLTAGE,Internal" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "HPM_IBIAS_WAIT_CNT,Internal"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "LPM_IBIAS_WAIT_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "IDAC_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x3D0++0x0F
|
|
line.long 0x00 "SHDW_DIE_ID_0,Shadow of DIE_ID_0 register in eFuse"
|
|
line.long 0x04 "SHDW_DIE_ID_1,Shadow of DIE_ID_1 register in eFuse"
|
|
line.long 0x08 "SHDW_DIE_ID_2,Shadow of DIE_ID_2 register in eFuse"
|
|
line.long 0x0C "SHDW_DIE_ID_3,Shadow of DIE_ID_3 register in eFuse"
|
|
rgroup.long 0x3F8++0x07
|
|
line.long 0x00 "SHDW_SCAN_MCU3_SEC,Internal"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SECURITY,Internal"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 11.--22. 1. "ULL_MCU_RAM_0_REP,Internal"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "ULL_MCU_RAM_1_REP_1,Internal"
|
|
line.long 0x04 "SHDW_SCAN_DATA1_CRC,Internal"
|
|
bitfld.long 0x04 31. "FLASH_RDY,Internal" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x04 9.--30. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 1.--8. 1. "CRC,Internal"
|
|
newline
|
|
bitfld.long 0x04 0. "TAP_DAP_LOCK_N,Internal" "0,1"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "DAC_BIAS_CNF,Internal"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "LPM_TRIM_IOUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "LPM_BIAS_WIDTH_TRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "LPM_BIAS_BACKUP_EN,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED1,Internal"
|
|
rgroup.long 0x418++0x17
|
|
line.long 0x00 "TFW_PROBE,Internal"
|
|
line.long 0x04 "TFW_FT,Internal"
|
|
line.long 0x08 "DAC_CAL0,Internal"
|
|
hexmask.long.word 0x08 16.--31. 1. "SOC_DAC_VOUT_CAL_DECOUPLE_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "SOC_DAC_VOUT_CAL_DECOUPLE_C1,Internal"
|
|
line.long 0x0C "DAC_CAL1,Internal"
|
|
hexmask.long.word 0x0C 16.--31. 1. "SOC_DAC_VOUT_CAL_PRECH_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--15. 1. "SOC_DAC_VOUT_CAL_PRECH_C1,Internal"
|
|
line.long 0x10 "DAC_CAL2,Internal"
|
|
hexmask.long.word 0x10 16.--31. 1. "SOC_DAC_VOUT_CAL_ADCREF_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "SOC_DAC_VOUT_CAL_ADCREF_C1,Internal"
|
|
line.long 0x14 "DAC_CAL3,Internal"
|
|
hexmask.long.word 0x14 16.--31. 1. "SOC_DAC_VOUT_CAL_VDDS_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "SOC_DAC_VOUT_CAL_VDDS_C1,Internal"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "RESERVED_N,Software should not rely on the value of a reserved"
|
|
tree.end
|
|
tree "FLASH"
|
|
base ad:0x40030000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "WEPROT_B0_31_0_BY1,Internal"
|
|
line.long 0x04 "WEPROT_AUX_BY1,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x04 5. "WEPROT_B1_ENGR_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "WEPROT_B0_ENGR_BY1,Internal" "0,1"
|
|
bitfld.long 0x04 3. "WEPROT_B1_TRIM_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "WEPROT_B0_TRIM_BY1,Internal" "0,1"
|
|
bitfld.long 0x04 1. "WEPROT_B1_FCFG_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "WEPROT_B0_CCFG_BY1,Internal" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STAT,NW and Efuse Status"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "STALLSTAT,An ocp1 or ocp3 read stall has occurred.0 : No stall or stall acknowledged by writing a" "No stall or stall acknowledged by writing a 1,Stall condition occurred/occurringThis is a.."
|
|
newline
|
|
bitfld.long 0x00 15. "EFUSE_BLANK,Efuse scanning detected if fuse ROM is blank:0 : Not blank1 : Blank" "Not blank,Blank"
|
|
bitfld.long 0x00 14. "EFUSE_TIMEOUT,Efuse scanning resulted in timeout error.0 : No Timeout error1 : Timeout Error" "No Timeout error,Timeout Error"
|
|
newline
|
|
bitfld.long 0x00 13. "SPRS_BYTE_NOT_OK,Efuse scanning resulted in scan chain Sparse byte error.0 : No Sparse error1 : Sparse Error" "No Sparse error,Sparse Error"
|
|
rbitfld.long 0x00 8.--12. "EFUSE_ERRCODE,Same as EFUSEERROR.CODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED7,Software should not rely on the value of a reserved bit" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "BUSY,NW FW_SMSTAT.CMD_IN_PROGRESS bit.This flag is valid immediately after the operation setting it" "Not busy,BusyBit 4 is for the..,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "READY1T,1T access readiness status indicator from NW" "FLASH banks are not ready for 1T accesses,FLASH banks are ready for 1T accesses"
|
|
bitfld.long 0x00 2. "READY2T,2T access readiness status indicator from NW1: FLASH banks are ready for 2T accesses0: FLASH banks are not ready for 2T accesses" "FLASH banks are not ready for 2T accesses,FLASH banks are ready for 2T accesses"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "POWER_MODE,Power state of each of the 2 flash arbiter FSM instances in the flash sub-system" "Active,Ready for Low..,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFG,Internal"
|
|
bitfld.long 0x00 31. "RESERVED31,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x00 30. "DIS_FWTEST,Internal" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 12.--29. 1. "RESERVED12,Internal"
|
|
bitfld.long 0x00 11. "MAIN_STICKY_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CCFG_STICKY_EN,Internal" "0,1"
|
|
bitfld.long 0x00 9. "FCFG_STICKY_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ENGR_TRIM_STICKY_EN,Internal" "0,1"
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "DIS_EFUSECLK,Internal" "0,1"
|
|
bitfld.long 0x00 4. "DIS_READACCESS,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "BP_TRIMCFG_EN,Internal" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FLASH_SIZE,Internal"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED10,Internal"
|
|
bitfld.long 0x00 7.--9. "SECTORS,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "RESERVED0,Internal"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "FWLOCK,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x00 0.--2. "FWLOCK,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FWFLAG,Internal"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x04 0.--2. "FWFLAG,Internal" "0,1,2,3,4,5,6,7"
|
|
repeat 2. (list 3. 2. )(list 0x00 0x04 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "BANK0_TRIM_CFG_$1,Internal"
|
|
repeat.end
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "BANK0_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x00 28.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--27. "REDSWSELW3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "REDSWSELW2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. "REDSWSELW1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "REDSWSELW0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3. "REDSWENW3,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REDSWENW2,Internal" "0,1"
|
|
bitfld.long 0x00 1. "REDSWENW1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "REDSWENW0,Internal" "0,1"
|
|
line.long 0x04 "BANK0_TRIM_CFG_0,Internal"
|
|
repeat 2. (list 3. 2. )(list 0x00 0x04 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "BANK1_TRIM_CFG_$1,Internal"
|
|
repeat.end
|
|
group.long 0x68++0x13
|
|
line.long 0x00 "BANK1_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x00 28.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--27. "REDSWSELW3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "REDSWSELW2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. "REDSWSELW1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "REDSWSELW0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3. "REDSWENW3,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REDSWENW2,Internal" "0,1"
|
|
bitfld.long 0x00 1. "REDSWENW1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "REDSWENW0,Internal" "0,1"
|
|
line.long 0x04 "BANK1_TRIM_CFG_0,Internal"
|
|
line.long 0x08 "PUMP_TRIM_CFG_2,Internal"
|
|
bitfld.long 0x08 26.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--25. "VWLCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 14.--19. "VSLCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 9.--13. "VREADCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 4.--8. "VINLOWCCORCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--3. "VINHICCORCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "PUMP_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x0C 31. "VINHICCORCTLSB,Internal" "0,1"
|
|
bitfld.long 0x0C 25.--30. "VINHCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 20.--24. "VCGCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 15.--19. "IREFVRDCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 10.--14. "IREFTCCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 6.--9. "IREFCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 0.--5. "FOSCCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "PUMP_TRIM_CFG_0,Internal"
|
|
bitfld.long 0x10 30.--31. "RESERVED2,Internal" "0,1,2,3"
|
|
hexmask.long.word 0x10 20.--29. 1. "VHVCT_PV,Internal"
|
|
newline
|
|
hexmask.long.word 0x10 10.--19. 1. "VHVCT_PGM,Internal"
|
|
hexmask.long.word 0x10 0.--9. 1. "VHVCT_ERS,Internal"
|
|
group.long 0x1000++0x4F
|
|
line.long 0x00 "EFUSE,Internal"
|
|
rbitfld.long 0x00 29.--31. "RESERVED29,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "INSTRUCTION,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RESERVED16,Internal"
|
|
hexmask.long.word 0x00 0.--15. 1. "DUMPWORD,Internal"
|
|
line.long 0x04 "EFUSEADDR,Internal"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Internal"
|
|
bitfld.long 0x04 11.--15. "BLOCK,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x04 0.--10. 1. "ROW,Internal"
|
|
line.long 0x08 "DATAUPPER,Internal"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Internal"
|
|
bitfld.long 0x08 3.--7. "SPARE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "P,Internal" "0,1"
|
|
bitfld.long 0x08 1. "R,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "EEN,Internal" "0,1"
|
|
line.long 0x0C "DATALOWER,Internal"
|
|
line.long 0x10 "EFUSECFG,Internal"
|
|
hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x10 8. "IDLEGATING,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 5.--7. "RESERVED5,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 3.--4. "SLAVEPOWER,Internal" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x10 1.--2. "RESERVED1,Internal" "0,1,2,3"
|
|
bitfld.long 0x10 0. "GATING,Internal" "0,1"
|
|
line.long 0x14 "EFUSESTAT,Internal"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x14 0. "RESETDONE,Internal" "0,1"
|
|
line.long 0x18 "ACC,Internal"
|
|
hexmask.long.byte 0x18 24.--31. 1. "RESERVED24,Internal"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "ACCUMULATOR,Internal"
|
|
line.long 0x1C "BOUNDARY,Internal"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "RESERVED24,Internal"
|
|
bitfld.long 0x1C 23. "DISROW0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "SPARE,Internal" "0,1"
|
|
bitfld.long 0x1C 21. "EFC_SELF_TEST_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 20. "EFC_INSTRUCTION_INFO,Internal" "0,1"
|
|
bitfld.long 0x1C 19. "EFC_INSTRUCTION_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 18. "EFC_AUTOLOAD_ERROR,Internal" "0,1"
|
|
bitfld.long 0x1C 14.--17. "OUTPUTENABLE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 13. "SYS_ECC_SELF_TEST_EN,Internal" "0,1"
|
|
bitfld.long 0x1C 12. "SYS_ECC_OVERRIDE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "EFC_FDI,Internal" "0,1"
|
|
bitfld.long 0x1C 10. "SYS_DIEID_AUTOLOAD_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8.--9. "SYS_REPAIR_EN,Internal" "0,1,2,3"
|
|
bitfld.long 0x1C 4.--7. "SYS_WS_READ_STATES,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 0.--3. "INPUTENABLE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "EFUSEFLAG,Internal"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x20 0. "KEY,Internal" "0,1"
|
|
line.long 0x24 "EFUSEKEY,Internal"
|
|
line.long 0x28 "EFUSERELEASE,Internal"
|
|
hexmask.long.byte 0x28 25.--31. 1. "ODPYEAR,Internal"
|
|
bitfld.long 0x28 21.--24. "ODPMONTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x28 16.--20. "ODPDAY,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x28 9.--15. 1. "EFUSEYEAR,Internal"
|
|
newline
|
|
bitfld.long 0x28 5.--8. "EFUSEMONTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 0.--4. "EFUSEDAY,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "EFUSEPINS,Internal"
|
|
hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Internal"
|
|
bitfld.long 0x2C 15. "EFC_SELF_TEST_DONE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 14. "EFC_SELF_TEST_ERROR,Internal" "0,1"
|
|
bitfld.long 0x2C 13. "SYS_ECC_SELF_TEST_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 12. "EFC_INSTRUCTION_INFO,Internal" "0,1"
|
|
bitfld.long 0x2C 11. "EFC_INSTRUCTION_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 10. "EFC_AUTOLOAD_ERROR,Internal" "0,1"
|
|
bitfld.long 0x2C 9. "SYS_ECC_OVERRIDE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "EFC_READY,Internal" "0,1"
|
|
bitfld.long 0x2C 7. "EFC_FCLRZ,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 6. "SYS_DIEID_AUTOLOAD_EN,Internal" "0,1"
|
|
bitfld.long 0x2C 4.--5. "SYS_REPAIR_EN,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 0.--3. "SYS_WS_READ_STATES,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "EFUSECRA,Internal"
|
|
hexmask.long 0x30 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x30 0.--5. "DATA,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x34 "EFUSEREAD,Internal"
|
|
hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED10,Internal"
|
|
bitfld.long 0x34 8.--9. "DATABIT,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x34 4.--7. "READCLOCK,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 3. "DEBUG,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "SPARE,Internal" "0,1"
|
|
bitfld.long 0x34 0.--1. "MARGIN,Internal" "0,1,2,3"
|
|
line.long 0x38 "EFUSEPROGRAM,Internal"
|
|
rbitfld.long 0x38 31. "RESERVED31,Internal" "0,1"
|
|
bitfld.long 0x38 30. "COMPAREDISABLE,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x38 14.--29. 1. "CLOCKSTALL,Internal"
|
|
bitfld.long 0x38 13. "VPPTOVDD,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x38 9.--12. "ITERATIONS,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x38 0.--8. 1. "WRITECLOCK,Internal"
|
|
line.long 0x3C "EFUSEERROR,Internal"
|
|
hexmask.long 0x3C 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x3C 5. "DONE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 0.--4. "CODE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x40 "SINGLEBIT,Internal"
|
|
hexmask.long 0x40 1.--31. 1. "FROMN,Internal"
|
|
bitfld.long 0x40 0. "FROM0,Internal" "0,1"
|
|
line.long 0x44 "TWOBIT,Internal"
|
|
hexmask.long 0x44 1.--31. 1. "FROMN,Internal"
|
|
bitfld.long 0x44 0. "FROM0,Internal" "0,1"
|
|
line.long 0x48 "SELFTESTCYC,Internal"
|
|
line.long 0x4C "SELFTESTSIGN,Internal"
|
|
tree.end
|
|
tree "GPIO"
|
|
base ad:0x40022000
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "DOUT3_0,Data Out 0 to 3Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 24. "DIO3,Sets the state of the pin that is configured as DIO#3 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "DIO2,Sets the state of the pin that is configured as DIO#2 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "DIO1,Sets the state of the pin that is configured as DIO#1 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "DIO0,Sets the state of the pin that is configured as DIO#0 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x04 "DOUT7_4,Data Out 4 to 7Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x04 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 24. "DIO7,Sets the state of the pin that is configured as DIO#7 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 16. "DIO6,Sets the state of the pin that is configured as DIO#6 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "DIO5,Sets the state of the pin that is configured as DIO#5 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "DIO4,Sets the state of the pin that is configured as DIO#4 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x08 "DOUT11_8,Data Out 8 to 11Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 24. "DIO11,Sets the state of the pin that is configured as DIO#11 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 16. "DIO10,Sets the state of the pin that is configured as DIO#10 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 8. "DIO9,Sets the state of the pin that is configured as DIO#9 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "DIO8,Sets the state of the pin that is configured as DIO#8 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x0C "DOUT15_12,Data Out 12 to 15Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x0C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 24. "DIO15,Sets the state of the pin that is configured as DIO#15 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 16. "DIO14,Sets the state of the pin that is configured as DIO#14 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 8. "DIO13,Sets the state of the pin that is configured as DIO#13 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "DIO12,Sets the state of the pin that is configured as DIO#12 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x10 "DOUT19_16,Data Out 16 to 19Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x10 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 24. "DIO19,Sets the state of the pin that is configured as DIO#19 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 16. "DIO18,Sets the state of the pin that is configured as DIO#18 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 8. "DIO17,Sets the state of the pin that is configured as DIO#17 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "DIO16,Sets the state of the pin that is configured as DIO#16 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x14 "DOUT23_20,Data Out 20 to 23Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x14 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 24. "DIO23,Sets the state of the pin that is configured as DIO#23 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 16. "DIO22,Sets the state of the pin that is configured as DIO#22 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 8. "DIO21,Sets the state of the pin that is configured as DIO#21 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "DIO20,Sets the state of the pin that is configured as DIO#20 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x18 "DOUT27_24,Data Out 24 to 27Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x18 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 24. "DIO27,Sets the state of the pin that is configured as DIO#27 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 16. "DIO26,Sets the state of the pin that is configured as DIO#26 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 8. "DIO25,Sets the state of the pin that is configured as DIO#25 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "DIO24,Sets the state of the pin that is configured as DIO#24 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x1C "DOUT31_28,Data Out 28 to 31Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x1C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 24. "DIO31,Sets the state of the pin that is configured as DIO#31 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 16. "DIO30,Sets the state of the pin that is configured as DIO#30 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 8. "DIO29,Sets the state of the pin that is configured as DIO#29 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "DIO28,Sets the state of the pin that is configured as DIO#28 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x20 "DOUT35_32,Data Out 35 to 32Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x20 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 24. "DIO35,Sets the state of the pin that is configured as DIO#35 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 16. "DIO34,Sets the state of the pin that is configured as DIO#34 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 8. "DIO33,Sets the state of the pin that is configured as DIO#33 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "DIO32,Sets the state of the pin that is configured as DIO#32 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x24 "DOUT39_36,Data Out 39 to 36Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x24 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 24. "DIO39,Sets the state of the pin that is configured as DIO#39 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 16. "DIO38,Sets the state of the pin that is configured as DIO#38 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 8. "DIO37,Sets the state of the pin that is configured as DIO#37 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0. "DIO36,Sets the state of the pin that is configured as DIO#36 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x28 "DOUT43_40,Data Out 43 to 40Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x28 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 24. "DIO43,Sets the state of the pin that is configured as DIO#43 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 16. "DIO42,Sets the state of the pin that is configured as DIO#42 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 8. "DIO41,Sets the state of the pin that is configured as DIO#41 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "DIO40,Sets the state of the pin that is configured as DIO#40 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x2C "DOUT47_44,Data Out 47 to 44Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x2C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 24. "DIO47,Sets the state of the pin that is configured as DIO#47 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 16. "DIO46,Sets the state of the pin that is configured as DIO#46 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 8. "DIO45,Sets the state of the pin that is configured as DIO#45 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "DIO44,Sets the state of the pin that is configured as DIO#44 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "DOUT31_0,Data Output for DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data output for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data output for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data output for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data output for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data output for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data output for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data output for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data output for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data output for DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data output for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data output for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data output for DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data output for DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data output for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data output for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data output for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data output for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data output for DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data output for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data output for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data output for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data output for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data output for DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data output for DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data output for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data output for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Data output for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Data output for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data output for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data output for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data output for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data output for DIO 0" "0,1"
|
|
line.long 0x04 "DOUT47_32,Data Output for DIO 0 to 31"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data output for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data output for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data output for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data output for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data output for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data output for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data output for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data output for DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Data output for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data output for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data output for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data output for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data output for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data output for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data output for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data output for DIO 32" "0,1"
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "DOUTSET31_0,Data Out SetWriting 1 to a bit position sets the corresponding bit in the DOUT47_0 register"
|
|
bitfld.long 0x00 31. "DIO31,Set bit 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Set bit 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Set bit 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Set bit 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Set bit 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Set bit 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Set bit 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Set bit 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Set bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Set bit 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Set bit 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Set bit 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Set bit 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Set bit 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Set bit 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Set bit 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Set bit 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Set bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Set bit 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Set bit 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Set bit 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Set bit 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Set bit 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Set bit 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Set bit 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Set bit 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Set bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Set bit 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Set bit 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Set bit 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Set bit 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Set bit 0" "0,1"
|
|
line.long 0x04 "DOUTSET47_32,Data Out SetWriting 1 to a bit position sets the corresponding bit in the DOUT47_0 register"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Set bit 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Set bit 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Set bit 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Set bit 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Set bit 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Set bit 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Set bit 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Set bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Set bit 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Set bit 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Set bit 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Set bit 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Set bit 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Set bit 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Set bit 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Set bit 32" "0,1"
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "DOUTCLR31_0,Data Out ClearWriting 1 to a bit position clears the corresponding bit in the DOUT47_0 register"
|
|
bitfld.long 0x00 31. "DIO31,Clears bit 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Clears bit 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Clears bit 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Clears bit 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Clears bit 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Clears bit 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Clears bit 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Clears bit 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Clears bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Clears bit 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Clears bit 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Clears bit 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Clears bit 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Clears bit 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Clears bit 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Clears bit 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Clears bit 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Clears bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Clears bit 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Clears bit 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Clears bit 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Clears bit 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Clears bit 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Clears bit 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Clears bit 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Clears bit 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Clears bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Clears bit 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Clears bit 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Clears bit 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Clears bit 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Clears bit 0" "0,1"
|
|
line.long 0x04 "DOUTCLR47_32,Data Out ClearWriting 1 to a bit position clears the corresponding bit in the DOUT47_0 register"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Clears bit 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Clears bit 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Clears bit 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Clears bit 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Clears bit 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Clears bit 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Clears bit 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Clears bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Clears bit 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Clears bit 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Clears bit 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Clears bit 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Clears bit 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Clears bit 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Clears bit 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Clears bit 32" "0,1"
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "DOUTTGL31_0,Data Out ToggleWriting 1 to a bit position will invert the corresponding DIO output"
|
|
bitfld.long 0x00 31. "DIO31,Toggles bit 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Toggles bit 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Toggles bit 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Toggles bit 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Toggles bit 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Toggles bit 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Toggles bit 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Toggles bit 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Toggles bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Toggles bit 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Toggles bit 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Toggles bit 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Toggles bit 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Toggles bit 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Toggles bit 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Toggles bit 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Toggles bit 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Toggles bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Toggles bit 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Toggles bit 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Toggles bit 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Toggles bit 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Toggles bit 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Toggles bit 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Toggles bit 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Toggles bit 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Toggles bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Toggles bit 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Toggles bit 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Toggles bit 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Toggles bit 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Toggles bit 0" "0,1"
|
|
line.long 0x04 "DOUTTGL47_32,Data Out ToggleWriting 1 to a bit position will invert the corresponding DIO output"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Toggles bit 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Toggles bit 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Toggles bit 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Toggles bit 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Toggles bit 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Toggles bit 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Toggles bit 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Toggles bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Toggles bit 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Toggles bit 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Toggles bit 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Toggles bit 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Toggles bit 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Toggles bit 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Toggles bit 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Toggles bit 32" "0,1"
|
|
rgroup.long 0xC0++0x07
|
|
line.long 0x00 "DIN31_0,Data Input from DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data input from DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data input from DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data input from DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data input from DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data input from DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data input from DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data input from DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data input from DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data input from DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data input from DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data input from DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data input from DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data input from DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data input from DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data input from DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data input from DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data input from DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data input from DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data input from DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data input from DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data input from DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data input from DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data input from DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data input from DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data input from DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data input from DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Data input from DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Data input from DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data input from DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data input from DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data input from DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data input from DIO 0" "0,1"
|
|
line.long 0x04 "DIN47_32,Data Input from DIO 32 to 47"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data input from DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data input from DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data input from DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data input from DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data input from DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data input from DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data input from DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data input from DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Data input from DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data input from DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data input from DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data input from DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data input from DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data input from DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data input from DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data input from DIO 32" "0,1"
|
|
group.long 0xD0++0x07
|
|
line.long 0x00 "DOE31_0,Data Output Enable for DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data output enable for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data output enable for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data output enable for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data output enable for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data output enable for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data output enable for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data output enable for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data output enable for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data output enable for DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data output enable for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data output enable for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data output enable for DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data output enable for DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data output enable for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data output enable for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data output enable for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data output enable for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data output enable for DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data output enable for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data output enable for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data output enable for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data output enable for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data output enable for DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data output enable for DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data output enable for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data output enable for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Data output enable for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Data output enable for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data output enable for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data output enable for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data output enable for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data output enable for DIO 0" "0,1"
|
|
line.long 0x04 "DOE47_32,Data Output Enable for DIO 32 to 47"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data output enable for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data output enable for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data output enable for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data output enable for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data output enable for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data output enable for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data output enable for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data output enable for DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Data output enable for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data output enable for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data output enable for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data output enable for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data output enable for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data output enable for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data output enable for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data output enable for DIO 32" "0,1"
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "EVFLAGS31_0,Event Register for DIO 0 to 31Reading this registers will return 1 for triggered event and 0 for non-triggered events"
|
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bitfld.long 0x00 31. "DIO31,Event for DIO 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Event for DIO 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Event for DIO 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Event for DIO 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Event for DIO 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Event for DIO 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Event for DIO 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Event for DIO 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Event for DIO 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Event for DIO 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Event for DIO 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Event for DIO 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Event for DIO 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Event for DIO 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Event for DIO 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Event for DIO 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Event for DIO 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Event for DIO 14" "0,1"
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newline
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bitfld.long 0x00 13. "DIO13,Event for DIO 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Event for DIO 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Event for DIO 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Event for DIO 10" "0,1"
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bitfld.long 0x00 9. "DIO9,Event for DIO 9" "0,1"
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bitfld.long 0x00 8. "DIO8,Event for DIO 8" "0,1"
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bitfld.long 0x00 7. "DIO7,Event for DIO 7" "0,1"
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bitfld.long 0x00 6. "DIO6,Event for DIO 6" "0,1"
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bitfld.long 0x00 5. "DIO5,Event for DIO 5" "0,1"
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newline
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bitfld.long 0x00 4. "DIO4,Event for DIO 4" "0,1"
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bitfld.long 0x00 3. "DIO3,Event for DIO 3" "0,1"
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bitfld.long 0x00 2. "DIO2,Event for DIO 2" "0,1"
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bitfld.long 0x00 1. "DIO1,Event for DIO 1" "0,1"
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bitfld.long 0x00 0. "DIO0,Event for DIO 0" "0,1"
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line.long 0x04 "EVFLAGS47_32,Event Register for DIO 32 to 47Reading this registers will return 1 for triggered event and 0 for non-triggered events"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "DIO47,Event for DIO 47" "0,1"
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bitfld.long 0x04 14. "DIO46,Event for DIO 46" "0,1"
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bitfld.long 0x04 13. "DIO45,Event for DIO 45" "0,1"
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bitfld.long 0x04 12. "DIO44,Event for DIO 44" "0,1"
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bitfld.long 0x04 11. "DIO43,Event for DIO 43" "0,1"
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bitfld.long 0x04 10. "DIO42,Event for DIO 42" "0,1"
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bitfld.long 0x04 9. "DIO41,Event for DIO 41" "0,1"
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bitfld.long 0x04 8. "DIO40,Event for DIO 40" "0,1"
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newline
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bitfld.long 0x04 7. "DIO39,Event for DIO 39" "0,1"
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bitfld.long 0x04 6. "DIO38,Event for DIO 38" "0,1"
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bitfld.long 0x04 5. "DIO37,Event for DIO 37" "0,1"
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bitfld.long 0x04 4. "DIO36,Event for DIO 36" "0,1"
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bitfld.long 0x04 3. "DIO35,Event for DIO 35" "0,1"
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bitfld.long 0x04 2. "DIO34,Event for DIO 34" "0,1"
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bitfld.long 0x04 1. "DIO33,Event for DIO 33" "0,1"
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bitfld.long 0x04 0. "DIO32,Event for DIO 32" "0,1"
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tree.end
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tree "GPT"
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repeat 4. (list 0. 1. 2. 3. )(list ad:0x40010000 ad:0x40011000 ad:0x40012000 ad:0x40013000 )
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tree "GPT$1"
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base $2
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group.long 0x00++0x13
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line.long 0x00 "CFG,Configuration"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--2. "CFG,GPT Configuration0x2" "32-bit timer configuration,?,?,?,16-bit timer configuration. Configure for two..,?,?,?"
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line.long 0x04 "TAMR,Timer A Mode"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 13.--15. "TCACT,Timer Compare Action Select " "Disable compare operations,Toggle State on Time-Out,Clear CCP output pin on Time-Out,Set CCP output pin on Time-Out ,Set CCP output pin immediately and toggle on..,Clear CCP output pin immediately and toggle on..,Set CCP output pin immediately and clear on..,Clear CCP output pin immediately and set on.."
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newline
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bitfld.long 0x04 12. "TACINTD,One-Shot/Periodic Interrupt Disable" "Time-out interrupt function as normal,Time-out interrupt are disabled"
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newline
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bitfld.long 0x04 11. "TAPLO,GPTM Timer A PWM Legacy Operation0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0.1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0.This bit is only valid in.." "Legacy operation,CCP output pin is set to 1 on time-out"
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newline
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bitfld.long 0x04 10. "TAMRSU,Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated.If the timer is disabled (CTL.TAEN = 0) when this bit is set TAMATCHR and TAPR are updated when the timer is enabled.If the timer is stalled.." "Update TAMATCHR and TAPR if used on the next..,Update TAMATCHR and TAPR if used on the next.."
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newline
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bitfld.long 0x04 9. "TAPWMIE,GPTM Timer A PWM Interrupt EnableThis bit enables interrupts in PWM mode on rising falling or both edges of the CCP output as defined by the CTL.TAEVENTIn addition when this bit is set and a capture event occurs Timer Aautomatically generates.." "Interrupt is disabled. ,Interrupt is enabled. This bit is only valid in.."
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newline
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bitfld.long 0x04 8. "TAILD,GPT Timer A PWM Interval Load" "Update the TAR register with the value in the..,Update the TAR register with the value in the.."
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newline
|
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bitfld.long 0x04 7. "TASNAPS,GPT Timer A Snap-Shot Mode" "Snap-shot mode is disabled. ,If Timer A is configured in the periodic mode .."
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newline
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bitfld.long 0x04 6. "TAWOT,GPT Timer A Wait-On-Trigger" "Timer A begins counting as soon as it is enabled.,If Timer A is enabled (CTL.TAEN = 1) Timer A.."
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newline
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bitfld.long 0x04 5. "TAMIE,GPT Timer A Match Interrupt Enable" "The match interrupt is disabled for match..,An interrupt is generated when the match value.."
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newline
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bitfld.long 0x04 4. "TACDIR,GPT Timer A Count Direction" "The timer counts down. ,The timer counts up. When counting up the timer.."
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newline
|
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bitfld.long 0x04 3. "TAAMS,GPT Timer A Alternate Mode Note: To enable PWM mode you must also clear TACM and then configure TAMR field to 0x2" "Capture/Compare mode is enabled.,PWM mode is enabled"
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newline
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bitfld.long 0x04 2. "TACM,GPT Timer A Capture Mode" "Edge-Count mode,Edge-Time mode"
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newline
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bitfld.long 0x04 0.--1. "TAMR,GPT Timer A Mode0x0 Reserved0x1 One-Shot Timer mode0x2 Periodic Timer mode0x3 Capture modeThe Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register" "?,One-Shot Timer mode,Periodic Timer mode ,Capture mode"
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line.long 0x08 "TBMR,Timer B Mode"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 13.--15. "TCACT,Timer Compare Action Select" "Disable compare operations,Toggle State on Time-Out,Clear CCP output pin on Time-Out,Set CCP output pin on Time-Out ,Set CCP output pin immediately and toggle on..,Clear CCP output pin immediately and toggle on..,Set CCP output pin immediately and clear on..,Clear CCP output pin immediately and set on.."
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newline
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bitfld.long 0x08 12. "TBCINTD,One-Shot/Periodic Interrupt Mode" "Normal Time-Out Interrupt ,Mask Time-Out Interrupt"
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newline
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bitfld.long 0x08 11. "TBPLO,GPTM Timer B PWM Legacy Operation0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0.1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0.This bit is only valid in.." "Legacy operation,CCP output pin is set to 1 on time-out"
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newline
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bitfld.long 0x08 10. "TBMRSU,Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updatedIf the timer is disabled (CTL.TBEN is clear) when this bit is set TBMATCHR and TBPR are updated when the timer is enabled.If the timer is stalled.." "Update TBMATCHR and TBPR if used on the next..,Update TBMATCHR and TBPR if used on the next.."
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newline
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bitfld.long 0x08 9. "TBPWMIE,GPTM Timer B PWM Interrupt EnableThis bit enables interrupts in PWM mode on rising falling or both edges of the CCP output as defined by the CTL.TBEVENTIn addition when this bit is set and a capture event occurs Timer Aautomatically generates.." "Interrupt is disabled. ,Interrupt is enabled. This bit is only valid in.."
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newline
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bitfld.long 0x08 8. "TBILD,GPT Timer B PWM Interval Load" "Update the TBR register with the value in the..,Update the TBR register with the value in the.."
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newline
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bitfld.long 0x08 7. "TBSNAPS,GPT Timer B Snap-Shot Mode" "Snap-shot mode is disabled. ,If Timer B is configured in the periodic mode"
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newline
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bitfld.long 0x08 6. "TBWOT,GPT Timer B Wait-On-Trigger" "Timer B begins counting as soon as it is enabled. ,If Timer B is enabled (CTL.TBEN is set) Timer B.."
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newline
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bitfld.long 0x08 5. "TBMIE,GPT Timer B Match Interrupt Enable" "The match interrupt is disabled for match..,An interrupt is generated when the match value.."
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newline
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bitfld.long 0x08 4. "TBCDIR,GPT Timer B Count Direction" "The timer counts down. ,The timer counts up. When counting up the timer.."
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newline
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bitfld.long 0x08 3. "TBAMS,GPT Timer B Alternate Mode Note: To enable PWM mode you must also clear TBCM bit and configure TBMR field to 0x2" "Capture/Compare mode is enabled.,PWM mode is enabled"
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newline
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bitfld.long 0x08 2. "TBCM,GPT Timer B Capture Mode" "Edge-Count mode,Edge-Time mode"
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newline
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bitfld.long 0x08 0.--1. "TBMR,GPT Timer B Mode0x0 Reserved0x1 One-Shot Timer mode0x2 Periodic Timer mode0x3 Capture modeThe Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register" "?,One-Shot Timer mode,Periodic Timer mode ,Capture mode"
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line.long 0x0C "CTL,Control"
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hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 14. "TBPWML,GPT Timer B PWM Output Level0: Output is unaffected" "Output is unaffected,Output is inverted"
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newline
|
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bitfld.long 0x0C 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
|
|
bitfld.long 0x0C 10.--11. "TBEVENT,GPT Timer B Event ModeThe values in this register are defined as follows:Value Description0x0 Positive edge0x1 Negative edge0x2 Reserved0x3 Both edgesNote: If PWM output inversion is enabled edge detection interruptbehavior is reversed" "Positive edge,Negative edge ,?,Both edges"
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newline
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bitfld.long 0x0C 9. "TBSTALL,GPT Timer B Stall Enable" "Timer B continues counting while the processor..,Timer B freezes counting while the processor is.."
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newline
|
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bitfld.long 0x0C 8. "TBEN,GPT Timer B Enable" "Timer B is disabled. ,Timer B is enabled and begins counting or the.."
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newline
|
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rbitfld.long 0x0C 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
|
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bitfld.long 0x0C 6. "TAPWML,GPT Timer A PWM Output Level" "Not inverted,Inverted"
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|
newline
|
|
bitfld.long 0x0C 4.--5. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0C 2.--3. "TAEVENT,GPT Timer A Event ModeThe values in this register are defined as follows:Value Description0x0 Positive edge0x1 Negative edge0x2 Reserved0x3 Both edgesNote: If PWM output inversion is enabled edge detection interruptbehavior is reversed" "Positive edge,Negative edge ,?,Both edges"
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newline
|
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bitfld.long 0x0C 1. "TASTALL,GPT Timer A Stall Enable" "Timer A continues counting while the processor..,Timer A freezes counting while the processor is.."
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|
newline
|
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bitfld.long 0x0C 0. "TAEN,GPT Timer A Enable" "Timer A is disabled. ,Timer A is enabled and begins counting or the.."
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|
line.long 0x10 "SYNC,Synch Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "SYNC3,Synchronize GPT Timer 3" "No Sync. GPT3 is not affected. ,A timeout event for Timer A of GPT3 is triggered,A timeout event for Timer B of GPT3 is triggered,A timeout event for both Timer A and Timer B of.."
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newline
|
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bitfld.long 0x10 4.--5. "SYNC2,Synchronize GPT Timer 2" "No Sync. GPT2 is not affected. ,A timeout event for Timer A of GPT2 is triggered,A timeout event for Timer B of GPT2 is triggered,A timeout event for both Timer A and Timer B of.."
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newline
|
|
bitfld.long 0x10 2.--3. "SYNC1,Synchronize GPT Timer 1" "No Sync. GPT1 is not affected. ,A timeout event for Timer A of GPT1 is triggered,A timeout event for Timer B of GPT1 is triggered,A timeout event for both Timer A and Timer B of.."
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newline
|
|
bitfld.long 0x10 0.--1. "SYNC0,Synchronize GPT Timer 0" "No Sync. GPT0 is not affected. ,A timeout event for Timer A of GPT0 is triggered,A timeout event for Timer B of GPT0 is triggered,A timeout event for both Timer A and Timer B of.."
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group.long 0x18++0x3F
|
|
line.long 0x00 "IMR,Interrupt MaskThis register is used to enable the interrupts.Associated registers:RIS. MIS. ICLR"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 13. "DMABIM,Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
|
rbitfld.long 0x00 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "TBMIM,Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
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bitfld.long 0x00 10. "CBEIM,Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
|
bitfld.long 0x00 9. "CBMIM,Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS" "Disable Interrupt,Enable Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8. "TBTOIM,Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "DMAAIM,Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
|
bitfld.long 0x00 4. "TAMIM,Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
|
bitfld.long 0x00 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
|
bitfld.long 0x00 2. "CAEIM,Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
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bitfld.long 0x00 1. "CAMIM,Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS" "Disable Interrupt,Enable Interrupt"
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|
newline
|
|
bitfld.long 0x00 0. "TATOIM,Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS" "Disable Interrupt,Enable Interrupt"
|
|
line.long 0x04 "RIS,Raw Interrupt StatusAssociated registers:IMR. MIS. ICLR"
|
|
hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 13. "DMABRIS,GPT Timer B DMA Done Raw Interrupt Status0: Transfer has not completed1: Transfer has completed" "Transfer has not completed,Transfer has completed"
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|
newline
|
|
bitfld.long 0x04 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x04 11. "TBMRIS,GPT Timer B Match Raw Interrupt0: The match value has not been reached1: The match value is reached.TBMR.TBMIE is set and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode" "The match value has not been reached,The match value is reached.TBMR.TBMIE is set and.."
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|
newline
|
|
bitfld.long 0x04 10. "CBERIS,GPT Timer B Capture Mode Event Raw Interrupt0: The event has not occured.1: The event has occured.This interrupt asserts when the subtimer is configured in Input Edge-Time mode" "The event has not occured,The event has occured.This interrupt asserts.."
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|
newline
|
|
bitfld.long 0x04 9. "CBMRIS,GPT Timer B Capture Mode Match Raw Interrupt0: The capture mode match for Timer B has not occurred.1: A capture mode match has occurred for Timer B" "The capture mode match for Timer B has not..,A capture mode match has occurred for Timer B"
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|
newline
|
|
bitfld.long 0x04 8. "TBTORIS,GPT Timer B Time-out Raw Interrupt0: Timer B has not timed out1: Timer B has timed out" "Timer B has not timed out,Timer B has timed out"
|
|
newline
|
|
bitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 5. "DMAARIS,GPT Timer A DMA Done Raw Interrupt Status0: Transfer has not completed1: Transfer has completed" "Transfer has not completed,Transfer has completed"
|
|
newline
|
|
bitfld.long 0x04 4. "TAMRIS,GPT Timer A Match Raw Interrupt0: The match value has not been reached1: The match value is reached.TAMR.TAMIE is set and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode" "The match value has not been reached,The match value is reached.TAMR.TAMIE is set and.."
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|
newline
|
|
bitfld.long 0x04 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "CAERIS,GPT Timer A Capture Mode Event Raw Interrupt0: The event has not occured.1: The event has occured.This interrupt asserts when the subtimer is configured in Input Edge-Time mode" "The event has not occured,The event has occured.This interrupt asserts.."
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|
newline
|
|
bitfld.long 0x04 1. "CAMRIS,GPT Timer A Capture Mode Match Raw Interrupt0: The capture mode match for Timer A has not occurred.1: A capture mode match has occurred for Timer A" "The capture mode match for Timer A has not..,A capture mode match has occurred for Timer A"
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newline
|
|
bitfld.long 0x04 0. "TATORIS,GPT Timer A Time-out Raw Interrupt0: Timer A has not timed out1: Timer A has timed out" "Timer A has not timed out,Timer A has timed out"
|
|
line.long 0x08 "MIS,Masked Interrupt StatusValues are result of bitwise AND operation between RIS and IMRAssosciated clear register: ICLR"
|
|
hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 13. "DMABMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x08 11. "TBMMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. "CBEMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. "CBMMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "TBTOMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 5. "DMAAMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "TAMMIS," "0,1"
|
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newline
|
|
bitfld.long 0x08 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "CAEMIS," "0,1"
|
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newline
|
|
bitfld.long 0x08 1. "CAMMIS," "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "TATOMIS," "0,1"
|
|
line.long 0x0C "ICLR,Interrupt ClearThis register is used to clear status bits in the RIS and MIS registers"
|
|
hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 13. "DMABINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 11. "TBMCINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 10. "CBECINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "CBMCINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "TBTOCINT," "0,1"
|
|
newline
|
|
rbitfld.long 0x0C 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 5. "DMAAINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "TAMCINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "CAECINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "CAMCINT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "TATOCINT," "0,1"
|
|
line.long 0x10 "TAILR,Timer A Interval Load Register"
|
|
line.long 0x14 "TBILR,Timer B Interval Load Register"
|
|
line.long 0x18 "TAMATCHR,Timer A Match RegisterInterrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode.In Edge-Count mode. this register along with TAILR. determines how many edge events are counted.The total.."
|
|
line.long 0x1C "TBMATCHR,Timer B Match Register When a GPT is configured to one of the 32-bit modes. the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR.Reads from this register return the current match value of Timer B and writes.."
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "TBMATCHR,GPT Timer B Match Register"
|
|
line.long 0x20 "TAPR,Timer A Pre-scaleThis register allows software to extend the range of the timers when they are used individually.When in one-shot or periodic down count modes. this register acts as a true prescaler for the timer counter.When acting as a true.."
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
abitfld.long 0x20 0.--7. "TAPSR,Timer A Pre-scale.Prescaler ratio in one-shot and periodic count mode is TAPSR + 1 that is:0: Prescaler ratio =" "0x00=Prescaler ratio = 1,0x01=Prescaler ratio = 2,0x02=Prescaler ratio = 3,0xFF=Prescaler ratio = 256"
|
|
line.long 0x24 "TBPR,Timer B Pre-scaleThis register allows software to extend the range of the timers when they are used individually.When in one-shot or periodic down count modes. this register acts as a true prescaler for the timer counter.When acting as a true.."
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
abitfld.long 0x24 0.--7. "TBPSR,Timer B Pre-scale.Prescale ratio in one-shot and periodic count mode is TBPSR + 1 that is:0: Prescaler ratio =" "0x00=Prescaler ratio = 1,0x01=Prescaler ratio = 2,0x02=Prescaler ratio = 3,0xFF=Prescaler ratio = 256"
|
|
line.long 0x28 "TAPMR,Timer A Pre-scale MatchThis register allows software to extend the range of the TAMATCHR when used individually"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "TAPSMR,GPT Timer A Pre-scale Match"
|
|
line.long 0x2C "TBPMR,Timer B Pre-scale MatchThis register allows software to extend the range of the TBMATCHR when used individually"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "TBPSMR,GPT Timer B Pre-scale Match Register"
|
|
line.long 0x30 "TAR,Timer A RegisterThis register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes"
|
|
line.long 0x34 "TBR,Timer B RegisterThis register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes"
|
|
line.long 0x38 "TAV,Timer A Value When read. this register shows the current. free-running value of Timer A in all modes"
|
|
line.long 0x3C "TBV,Timer B Value When read. this register shows the current. free-running value of Timer B in all modes"
|
|
rgroup.long 0x5C++0x13
|
|
line.long 0x00 "TAPS,Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD. this register is updated with the value from TAPR register either on the next cycle or on the next timeout.This register shows the current value of the Timer A.."
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|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSS,GPT Timer A Pre-scaler"
|
|
line.long 0x04 "TBPS,Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD. this register is updated with the value from TBPR register either on the next cycle or on the next timeout.This register shows the current value of the Timer B.."
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "PSS,GPT Timer B Pre-scaler"
|
|
line.long 0x08 "TAPV,Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "PSV,GPT Timer A Pre-scaler Value"
|
|
line.long 0x0C "TBPV,Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PSV,GPT Timer B Pre-scaler Value"
|
|
line.long 0x10 "DMAEV,DMA Event This register allows software to enable/disable GPT DMA trigger events"
|
|
hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved field"
|
|
newline
|
|
bitfld.long 0x10 11. "TBMDMAEN,GPT Timer B Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CBEDMAEN,GPT Timer B Capture Event DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CBMDMAEN,GPT Timer B Capture Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "TBTODMAEN,GPT Timer B Time-Out DMA Trigger Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 5.--7. "RESERVED5,Software should not rely on the value of a reserved field" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 4. "TAMDMAEN,GPT Timer A Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "CAEDMAEN,GPT Timer A Capture Event DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CAMDMAEN,GPT Timer A Capture Match DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "TATODMAEN,GPT Timer A Time-Out DMA Trigger Enable" "0,1"
|
|
rgroup.long 0xFB0++0x07
|
|
line.long 0x00 "VERSION,Peripheral VersionThis register provides information regarding the GPT version"
|
|
line.long 0x04 "ANDCCP,Combined CCP OutputThis register is used to logically AND CCP output pairs for each timer"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 1. "LD_TO_EN,PWM assertion would happen at timeout0: PWM assertion happens when counter matches load value1: PWM assertion happens at timeout of the counter" "PWM assertion happens when counter matches load..,PWM assertion happens at timeout of the counter"
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|
newline
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bitfld.long 0x04 0. "CCP_AND_EN,Enables AND operation of the CCP outputs for timers A and B.0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers.1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals.." "PWM outputs of Timer A and Timer B are the..,PWM output of Timer A is ANDed version of Timer.."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "Hidden"
|
|
base ad:0x00
|
|
rgroup.quad 0x00++0x07
|
|
line.quad 0x00 "JSTATE4,Digital JTAG State Register"
|
|
bitfld.quad 0x00 62. "MODACT10,CLK.I2C0" "0,1"
|
|
bitfld.quad 0x00 61. "MODACT11,CLK.I2S0" "0,1"
|
|
bitfld.quad 0x00 60. "MODACT12,CLK.DMA" "0,1"
|
|
bitfld.quad 0x00 59. "MODACT13,CLK.TRNG" "0,1"
|
|
bitfld.quad 0x00 58. "MODACT14,CLK.SEC" "0,1"
|
|
bitfld.quad 0x00 57. "MODACT15,CLK.PKA" "0,1"
|
|
bitfld.quad 0x00 56. "MODACT16,CLK.SSI0" "0,1"
|
|
bitfld.quad 0x00 55. "MODACT17,CLK.SSI1" "0,1"
|
|
bitfld.quad 0x00 54. "MODACT18,CLK.UART0" "0,1"
|
|
bitfld.quad 0x00 53. "MODACT19,CLK.UART1" "0,1"
|
|
newline
|
|
bitfld.quad 0x00 51.--52. "PWRSTATE0,CPU%CORTEXM_PM" "0,1,2,3"
|
|
bitfld.quad 0x00 49. "MODACT5,MCU.CPU_PD" "0,1"
|
|
bitfld.quad 0x00 48. "MODACT4,MCU.SERIAL_PD" "0,1"
|
|
bitfld.quad 0x00 47. "MODACT3,MCU.PERIPH_PD" "0,1"
|
|
bitfld.quad 0x00 46. "MODACT2,MCU.RFCORE_PD" "0,1"
|
|
bitfld.quad 0x00 45. "MODACT1,MCU.VIMS_PD" "0,1"
|
|
bitfld.quad 0x00 44. "MODACT0,MCU.MCU_CTL" "0,1"
|
|
bitfld.quad 0x00 43. "MODACT9,CLK.XOSC_EN" "0,1"
|
|
bitfld.quad 0x00 42. "MODACT8,CLK.SCLK_HF_SRC" "0,1"
|
|
bitfld.quad 0x00 36.--39. "PWRSTATE1,RF%LPRF_PM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 28.--35. 1. "MODACT7,PRCM:PWRPROFSTAT"
|
|
bitfld.quad 0x00 27. "MODACT20,PC_Error" "0,1"
|
|
hexmask.quad.tbyte 0x00 6.--26. 1. "PC,PC"
|
|
bitfld.quad 0x00 0.--5. "MODACT6,Interrupts%HWI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
tree.end
|
|
tree "I2C0"
|
|
base ad:0x40002000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SOAR,Slave Own AddressThis register consists of seven address bits that identify this I2C device on the I2C bus"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--6. 1. "OAR,I2C slave own addressThis field specifies bits a6 through a0 of the slave address"
|
|
line.long 0x04 "SSTAT,Slave Status Note: This register shares address with SCTL. meaning that this register functions as a control register when written. and a status register when"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 2. "FBR,First byte received0: The first byte has not been received.1: The first byte following the slave's own address has been received.This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR.." "The first byte has not been received,The first byte following the slave's own address.."
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|
newline
|
|
bitfld.long 0x04 1. "TREQ,Transmit request0: No outstanding transmit request.1: The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the SDR register" "No outstanding transmit request,The I2C controller has been addressed as a slave.."
|
|
bitfld.long 0x04 0. "RREQ,Receive request0: No outstanding receive data1: The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until data has been read from the SDR register." "No outstanding receive data,The I2C controller has outstanding receive data.."
|
|
wgroup.long 0x04++0x17
|
|
line.long 0x00 "SCTL,Slave ControlNote: This register shares address with SSTAT. meaning that this register functions as a control register when written. and a status register when"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved field"
|
|
bitfld.long 0x00 0. "DA,Device active0: Disables the I2C slave operation1: Enables the I2C slave operation" "Disables the I2C slave operation,Enables the I2C slave operation"
|
|
line.long 0x04 "SDR,Slave DataThis register contains the data to be transmitted when in the Slave Transmit state. and the data received when in the Slave Receive state"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "DATA,Data for transferThis field contains the data for transfer during a slave receive or transmit operation"
|
|
line.long 0x08 "SIMR,Slave Interrupt MaskThis register controls whether a raw interrupt is promoted to a controller interrupt"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 2. "STOPIM,Stop condition interrupt mask0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt controller." "The SRIS.STOPRIS interrupt is suppressed and not..,The SRIS.STOPRIS interrupt is enabled and sent.."
|
|
newline
|
|
bitfld.long 0x08 1. "STARTIM,Start condition interrupt mask0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt controller." "The SRIS.STARTRIS interrupt is suppressed and..,The SRIS.STARTRIS interrupt is enabled and sent.."
|
|
bitfld.long 0x08 0. "DATAIM,Data interrupt mask0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt controller" "The SRIS.DATARIS interrupt is suppressed and not..,The SRIS.DATARIS interrupt is enabled and sent.."
|
|
line.long 0x0C "SRIS,Slave Raw Interrupt StatusThis register shows the unmasked interrupt status"
|
|
hexmask.long 0x0C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 2. "STOPRIS,Stop condition raw interrupt status0: No interrupt1: A Stop condition interrupt is pending.This bit is cleared by writing a 1 to SICR.STOPIC" "No interrupt,A Stop condition interrupt is.."
|
|
newline
|
|
bitfld.long 0x0C 1. "STARTRIS,Start condition raw interrupt status0: No interrupt1: A Start condition interrupt is pending.This bit is cleared by writing a 1 to SICR.STARTIC" "No interrupt,A Start condition interrupt is.."
|
|
bitfld.long 0x0C 0. "DATARIS,Data raw interrupt status0: No interrupt1: A data received or data requested interrupt is pending.This bit is cleared by writing a 1 to the SICR.DATAIC" "No interrupt,A data received or data requested.."
|
|
line.long 0x10 "SMIS,Slave Masked Interrupt StatusThis register show which interrupt is active (based on result from SRIS and SIMR)"
|
|
hexmask.long 0x10 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 2. "STOPMIS,Stop condition masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked Stop condition interrupt is pending.This bit is cleared by writing a 1 to the SICR.STOPIC" "An interrupt has not occurred or is..,An unmasked Stop condition interrupt is.."
|
|
newline
|
|
bitfld.long 0x10 1. "STARTMIS,Start condition masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked Start condition interrupt is pending.This bit is cleared by writing a 1 to the SICR.STARTIC" "An interrupt has not occurred or is..,An unmasked Start condition interrupt is.."
|
|
bitfld.long 0x10 0. "DATAMIS,Data masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked data received or data requested interrupt is pending.This bit is cleared by writing a 1 to the SICR.DATAIC" "An interrupt has not occurred or is..,An unmasked data received or data requested.."
|
|
line.long 0x14 "SICR,Slave Interrupt ClearThis register clears the raw interrupt SRIS"
|
|
hexmask.long 0x14 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 2. "STOPIC,Stop condition interrupt clearWriting 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "STARTIC,Start condition interrupt clearWriting 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS" "0,1"
|
|
bitfld.long 0x14 0. "DATAIC,Data interrupt clearWriting 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS" "0,1"
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "MSA,Master Salve AddressThis register contains seven address bits of the slave to be accessed by the master (a6-a0). and an RS bit determining if the next operation is a receive or transmit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,I2C master slave addressDefines which slave is addressed for the transaction in master mode"
|
|
newline
|
|
bitfld.long 0x00 0. "RS,Receive or SendThis bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA" "Transmit/send data to slave,Receive data from slave"
|
|
line.long 0x04 "MSTAT,Master Status"
|
|
hexmask.long 0x04 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 6. "BUSBSY,Bus busy0: The I2C bus is idle.1: The I2C bus is busy.The bit changes based on the MCTRL.START and MCTRL.STOP conditions" "The I2C bus is idle,The I2C bus is busy.The bit changes based on the.."
|
|
newline
|
|
bitfld.long 0x04 5. "IDLE,I2C idle0: The I2C controller is not idle.1: The I2C controller is idle" "The I2C controller is not idle,The I2C controller is idle"
|
|
bitfld.long 0x04 4. "ARBLST,Arbitration lost0: The I2C controller won arbitration.1: The I2C controller lost arbitration" "The I2C controller won arbitration,The I2C controller lost arbitration"
|
|
newline
|
|
bitfld.long 0x04 3. "DATACK_N,Data Was Not Acknowledge0: The transmitted data was acknowledged.1: The transmitted data was not acknowledged" "The transmitted data was acknowledged,The transmitted data was not acknowledged"
|
|
bitfld.long 0x04 2. "ADRACK_N,Address Was Not Acknowledge0: The transmitted address was acknowledged.1: The transmitted address was not acknowledged" "The transmitted address was acknowledged,The transmitted address was not acknowledged"
|
|
newline
|
|
bitfld.long 0x04 1. "ERR,Error0: No error was detected on the last operation.1: An error occurred on the last operation" "No error was detected on the last operation,An error occurred on the last operation"
|
|
bitfld.long 0x04 0. "BUSY,I2C busy0: The controller is idle.1: The controller is busy.When this bit-field is set the other status bits are not valid.Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been.." "The controller is idle,The controller is busy.When this bit-field is.."
|
|
wgroup.long 0x804++0x1F
|
|
line.long 0x00 "MCTRL,Master ControlThis register accesses status bits when read and control bits when written"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "ACK,Data acknowledge enable0: The received data byte is not acknowledged automatically by the master.1: The received data byte is acknowledged automatically by the master.This bit-field must be cleared when the I2C bus controller requires no further.." "The received data byte is not acknowledged..,The received data byte is acknowledged.."
|
|
newline
|
|
bitfld.long 0x00 2. "STOP,This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.0: The controller does not generate the Stop condition.1: The controller generates the Stop condition" "The controller does not generate the Stop..,The controller generates the Stop condition"
|
|
bitfld.long 0x00 1. "START,This bit-field generates the Start or Repeated Start condition" "The controller does not generate the Start..,The controller generates the Start condition"
|
|
newline
|
|
bitfld.long 0x00 0. "RUN,I2C master enable0: The master is disabled.1: The master is enabled to transmit or receive data." "The master is disabled,The master is enabled to transmit or receive data"
|
|
line.long 0x04 "MDR,Master DataThis register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "DATA,When Read: Last RX Data is returnedWhen Written: Data is transferred during TX transaction"
|
|
line.long 0x08 "MTPR,I2C Master Timer PeriodThis register specifies the period of the SCL clock"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 7. "TPR_7,Must be set to 0 to set TPR" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--6. 1. "TPR,SCL clock periodThis field specifies the period of the SCL clock.SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRDwhere:SCL_PRD is the SCL line period (I2C clock).TPR is the timer period register value (range of 1 to 127)SCL_LP is the SCL low period.."
|
|
line.long 0x0C "MIMR,Master Interrupt MaskThis register controls whether a raw interrupt is promoted to a controller interrupt"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "IM,Interrupt mask0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt controller.1: The master interrupt is sent to the interrupt controller when the MRIS.RIS is set." "The MRIS.RIS interrupt is suppressed and not..,The master interrupt is sent to the interrupt.."
|
|
line.long 0x10 "MRIS,Master Raw Interrupt StatusThis register show the unmasked interrupt status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "RIS,Raw interrupt status0: No interrupt1: A master interrupt is pending.This bit is cleared by writing 1 to the MICR.IC bit" "No interrupt,A master interrupt is pending.This.."
|
|
line.long 0x14 "MMIS,Master Masked Interrupt StatusThis register show which interrupt is active (based on result from MRIS and MIMR)"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "MIS,Masked interrupt status0: An interrupt has not occurred or is masked.1: A master interrupt is pending.This bit is cleared by writing 1 to the MICR.IC bit" "An interrupt has not occurred or is masked,A master interrupt is pending.This bit is.."
|
|
line.long 0x18 "MICR,Master Interrupt ClearThis register clears the raw and masked interrupt"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "IC,Interrupt clearWriting 1 to this bit clears MRIS.RIS and MMIS.MIS .Reading this register returns no meaningful data" "0,1"
|
|
line.long 0x1C "MCR,Master ConfigurationThis register configures the mode (Master or Slave) and sets the interface for test mode loopback"
|
|
hexmask.long 0x1C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 5. "SFE,I2C slave function enable" "Slave mode is disabled.,Slave mode is enabled."
|
|
newline
|
|
bitfld.long 0x1C 4. "MFE,I2C master function enable" "Master mode is disabled.,Master mode is enabled."
|
|
rbitfld.long 0x1C 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x1C 0. "LPBK,I2C loopback0: Normal operation1: Loopback operation (test mode)" "Normal operation,Loopback operation (test mode)"
|
|
tree.end
|
|
tree "I2S0"
|
|
base ad:0x40021000
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "AIFWCLKSRC,WCLK Source Selection"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "WCLK_INV,Inverts WCLK source (pad or internal) when set.0: Not inverted1: Inverted" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "WCLK_SRC,Selects WCLK source for AIF (should be the same as the BCLK source)" "None ('0'),External WCLK generator from pad,Internal WCLK generator from module PRCM,Not supported. Will give same WCLK as 'NONE'.."
|
|
line.long 0x04 "AIFDMACFG,DMA Buffer Size Configuration"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "END_FRAME_IDX,Defines the length of the DMA buffer"
|
|
line.long 0x08 "AIFDIRCFG,Pin Direction"
|
|
hexmask.long 0x08 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 4.--5. "AD1,Configures the AD1 audio data pin usage:0x3: Reserved" "Not in use (disabled),Input mode,Output mode,?"
|
|
newline
|
|
rbitfld.long 0x08 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "AD0,Configures the AD0 audio data pin usage:0x3: Reserved" "Not in use (disabled),Input mode,Output mode,?"
|
|
line.long 0x0C "AIFFMTCFG,Serial Interface Format Configuration"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
abitfld.long 0x0C 8.--15. "DATA_DELAY,The number of BCLK periods between a WCLK edge and MSB of the first word in a phase:0x00: LJF and DSP" "0x00=LJF and DSP format,0x01=I2S and DSP format,0x02=RJF format,0xFF=RJF format"
|
|
newline
|
|
bitfld.long 0x0C 7. "MEM_LEN_24,The size of each word stored to or loaded from memory" "16-bit (one 16 bit access per sample),24-bit (one 8 bit and one 16 bit locked access.."
|
|
newline
|
|
bitfld.long 0x0C 6. "SMPL_EDGE,On the serial audio interface data (and wclk) is sampled and clocked out on opposite edges of BCLK" "Data is sampled on the negative edge and clocked..,Data is sampled on the positive edge and clocked.."
|
|
newline
|
|
bitfld.long 0x0C 5. "DUAL_PHASE,Selects dual- or single-phase format.0: Single-phase: DSP format1" "Single-phase,Dual-phase"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "WORD_LEN,Number of bits per word (8-24):In single-phase format this is the exact number of bits per word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "AIFWMASK0,Word Selection Bit Mask for Pin 0"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "MASK,Bit-mask indicating valid channels in a frame on AD0.In single-phase mode each bit represents one channel starting with LSB for the first word in the frame"
|
|
line.long 0x14 "AIFWMASK1,Word Selection Bit Mask for Pin 1"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "MASK,Bit-mask indicating valid channels in a frame on AD1.In single-phase mode each bit represents one channel starting with LSB for the first word in the frame"
|
|
line.long 0x18 "AIFWMASK2,Internal"
|
|
line.long 0x1C "AIFPWMVALUE,Audio Interface PWM Debug Value"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
abitfld.long 0x1C 0.--15. "PULSE_WIDTH,The value written to this register determines the width of the active high PWM pulse (pwm_debug) which starts together with MSB of the first output word in a DMA" "0x0000=Constant low,0x0001=Width of the pulse (number of BCLK cycles..,0xFFFE=Width of the pulse (number of BCLK cycles..,0xFFFF=Constant high"
|
|
line.long 0x20 "AIFINPTRNEXT,DMA Input Buffer Next Pointer"
|
|
line.long 0x24 "AIFINPTR,DMA Input Buffer Current Pointer"
|
|
line.long 0x28 "AIFOUTPTRNEXT,DMA Output Buffer Next Pointer"
|
|
line.long 0x2C "AIFOUTPTR,DMA Output Buffer Current Pointer"
|
|
group.long 0x34++0x37
|
|
line.long 0x00 "STMPCTL,Samplestamp Generator Control Register"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 2. "OUT_RDY,Low until the output pins are ready to be started by the samplestamp generator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "IN_RDY,Low until the input pins are ready to be started by the samplestamp generator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STMP_EN,Enables the samplestamp generator" "0,1"
|
|
line.long 0x04 "STMPXCNTCAPT0,Captured XOSC Counter Value. Capture Channel 0"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "CAPT_VALUE,The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0)"
|
|
line.long 0x08 "STMPXPER,XOSC Period Value"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "VALUE,The number of 24 MHz clock cycles in the previous WCLK period (that is - the next value of the XOSC counter at the positive WCLK edge had it not been reset to 0).The value is cleared when STMPCTL.STMP_EN = 0."
|
|
line.long 0x0C "STMPWCNTCAPT0,Captured WCLK Counter Value. Capture Channel 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--15. 1. "CAPT_VALUE,The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel 0)"
|
|
line.long 0x10 "STMPWPER,WCLK Counter Period Value"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "VALUE,Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer"
|
|
line.long 0x14 "STMPINTRIG,WCLK Counter Trigger Value for Input Pins"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "IN_START_WCNT,Compare value used to start the incoming audio streams.This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very.."
|
|
line.long 0x18 "STMPOUTTRIG,WCLK Counter Trigger Value for Output Pins"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "OUT_START_WCNT,Compare value used to start the outgoing audio streams.This bit field must equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very.."
|
|
line.long 0x1C "STMPWSET,WCLK Counter Set Operation"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "VALUE,WCLK counter modification: Sets the running WCLK counter equal to the written value"
|
|
line.long 0x20 "STMPWADD,WCLK Counter Add Operation"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "VALUE_INC,WCLK counter modification: Adds the written value to the running WCLK counter"
|
|
line.long 0x24 "STMPXPERMIN,XOSC Minimum Period ValueMinimum Value of STMPXPER"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "VALUE,Each time STMPXPER is updated the value is also loaded into this register provided that the value is smaller than the current value in this register.When written the register is reset to 0xFFFF (65535) regardless of the value written.The minimum.."
|
|
line.long 0x28 "STMPWCNT,Current Value of WCNT"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "CURR_VALUE,Current value of the WCLK counter"
|
|
line.long 0x2C "STMPXCNT,Current Value of XCNT"
|
|
hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x2C 0.--15. 1. "CURR_VALUE,Current value of the XOSC counter latched when reading STMPWCNT"
|
|
line.long 0x30 "STMPXCNTCAPT1,Internal"
|
|
hexmask.long.word 0x30 16.--31. 1. "RESERVED16,Internal"
|
|
newline
|
|
hexmask.long.word 0x30 0.--15. 1. "CAPT_VALUE,Internal"
|
|
line.long 0x34 "STMPWCNTCAPT1,Internal"
|
|
hexmask.long.word 0x34 16.--31. 1. "RESERVED16,Internal"
|
|
newline
|
|
hexmask.long.word 0x34 0.--15. 1. "CAPT_VALUE,Internal"
|
|
group.long 0x70++0x0F
|
|
line.long 0x00 "IRQMASK,Interrupt Mask RegisterSelects mask states of the flags in IRQFLAGS that contribute to the I2S_IRQ event"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 5. "AIF_DMA_IN,IRQFLAGS.AIF_DMA_IN interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "AIF_DMA_OUT,IRQFLAGS.AIF_DMA_OUT interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "WCLK_TIMEOUT,IRQFLAGS.WCLK_TIMEOUT interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 2. "BUS_ERR,IRQFLAGS.BUS_ERR interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. "WCLK_ERR,IRQFLAGS.WCLK_ERR interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 0. "PTR_ERR,IRQFLAGS.PTR_ERR interrupt mask.0: Disable1: Enable" "Disable,Enable"
|
|
line.long 0x04 "IRQFLAGS,Raw Interrupt Status Register"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "AIF_DMA_IN,Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT) see description of AIFINPTRNEXT register for details" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "AIF_DMA_OUT,Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTRNEXT) see description of AIFOUTPTRNEXT register for details" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "WCLK_TIMEOUT,Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "BUS_ERR,Set when a DMA operation is not completed in time (that is audio output buffer underflow or audio input buffer overflow)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "WCLK_ERR,Set when: - An unexpected WCLK edge occurs during the data delay period of a phase" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "PTR_ERR,Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time" "0,1"
|
|
line.long 0x08 "IRQSET,Interrupt Set Register"
|
|
hexmask.long 0x08 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 5. "AIF_DMA_IN," "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "AIF_DMA_OUT," "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "WCLK_TIMEOUT," "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "BUS_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "WCLK_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PTR_ERR," "0,1"
|
|
line.long 0x0C "IRQCLR,Interrupt Clear Register"
|
|
hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 5. "AIF_DMA_IN," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "AIF_DMA_OUT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "WCLK_TIMEOUT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "BUS_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "WCLK_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "PTR_ERR," "0,1"
|
|
tree.end
|
|
tree "IOC"
|
|
base ad:0x40081000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IOCFG0,Configuration of DIO0"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO0Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO1"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
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|
newline
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bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
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|
newline
|
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bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
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|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
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|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
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|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
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|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
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|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
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|
newline
|
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bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
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|
newline
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bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
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|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO1Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
repeat 15. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
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|
group.long ($2+0x44)++0x03
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|
line.long 0x00 "IOCFG$1,Configuration of DIO17"
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|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
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|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
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|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
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newline
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bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
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|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
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|
newline
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bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
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|
newline
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bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
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|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
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newline
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bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
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newline
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bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
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newline
|
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bitfld.long 0x00 13. "SLEW_RED," "0,1"
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|
newline
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bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
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newline
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bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
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newline
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bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
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newline
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rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO17Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
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|
repeat.end
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repeat 15. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x30 0x34 0x38 0x3C )
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|
group.long ($2+0x80)++0x03
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|
line.long 0x00 "IOCFG$1,Configuration of DIO32"
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|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
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newline
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bitfld.long 0x00 30. "HYST_EN," "0,1"
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|
newline
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bitfld.long 0x00 29. "IE," "0,1"
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|
newline
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bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
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newline
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bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
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|
newline
|
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bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
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newline
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bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
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|
newline
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bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
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|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
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|
newline
|
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bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
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|
newline
|
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bitfld.long 0x00 13. "SLEW_RED," "0,1"
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|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
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|
newline
|
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bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
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|
newline
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bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
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newline
|
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rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO32Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "IOCFG43,Configuration of DIO43"
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|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
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|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
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|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
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|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
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|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
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|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
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|
newline
|
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bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
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|
newline
|
|
bitfld.long 0x00 18.--20. "EDGE_IRQ_EN,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
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|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
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|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
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|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
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|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
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|
newline
|
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bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
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|
newline
|
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rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO43Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
tree.end
|
|
tree "PRCM"
|
|
base ad:0x40082000
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "INFRCLKDIVR,Infrastructure Clock Division Factor For Run Mode"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
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line.long 0x04 "INFRCLKDIVS,Infrastructure Clock Division Factor For Sleep Mode"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x08 "INFRCLKDIVDS,Infrastructure Clock Division Factor For DeepSleep Mode"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x0C "VDCTL,MCU Voltage Domain Control"
|
|
hexmask.long 0x0C 1.--31. 1. "SPARE1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ULDO,Request PMCTL to switch to uLDO.0: No request1: Assert request when possibleThe bit will have no effect before the following requirements are met:1" "No request,Assert request when.."
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "CLKLOADCTL,Load PRCM Settings To CLKCTRL Power Domain"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "LOAD_DONE,Status of LOAD" "One or more registers have been write accessed..,No registers are write accessed after last LOAD"
|
|
newline
|
|
bitfld.long 0x00 0. "LOAD," "No action,Load settings to CLKCTRL"
|
|
line.long 0x04 "RFCCLKG,RFC Clock Gate"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "CLK_EN," "Disable Clock,Enable clock if RFC power domain is.."
|
|
line.long 0x08 "VIMSCLKG,VIMS Clock Gate"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "CLK_EN," "0,1,2,3"
|
|
group.long 0x3C++0x53
|
|
line.long 0x00 "SECDMACLKGR,SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 24. "DMA_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "PKA_ZERIOZE_RESET_N,Zeroization logic hardware reset.0: pka_zeroize logic inactive.1: pka_zeroize of memory is enabled" "pka_zeroize logic inactive,pka_zeroize of memory is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "PKA_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
bitfld.long 0x00 17. "TRNG_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
bitfld.long 0x00 16. "CRYPTO_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x00 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x00 1. "TRNG_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x00 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x04 "SECDMACLKGS,SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode"
|
|
hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x04 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x04 1. "TRNG_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x04 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x08 "SECDMACLKGDS,SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode"
|
|
hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x08 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x08 1. "TRNG_CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
newline
|
|
bitfld.long 0x08 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
line.long 0x0C "GPIOCLKGR,GPIO Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 8. "AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x10 "GPIOCLKGS,GPIO Clock Gate For Sleep Mode"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x14 "GPIOCLKGDS,GPIO Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x18 "GPTCLKGR,GPT Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "AM_CLK_EN,Each bit below has the following meaning:0: No force1: Force clock on for all modes (Run Sleep and Deep Sleep)Overrides CLK_EN GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled.ENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD.." "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x18 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clock Can be forced on by AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clock Can be forced on by..,?..."
|
|
line.long 0x1C "GPTCLKGS,GPT Clock Gate For Sleep Mode"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clockCan be forced on by GPTCLKGR.AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x20 "GPTCLKGDS,GPT Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x20 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clockCan be forced on by GPTCLKGR.AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x24 "I2CCLKGR,I2C Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 8.--9. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x24 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x24 0.--1. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x28 "I2CCLKGS,I2C Clock Gate For Sleep Mode"
|
|
hexmask.long 0x28 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0.--1. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x2C "I2CCLKGDS,I2C Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x2C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x2C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x30 "UARTCLKGR,UART Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x30 8.--11. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x30 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x30 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x34 "UARTCLKGS,UART Clock Gate For Sleep Mode"
|
|
hexmask.long 0x34 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x34 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x38 "UARTCLKGDS,UART Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x38 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x38 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x3C "SSICLKGR,SSI Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x3C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x3C 8.--11. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x3C 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x3C 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x40 "SSICLKGS,SSI Clock Gate For Sleep Mode"
|
|
hexmask.long 0x40 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x40 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x44 "SSICLKGDS,SSI Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x44 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x44 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x48 "I2SCLKGR,I2S Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x48 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x48 8. "AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x48 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x48 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x4C "I2SCLKGS,I2S Clock Gate For Sleep Mode"
|
|
hexmask.long 0x4C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x4C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x50 "I2SCLKGDS,I2S Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x50 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x50 0. "CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
group.long 0xB4++0x2B
|
|
line.long 0x00 "SYSBUSCLKDIV,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?"
|
|
line.long 0x04 "CPUCLKDIV,Internal"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Internal"
|
|
newline
|
|
bitfld.long 0x04 0. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
line.long 0x08 "PERBUSCPUCLKDIV,Internal"
|
|
hexmask.long 0x08 4.--31. 1. "RESERVED4,Internal"
|
|
newline
|
|
bitfld.long 0x08 0.--3. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.long 0x0C "PERBUSDMACLKDIV,Internal"
|
|
line.long 0x10 "PERDMACLKDIV,Internal"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Internal"
|
|
newline
|
|
bitfld.long 0x10 0.--3. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.long 0x14 "I2SBCLKSEL,I2S Clock Control"
|
|
hexmask.long 0x14 1.--31. 1. "SPARE1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "SRC,BCLK source selector0: Use external BCLK1: Use internally generated clockFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Use external BCLK,Use internally generated clockFor changes to.."
|
|
line.long 0x18 "GPTCLKDIV,GPT Scalar"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "RATIO,Scalar used for GPTs" "Divide by 1,Divide by 2,Divide by 4,Divide by 8,Divide by 16,Divide by 32,Divide by 64,Divide by 128,Divide by 256,?,?,?,?,?,?,?"
|
|
line.long 0x1C "I2SCLKCTL,I2S Clock Control"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 3. "SMPL_ON_POSEDGE,On the I2S serial interface data and WCLK is sampled and clocked out on opposite edges of BCLK" "data and WCLK are sampled on the negative edge..,data and WCLK are sampled on the positive edge.."
|
|
newline
|
|
bitfld.long 0x1C 1.--2. "WCLK_PHASE,Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV)" "Single phase,Dual phase,User Defined,Reserved/UndefinedFor changes to.."
|
|
newline
|
|
bitfld.long 0x1C 0. "EN," "MCLK BCLK and WCLK will be static low,Enables the generation of MCLK BCLK and WCLKFor.."
|
|
line.long 0x20 "I2SMCLKDIV,MCLK Division Ratio"
|
|
hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--9. 1. "MDIV,An unsigned factor of the division ratio used to generate MCLK [2-1024]:MCLK = MCUCLK/MDIV[Hz]MCUCLK is 48MHz.A value of 0 is interpreted as 1024.A value of 1 is invalid.If MDIV is odd the low phase of the clock is one MCUCLK period longer than the.."
|
|
line.long 0x24 "I2SBCLKDIV,BCLK Division Ratio"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--9. 1. "BDIV,An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]:BCLK = MCUCLK/BDIV[Hz]MCUCLK is 48MHz.A value of 0 is interpreted as 1024.A value of 1 is invalid.If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0 the low phase of the.."
|
|
line.long 0x28 "I2SWCLKDIV,WCLK Division Ratio"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "WDIV,If I2SCLKCTL.WCLK_PHASE = 0 Single phase.WCLK is high one BCLK period and low WDIV[9:0] (unsigned [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]MCUCLK is 48MHz.If I2SCLKCTL.WCLK_PHASE = 1 Dual phase.Each phase on WCLK (50% duty.."
|
|
group.long 0xF0++0x1B
|
|
line.long 0x00 "RESETSECDMA,RESET For SEC (PKA And TRNG And CRYPTO) And UDMA"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA,Write 1 to reset" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "PKA,Write 1 to reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRNG,Write 1 to reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CRYPTO,Write 1 to reset" "0,1"
|
|
line.long 0x04 "RESETGPIO,RESET For GPIO IPs"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "GPIO," "No action,Reset GPIO"
|
|
line.long 0x08 "RESETGPT,RESET For GPT Ips"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "GPT," "No action,Reset all GPTs"
|
|
line.long 0x0C "RESETI2C,RESET For I2C IPs"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "I2C1," "No action,Reset I2C1"
|
|
newline
|
|
bitfld.long 0x0C 0. "I2C0," "No action,Reset I2C0"
|
|
line.long 0x10 "RESETUART,RESET For UART IPs"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 3. "UART3," "No action,Reset UART3"
|
|
newline
|
|
bitfld.long 0x10 2. "UART2," "No action,Reset UART2"
|
|
newline
|
|
bitfld.long 0x10 1. "UART1," "No action,Reset UART1"
|
|
newline
|
|
bitfld.long 0x10 0. "UART0," "No action,Reset UART0"
|
|
line.long 0x14 "RESETSSI,RESET For SSI IPs"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3. "SSI3," "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "SSI2," "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "SSI1," "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SSI0," "0,1"
|
|
line.long 0x18 "RESETI2S,RESET For I2S IP"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 0. "I2S," "No action,Reset module"
|
|
group.long 0x12C++0x0F
|
|
line.long 0x00 "PDCTL0,Power Domain Control"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "PERIPH_ON,PERIPH Power domain.0: PERIPH power domain is powered down1: PERIPH power domain is powered up" "PERIPH power domain is powered down,PERIPH power domain is powered up"
|
|
newline
|
|
bitfld.long 0x00 1. "SERIAL_ON,SERIAL Power domain.0: SERIAL power domain is powered down1: SERIAL power domain is powered up" "SERIAL power domain is powered down,SERIAL power domain is powered up"
|
|
newline
|
|
bitfld.long 0x00 0. "RFC_ON," "RFC power domain powered off if also..,RFC power domain powered on"
|
|
line.long 0x04 "PDCTL0RFC,RFC Power Domain Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,Alias for PDCTL0.RFC_ON" "0,1"
|
|
line.long 0x08 "PDCTL0SERIAL,SERIAL Power Domain Control"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,Alias for PDCTL0.SERIAL_ON" "0,1"
|
|
line.long 0x0C "PDCTL0PERIPH,PERIPH Power Domain Control"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,Alias for PDCTL0.PERIPH_ON" "0,1"
|
|
rgroup.long 0x140++0x0F
|
|
line.long 0x00 "PDSTAT0,Power Domain Status"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "PERIPH_ON,PERIPH Power domain.0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
newline
|
|
bitfld.long 0x00 1. "SERIAL_ON,SERIAL Power domain.0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
newline
|
|
bitfld.long 0x00 0. "RFC_ON,RFC Power domain0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
line.long 0x04 "PDSTAT0RFC,RFC Power Domain Status"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,Alias for PDSTAT0.RFC_ON" "0,1"
|
|
line.long 0x08 "PDSTAT0SERIAL,SERIAL Power Domain Status"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,Alias for PDSTAT0.SERIAL_ON" "0,1"
|
|
line.long 0x0C "PDSTAT0PERIPH,PERIPH Power Domain Status"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,Alias for PDSTAT0.PERIPH_ON" "0,1"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "PDCTL1,Power Domain Control"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "VIMS_MODE," "VIMS power domain is only powered when CPU power..,VIMS power domain is powered whenever the BUS..,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "RFC_ON," "RFC power domain powered off if also..,RFC power domain powered on Bit shall be used by.."
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_ON," "Causes a power down of the CPU power domain when..,Initiates power-on of the CPU power domain.This.."
|
|
newline
|
|
rbitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
group.long 0x184++0x0B
|
|
line.long 0x00 "PDCTL1CPU,CPU Power Domain Direct Control"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "ON,This is an alias for PDCTL1.CPU_ON" "0,1"
|
|
line.long 0x04 "PDCTL1RFC,RFC Power Domain Direct Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,This is an alias for PDCTL1.RFC_ON" "0,1"
|
|
line.long 0x08 "PDCTL1VIMS,VIMS Mode Direct Control"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "MODE,This is an alias for PDCTL1.VIMS_MODE" "0,1,2,3"
|
|
rgroup.long 0x194++0x13
|
|
line.long 0x00 "PDSTAT1,Power Manager Status"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4. "BUS_ON," "BUS domain not accessible,BUS domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 3. "VIMS_ON," "VIMS domain not accessible,VIMS domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 2. "RFC_ON," "RFC domain not accessible,RFC domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_ON," "CPU and BUS domain not accessible,CPU and BUS domains are both currently accessible"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x04 "PDSTAT1BUS,BUS Power Domain Direct Read Status"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,This is an alias for PDSTAT1.BUS_ON" "0,1"
|
|
line.long 0x08 "PDSTAT1RFC,RFC Power Domain Direct Read Status"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,This is an alias for PDSTAT1.RFC_ON" "0,1"
|
|
line.long 0x0C "PDSTAT1CPU,CPU Power Domain Direct Read Status"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,This is an alias for PDSTAT1.CPU_ON" "0,1"
|
|
line.long 0x10 "PDSTAT1VIMS,VIMS Mode Direct Read Status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "ON,This is an alias for PDSTAT1.VIMS_ON" "0,1"
|
|
group.long 0x1CC++0x0B
|
|
line.long 0x00 "RFCBITS,Control To RFC"
|
|
line.long 0x04 "RFCMODESEL,Selected RFC Mode"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "CURR,Selects the set of commands that the RFC will accept" "Select Mode 0,Select Mode 1,Select Mode 2,Select Mode 3,Select Mode 4,Select Mode 5,Select Mode 6,Select Mode 7"
|
|
line.long 0x08 "RFCMODEHWOPT,Allowed RFC Modes"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "AVAIL,Permitted RFC modes"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "PWRPROFSTAT,Power Profiler Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VALUE,SW can use these bits to timestamp the application"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "MCUSRAMCFG,MCU SRAM configuration"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "PARITY_EN,Parity enable0: Parity disabled Parity section available as GPRAM1: Parity enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BM_OFF,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PAGE,Page Mode select0: Page Mode disabled" "Page Mode disabled,Page Mode enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "PGS,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BM,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PCH_F,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PCH_L,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "RAMRETEN,Memory Retention Control"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3. "RFCULL," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RFC," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "VIMS," "VIMS,VIMS,?..."
|
|
group.long 0x290++0x0B
|
|
line.long 0x00 "OSCIMSC,Oscillator Interrupt Mask Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "HFSRCPENDIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LFSRCDONEIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "XOSCDLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "XOSCLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RCOSCDLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RCOSCLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "XOSCHFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RCOSCHFIM," "0,1"
|
|
line.long 0x04 "OSCRIS,Oscillator Raw Interrupt Status"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 7. "HFSRCPENDRIS,SCLK_HF source switch pending interrupt.After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source change request then the requested SCLK_HF source will be enabled and qualified" "Indicates SCLK_HF source is not ready to be..,Indicates SCLK_HF source is ready to be.."
|
|
newline
|
|
bitfld.long 0x04 6. "LFSRCDONERIS,SCLK_LF source switch done.The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that the SCLK_LF source shall be changed" "Indicates SCLK_LF source switch has not completed,Indicates SCLK_LF source switch has completed.."
|
|
newline
|
|
bitfld.long 0x04 5. "XOSCDLFRIS,The XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF" "XOSCDLF has not been qualified,XOSCDLF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 4. "XOSCLFRIS,The XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator has been qualified with respect to frequency" "XOSCLF has not been qualified,XOSCLF has been qualified Interrupt is qualified.."
|
|
newline
|
|
bitfld.long 0x04 3. "RCOSCDLFRIS,The RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF" "RCOSCDLF has not been qualified,RCOSCDLF has been qualifiedInterrupt is.."
|
|
newline
|
|
bitfld.long 0x04 2. "RCOSCLFRIS,The RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF oscillator has been qualified with respect to frequency" "RCOSCLF has not been qualified,RCOSCLF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 1. "XOSCHFRIS,The XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been qualified for use as a clock source" "XOSC_HF has not been qualified,XOSC_HF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 0. "RCOSCHFRIS,The RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been qualified for use as a clock source When the RCOSCHFRIS interrupt is high the oscillator is qualified and will be used as a clock source when selected" "RCOSC_HF has not been qualified,RCOSC_HF has been qualifiedInterrupt is.."
|
|
line.long 0x08 "OSCICR,Oscillator Raw Interrupt Clear"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 7. "HFSRCPENDC,Writing 1 to this field clears the HFSRCPEND raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. "LFSRCDONEC,Writing 1 to this field clears the LFSRCDONE raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "XOSCDLFC,Writing 1 to this field clears the XOSCDLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "XOSCLFC,Writing 1 to this field clears the XOSCLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "RCOSCDLFC,Writing 1 to this field clears the RCOSCDLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "RCOSCLFC,Writing 1 to this field clears the RCOSCLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "XOSCHFC,Writing 1 to this field clears the XOSCHF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "RCOSCHFC,Writing 1 to this field clears the RCOSCHF raw interrupt status" "0,1"
|
|
group.long 0x2B0++0x17
|
|
line.long 0x00 "NVMNSCADDR,NVM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x00 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "BOUNDARY,Non-Secure callable boundary address"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "NVMNSADDR,NVM Non-Secure boundary Address"
|
|
rbitfld.long 0x04 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 21.--30. 1. "RESERVED21,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x04 20. "BOUNDARY_MSB,Non-Secure boundary address MSBHW controlled." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 13.--19. 1. "BOUNDARY,Non-Secure boundary address.Writing this field when BUSSECCFG.VALID is set may result in undefined behavior."
|
|
newline
|
|
hexmask.long.word 0x04 0.--12. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x08 "SRAMNSCADDR,SRAM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x08 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x08 19.--30. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 10.--18. 1. "BOUNDARY,Non-Secure callable boundary address"
|
|
newline
|
|
hexmask.long.word 0x08 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "SRAMNSADDR,SRAM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x0C 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0C 19.--30. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x0C 10.--18. 1. "BOUNDARY,Non-Secure boundary address.Writing this field when BUSSECCFG.VALID is set may result in undefined behavior."
|
|
newline
|
|
hexmask.long.word 0x0C 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x10 "BUSSECCFG,BUS Secuirty Configuration Register"
|
|
bitfld.long 0x10 31. "VALID,Security configuration validRegisters that needs to be followed by VALID before settings being applied are:- NVMNSCADDR- NVMNSADDR- SRAMNSCADDR- SRAMNSADDR- BUSSECCFG- CPULOCK" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x10 8.--30. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "BUS_CFG,Bus interconnect security and firewall configuration"
|
|
line.long 0x14 "CPULOCK,CPU Lock Register"
|
|
rbitfld.long 0x14 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long 0x14 5.--30. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 4. "LOCKNSVTOR,When set will lock non-secure vector table base addressWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LOCKSVTAIRCR,When set will lock- Secure vector table base address- Secure interrupt priority- Busfault- Hardfault NMI security targetWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "LOCKSAU,When set will lock SAU regionsWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LOCKNSMPU,When set will lock non-secure MPUWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "LOCKSMPU,When set will lock secure MPUWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
tree.end
|
|
tree "RFC"
|
|
tree "RFC_DBELL"
|
|
base ad:0x40041000
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "CMDR,Doorbell Command Register"
|
|
line.long 0x04 "CMDSTA,Doorbell Command Status Register"
|
|
line.long 0x08 "RFHWIFG,Interrupt Flags From RF Hardware Modules"
|
|
hexmask.long.word 0x08 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 19. "RATCH7,Radio timer channel 7 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 18. "RATCH6,Radio timer channel 6 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 17. "RATCH5,Radio timer channel 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. "RATCH4,Radio timer channel 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 15. "RATCH3,Radio timer channel 3 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 14. "RATCH2,Radio timer channel 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 13. "RATCH1,Radio timer channel 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "RATCH0,Radio timer channel 0 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 11. "RFESOFT2,RF engine software defined interrupt 2 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. "RFESOFT1,RF engine software defined interrupt 1 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. "RFESOFT0,RF engine software defined interrupt 0 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "RFEDONE,RF engine command done interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. "TRCTK,Debug tracer system tick interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "MDMSOFT,Modem software defined interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "MDMOUT,Modem FIFO output interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "MDMIN,Modem FIFO input interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "MDMDONE,Modem command done interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "FSCA,Frequency synthesizer calibration accelerator interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x0C "RFHWIEN,Interrupt Enable For RF Hardware Modules"
|
|
hexmask.long.word 0x0C 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 19. "RATCH7,Interrupt enable for RFHWIFG.RATCH7" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 18. "RATCH6,Interrupt enable for RFHWIFG.RATCH6" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 17. "RATCH5,Interrupt enable for RFHWIFG.RATCH5" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. "RATCH4,Interrupt enable for RFHWIFG.RATCH4" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 15. "RATCH3,Interrupt enable for RFHWIFG.RATCH3" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 14. "RATCH2,Interrupt enable for RFHWIFG.RATCH2" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 13. "RATCH1,Interrupt enable for RFHWIFG.RATCH1" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 12. "RATCH0,Interrupt enable for RFHWIFG.RATCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 11. "RFESOFT2,Interrupt enable for RFHWIFG.RFESOFT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 10. "RFESOFT1,Interrupt enable for RFHWIFG.RFESOFT1" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RFESOFT0,Interrupt enable for RFHWIFG.RFESOFT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "RFEDONE,Interrupt enable for RFHWIFG.RFEDONE" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "TRCTK,Interrupt enable for RFHWIFG.TRCTK" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "MDMSOFT,Interrupt enable for RFHWIFG.MDMSOFT" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "MDMOUT,Interrupt enable for RFHWIFG.MDMOUT" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "MDMIN,Interrupt enable for RFHWIFG.MDMIN" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "MDMDONE,Interrupt enable for RFHWIFG.MDMDONE" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "FSCA,Interrupt enable for RFHWIFG.FSCA" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x10 "RFCPEIFG,Interrupt Flags For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x10 31. "INTERNAL_ERROR,Interrupt flag 31" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "BOOT_DONE,Interrupt flag 30" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "MODULES_UNLOCKED,Interrupt flag 29" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. "SYNTH_NO_LOCK,Interrupt flag 28" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "IRQ27,Interrupt flag 27" "0,1"
|
|
newline
|
|
bitfld.long 0x10 26. "RX_ABORTED,Interrupt flag 26" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "RX_N_DATA_WRITTEN,Interrupt flag 25" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "RX_DATA_WRITTEN,Interrupt flag 24" "0,1"
|
|
newline
|
|
bitfld.long 0x10 23. "RX_ENTRY_DONE,Interrupt flag 23" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "RX_BUF_FULL,Interrupt flag 22" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "RX_CTRL_ACK,Interrupt flag 21" "0,1"
|
|
newline
|
|
bitfld.long 0x10 20. "RX_CTRL,Interrupt flag 20" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "RX_EMPTY,Interrupt flag 19" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "RX_IGNORED,Interrupt flag 18" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "RX_NOK,Interrupt flag 17" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "RX_OK,Interrupt flag 16" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "IRQ15,Interrupt flag 15" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "IRQ14,Interrupt flag 14" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FG_COMMAND_STARTED,Interrupt flag 13" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "COMMAND_STARTED,Interrupt flag 12" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "TX_BUFFER_CHANGED,Interrupt flag 11" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "TX_ENTRY_DONE,Interrupt flag 10" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "TX_RETRANS,Interrupt flag 9" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "TX_CTRL_ACK_ACK,Interrupt flag 8" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "TX_CTRL_ACK,Interrupt flag 7" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "TX_CTRL,Interrupt flag 6" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "TX_ACK,Interrupt flag 5" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "TX_DONE,Interrupt flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "LAST_FG_COMMAND_DONE,Interrupt flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "FG_COMMAND_DONE,Interrupt flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "LAST_COMMAND_DONE,Interrupt flag 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "COMMAND_DONE,Interrupt flag 0" "0,1"
|
|
line.long 0x14 "RFCPEIEN,Interrupt Enable For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x14 31. "INTERNAL_ERROR,Interrupt enable for RFCPEIFG.INTERNAL_ERROR" "0,1"
|
|
newline
|
|
bitfld.long 0x14 30. "BOOT_DONE,Interrupt enable for RFCPEIFG.BOOT_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "MODULES_UNLOCKED,Interrupt enable for RFCPEIFG.MODULES_UNLOCKED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. "SYNTH_NO_LOCK,Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "IRQ27,Interrupt enable for RFCPEIFG.IRQ27" "0,1"
|
|
newline
|
|
bitfld.long 0x14 26. "RX_ABORTED,Interrupt enable for RFCPEIFG.RX_ABORTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "RX_N_DATA_WRITTEN,Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24. "RX_DATA_WRITTEN,Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN" "0,1"
|
|
newline
|
|
bitfld.long 0x14 23. "RX_ENTRY_DONE,Interrupt enable for RFCPEIFG.RX_ENTRY_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. "RX_BUF_FULL,Interrupt enable for RFCPEIFG.RX_BUF_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "RX_CTRL_ACK,Interrupt enable for RFCPEIFG.RX_CTRL_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 20. "RX_CTRL,Interrupt enable for RFCPEIFG.RX_CTRL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "RX_EMPTY,Interrupt enable for RFCPEIFG.RX_EMPTY" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "RX_IGNORED,Interrupt enable for RFCPEIFG.RX_IGNORED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 17. "RX_NOK,Interrupt enable for RFCPEIFG.RX_NOK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. "RX_OK,Interrupt enable for RFCPEIFG.RX_OK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "IRQ15,Interrupt enable for RFCPEIFG.IRQ15" "0,1"
|
|
newline
|
|
bitfld.long 0x14 14. "IRQ14,Interrupt enable for RFCPEIFG.IRQ14" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "FG_COMMAND_STARTED,Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "COMMAND_STARTED,Interrupt enable for RFCPEIFG.COMMAND_STARTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "TX_BUFFER_CHANGED,Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "TX_ENTRY_DONE,Interrupt enable for RFCPEIFG.TX_ENTRY_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "TX_RETRANS,Interrupt enable for RFCPEIFG.TX_RETRANS" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "TX_CTRL_ACK_ACK,Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "TX_CTRL_ACK,Interrupt enable for RFCPEIFG.TX_CTRL_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "TX_CTRL,Interrupt enable for RFCPEIFG.TX_CTRL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "TX_ACK,Interrupt enable for RFCPEIFG.TX_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "TX_DONE,Interrupt enable for RFCPEIFG.TX_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LAST_FG_COMMAND_DONE,Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "FG_COMMAND_DONE,Interrupt enable for RFCPEIFG.FG_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LAST_COMMAND_DONE,Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "COMMAND_DONE,Interrupt enable for RFCPEIFG.COMMAND_DONE" "0,1"
|
|
line.long 0x18 "RFCPEISL,Interrupt Vector Selection For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x18 31. "INTERNAL_ERROR,Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 30. "BOOT_DONE,Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 29. "MODULES_UNLOCKED,Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 28. "SYNTH_NO_LOCK,Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 27. "IRQ27,Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 26. "RX_ABORTED,Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 25. "RX_N_DATA_WRITTEN,Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 24. "RX_DATA_WRITTEN,Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 23. "RX_ENTRY_DONE,Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 22. "RX_BUF_FULL,Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 21. "RX_CTRL_ACK,Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 20. "RX_CTRL,Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 19. "RX_EMPTY,Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 18. "RX_IGNORED,Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 17. "RX_NOK,Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 16. "RX_OK,Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 15. "IRQ15,Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 14. "IRQ14,Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 13. "FG_COMMAND_STARTED,Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 12. "COMMAND_STARTED,Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 11. "TX_BUFFER_CHANGED,Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 10. "TX_ENTRY_DONE,Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 9. "TX_RETRANS,Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 8. "TX_CTRL_ACK_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 7. "TX_CTRL_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 6. "TX_CTRL,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 5. "TX_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 4. "TX_DONE,Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 3. "LAST_FG_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 2. "FG_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 1. "LAST_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 0. "COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
line.long 0x1C "RFACKIFG,Doorbell Command Acknowledgement Interrupt Flag"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0. "ACKFLAG,Interrupt flag for Command ACK" "0,1"
|
|
line.long 0x20 "SYSGPOCTL,RF Core General Purpose Output Control"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 12.--15. "GPOCTL3,RF Core GPO control bit 3" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 8.--11. "GPOCTL2,RF Core GPO control bit 2" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 4.--7. "GPOCTL1,RF Core GPO control bit 1" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 0.--3. "GPOCTL0,RF Core GPO control bit 0" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
tree.end
|
|
tree "RFC_PWR"
|
|
base ad:0x40040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCLKEN,RF Core Power Management and Clock Enable"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 13. "DEMOD,Enable clock to the Demodulator" "0,1"
|
|
bitfld.long 0x00 12. "MOD,Enable clock to the Modulator" "0,1"
|
|
bitfld.long 0x00 11. "IQRAM,Enable clock to IQ RAM in coherent demodulator" "0,1"
|
|
bitfld.long 0x00 10. "RFCTRC,Enable clock to the RF Core Tracer (RFCTRC) module" "0,1"
|
|
bitfld.long 0x00 9. "FSCA,Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) module" "0,1"
|
|
bitfld.long 0x00 8. "PHA,Enable clock to the Packet Handling Accelerator (PHA) module" "0,1"
|
|
bitfld.long 0x00 7. "RAT,Enable clock to the Radio Timer (RAT) module" "0,1"
|
|
bitfld.long 0x00 6. "RFERAM,Enable clock to the RF Engine RAM module" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RFE,Enable clock to the RF Engine (RFE) module" "0,1"
|
|
bitfld.long 0x00 4. "MDMRAM,Enable clock to the Modem RAM module" "0,1"
|
|
bitfld.long 0x00 3. "MDM,Enable clock to the Modem (MDM) module" "0,1"
|
|
bitfld.long 0x00 2. "CPERAM,Enable clock to the Command and Packet Engine (CPE) RAM module" "0,1"
|
|
bitfld.long 0x00 1. "CPE,Enable processor clock (hclk) to the Command and Packet Engine (CPE)" "0,1"
|
|
rbitfld.long 0x00 0. "RFC,Enable essential clocks for the RF Core interface" "0,1"
|
|
tree.end
|
|
tree "RFC_RAT"
|
|
base ad:0x40043000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RATCNT,Radio Timer Counter Value"
|
|
group.long 0x80++0x1F
|
|
line.long 0x00 "RATCH0VAL,Timer Channel 0 Capture/Compare Register"
|
|
line.long 0x04 "RATCH1VAL,Timer Channel 1 Capture/Compare Register"
|
|
line.long 0x08 "RATCH2VAL,Timer Channel 2 Capture/Compare Register"
|
|
line.long 0x0C "RATCH3VAL,Timer Channel 3 Capture/Compare Register"
|
|
line.long 0x10 "RATCH4VAL,Timer Channel 4 Capture/Compare Register"
|
|
line.long 0x14 "RATCH5VAL,Timer Channel 5 Capture/Compare Register"
|
|
line.long 0x18 "RATCH6VAL,Timer Channel 6 Capture/Compare Register"
|
|
line.long 0x1C "RATCH7VAL,Timer Channel 7 Capture/Compare Register"
|
|
tree.end
|
|
tree.end
|
|
tree "SMPH"
|
|
base ad:0x40084000
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SMPH$1,MCU SEMAPHORE 0"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is availableReading the register causes it to change value to 0" "Semaphore is taken,Semaphore is availableReading the register.."
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "SMPH$1,MCU SEMAPHORE 16"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is availableReading the register causes it to change value to 0" "Semaphore is taken,Semaphore is availableReading the register.."
|
|
repeat.end
|
|
rgroup.long 0x800++0x7F
|
|
line.long 0x00 "PEEK0,MCU SEMAPHORE 0 ALIAS"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x04 "PEEK1,MCU SEMAPHORE 1 ALIAS"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x08 "PEEK2,MCU SEMAPHORE 2 ALIAS"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x0C "PEEK3,MCU SEMAPHORE 3 ALIAS"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x10 "PEEK4,MCU SEMAPHORE 4 ALIAS"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x14 "PEEK5,MCU SEMAPHORE 5 ALIAS"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x18 "PEEK6,MCU SEMAPHORE 6 ALIAS"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x1C "PEEK7,MCU SEMAPHORE 7 ALIAS"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x20 "PEEK8,MCU SEMAPHORE 8 ALIAS"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x24 "PEEK9,MCU SEMAPHORE 9 ALIAS"
|
|
hexmask.long 0x24 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x28 "PEEK10,MCU SEMAPHORE 10 ALIAS"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x2C "PEEK11,MCU SEMAPHORE 11 ALIAS"
|
|
hexmask.long 0x2C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x30 "PEEK12,MCU SEMAPHORE 12 ALIAS"
|
|
hexmask.long 0x30 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x30 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x34 "PEEK13,MCU SEMAPHORE 13 ALIAS"
|
|
hexmask.long 0x34 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x34 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x38 "PEEK14,MCU SEMAPHORE 14 ALIAS"
|
|
hexmask.long 0x38 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x38 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x3C "PEEK15,MCU SEMAPHORE 15 ALIAS"
|
|
hexmask.long 0x3C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x3C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x40 "PEEK16,MCU SEMAPHORE 16 ALIAS"
|
|
hexmask.long 0x40 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x40 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x44 "PEEK17,MCU SEMAPHORE 17 ALIAS"
|
|
hexmask.long 0x44 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x44 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x48 "PEEK18,MCU SEMAPHORE 18 ALIAS"
|
|
hexmask.long 0x48 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x48 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x4C "PEEK19,MCU SEMAPHORE 19 ALIAS"
|
|
hexmask.long 0x4C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x4C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x50 "PEEK20,MCU SEMAPHORE 20 ALIAS"
|
|
hexmask.long 0x50 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x50 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x54 "PEEK21,MCU SEMAPHORE 21 ALIAS"
|
|
hexmask.long 0x54 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x54 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x58 "PEEK22,MCU SEMAPHORE 22 ALIAS"
|
|
hexmask.long 0x58 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x58 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x5C "PEEK23,MCU SEMAPHORE 23 ALIAS"
|
|
hexmask.long 0x5C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x5C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x60 "PEEK24,MCU SEMAPHORE 24 ALIAS"
|
|
hexmask.long 0x60 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x60 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x64 "PEEK25,MCU SEMAPHORE 25 ALIAS"
|
|
hexmask.long 0x64 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x64 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x68 "PEEK26,MCU SEMAPHORE 26 ALIAS"
|
|
hexmask.long 0x68 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x68 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x6C "PEEK27,MCU SEMAPHORE 27 ALIAS"
|
|
hexmask.long 0x6C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x6C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x70 "PEEK28,MCU SEMAPHORE 28 ALIAS"
|
|
hexmask.long 0x70 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x70 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x74 "PEEK29,MCU SEMAPHORE 29 ALIAS"
|
|
hexmask.long 0x74 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x74 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x78 "PEEK30,MCU SEMAPHORE 30 ALIAS"
|
|
hexmask.long 0x78 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x78 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x7C "PEEK31,MCU SEMAPHORE 31 ALIAS"
|
|
hexmask.long 0x7C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x7C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
tree.end
|
|
tree "SSI0"
|
|
base ad:0x40000000
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CR0,Control 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "SCR,Serial clock rate:This is used to generate the transmit and receive bit rate of the SSI"
|
|
newline
|
|
bitfld.long 0x00 7. "SPH,CLKOUT phase (Motorola SPI frame format only)This bit selects the clock edge that captures data and enables it to change state" "Data is captured on the first clock edge..,Data is captured on the second clock edge.."
|
|
newline
|
|
bitfld.long 0x00 6. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "SSI produces a steady state LOW value on..,SSI produces a steady state HIGH value on the.."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "FRF,Frame format" "Motorola SPI frame format,TI synchronous serial frame format,National Microwire frame format,?"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DSS,Data Size Select" "?,?,?,4-bit data,5-bit data,6-bit data,7-bit data,8-bit data,9-bit data,10-bit data,11-bit data,12-bit data,13-bit data,14-bit data,15-bit data,16-bit data"
|
|
line.long 0x04 "CR1,Control 1"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 3. "SOD,Slave-mode output disabledThis bit is relevant only in the slave mode MS=1" "SSI can drive the TXD output in slave mode,SSI cannot drive the TXD output in slave mode"
|
|
newline
|
|
bitfld.long 0x04 2. "MS,Master or slave mode select" "Device configured as master,Device configured as slave"
|
|
newline
|
|
bitfld.long 0x04 1. "SSE,Synchronous serial interface enable" "Operation disabled,Operation enabled"
|
|
newline
|
|
bitfld.long 0x04 0. "LBM,Loop back mode:0: Normal serial port operation enabled.1: Output of transmit serial shifter is connected to input of receive serial shifter internally" "Normal serial port operation enabled,Output of transmit serial shifter is connected.."
|
|
line.long 0x08 "DR,Data16-bits wide data register:When read. the entry in the receive FIFO. pointed to by the current FIFO read pointer. is accessed"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "DATA,Transmit/receive dataThe values read from this field or written to this field must be right-justified when SSI is programmed for a data size that is less than 16 bits (CR0.DSS != 0b1111)"
|
|
line.long 0x0C "SR,Status"
|
|
hexmask.long 0x0C 5.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 4. "BSY,Serial interface busy:0: SSI is idle1: SSI is currently transmitting and/or receiving a frame or the transmit FIFO is not empty" "SSI is idle,SSI is currently transmitting.."
|
|
newline
|
|
bitfld.long 0x0C 3. "RFF,Receive FIFO full:0: Receive FIFO is not full.1: Receive FIFO is full" "Receive FIFO is not full,Receive FIFO is full"
|
|
newline
|
|
bitfld.long 0x0C 2. "RNE,Receive FIFO not empty0: Receive FIFO is empty.1: Receive FIFO is not empty" "Receive FIFO is empty,Receive FIFO is not empty"
|
|
newline
|
|
bitfld.long 0x0C 1. "TNF,Transmit FIFO not full:0: Transmit FIFO is full.1: Transmit FIFO is not full" "Transmit FIFO is full,Transmit FIFO is not full"
|
|
newline
|
|
bitfld.long 0x0C 0. "TFE,Transmit FIFO empty:0: Transmit FIFO is not empty.1: Transmit FIFO is empty" "Transmit FIFO is not empty,Transmit FIFO is empty"
|
|
line.long 0x10 "CPSR,Clock Prescale"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "CPSDVSR,Clock prescale divisor:This field specifies the division factor by which the input system clock to SSI must be internally divided before further use.The value programmed into this field must be an even non-zero number (2-254)"
|
|
line.long 0x14 "IMSC,Interrupt Mask Set and Clear"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3. "TXIM,Transmit FIFO interrupt mask:A read returns the current mask for transmit FIFO interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "RXIM,Receive FIFO interrupt mask:A read returns the current mask for receive FIFO interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "RTIM,Receive timeout interrupt mask:A read returns the current mask for receive timeout interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "RORIM,Receive overrun interrupt mask:A read returns the current mask for receive overrun interrupt" "0,1"
|
|
line.long 0x18 "RIS,Raw Interrupt Status"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 3. "TXRIS,Raw transmit FIFO interrupt status:The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "RXRIS,Raw interrupt state of receive FIFO interrupt:The receive interrupt is asserted when there are four or more valid entries in the receive FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "RTRIS,Raw interrupt state of receive timeout interrupt:The receive timeout interrupt is asserted when the receive FIFO is not empty and SSI has remained idle for a fixed 32 bit period" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "RORRIS,Raw interrupt state of receive overrun interrupt:The receive overrun interrupt is asserted when the FIFO is already full and an additional data frame is received causing an overrun of the FIFO" "0,1"
|
|
line.long 0x1C "MIS,Masked Interrupt Status"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 3. "TXMIS,Masked interrupt state of transmit FIFO interrupt:This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2. "RXMIS,Masked interrupt state of receive FIFO interrupt:This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "RTMIS,Masked interrupt state of receive timeout interrupt:This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "RORMIS,Masked interrupt state of receive overrun interrupt:This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM" "0,1"
|
|
line.long 0x20 "ICR,Interrupt ClearOn a write of 1. the corresponding interrupt is cleared"
|
|
hexmask.long 0x20 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 1. "RTIC,Clear the receive timeout interrupt:Writing 1 to this field clears the timeout interrupt (RIS.RTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "RORIC,Clear the receive overrun interrupt:Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS)" "0,1"
|
|
line.long 0x24 "DMACR,DMA Control"
|
|
hexmask.long 0x24 2.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 1. "TXDMAE,Transmit DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "RXDMAE,Receive DMA enable" "0,1"
|
|
repeat 2. (list 1. 2. )(list 0x00 0x68 )
|
|
rgroup.long ($2+0x28)++0x03
|
|
line.long 0x00 "RESERVED$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
tree.end
|
|
tree "TRNG"
|
|
base ad:0x40028000
|
|
rgroup.long 0x00++0x3B
|
|
line.long 0x00 "OUT0,Random Number Lower Word Readout Value"
|
|
line.long 0x04 "OUT1,Random Number Upper Word Readout Value"
|
|
line.long 0x08 "IRQFLAGSTAT,Interrupt Status"
|
|
bitfld.long 0x08 31. "NEED_CLOCK," "0,1"
|
|
hexmask.long 0x08 2.--30. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "SHUTDOWN_OVF," "0,1"
|
|
bitfld.long 0x08 0. "RDY," "0,1"
|
|
line.long 0x0C "IRQFLAGMASK,Interrupt Mask"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 1. "SHUTDOWN_OVF," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "RDY," "0,1"
|
|
line.long 0x10 "IRQFLAGCLR,Interrupt Flag Clear"
|
|
hexmask.long 0x10 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 1. "SHUTDOWN_OVF," "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "RDY," "0,1"
|
|
line.long 0x14 "CTL,Control"
|
|
abitfld.long 0x14 16.--31. "STARTUP_CYCLES,This field determines the number of samples (between 2^8 and 2^24) taken to gather entropy from the FROs during startup" "0x0000=2^24 samples,0x0001=1*2^8 samples,0x0002=2*2^8 samples,0x0003=3*2^8 samples,0x8000=32768*2^8 samples,0xC000=49152*2^8 samples,0xFFFF=65535*2^8 samplesThis field can only be.."
|
|
rbitfld.long 0x14 11.--15. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x14 10. "TRNG_EN," "0,1"
|
|
hexmask.long.byte 0x14 3.--9. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 2. "NO_LFSR_FB," "0,1"
|
|
bitfld.long 0x14 1. "TEST_MODE," "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x18 "CFG0,Configuration 0"
|
|
abitfld.long 0x18 16.--31. "MAX_REFILL_CYCLES,This field determines the maximum number of samples (between 2^8 and 2^24) taken to re-generate entropy from the FROs after reading out a 64 bits random number" "0x0000=2^24 samples,0x0001=1*2^8 samples,0x0002=2*2^8 samples,0x0003=3*2^8 samples,0x8000=32768*2^8 samples,0xC000=49152*2^8 samples,0xFFFF=65535*2^8 samplesThis field can only be.."
|
|
rbitfld.long 0x18 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "SMPL_DIV,This field directly controls the number of clock cycles between samples taken from the FROs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
abitfld.long 0x18 0.--7. "MIN_REFILL_CYCLES,This field determines the minimum number of samples (between 2^6 and 2^14) taken to re-generate entropy from the FROs after reading out a 64 bits random number" "0x00=Minimum samples = MAX_REFILL_CYCLES (all..,0x01=1*2^6 samples,0x02=2*2^6 samples,0xFF=255*2^6 samples"
|
|
line.long 0x1C "ALARMCNT,Alarm Control"
|
|
rbitfld.long 0x1C 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x1C 24.--29. "SHUTDOWN_CNT,Read-only indicates the number of '1' bits in ALARMSTOP register.The maximum value equals the number of FROs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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rbitfld.long 0x1C 21.--23. "RESERVED21,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 16.--20. "SHUTDOWN_THR,Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x1C 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x1C 0.--7. 1. "ALARM_THR,Alarm detection threshold for the repeating pattern detectors on each FRO"
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line.long 0x20 "FROEN,FRO Enable"
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hexmask.long.byte 0x20 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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|
hexmask.long.tbyte 0x20 0.--23. 1. "FRO_MASK,Enable bits for the individual FROs"
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|
line.long 0x24 "FRODETUNE,FRO De-tune Bit"
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hexmask.long.byte 0x24 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "FRO_MASK,De-tune bits for the individual FROs"
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line.long 0x28 "ALARMMASK,Alarm Event"
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|
hexmask.long.byte 0x28 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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|
hexmask.long.tbyte 0x28 0.--23. 1. "FRO_MASK,Logging bits for the 'alarm events' of individual FROs"
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line.long 0x2C "ALARMSTOP,Alarm Shutdown"
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hexmask.long.byte 0x2C 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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|
hexmask.long.tbyte 0x2C 0.--23. 1. "FRO_FLAGS,Logging bits for the 'alarm events' of individual FROs"
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line.long 0x30 "LFSR0,LFSR Readout Value"
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|
line.long 0x34 "LFSR1,LFSR Readout Value"
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line.long 0x38 "LFSR2,LFSR Readout Value"
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hexmask.long.word 0x38 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
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hexmask.long.tbyte 0x38 0.--16. 1. "LFSR_80_64,Bits [80:64] of the main entropy accumulation LFSR"
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rgroup.long 0x78++0x07
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line.long 0x00 "HWOPT,TRNG Engine Options Information"
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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bitfld.long 0x00 6.--11. "NR_OF_FROS,Number of FROs implemented in this TRNG value 24 (decimal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x04 "HWVER0,HW Version 0EIP Number And Core Revision"
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bitfld.long 0x04 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 24.--27. "HW_MAJOR_VER,4 bits binary encoding of the major hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 20.--23. "HW_MINOR_VER,4 bits binary encoding of the minor hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "HW_PATCH_LVL,4 bits binary encoding of the hardware patch level initial release will carry value zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x04 8.--15. 1. "EIP_NUM_COMPL,Bit-by-bit logic complement of bits [7:0]"
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hexmask.long.byte 0x04 0.--7. 1. "EIP_NUM,8 bits binary encoding of the module number"
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rgroup.long 0x1FD8++0x03
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line.long 0x00 "IRQSTATMASK,Interrupt Status After Masking"
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hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x00 1. "SHUTDOWN_OVF,Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with IRQFLAGMASK.SHUTDOWN_OVF)" "0,1"
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newline
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bitfld.long 0x00 0. "RDY,New random value available (result of IRQFLAGSTAT.RDY AND'ed with IRQFLAGMASK.RDY)" "0,1"
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rgroup.long 0x1FE0++0x03
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line.long 0x00 "HWVER1,HW Version 1TRNG Revision Number"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x00 0.--7. 1. "REV,The revision number of this module is Rev 2.0"
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group.long 0x1FEC++0x07
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line.long 0x00 "IRQSET,Interrupt Set"
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line.long 0x04 "SWRESET,SW Reset Control"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x04 0. "RESET,Write '1' to soft reset reset will be low for 4-5 clock cycles" "0,1"
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rgroup.long 0x1FF8++0x03
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line.long 0x00 "IRQSTAT,Interrupt Status"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x00 0. "STAT,TRNG Interrupt status" "0,1"
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tree.end
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tree "UART0"
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base ad:0x40001000
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group.long 0x00++0x07
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line.long 0x00 "DR,DataFor words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1). data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0). data is stored in the transmitter holding register (the bottom.."
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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rbitfld.long 0x00 11. "OE,UART Overrun Error:This bit is set to 1 if data is received and the receive FIFO is already full" "0,1"
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newline
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rbitfld.long 0x00 10. "BE,UART Break Error:This bit is set to 1 if a break condition was detected indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits).In FIFO mode.." "0,1"
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newline
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rbitfld.long 0x00 9. "PE,UART Parity Error:When set to 1 it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select.In FIFO mode this error is associated with the character at the top of the FIFO (that is the.." "0,1"
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newline
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rbitfld.long 0x00 8. "FE,UART Framing Error:When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).In FIFO mode this error is associated with the character at the top of the FIFO (that is. the oldest received data.." "0,1"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DATA,Data transmitted or received:On writes the transmit data character is pushed into the FIFO.On reads the oldest received data character since the last read is returned"
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line.long 0x04 "RSR,StatusThis register is mapped to the same address as ECR register"
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hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 3. "OE,UART Overrun Error:This bit is set to 1 if data is received and the receive FIFO is already full" "0,1"
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newline
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bitfld.long 0x04 2. "BE,UART Break Error:This bit is set to 1 if a break condition was detected indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits).When a break.." "0,1"
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newline
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bitfld.long 0x04 1. "PE,UART Parity Error:When set to 1 it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select" "0,1"
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newline
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bitfld.long 0x04 0. "FE,UART Framing Error:When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1)" "0,1"
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wgroup.long 0x04++0x03
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line.long 0x00 "ECR,Error ClearThis register is mapped to the same address as RSR register"
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hexmask.long 0x00 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 3. "OE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
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newline
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bitfld.long 0x00 2. "BE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
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newline
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bitfld.long 0x00 1. "PE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
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newline
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bitfld.long 0x00 0. "FE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
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repeat 5. (list 0. 2. 1. 3. 4. )(list 0x00 0x14 0x44 0x88 0xFC8 )
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rgroup.long ($2+0x08)++0x03
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line.long 0x00 "RESERVED$1,Software should not rely on the value of a reserved"
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repeat.end
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rgroup.long 0x18++0x03
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line.long 0x00 "FR,FlagReads from this register return the UART flags"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 7. "TXFE,UART Transmit FIFO Empty:The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled this bit is set when the transmit holding register is empty. - If the FIFO is enabled this bit is set when the transmit FIFO is empty.This.." "0,1"
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newline
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bitfld.long 0x00 6. "RXFF,UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled this bit is set when the receive holding register is full. - If the FIFO is enabled this bit is set when the receive FIFO is full" "0,1"
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newline
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bitfld.long 0x00 5. "TXFF,UART Transmit FIFO Full:Transmit FIFO full" "0,1"
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newline
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bitfld.long 0x00 4. "RXFE,UART Receive FIFO Empty:Receive FIFO empty" "0,1"
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newline
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bitfld.long 0x00 3. "BUSY,UART Busy: If this bit is set to 1 the UART is busy transmitting data" "0,1"
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newline
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bitfld.long 0x00 1.--2. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 0. "CTS,Clear To Send: This bit is the complement of the active-low UART CTS input pin.That is the bit is 1 when CTS input pin is LOW" "0,1"
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group.long 0x24++0x27
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line.long 0x00 "IBRD,Integer Baud-Rate DivisorIf this register is modified while transmission or reception is on-going. the baud rate will not be updated until transmission or reception of the current character is complete"
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hexmask.long.word 0x00 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x00 0.--15. 1. "DIVINT,The integer baud rate divisor:The baud rate divisor is calculated using the formula below:Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)Baud rate divisor must be minimum 1 and maximum 65535"
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line.long 0x04 "FBRD,Fractional Baud-Rate DivisorIf this register is modified while trasmission or reception is on-going. the baudrate will not be updated until transmission or reception of the current character is complete"
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hexmask.long 0x04 6.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0.--5. "DIVFRAC,Fractional Baud-Rate Divisor:The baud rate divisor is calculated using the formula below:Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)Baud rate divisor must be minimum 1 and maximum 65535" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x08 "LCRH,Line Control"
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hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 7. "SPS,UART Stick Parity Select:0: Stick parity is disabled1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0).This bit has no effect when PEN disables parity checking and.." "Stick parity is disabled,The parity bit is transmitted and checked as.."
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newline
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bitfld.long 0x08 5.--6. "WLEN,UART Word Length:These bits indicate the number of data bits transmitted or received in a frame" "Word Length 5 bits,Word Length 6 bits,Word Length 7 bits,Word Length 8 bits"
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newline
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bitfld.long 0x08 4. "FEN,UART Enable FIFOs" "FIFOs are disabled (character mode) that is the..,Transmit and receive FIFO buffers are enabled.."
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newline
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bitfld.long 0x08 3. "STP2,UART Two Stop Bits Select:If this bit is set to 1 two stop bits are transmitted at the end of the frame" "0,1"
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newline
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bitfld.long 0x08 2. "EPS,UART Even Parity Select" "Odd parity: The UART generates or checks for an..,Even parity: The UART generates or checks for an.."
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newline
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bitfld.long 0x08 1. "PEN,UART Parity EnableThis bit controls generation and checking of parity bit" "Parity is disabled and no parity bit is added to..,Parity checking and generation is enabled."
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newline
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bitfld.long 0x08 0. "BRK,UART Send BreakIf this bit is set to 1 a low-level is continually output on the UARTTXD output pin after completing transmission of the current character" "0,1"
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line.long 0x0C "CTL,Control"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 15. "CTSEN,CTS hardware flow control enable" "CTS hardware flow control disabled,CTS hardware flow control enabled"
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newline
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bitfld.long 0x0C 14. "RTSEN,RTS hardware flow control enable" "RTS hardware flow control disabled,RTS hardware flow control enabled"
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newline
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bitfld.long 0x0C 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x0C 11. "RTS,Request to SendThis bit is the complement of the active-low UART RTS output" "0,1"
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newline
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bitfld.long 0x0C 10. "RESERVED10,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x0C 9. "RXE,UART Receive EnableIf the UART is disabled in the middle of reception it completes the current character before stopping" "UART Receive disabled,UART Receive enabled"
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newline
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bitfld.long 0x0C 8. "TXE,UART Transmit EnableIf the UART is disabled in the middle of transmission it completes the current character before stopping" "UART Transmit disabled,UART Transmit enabled"
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newline
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bitfld.long 0x0C 7. "LBE,UART Loop Back Enable:Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART" "Loop Back disabled,Loop Back enabled"
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newline
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bitfld.long 0x0C 1.--6. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x0C 0. "UARTEN,UART Enable" "UART disabled,UART enabled"
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line.long 0x10 "IFLS,Interrupt FIFO Level Select"
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hexmask.long 0x10 6.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 3.--5. "RXSEL,Receive interrupt FIFO level select:This field sets the trigger points for the receive interrupt" "Receive FIFO becomes >= 1/8 full,Receive FIFO becomes >= 1/4 full,Receive FIFO becomes >= 1/2 full,Receive FIFO becomes >= 3/4 full,Receive FIFO becomes >= 7/8 full,?,?,?"
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newline
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bitfld.long 0x10 0.--2. "TXSEL,Transmit interrupt FIFO level select:This field sets the trigger points for the transmit interrupt" "Transmit FIFO becomes <= 1/8 full,Transmit FIFO becomes <= 1/4 full,Transmit FIFO becomes <= 1/2 full,Transmit FIFO becomes <= 3/4 full,Transmit FIFO becomes <= 7/8 full,?,?,?"
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line.long 0x14 "IMSC,Interrupt Mask Set/Clear"
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hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 11. "EOTIM,End of Transmission interrupt mask" "0,1"
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newline
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bitfld.long 0x14 10. "OEIM,Overrun error interrupt mask" "0,1"
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newline
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bitfld.long 0x14 9. "BEIM,Break error interrupt mask" "0,1"
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newline
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bitfld.long 0x14 8. "PEIM,Parity error interrupt mask" "0,1"
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newline
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bitfld.long 0x14 7. "FEIM,Framing error interrupt mask" "0,1"
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newline
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bitfld.long 0x14 6. "RTIM,Receive timeout interrupt mask" "0,1"
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newline
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bitfld.long 0x14 5. "TXIM,Transmit interrupt mask" "0,1"
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newline
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bitfld.long 0x14 4. "RXIM,Receive interrupt mask" "0,1"
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newline
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bitfld.long 0x14 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
|
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bitfld.long 0x14 1. "CTSMIM,Clear to Send (CTS) modem interrupt mask" "0,1"
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newline
|
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bitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x18 "RIS,Raw Interrupt Status"
|
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hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x18 11. "EOTRIS,End of Transmission interrupt status: This field returns the raw interrupt state of UART's end of transmission interrupt" "0,1"
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newline
|
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bitfld.long 0x18 10. "OERIS,Overrun error interrupt status: This field returns the raw interrupt state of UART's overrun error interrupt" "0,1"
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|
newline
|
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bitfld.long 0x18 9. "BERIS,Break error interrupt status:This field returns the raw interrupt state of UART's break error interrupt" "0,1"
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newline
|
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bitfld.long 0x18 8. "PERIS,Parity error interrupt status:This field returns the raw interrupt state of UART's parity error interrupt" "0,1"
|
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newline
|
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bitfld.long 0x18 7. "FERIS,Framing error interrupt status:This field returns the raw interrupt state of UART's framing error interrupt" "0,1"
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|
newline
|
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bitfld.long 0x18 6. "RTRIS,Receive timeout interrupt status:This field returns the raw interrupt state of UART's receive timeout interrupt" "0,1"
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newline
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bitfld.long 0x18 5. "TXRIS,Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt.When FIFOs are enabled (LCRH.FEN = 1) the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the.." "0,1"
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newline
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bitfld.long 0x18 4. "RXRIS,Receive interrupt status:This field returns the raw interrupt state of UART's receive interrupt" "0,1"
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newline
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bitfld.long 0x18 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x18 1. "CTSRMIS,Clear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of UART's clear to send interrupt" "0,1"
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newline
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bitfld.long 0x18 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
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line.long 0x1C "MIS,Masked Interrupt Status"
|
|
hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 11. "EOTMIS,End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM" "0,1"
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newline
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bitfld.long 0x1C 10. "OEMIS,Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 9. "BEMIS,Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8. "PEMIS,Parity error masked interrupt status:This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "FEMIS,Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "RTMIS,Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt.The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "TXMIS,Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "RXMIS,Receive masked interrupt status:This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 1. "CTSMMIS,Clear to Send (CTS) modem masked interrupt status:This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x20 "ICR,Interrupt ClearOn a write of 1. the corresponding interrupt is cleared"
|
|
hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 11. "EOTIC,End of Transmission interrupt clear:Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 10. "OEIC,Overrun error interrupt clear:Writing 1 to this field clears the overrun error interrupt (RIS.OERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 9. "BEIC,Break error interrupt clear:Writing 1 to this field clears the break error interrupt (RIS.BERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "PEIC,Parity error interrupt clear:Writing 1 to this field clears the parity error interrupt (RIS.PERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "FEIC,Framing error interrupt clear:Writing 1 to this field clears the framing error interrupt (RIS.FERIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 6. "RTIC,Receive timeout interrupt clear:Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 5. "TXIC,Transmit interrupt clear:Writing 1 to this field clears the transmit interrupt (RIS.TXRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "RXIC,Receive interrupt clear:Writing 1 to this field clears the receive interrupt (RIS.RXRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 1. "CTSMIC,Clear to Send (CTS) modem interrupt clear:Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x24 "DMACTL,DMA Control"
|
|
hexmask.long 0x24 3.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 2. "DMAONERR,DMA on error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "TXDMAE,Transmit DMA enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "RXDMAE,Receive DMA enable" "0,1"
|
|
tree.end
|
|
tree "UDMA0"
|
|
base ad:0x40020000
|
|
rgroup.long 0x00++0x3F
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 28.--31. "TEST," "Controller does not include the integration test..,Controller includes the integration test logic,Undefined,?,?,?,?,?,?,?,?,?,?,?,?,Undefined"
|
|
hexmask.long.byte 0x00 21.--27. 1. "RESERVED21,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TOTALCHANNELS,Register value returns number of available uDMA channels minus one" "Show that the controller is configured to use 1..,Shows that the controller is configured to use 2..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Shows that the controller is configured to use.."
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "STATE,Current state of the control state machine" "Idle,Reading channel controller data,Reading source data end pointer,Reading destination data end pointer,Reading source data,Writing destination data,Waiting for uDMA request to clear,Writing channel controller data,Stalled,Done,Peripheral scatter-gather transition,Undefined,?,?,?,Undefined"
|
|
bitfld.long 0x00 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTERENABLE,Shows the enable status of the controller as configured by CFG.MASTERENABLE:0: Controller is disabled1: Controller is enabled" "Controller is disabled,Controller is enabled"
|
|
line.long 0x04 "CFG,Configuration"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5.--7. "PRTOCTRL,Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows:Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring.Bit [6] Controls HProt[2] to indicate if a bufferable access is.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 1.--4. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0. "MASTERENABLE,Enables the controller:0: Disables the controller1: Enables the controller" "Disables the controller,Enables the controller"
|
|
line.long 0x08 "CTRL,Channel Control Data Base Pointer"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "BASEPTR,This register point to the base address for the primary data structures of each DMA channel"
|
|
hexmask.long.word 0x08 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "ALTCTRL,Channel Alternate Control Data Base Pointer"
|
|
line.long 0x10 "WAITONREQ,Channel Wait On Request Status"
|
|
line.long 0x14 "SOFTREQ,Channel Software Request"
|
|
line.long 0x18 "SETBURST,Channel Set UseBurst"
|
|
line.long 0x1C "CLEARBURST,Channel Clear UseBurst"
|
|
line.long 0x20 "SETREQMASK,Channel Set Request Mask"
|
|
line.long 0x24 "CLEARREQMASK,Clear Channel Request Mask"
|
|
line.long 0x28 "SETCHANNELEN,Set Channel Enable"
|
|
line.long 0x2C "CLEARCHANNELEN,Clear Channel Enable"
|
|
line.long 0x30 "SETCHNLPRIALT,Channel Set Primary-Alternate"
|
|
line.long 0x34 "CLEARCHNLPRIALT,Channel Clear Primary-Alternate"
|
|
line.long 0x38 "SETCHNLPRIORITY,Set Channel Priority"
|
|
line.long 0x3C "CLEARCHNLPRIORITY,Clear Channel Priority"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ERROR,Error Status and Clear"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STATUS,Returns the status of bus error flag in uDMA or clears this bit Read as:0: No bus error detected1: Bus error detectedWrite as:0: No effect status of bus error flag is unchanged.1: Clears the bus error flag" "No effect status of bus error flag is unchanged,Clears the bus error flag"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "REQDONE,Channel Request Done"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "DONEMASK,Channel Request Done Mask"
|
|
tree.end
|
|
tree "VIMS"
|
|
base ad:0x40034000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "STAT,StatusDisplays current VIMS mode and line buffer status"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 5. "IDCODE_LB_DIS,Icode/Dcode flash line buffer status0: Enabled or in transition to disabled1: Disabled and flushed" "Enabled or in transition to disabled,Disabled and flushed"
|
|
newline
|
|
bitfld.long 0x00 4. "SYSBUS_LB_DIS,Sysbus flash line buffer control0: Enabled or in transition to disabled1: Disabled and flushed" "Enabled or in transition to disabled,Disabled and flushed"
|
|
bitfld.long 0x00 3. "MODE_CHANGING,VIMS mode change status0: VIMS is in the mode defined by MODE1: VIMS is in the process of changing to the mode given in CTL.MODE" "VIMS is in the mode defined by MODE,VIMS is in the process of changing to the mode.."
|
|
newline
|
|
bitfld.long 0x00 2. "INV,This bit is set when invalidation of the cache memory is active / ongoing" "0,1"
|
|
bitfld.long 0x00 0.--1. "MODE,Current VIMS mode" "VIMS GPRAM mode,VIMS Cache mode,?,VIMS Off mode"
|
|
line.long 0x04 "CTL,ControlConfigure VIMS mode and line buffer settings"
|
|
bitfld.long 0x04 31. "STATS_CLR,Set this bit to clear statistic counters" "0,1"
|
|
bitfld.long 0x04 30. "STATS_EN,Set this bit to enable statistic counters" "0,1"
|
|
newline
|
|
bitfld.long 0x04 29. "DYN_CG_EN," "0,1"
|
|
hexmask.long.tbyte 0x04 6.--28. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "IDCODE_LB_DIS,Icode/Dcode flash line buffer control0: Enable1: Disable" "Enable,Disable"
|
|
bitfld.long 0x04 4. "SYSBUS_LB_DIS,Sysbus flash line buffer control0: Enable1: Disable" "Enable,Disable"
|
|
newline
|
|
bitfld.long 0x04 3. "ARB_CFG,Icode/Dcode and sysbus arbitation scheme0: Static arbitration (icode/docde > sysbus)1: Round-robin arbitration" "Static arbitration (icode/docde > sysbus),Round-robin arbitration"
|
|
bitfld.long 0x04 2. "PREF_EN,Tag prefetch control0: Disabled1: Enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "MODE,VIMS mode request.Write accesses to this field will be blocked while STAT.MODE_CHANGING is set to 1" "VIMS GPRAM mode,VIMS Cache mode,?,VIMS Off mode"
|
|
tree.end
|
|
tree "WDT"
|
|
base ad:0x40080000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "LOAD,Configuration"
|
|
line.long 0x04 "VALUE,Current Count Value"
|
|
line.long 0x08 "CTL,Control"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 2. "INTTYPE,WDT Interrupt Type0: WDT interrupt is a standard interrupt" "WDT interrupt is a standard interrupt,WDT interrupt is a non-maskable interrupt"
|
|
newline
|
|
bitfld.long 0x08 1. "RESEN,WDT Reset Enable" "Disabled,Enable the Watchdog.."
|
|
bitfld.long 0x08 0. "INTEN,WDT Interrupt Enable0: Interrupt event disabled" "Interrupt event disabled,Interrupt event enabled"
|
|
line.long 0x0C "ICR,Interrupt Clear"
|
|
line.long 0x10 "RIS,Raw Interrupt Status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "WDTRIS,This register is the raw interrupt status register" "The WDT has not timed out,A WDT time-out event has occurred"
|
|
line.long 0x14 "MIS,Masked Interrupt Status"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "WDTMIS,This register is the masked interrupt status register" "The WDT has not timed out or is masked,An unmasked WDT time-out event has occurred"
|
|
group.long 0x418++0x07
|
|
line.long 0x00 "TEST,Test Mode"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "STALL,WDT Stall Enable0: The WDT timer continues counting if the CPU is stopped with a debugger.1: If the CPU is stopped with a debugger the WDT stops counting" "The WDT timer continues counting if the CPU is..,If the CPU is stopped with a debugger the WDT.."
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "TEST_EN,The test enable bit" "Enable external reset,Disables the generation of an external reset"
|
|
line.long 0x04 "INT_CAUS,Interrupt Cause Test Mode"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 1. "CAUSE_RESET,Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "CAUSE_INTR,Replica of RIS.WDTRIS" "0,1"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "LOCK,Lock"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("CC2653P10")||cpuis("CC2674P10")||cpuis("CC2674R10"))
|
|
tree "AON"
|
|
tree "AON_BATMON"
|
|
base ad:0x40095000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTL,Internal"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Internal"
|
|
bitfld.long 0x00 1. "CALC_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MEAS_EN,Internal" "0,1"
|
|
line.long 0x04 "MEASCFG,Internal"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Internal"
|
|
bitfld.long 0x04 0.--1. "PER,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
group.long 0x0C++0x2B
|
|
line.long 0x00 "TEMPP0,Internal"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Internal"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CFG,Internal"
|
|
line.long 0x04 "TEMPP1,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x04 0.--5. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "TEMPP2,Internal"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED5,Internal"
|
|
bitfld.long 0x08 0.--4. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "BATMONP0,Internal"
|
|
hexmask.long 0x0C 7.--31. 1. "RESERVED6,Internal"
|
|
hexmask.long.byte 0x0C 0.--6. 1. "CFG,Internal"
|
|
line.long 0x10 "BATMONP1,Internal"
|
|
hexmask.long 0x10 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x10 0.--5. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "IOSTRP0,Internal"
|
|
hexmask.long 0x14 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x14 4.--5. "CFG2,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--3. "CFG1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "FLASHPUMPP0,Internal"
|
|
hexmask.long.tbyte 0x18 10.--31. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x18 9. "DIS_NOISE_FILTER,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "FALLB,Internal" "0,1"
|
|
bitfld.long 0x18 6.--7. "HIGHLIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 5. "LOWLIM,Internal" "0,1"
|
|
bitfld.long 0x18 4. "OVR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "CFG,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "BAT,Last Measured Battery VoltageThis register may be read while BATUPD.STAT = 1"
|
|
hexmask.long.tbyte 0x1C 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x1C 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x20 "BATUPD,Battery UpdateIndicates BAT Updates"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT," "No update since last clear,New battery voltage is present.Write 1 to clear.."
|
|
line.long 0x24 "TEMP,TemperatureLast Measured Temperature in Degrees CelsiusThis register may be read while TEMPUPD.STAT = 1."
|
|
hexmask.long.word 0x24 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x24 8.--16. "INT,Integer part (signed) of temperature value" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x28 "TEMPUPD,Temperature UpdateIndicates TEMP Updates"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "STAT," "No update since last clear,New temperature is present.Write 1 to clear the.."
|
|
group.long 0x48++0x17
|
|
line.long 0x00 "EVENTMASK,Event Mask"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 5. "TEMP_UPDATE_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "BATT_UPDATE_MASK," "0,1"
|
|
bitfld.long 0x00 3. "TEMP_BELOW_LL_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TEMP_OVER_UL_MASK," "0,1"
|
|
bitfld.long 0x00 1. "BATT_BELOW_LL_MASK," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "BATT_OVER_UL_MASK," "0,1"
|
|
line.long 0x04 "EVENT,Event"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5. "TEMP_UPDATE,Alias to TEMPUPD.STAT" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "BATT_UPDATE,Alias to BATUPD.STAT" "0,1"
|
|
bitfld.long 0x04 3. "TEMP_BELOW_LL,Read:1: Temperature level is below the lower limit set by TEMPLL.0: Temperature level is not below the lower limit set by TEMPLL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
newline
|
|
bitfld.long 0x04 2. "TEMP_OVER_UL,Read:1: Temperature level is above the upper limit set by TEMPUL.0: Temperature level is not above the upper limit set by TEMPUL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
bitfld.long 0x04 1. "BATT_BELOW_LL,Read:1: Battery level is below the lower limit set by BATTLL.0: Battery level is not below the lower limit set by BATTLL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
newline
|
|
bitfld.long 0x04 0. "BATT_OVER_UL,Read:1: Battery level is above the upper limit set by BATTUL.0: Battery level is not above the upper limit set by BATTUL.Write:1: Clears the flag0: No change in the flag" "No change in the flag,Clears the flag"
|
|
line.long 0x08 "BATTUL,Battery Upper Limit"
|
|
hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
|
|
newline
|
|
abitfld.long 0x08 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x0C "BATTLL,Battery Lower Limit"
|
|
hexmask.long.tbyte 0x0C 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 8.--10. "INT,Integer part:0x0: 0V + fractional part...0x3: 3V + fractional part0x4: 4V + fractional part" "0V + fractional part,?,?,3V + fractional part,4V + fractional part,?..."
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|
newline
|
|
abitfld.long 0x0C 0.--7. "FRAC,Fractional part standard binary fractional" "0x00=.0V,0x20=1/8 = .125V,0x40=1/4 = .25V,0x80=1/2 = .5V,0xA0=1/2 + 1/8 = .625V,0xFF=Max"
|
|
line.long 0x10 "TEMPUL,Temperature Upper Limit"
|
|
hexmask.long.word 0x10 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x10 8.--16. "INT,Integer part (signed) of temperature upper limit" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
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|
newline
|
|
bitfld.long 0x10 6.--7. "FRAC,Fractional part of temperature upper limit.Total value = INTEGER + FRACTIONALThe encoding is an extension of the 2's complement encoding.00" "0.0C,0.25C,?..."
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|
rbitfld.long 0x10 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "TEMPLL,Temperature Lower Limit"
|
|
hexmask.long.word 0x14 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
abitfld.long 0x14 8.--16. "INT,Integer part (signed) of temperature lower limit" "0x000=0C,0x01B=27C,0x055=85C,0x0FF=Max value,0x100=Min value,0x1D8=-40C,0x1FF=-1C"
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|
newline
|
|
bitfld.long 0x14 6.--7. "FRAC,Fractional part of temperature lower limit.Total value = INTEGER + FRACTIONALThe encoding is an extension of the 2's complement encoding.00" "0.0C,0.25C,?..."
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|
rbitfld.long 0x14 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "AON_EVENT"
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|
base ad:0x40093000
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "MCUWUSEL,Wake-up Selector For MCUThis register contains pointers to 4 of 8 events (events 0 to 3) which are routed to AON_PMCTRL as wakeup sources for MCU"
|
|
rbitfld.long 0x00 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x00 24.--29. "WU3_EV,MCU Wakeup Source #3AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
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|
newline
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rbitfld.long 0x00 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "WU2_EV,MCU Wakeup Source #2AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
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|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "WU1_EV,MCU Wakeup Source #1AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "WU0_EV,MCU Wakeup Source #0AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
line.long 0x04 "MCUWUSEL1,Wake-up Selector For MCUThis register contains pointers to 4 of 8 events (events 4 to 7) which are routed to AON_PMCTRL as wakeup sources for MCU"
|
|
rbitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x04 24.--29. "WU7_EV,MCU Wakeup Source #7AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
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|
newline
|
|
rbitfld.long 0x04 22.--23. "RESERVED22,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 16.--21. "WU6_EV,MCU Wakeup Source #6AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
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|
newline
|
|
rbitfld.long 0x04 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 8.--13. "WU5_EV,MCU Wakeup Source #5AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "WU4_EV,MCU Wakeup Source #4AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up the MCU domain from Power Off or Power Down.Note: " "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
line.long 0x08 "EVTOMCUSEL,Event Selector For MCU Event Fabric This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT"
|
|
hexmask.long.word 0x08 22.--31. 1. "RESERVED22,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 16.--21. "AON_PROG2_EV,Event selector for AON_PROG2 event.AON Event Source id# selecting event routed to EVENT as AON_PROG2 event." "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,RTC channel 1 - delayed event,RTC channel 2 - delayed event,RTC combined delayed event,RTC Update Tick (16 kHz signal i.e. event line..,JTAG generated event,AUX Software triggered event #0. Triggered by..,AUX Software triggered event #1. Triggered by..,AUX Software triggered event #2. Triggered by..,Comparator A triggered,Comparator B triggered,ADC conversion completed,TDC completed or timed out,AUX Timer 0 Event,AUX Timer 1 Event,BATMON temperature update event,BATMON voltage update event,Comparator B triggered. Asynchronous signal..,Comparator B not triggered. Asynchronous signal..,?,?,?,?,?,?,No event always low"
|
|
newline
|
|
rbitfld.long 0x08 14.--15. "RESERVED14,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 8.--13. "AON_PROG1_EV,Event selector for AON_PROG1 event.AON Event Source id# selecting event routed to EVENT as AON_PROG1 event." "Edge detect IO event from the DIO(s) which have..,Event 0 from AUX TImer2,Event 1 from AUX TImer2,Event 2 from AUX TImer2,Event 3 from AUX TImer2,BATMON event: Battery level above upper limit,BATMON event: Battery level below lower limit,BATMON event: Temperature level above upper limit,BATMON event: Temperature level below lower limit,Combined event from BATMON,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Edge detect on any PAD,?,?,RTC channel 0 event,RTC channel 1 event,RTC channel 2 event,RTC channel 0 - delayed event,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
|
|
newline
|
|
rbitfld.long 0x08 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "AON_PROG0_EV,Event selector for AON_PROG0 event.AON Event Source id# selecting event routed to EVENT as AON_PROG0 event." "Edge detect IO event from the DIO(s) which have..,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,0,?,?,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
|
|
line.long 0x0C "RTCSEL,RTC Capture Event Selector For AON_RTCThis register contains a pointer to select an AON event for RTC capture"
|
|
hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0.--5. "RTC_CH1_CAPT_EV,AON Event Source id# for RTCSEL event which is fed to AON_RTC" "Edge detect IO event from the DIO(s) which have..,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,0,?,?,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,?,?,?,?,?,?,0"
|
|
tree.end
|
|
tree "AON_IOC"
|
|
base ad:0x40094000
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "IOSTRMIN,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x00 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "IOSTRMED,Internal"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x04 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "IOSTRMAX,Internal"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x08 0.--2. "GRAY_CODE,Internal" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CLK32KCTL,SCLK_LF External Output Control"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "OE_N," "0,1"
|
|
line.long 0x04 "TCKCTL,TCK IO Pin Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "EN," "0,1"
|
|
tree.end
|
|
tree "AON_PMCTL"
|
|
base ad:0x58090000
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "AUXSCECLK,AUX SCE Clock ManagementThis register contains bitfields that are relevant for setting up the clock to the AUX domain"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "PD_SRC,Selects the clock source for the AUX domain when AUX is in powerdown mode.Note: Switching the clock source is guaranteed to be glitch-free" "No clock,LF clock (SCLK_LF )"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "SRC,Selects the clock source for the AUX domain when AUX is in active mode.Note: Switching the clock source is guaranteed to be glitch-free" "HF Clock divided by 2 (SCLK_HFDIV2),MF Clock (SCLK_MF)"
|
|
line.long 0x04 "RAMCFG,RAM ConfigurationThis register contains power management related configuration for the SRAM in the MCU and AUX domain"
|
|
hexmask.long.word 0x04 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 17. "AUX_SRAM_PWR_OFF,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "AUX_SRAM_RET_EN,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 4.--15. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--3. "BUS_SRAM_RET_EN,MCU SRAM is partitioned into 8 banks" "Retention is disabled,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,?,?,Retention on for BANK[0]: BANK[1]: BANK[2]:..,?,?,?,?,?,?,?,Retention on for all banks BANK[0]: BANK[1]:.."
|
|
group.long 0x10++0x1F
|
|
line.long 0x00 "PWRCTL,Power Management ControlThis register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDC_ACTIVE,Select to use DCDC regulator for VDDR in active mode" "Use GLDO for regulation of VDDR in active mode,Use DCDC for regulation of VDDR in active mode"
|
|
newline
|
|
bitfld.long 0x00 1. "EXT_REG_MODE,Status of source for VDDRsupply:0: DCDC or GLDO are generating VDDR1: DCDC and GLDO are bypassed and an external regulator supplies VDDR" "DCDC or GLDO are generating VDDR,DCDC and GLDO are bypassed and an external.."
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|
newline
|
|
bitfld.long 0x00 0. "DCDC_EN,Select to use DCDC regulator during recharge of VDDR0: Use GLDO for recharge of VDDR1: Use DCDC for recharge of VDDRNote: This bitfield should be set to the same as DCDC_ACTIVE" "Use GLDO for recharge of VDDR,Use DCDC for recharge of VDDR"
|
|
line.long 0x04 "PWRSTAT,AON Power and Reset StatusThis register is used to monitor various power management related signals in AON"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x04 2. "JTAG_PD_ON,Indicates JTAG power state:0: JTAG is powered off1: JTAG is powered on" "JTAG is powered off,JTAG is powered on"
|
|
newline
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bitfld.long 0x04 1. "AUX_BUS_RESET_DONE,Indicates Reset Done from AUX Bus:0: AUX Bus is being reset1: AUX Bus reset is released" "AUX Bus is being reset,AUX Bus reset is released"
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|
newline
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bitfld.long 0x04 0. "AUX_RESET_DONE,Indicates Reset Done from AUX:0: AUX is being reset1: AUX reset is released" "AUX is being reset,AUX reset is released"
|
|
line.long 0x08 "SHUTDOWN,Shutdown ControlThis register contains bitfields required for entering shutdown mode"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 0. "EN,Shutdown control.0: Do not write 0 to this bit" "Do not write 0 to this bit,Immediately start the process to enter shutdown.."
|
|
line.long 0x0C "RECHARGECFG,Recharge Controller ConfigurationThis register sets all relevant parameters for controlling the recharge algorithm"
|
|
bitfld.long 0x0C 30.--31. "MODE,Selects recharge algorithm for VDDR when the system is running on the uLDO" "Recharge disabled,Static timer,Adaptive timer,External recharge comparator. Note that the.."
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rbitfld.long 0x0C 24.--29. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 20.--23. "C2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "C1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 11.--15. "MAX_PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 8.--10. "MAX_PER_E,Internal" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 3.--7. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--2. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
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line.long 0x10 "RECHARGESTAT,Recharge Controller StatusThis register controls various status registers which are updated during recharge"
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hexmask.long.word 0x10 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 16.--19. "VDDR_SMPLS,The last 4 VDDR samples.For each bit:0: VDDR was below VDDR_OK threshold when recharge started1: VDDR was above VDDR_OK threshold when recharge startedThe register is updated prior to every recharge period with a shift left and bit 0 is.." "VDDR was below VDDR_OK threshold when recharge..,VDDR was above VDDR_OK threshold when recharge..,?..."
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hexmask.long.word 0x10 0.--15. 1. "MAX_USED_PER,Shows the maximum number of 32kHz periods that have separated two recharge cycles and VDDR still was above VDDR_OK threshold when the latter recharge started"
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line.long 0x14 "OSCCFG,Oscillator ConfigurationThis register sets the period for Amplitude compensation requests sent to the oscillator control system"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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bitfld.long 0x14 3.--7. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x14 0.--2. "PER_E,Internal" "0,1,2,3,4,5,6,7"
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line.long 0x18 "RESETCTL,Reset ManagementThis register contains bitfields related to system reset such as reset source and reset request and control of brown out resets"
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bitfld.long 0x18 31. "SYSRESET,Cold reset register" "No effect,Generate system reset"
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rbitfld.long 0x18 26.--30. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 25. "BOOT_DET_1_CLR,Internal" "0,1"
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newline
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bitfld.long 0x18 24. "BOOT_DET_0_CLR,Internal" "0,1"
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newline
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rbitfld.long 0x18 18.--23. "RESERVED18,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x18 17. "BOOT_DET_1_SET,Internal" "0,1"
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newline
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bitfld.long 0x18 16. "BOOT_DET_0_SET,Internal" "0,1"
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newline
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bitfld.long 0x18 15. "WU_FROM_SD,A Wakeup from SHUTDOWN on an IO event has occurred or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached" "Wakeup occurred from cold reset or brown out as..,A wakeup has occurred from SHUTDOWN"
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newline
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bitfld.long 0x18 14. "GPIO_WU_FROM_SD,A wakeup from SHUTDOWN on an IO event has occurred Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources.0: The wakeup did not occur from SHUTDOWN on an IO event1: A wakeup from SHUTDOWN occurred from an IO.." "The wakeup did not occur from SHUTDOWN on an IO..,A wakeup from SHUTDOWN occurred from an IO.."
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newline
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rbitfld.long 0x18 13. "BOOT_DET_1,Internal" "0,1"
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newline
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rbitfld.long 0x18 12. "BOOT_DET_0,Internal" "0,1"
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newline
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bitfld.long 0x18 9.--11. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x18 8. "VDDS_LOSS_EN,Controls reset generation in case VDDS is lost0: Brown out detect of VDDS is ignored unless VDDS_LOSS_EN_OVR=11: Brown out detect of VDDS generates system reset " "Brown out detect of VDDS is ignored unless..,Brown out detect of VDDS generates system reset"
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newline
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bitfld.long 0x18 7. "VDDR_LOSS_EN,Controls reset generation in case VDDR is lost0: Brown out detect of VDDR is ignored unless VDDR_LOSS_EN_OVR=11: Brown out detect of VDDR generates system reset" "Brown out detect of VDDR is ignored unless..,Brown out detect of VDDR generates system reset"
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newline
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bitfld.long 0x18 6. "VDD_LOSS_EN,Controls reset generation in case VDD is lost0: Brown out detect of VDD is ignored unless VDD_LOSS_EN_OVR=11: Brown out detect of VDD generates system reset" "Brown out detect of VDD is ignored unless..,Brown out detect of VDD generates system reset"
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newline
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bitfld.long 0x18 5. "CLK_LOSS_EN,Controls reset generation in case SCLK_LF SCLK_MF or SCLK_HF is lost when clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]0: Clock loss is ignored1: Clock loss generates system resetNote: Clock loss reset.." "Clock loss is ignored,Clock loss generates system reset"
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newline
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bitfld.long 0x18 4. "MCU_WARM_RESET,Internal" "0,1"
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|
newline
|
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rbitfld.long 0x18 1.--3. "RESET_SRC,Shows the root cause of the last system reset" "Power on reset,Reset pin,Brown out detect on VDDS,?,Brown out detect on VDDR,SCLK_LF SCLK_MF or SCLK_HF clock loss detect,Software reset via SYSRESET or hardware power..,Software reset via PRCM warm reset request"
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newline
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rbitfld.long 0x18 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x1C "SLEEPCTL,Sleep ControlThis register is used to unfreeze the IO pad ring after waking up from SHUTDOWN"
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hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 0. "IO_PAD_SLEEP_DIS,Controls the I/O pad sleep mode" "I/O pad sleep mode is enabled meaning all..,I/O pad sleep mode is disabledApplication.."
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group.long 0x34++0x03
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line.long 0x00 "JTAGCFG,JTAG ConfigurationThis register contains control for configuration of the JTAG domain"
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hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 8. "JTAG_PD_FORCE_ON,Controls JTAG Power domain power state:0: Controlled exclusively by debug subsystem" "Controlled exclusively by debug subsystem,JTAG Power Domain is forced on independent of.."
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newline
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hexmask.long.byte 0x00 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
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group.long 0x3C++0x03
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line.long 0x00 "JTAGUSERCODE,JTAG USERCODEBoot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem"
|
|
group.long 0xC4++0x07
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line.long 0x00 "WDTLOAD,ConfigurationLoad Value register"
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line.long 0x04 "WDTTEST,Test Mode"
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|
hexmask.long 0x04 1.--31. 1. "RESERVED0,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x04 0. "STALLEN,WDT Stall Enable0: The WDT timer continues counting if the CPU is stopped with a debugger.1: If the CPU is stopped with a debugger the WDT stops counting" "The WDT timer continues counting if the CPU is..,If the CPU is stopped with a debugger the WDT.."
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|
group.long 0xD0++0x03
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|
line.long 0x00 "WDTLOCK,Lock"
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tree.end
|
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tree "AON_RTC"
|
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base ad:0x58092000
|
|
group.long 0x00++0x37
|
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line.long 0x00 "CTL,ControlThis register contains various bitfields for configuration of RTCRTL Name = CONFIG"
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hexmask.long.word 0x00 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
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bitfld.long 0x00 16.--18. "COMB_EV_MASK,Eventmask selecting which delayed events that form the combined event." "No event is selected for combined event.,Use Channel 0 delayed event in combined event,Use Channel 1 delayed event in combined event,?,Use Channel 2 delayed event in combined event,?,?,?"
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newline
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rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EV_DELAY,Number of SCLK_LF clock cycles waited before generating delayed events" "No delay on delayed event,Delay by 1 clock cycles,Delay by 2 clock cycles,Delay by 4 clock cycles,Delay by 8 clock cycles,Delay by 16 clock cycles,Delay by 32 clock cycles,Delay by 48 clock cycles,Delay by 64 clock cycles,Delay by 80 clock cycles,Delay by 96 clock cycles,Delay by 112 clock cycles,Delay by 128 clock cycles,Delay by 144 clock cycles,?,?"
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newline
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bitfld.long 0x00 7. "RESET,RTC Counter reset.Writing 1 to this bit will reset the RTC counter.This bit is cleared when reset takes effect" "0,1"
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rbitfld.long 0x00 3.--6. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 2. "RTC_4KHZ_EN,RTC_4KHZ is a 4 KHz reference output tapped from SUBSEC.VALUE bit 19 which is used by AUX timer" "RTC_4KHZ signal is forced to 0,RTC_4KHZ is enabled ( provied that RTC is.."
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bitfld.long 0x00 1. "RTC_UPD_EN,RTC_UPD is a 16 KHz signal used to sync up the radio timer" "RTC_UPD signal is forced to 0,RTC_UPD signal is toggling @16 kHz"
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newline
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bitfld.long 0x00 0. "EN,Enable RTC counter0: Halted (frozen)1: Running" "Halted (frozen),Running"
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|
line.long 0x04 "EVFLAGS,Event Flags. RTC StatusThis register contains event flags from the 3 RTC channels"
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hexmask.long.word 0x04 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
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bitfld.long 0x04 16. "CH2,Channel 2 event flag set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value.An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any.." "0,1"
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|
newline
|
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hexmask.long.byte 0x04 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "CH1,Channel 1 event flag set when CHCTL.CH1_EN = 1 and one of the following:- CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value.- CHCTL.CH1_CAPT_EN = 1 and capture occurs.An event will be scheduled to occur as soon as possible.." "0,1"
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|
newline
|
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hexmask.long.byte 0x04 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "CH0,Channel 0 event flag set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value.An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any.." "0,1"
|
|
line.long 0x08 "SEC,Second Counter Value. Integer Part"
|
|
line.long 0x0C "SUBSEC,Second Counter Value. Fractional Part"
|
|
line.long 0x10 "SUBSECINC,Subseconds IncrementValue added to SUBSEC.VALUE on every SCLK_LFclock cycle"
|
|
hexmask.long.byte 0x10 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "VALUEINC,This value compensates for a SCLK_LF clock which has an offset from 32768 Hz.The compensation value can be found as 2^38 / freq where freq is SCLK_LF clock frequency in HertzThis value is added to SUBSEC.VALUE on every cycle and carry of this.."
|
|
line.long 0x14 "CHCTL,Channel Configuration"
|
|
hexmask.long.word 0x14 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 18. "CH2_CONT_EN,Set to enable continuous operation of Channel 2" "0,1"
|
|
newline
|
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rbitfld.long 0x14 17. "RESERVED17,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x14 16. "CH2_EN,RTC Channel 2 Enable0: Disable RTC Channel 21: Enable RTC Channel 2" "Disable RTC Channel 2,Enable RTC Channel 2"
|
|
newline
|
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rbitfld.long 0x14 10.--15. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 9. "CH1_CAPT_EN,Set Channel 1 mode0: Compare mode (default)1: Capture mode" "Compare mode (default),Capture mode"
|
|
newline
|
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bitfld.long 0x14 8. "CH1_EN,RTC Channel 1 Enable0: Disable RTC Channel 11: Enable RTC Channel 1" "Disable RTC Channel 1,Enable RTC Channel 1"
|
|
hexmask.long.byte 0x14 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x14 0. "CH0_EN,RTC Channel 0 Enable0: Disable RTC Channel 01: Enable RTC Channel 0" "Disable RTC Channel 0,Enable RTC Channel 0"
|
|
line.long 0x18 "CH0CMP,Channel 0 Compare Value"
|
|
line.long 0x1C "CH1CMP,Channel 1 Compare Value"
|
|
line.long 0x20 "CH2CMP,Channel 2 Compare Value"
|
|
line.long 0x24 "CH2CMPINC,Channel 2 Compare Value Auto-incrementThis register is primarily used to generate periodical wake-up for the AUX_SCE module. through the [AUX_EVCTL.EVSTAT0.AON_RTC] event."
|
|
line.long 0x28 "CH1CAPT,Channel 1 Capture ValueIf CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1. capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL."
|
|
hexmask.long.word 0x28 16.--31. 1. "SEC,Value of SEC.VALUE bits 15:0 at capture time"
|
|
hexmask.long.word 0x28 0.--15. 1. "SUBSEC,Value of SUBSEC.VALUE bits 31:16 at capture time"
|
|
line.long 0x2C "SYNC,AON SynchronizationThis register is used for synchronizing between MCU and entire AON domain"
|
|
hexmask.long 0x2C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "WBUSY,This register will always return 0 - however it will not return the value until there are no outstanding write requests between MCU and AONNote: Writing to this register prior to reading will force a wait until next SCLK_MF edge" "0,1"
|
|
line.long 0x30 "TIME,Current Counter Value"
|
|
hexmask.long.word 0x30 16.--31. 1. "SEC_L,Returns the lower halfword of SEC register"
|
|
hexmask.long.word 0x30 0.--15. 1. "SUBSEC_H,Returns the upper halfword of SUBSEC register"
|
|
line.long 0x34 "SYNCLF,Synchronization to SCLK_LFThis register is used for synchronizing MCU to positive or negative edge of SCLK_LF"
|
|
hexmask.long 0x34 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x34 0. "PHASE,This bit will always return the SCLK_LF phase" "Falling edge of SCLK_LF,Rising edge of SCLK_LF"
|
|
tree.end
|
|
tree.end
|
|
tree "AUX"
|
|
tree "AUX_ADI4"
|
|
base ad:0x400CB000
|
|
group.byte 0x00++0x05
|
|
line.byte 0x00 "MUX0,Internal"
|
|
bitfld.byte 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x00 6. "ADCCOMPB_IN,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
newline
|
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bitfld.byte 0x00 4.--5. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "COMPA_REF,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.byte 0x01 "MUX1,Internal"
|
|
line.byte 0x02 "MUX2,Internal"
|
|
bitfld.byte 0x02 3.--7. "ADCCOMPB_IN,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x02 0.--2. "DAC_VREF_SEL,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,Internal. Only to be used through TI provided API.,?,?,?"
|
|
line.byte 0x03 "MUX3,Internal"
|
|
line.byte 0x04 "ISRC,Current SourceStrength and trim control for current source"
|
|
bitfld.byte 0x04 2.--7. "TRIM,Adjust current from current source.Output currents may be combined to get desired total current" "No current connected,0.25 uA,0.5 uA,?,1.0 uA,?,?,?,2.0 uA,?,?,?,?,?,?,?,4.5 uA,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,11.75 uA,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x04 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.byte 0x04 0. "EN,Current source enable" "0,1"
|
|
line.byte 0x05 "COMP,ComparatorControl COMPA and COMPB comparators"
|
|
bitfld.byte 0x05 7. "COMPA_REF_RES_EN,Enables 400kohm resistance from COMPA reference node to ground" "0,1"
|
|
bitfld.byte 0x05 6. "COMPA_REF_CURR_EN,Enables 2uA IPTAT current from ISRC to COMPA reference node" "0,1"
|
|
newline
|
|
bitfld.byte 0x05 3.--5. "LPM_BIAS_WIDTH_TRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x05 2. "COMPB_EN,COMPB enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x05 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.byte 0x05 0. "COMPA_EN,COMPA enable" "0,1"
|
|
group.byte 0x07++0x04
|
|
line.byte 0x00 "MUX4,Internal"
|
|
line.byte 0x01 "ADC0,ADC Control 0ADC Sample Control"
|
|
bitfld.byte 0x01 7. "SMPL_MODE,ADC Sampling mode:0: Synchronous mode1: Asynchronous modeThe ADC does a sample-and-hold before conversion" "Synchronous mode,Asynchronous modeThe ADC does a.."
|
|
bitfld.byte 0x01 3.--6. "SMPL_CYCLE_EXP,Controls the sampling duration before conversion when the ADC is operated in synchronous mode (SMPL_MODE = 0)" "?,?,?,16x 6 MHz clock periods = 2.7us,32x 6 MHz clock periods = 5.3us,64x 6 MHz clock periods = 10.6us,128x 6 MHz clock periods = 21.3us,256x 6 MHz clock periods = 42.6us,512x 6 MHz clock periods = 85.3us,1024x 6 MHz clock periods = 170us,2048x 6 MHz clock periods = 341us,4096x 6 MHz clock periods = 682us,8192x 6 MHz clock periods = 1.37ms,16384x 6 MHz clock periods = 2.73ms,32768x 6 MHz clock periods = 5.46ms,65536x 6 MHz clock periods = 10.9ms"
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|
newline
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bitfld.byte 0x01 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
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|
bitfld.byte 0x01 1. "RESET_N,Reset ADC digital subchip active low" "Reset,Normal.."
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|
newline
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bitfld.byte 0x01 0. "EN,ADC Enable0: Disable1: Enable" "Disable,Enable"
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|
line.byte 0x02 "ADC1,ADC Control 1ADC Comparator Control"
|
|
hexmask.byte 0x02 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.byte 0x02 0. "SCALE_DIS,Internal" "0,1"
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|
line.byte 0x03 "ADCREF0,ADC Reference 0Control reference used by the ADC"
|
|
bitfld.byte 0x03 7. "SPARE7,Software should not rely on the value of a reserved" "0,1"
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|
bitfld.byte 0x03 6. "REF_ON_IDLE,Enable ADCREF in IDLE state.0: Disabled in IDLE state1: Enabled in IDLE stateKeep ADCREF enabled when ADC0.SMPL_MODE =" "Disabled in IDLE state,Enabled in IDLE stateKeep ADCREF enabled when.."
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|
newline
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bitfld.byte 0x03 5. "IOMUX,Internal" "0,1"
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|
bitfld.byte 0x03 4. "EXT,Internal" "0,1"
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|
newline
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bitfld.byte 0x03 3. "SRC,ADC reference source:0: Fixed reference =" "Fixed reference = 4.3V,Relative reference = VDDS"
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bitfld.byte 0x03 1.--2. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.byte 0x03 0. "EN,ADC reference module enable:0: ADC reference module powered down1: ADC reference module enabled" "ADC reference module powered down,ADC reference module enabled"
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line.byte 0x04 "ADCREF1,ADC Reference 1Control reference used by the ADC"
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|
bitfld.byte 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.byte 0x04 0.--5. "VTRIM,Trim output voltage of ADC fixed reference (64 steps 2's complement)" "nominal voltage 1.43V,nominal + 0.4% 1.435V,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,maximum voltage 1.6V,minimum voltage 1.3V,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,nominal - 0.4% 1.425V"
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group.byte 0x0E++0x01
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line.byte 0x00 "LPMBIAS,Internal"
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|
bitfld.byte 0x00 6.--7. "SPARE6,Internal" "0,1,2,3"
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|
bitfld.byte 0x00 0.--5. "LPM_TRIM_IOUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.byte 0x01 "STAT,Software should not rely on the value of a reserved"
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tree.end
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repeat 4. (list 0. 1. 2. 3. )(list ad:0x400CC000 ad:0x400CD000 ad:0x400CE000 ad:0x400CF000 )
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|
tree "AUX_AIODIO$1"
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base $2
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group.long 0x00++0x47
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line.long 0x00 "IOMODE,Input Output ModeThis register controls pull-up. pull-down. and output mode for AUXIO that are controlled by instance i of AUX_AIODIO"
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hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 14.--15. "IO7,Selects mode for AUXIO[8i+7]" "Output Mode:When IOPOE bit 7 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 7 is 0:..,Open-Drain Mode: When IOPOE bit 7 is 0: - If..,Open-Source Mode: When IOPOE bit 7 is 0: - If.."
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newline
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bitfld.long 0x00 12.--13. "IO6,Selects mode for AUXIO[8i+6]" "Output Mode:When IOPOE bit 6 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 6 is 0:..,Open-Drain Mode: When IOPOE bit 6 is 0: - If..,Open-Source Mode: When IOPOE bit 6 is 0: - If.."
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newline
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bitfld.long 0x00 10.--11. "IO5,Selects mode for AUXIO[8i+5]" "Output Mode:When IOPOE bit 5 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 5 is 0:..,Open-Drain Mode: When IOPOE bit 5 is 0: - If..,Open-Source Mode: When IOPOE bit 5 is 0: - If.."
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newline
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bitfld.long 0x00 8.--9. "IO4,Selects mode for AUXIO[8i+4]" "Output Mode:When IOPOE bit 4 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 4 is 0:..,Open-Drain Mode: When IOPOE bit 4 is 0: - If..,Open-Source Mode: When IOPOE bit 4 is 0: - If.."
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newline
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bitfld.long 0x00 6.--7. "IO3,Selects mode for AUXIO[8i+3]" "Output Mode:When IOPOE bit 3 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 3 is 0:..,Open-Drain Mode: When IOPOE bit 3 is 0: - If..,Open-Source Mode: When IOPOE bit 3 is 0: - If.."
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newline
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bitfld.long 0x00 4.--5. "IO2,Select mode for AUXIO[8i+2]" "Output Mode:When IOPOE bit 2 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 2 is 0:..,Open-Drain Mode: When IOPOE bit 2 is 0: - If..,Open-Source Mode: When IOPOE bit 2 is 0: - If.."
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newline
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bitfld.long 0x00 2.--3. "IO1,Select mode for AUXIO[8i+1]" "Output Mode:When IOPOE bit 1 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 1 is 0:..,Open-Drain Mode: When IOPOE bit 1 is 0: - If..,Open-Source Mode: When IOPOE bit 1 is 0: - If.."
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newline
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bitfld.long 0x00 0.--1. "IO0,Select mode for AUXIO[8i+0]" "Output Mode:When IOPOE bit 0 is 0: GPIODOUT..,Input Mode:When GPIODIE bit 0 is 0:..,Open-Drain Mode: When IOPOE bit 0 is 0: - If..,Open-Source Mode: When IOPOE bit 0 is 0: - If.."
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line.long 0x04 "GPIODIE,General Purpose Input Output Digital Input EnableThis register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO"
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|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x04 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]"
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|
line.long 0x08 "IOPOE,Input Output Peripheral Output EnableThis register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO"
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|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x08 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*].Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT"
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line.long 0x0C "GPIODOUT,General Purpose Input Output Data OutThe output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO"
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hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.byte 0x0C 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to set AUXIO[8i+n].Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]"
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|
line.long 0x10 "GPIODIN,General Purpose Input Output Data InThis register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.byte 0x10 0.--7. 1. "IO7_0,Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set"
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line.long 0x14 "GPIODOUTSET,General Purpose Input Output Data Out SetSet bits in GPIODOUT in instance i of AUX_AIODIO"
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|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x14 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to set GPIODOUT bit n"
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|
line.long 0x18 "GPIODOUTCLR,General Purpose Input Output Data Out ClearClear bits in GPIODOUT instance i of AUX_AIODIO"
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|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x18 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to clear GPIODOUT bit n.Read value is 0"
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line.long 0x1C "GPIODOUTTGL,General Purpose Input Output Data Out ToggleToggle bits in GPIODOUT in instance i of AUX_AIODIO"
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hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.byte 0x1C 0.--7. 1. "IO7_0,Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n"
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|
line.long 0x20 "IO0PSEL,Input Output 0 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1"
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hexmask.long 0x20 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x20 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x24 "IO1PSEL,Input Output 1 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1"
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|
hexmask.long 0x24 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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|
newline
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bitfld.long 0x24 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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|
line.long 0x28 "IO2PSEL,Input Output 2 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1"
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|
hexmask.long 0x28 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x28 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x2C "IO3PSEL,Input Output 3 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1"
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|
hexmask.long 0x2C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x2C 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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line.long 0x30 "IO4PSEL,Input Output 4 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1"
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|
hexmask.long 0x30 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x30 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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|
line.long 0x34 "IO5PSEL,Input Output 5 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1"
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|
hexmask.long 0x34 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x34 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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|
line.long 0x38 "IO6PSEL,Input Output 6 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1"
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|
hexmask.long 0x38 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x38 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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|
line.long 0x3C "IO7PSEL,Input Output 7 Peripheral SelectThis register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1"
|
|
hexmask.long 0x3C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x3C 0.--2. "SRC,Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set" "Peripheral output mux selects event selected by..,Peripheral output mux selects AUX_SPIM SCLK.,Peripheral output mux selects AUX_SPIM MOSI.,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous..,Peripheral output mux selects asynchronous.."
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|
line.long 0x40 "IOMODEL,Input Output Mode LowThis is an alias register for IOMODE.IO0 thru IOMODE.IO3"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x40 6.--7. "IO3,See IOMODE.IO3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x40 4.--5. "IO2,See IOMODE.IO2" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x40 2.--3. "IO1,See IOMODE.IO1" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x40 0.--1. "IO0,See IOMODE.IO0" "0,1,2,3"
|
|
line.long 0x44 "IOMODEH,Input Output Mode HighThis is an alias register for IOMODE.IO4 thru IOMODE.IO7"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x44 6.--7. "IO7,See IOMODE.IO7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x44 4.--5. "IO6,See IOMODE.IO6" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x44 2.--3. "IO5,See IOMODE.IO5" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x44 0.--1. "IO4,See IOMODE.IO4" "0,1,2,3"
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|
tree.end
|
|
repeat.end
|
|
tree "AUX_ANAIF"
|
|
base ad:0x400C9000
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "ADCCTL,ADC ControlConfiguration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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|
newline
|
|
bitfld.long 0x00 14. "START_POL,Select active polarity for START_SRC event" "Set ADC trigger on rising edge of event source.,Set ADC trigger on falling edge of event source."
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|
newline
|
|
bitfld.long 0x00 8.--13. "START_SRC,Select ADC trigger event source from the asynchronous AUX event bus.Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10,AUX_EVCTL:EVSTAT0.AUXIO11,AUX_EVCTL:EVSTAT0.AUXIO12,AUX_EVCTL:EVSTAT0.AUXIO13,AUX_EVCTL:EVSTAT0.AUXIO14,AUX_EVCTL:EVSTAT0.AUXIO15,AUX_EVCTL:EVSTAT1.AUXIO16,AUX_EVCTL:EVSTAT1.AUXIO17,AUX_EVCTL:EVSTAT1.AUXIO18,AUX_EVCTL:EVSTAT1.AUXIO19,AUX_EVCTL:EVSTAT1.AUXIO20,AUX_EVCTL:EVSTAT1.AUXIO21,AUX_EVCTL:EVSTAT1.AUXIO22,AUX_EVCTL:EVSTAT1.AUXIO23,AUX_EVCTL:EVSTAT1.AUXIO24,AUX_EVCTL:EVSTAT1.AUXIO25,AUX_EVCTL:EVSTAT1.AUXIO26,AUX_EVCTL:EVSTAT1.AUXIO27,AUX_EVCTL:EVSTAT1.AUXIO28,AUX_EVCTL:EVSTAT1.AUXIO29,AUX_EVCTL:EVSTAT1.AUXIO30,AUX_EVCTL:EVSTAT1.AUXIO31,AUX_EVCTL:EVSTAT2.MANUAL_EV ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,?,?,AUX_EVCTL:EVSTAT2.AUX_COMPA,AUX_EVCTL:EVSTAT2.AUX_COMPB,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,?,?,?,?,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
|
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rbitfld.long 0x00 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
bitfld.long 0x00 0.--1. "CMD,ADC interface command.Non-enumerated values are not supported" "Disable ADC interface.,Enable ADC interface.,?,Flush ADC FIFO.You must set CMD to EN or DIS.."
|
|
line.long 0x04 "ADCFIFOSTAT,ADC FIFO StatusFIFO can hold up to four ADC samples"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 4. "OVERFLOW,FIFO overflow flag.0: FIFO has not overflowed.1: FIFO has overflowed this flag is sticky until you flush the FIFO.When the flag is set the ADC FIFO write pointer is static" "FIFO has not overflowed,FIFO has overflowed this flag is sticky until.."
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newline
|
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bitfld.long 0x04 3. "UNDERFLOW,FIFO underflow flag.0: FIFO has not underflowed.1: FIFO has underflowed this flag is sticky until you flush the FIFO.When the flag is set the ADC FIFO read pointer is static" "FIFO has not underflowed,FIFO has underflowed this flag is sticky until.."
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|
newline
|
|
bitfld.long 0x04 2. "FULL,FIFO full flag.0: FIFO is not full there is less than 4 samples in the FIFO" "FIFO is not full there is less than 4 samples in..,FIFO is full there are 4 samples in the.."
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newline
|
|
bitfld.long 0x04 1. "ALMOST_FULL,FIFO almost full flag.0: There are less than 3 samples in the FIFO or the FIFO is full" "There are less than 3 samples in the FIFO or the..,There are 3 samples in the FIFO there is room.."
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|
newline
|
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bitfld.long 0x04 0. "EMPTY,FIFO empty flag.0: FIFO contains one or more samples.1: FIFO is empty.When the flag is set read returns the previous sample that was read and sets the UNDERFLOW flag" "FIFO contains one or more samples,FIFO is empty.When the flag is set read returns.."
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|
line.long 0x08 "ADCFIFO,ADC FIFO"
|
|
hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. "DATA,FIFO data.Read:Get oldest ADC sample from FIFO.Write:Write dummy sample to FIFO"
|
|
line.long 0x0C "ADCTRIG,ADC Trigger"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "START,Manual ADC trigger" "0,1"
|
|
line.long 0x10 "ISRCCTL,Current Source Control"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "RESET_N,ISRC reset control.0: ISRC drives 0 uA.1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN" "ISRC drives 0 uA,ISRC drives current ADI_4_AUX"
|
|
group.long 0x30++0x1B
|
|
line.long 0x00 "DACCTL,DAC ControlThis register controls the analog part of the DAC."
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 5. "DAC_EN,DAC module enable.0: Disable DAC.1: Enable DAC.The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA.The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA in Standby TI-RTOS power mode" "Disable DAC,Enable DAC.The Sensor.."
|
|
newline
|
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bitfld.long 0x00 4. "DAC_BUFFER_EN,DAC buffer enable.DAC buffer reduces the time required to produce the programmed voltage at the expense of increased current consumption.0: Disable DAC buffer.1: Enable DAC buffer.Enable buffer when DAC_VOUT_SEL equals COMPA_IN.Do not.." "Disable DAC buffer,Enable DAC buffer.Enable buffer when.."
|
|
newline
|
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bitfld.long 0x00 3. "DAC_PRECHARGE_EN,DAC precharge enable.Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and VDDS is higher than 2.65 V" "0 V to 1.28 V,1.28 V to 2.56 V"
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|
newline
|
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bitfld.long 0x00 0.--2. "DAC_VOUT_SEL,DAC output connection.An analog node must only have one driver" "Connect to nothingIt is recommended to use NC..,Connect to COMPB_REF analog node.Required..,Connect to COMPA_REF analog node.It is not..,?,Connect to COMPA_IN analog node.Required..,?,?,?"
|
|
line.long 0x04 "LPMBIASCTL,Low Power Mode Bias ControlThe low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 0. "EN,Module enable.0: Disable low power mode bias module.1: Enable low power mode bias module.Set EN to 1 15 us before you enable the DAC or Comparator A" "Disable low power mode bias module,Enable low power mode bias module.Set EN to 1 15.."
|
|
line.long 0x08 "DACSMPLCTL,DAC Sample ControlThe DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor"
|
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hexmask.long 0x08 1.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 0. "EN,DAC sample clock enable.0: Disable sample clock" "Disable sample clock,Enable DAC sample clock"
|
|
line.long 0x0C "DACSMPLCFG0,DAC Sample Configuration 0"
|
|
hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
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bitfld.long 0x0C 0.--5. "CLKDIV,Clock division.AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the sample clock base frequency" "Divide by 1,Divide by 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 64"
|
|
line.long 0x10 "DACSMPLCFG1,DAC Sample Configuration 1The sample clock period equals (high time + low time) * base period"
|
|
hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x10 14. "H_PER,High time.The sample clock period is high for this many base periods.0: 2 periods1: 4 periods" "2 periods,4 periods"
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|
newline
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bitfld.long 0x10 12.--13. "L_PER,Low time.The sample clock period is low for this many base periods.0: 1 period1: 2 periods2: 3 periods3: 4 periods" "1 period,2 periods,3 periods,4 periods"
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newline
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bitfld.long 0x10 8.--11. "SETUP_CNT,Setup count.Number of active sample clock periods during the setup phase.0: 1 sample clock period" "1 sample clock period,2 sample clock periods,?,?,?,?,?,?,?,?,?,?,?,?,?,16 sample clock periods"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "HOLD_INTERVAL,Hold interval.Number of inactive sample clock periods between each active sample clock period during hold phase"
|
|
line.long 0x14 "DACVALUE,DAC Value"
|
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x14 0.--7. 1. "VALUE,DAC value.Digital data word for the DAC.Only change VALUE when DACCTL.DAC_EN is 0"
|
|
line.long 0x18 "DACSTAT,DAC Status"
|
|
hexmask.long 0x18 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x18 1. "SETUP_ACTIVE,DAC setup phase status.0: Sample clock is disabled or setup phase is complete.1: Setup phase in progress" "Sample clock is disabled or setup phase is..,Setup phase in progress"
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newline
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bitfld.long 0x18 0. "HOLD_ACTIVE,DAC hold phase status.0: Sample clock is disabled or DAC is not in hold phase.1: Hold phase in progress" "Sample clock is disabled or DAC is not in hold..,Hold phase in progress"
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tree.end
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tree "AUX_DDI0_OSC"
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base ad:0x580CA000
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group.long 0x00++0x37
|
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line.long 0x00 "CTL0,Control 0Controls clock source selects"
|
|
bitfld.long 0x00 31. "XTAL_IS_24M,Set based on the accurate high frequency XTAL" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
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newline
|
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bitfld.long 0x00 30. "RESERVED30,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
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bitfld.long 0x00 29. "BYPASS_XOSC_LF_CLK_QUAL,Internal" "0,1"
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|
newline
|
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bitfld.long 0x00 28. "BYPASS_RCOSC_LF_CLK_QUAL,Internal" "0,1"
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newline
|
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bitfld.long 0x00 26.--27. "DOUBLER_START_DURATION,Internal" "0,1,2,3"
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newline
|
|
bitfld.long 0x00 25. "DOUBLER_RESET_DURATION,Internal" "0,1"
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|
newline
|
|
bitfld.long 0x00 24. "CLK_DCDC_SRC_SEL,Select DCDC clock source.0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC1: CLK_DCDC is always 48 MHz clock from RCOSC" "CLK_DCDC is 48 MHz clock from RCOSC or XOSC /..,CLK_DCDC is always 48 MHz clock from RCOSC"
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|
newline
|
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hexmask.long.word 0x00 15.--23. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 14. "HPOSC_MODE_EN," "0,1"
|
|
newline
|
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bitfld.long 0x00 13. "RESERVED13,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RCOSC_LF_TRIMMED,Internal" "0,1"
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|
newline
|
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bitfld.long 0x00 11. "XOSC_HF_POWER_MODE,Internal" "0,1"
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newline
|
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bitfld.long 0x00 10. "XOSC_LF_DIG_BYPASS,Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock.0: Use 32kHz XOSC as xosc_lf clock source1: Use digital input (from AON) as xosc_lf clock source.This bit will only have effect when SCLK_LF_SRC_SEL is.." "Use 32kHz XOSC as xosc_lf clock source,Use digital input (from AON) as xosc_lf clock.."
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newline
|
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bitfld.long 0x00 9. "CLK_LOSS_EN,Enable clock loss detection and hence the indicators to the system controller" "Disable,EnableClock loss.."
|
|
newline
|
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bitfld.long 0x00 7.--8. "ACLK_TDC_SRC_SEL,Source select for aclk_tdc.00: RCOSC_HF (48MHz)01: RCOSC_HF (24MHz)10: XOSC_HF (24MHz)11: Not used" "RCOSC_HF (48MHz),RCOSC_HF (24MHz),?..."
|
|
newline
|
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bitfld.long 0x00 4.--6. "ACLK_REF_SRC_SEL,Source select for aclk_ref000: RCOSC_HF derived (31.25kHz)001: XOSC_HF derived (31.25kHz)010: RCOSC_LF (32kHz)011: XOSC_LF (32.768kHz)100: RCOSC_MF (2MHz)101-111: Not used" "RCOSC_HF derived (31.25kHz),XOSC_HF derived (31.25kHz),?..."
|
|
newline
|
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bitfld.long 0x00 2.--3. "SCLK_LF_SRC_SEL,Source select for sclk_lf" "Low frequency clock derived from High Frequency..,Low frequency clock derived from High Frequency..,Low frequency RCOSC,Low frequency XOSC"
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newline
|
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bitfld.long 0x00 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SCLK_HF_SRC_SEL,Source select for sclk_hf" "High frequency RCOSC clock,High frequency XOSC or HPOSC clk (use HPOSC when.."
|
|
line.long 0x04 "CTL1,Control 1This register contains OSC_DIG configuration"
|
|
hexmask.long.word 0x04 23.--31. 1. "RESERVED23,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x04 18.--22. "RCOSCHFCTRIMFRACT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
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bitfld.long 0x04 17. "RCOSCHFCTRIMFRACT_EN,Internal" "0,1"
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|
newline
|
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hexmask.long.byte 0x04 10.--16. 1. "SPARE10,Software should not rely on the value of a reserved"
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|
newline
|
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bitfld.long 0x04 9. "FORCE_RCOSC_LF,Force rcosc_lf to be enabled0: Disabled1: Enabled" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x04 8. "CLK_LF_LOSS_EN,Enable LF clock loss detection and hence the indicators to the system controller" "Disable,EnableClock loss.."
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|
newline
|
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bitfld.long 0x04 2.--7. "SPARE2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
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bitfld.long 0x04 0.--1. "XOSC_HF_FAST_START,Internal" "0,1,2,3"
|
|
line.long 0x08 "RADCEXTCFG,RADC External Configuration"
|
|
hexmask.long.word 0x08 22.--31. 1. "HPM_IBIAS_WAIT_CNT,Internal"
|
|
newline
|
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bitfld.long 0x08 16.--21. "LPM_IBIAS_WAIT_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x08 12.--15. "IDAC_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x08 6.--11. "RADC_DAC_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x08 5. "RADC_MODE_IS_SAR,Internal" "0,1"
|
|
newline
|
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bitfld.long 0x08 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x0C "AMPCOMPCTL,Amplitude Compensation Control"
|
|
bitfld.long 0x0C 31. "SPARE31,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
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bitfld.long 0x0C 30. "AMPCOMP_REQ_MODE,Internal" "0,1"
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|
newline
|
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bitfld.long 0x0C 28.--29. "AMPCOMP_FSM_UPDATE_RATE,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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|
newline
|
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bitfld.long 0x0C 27. "AMPCOMP_SW_CTRL,Internal" "0,1"
|
|
newline
|
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bitfld.long 0x0C 26. "AMPCOMP_SW_EN,Internal" "0,1"
|
|
newline
|
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bitfld.long 0x0C 24.--25. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 20.--23. "IBIAS_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x0C 16.--19. "IBIAS_INIT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--15. 1. "LPM_IBIAS_WAIT_CNT_FINAL,Internal"
|
|
newline
|
|
bitfld.long 0x0C 4.--7. "CAP_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 0.--3. "IBIASCAP_HPTOLP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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line.long 0x10 "AMPCOMPTH1,Amplitude Compensation Threshold 1This register contains threshold values for amplitude compensation algorithm"
|
|
hexmask.long.byte 0x10 24.--31. 1. "SPARE24,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 18.--23. "HPMRAMP3_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x10 16.--17. "SPARE16,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10.--15. "HPMRAMP3_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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newline
|
|
bitfld.long 0x10 6.--9. "IBIASCAP_LPTOHP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x10 0.--5. "HPMRAMP1_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x14 "AMPCOMPTH2,Amplitude Compensation Threshold 2This register contains threshold values for amplitude compensation algorithm."
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bitfld.long 0x14 26.--31. "LPMUPDATE_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x14 24.--25. "SPARE24,Software should not rely on the value of a reserved" "0,1,2,3"
|
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newline
|
|
bitfld.long 0x14 18.--23. "LPMUPDATE_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x14 16.--17. "SPARE16,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x14 10.--15. "ADC_COMP_AMPTH_LPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x14 8.--9. "SPARE8,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x14 2.--7. "ADC_COMP_AMPTH_HPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
|
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bitfld.long 0x14 0.--1. "SPARE0,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
line.long 0x18 "ANABYPASSVAL1,Analog Bypass Values 1"
|
|
hexmask.long.word 0x18 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x18 16.--19. "XOSC_HF_ROW_Q12,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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newline
|
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hexmask.long.word 0x18 0.--15. 1. "XOSC_HF_COLUMN_Q12,Internal"
|
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line.long 0x1C "ANABYPASSVAL2,Internal"
|
|
hexmask.long.tbyte 0x1C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--13. 1. "XOSC_HF_IBIASTHERM,Internal"
|
|
line.long 0x20 "ATESTCTL,Analog Test Control"
|
|
bitfld.long 0x20 31. "SCLK_LF_AUX_EN,Enable 32 kHz clock to AUX_COMPB." "0,1"
|
|
newline
|
|
hexmask.long.word 0x20 16.--30. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 14.--15. "TEST_RCOSCMF,Test mode control for RCOSC_MF0x0: test modes" "test modes disabled,boosted bias current into self biased inverter,clock qualification disabled,boosted bias current into self biased inverter +.."
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|
newline
|
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bitfld.long 0x20 12.--13. "ATEST_RCOSCMF,ATEST control for RCOSC_MF0x0: ATEST" "ATEST disabled,ATEST enabled VDD_LOCAL connected ATEST internal..,ATEST disabled,ATEST enabled bias current connected ATEST.."
|
|
newline
|
|
hexmask.long.word 0x20 0.--11. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x24 "ADCDOUBLERNANOAMPCTL,ADC Doubler Nanoamp Control"
|
|
hexmask.long.byte 0x24 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 24. "NANOAMP_BIAS_ENABLE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x24 23. "SPARE23,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x24 6.--22. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 5. "ADC_SH_MODE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "ADC_SH_VBUF_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x24 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x24 0.--1. "ADC_IREF_CTRL,Internal" "0,1,2,3"
|
|
line.long 0x28 "XOSCHFCTL,XOSCHF Control"
|
|
hexmask.long.tbyte 0x28 14.--31. 1. "SPARE14,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x28 13. "TCXO_MODE_XOSC_HF_EN,If this register is 1 when TCXO_MODE is 1 then the XOSC_HF is enabled turning on the XOSC_HF bias current allowing a DC bias point to be provided to the clipped-sine wave clock signal on external input" "0,1"
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newline
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bitfld.long 0x28 12. "TCXO_MODE,If this register is 1 when BYPASS is 1 this will enable clock qualification on the TCXO clock on external input" "0,1"
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newline
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bitfld.long 0x28 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x28 8.--9. "PEAK_DET_ITRIM,Internal" "0,1,2,3"
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newline
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bitfld.long 0x28 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x28 6. "BYPASS,Internal" "0,1"
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newline
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bitfld.long 0x28 5. "RESERVED5,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x28 2.--4. "HP_BUF_ITRIM,Internal" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x28 0.--1. "LP_BUF_ITRIM,Internal" "0,1,2,3"
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line.long 0x2C "LFOSCCTL,Low Frequency Oscillator Control"
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hexmask.long.byte 0x2C 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 22.--23. "XOSCLF_REGULATOR_TRIM,Internal" "0,1,2,3"
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newline
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bitfld.long 0x2C 18.--21. "XOSCLF_CMIRRWR_RATIO,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x2C 10.--17. 1. "RESERVED10,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 8.--9. "RCOSCLF_RTUNE_TRIM,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
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newline
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hexmask.long.byte 0x2C 0.--7. 1. "RCOSCLF_CTUNE_TRIM,Internal"
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line.long 0x30 "RCOSCHFCTL,RCOSCHF Control"
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hexmask.long.word 0x30 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x30 8.--15. 1. "RCOSCHF_CTRIM,Internal"
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newline
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hexmask.long.byte 0x30 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
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line.long 0x34 "RCOSCMFCTL,RCOSC_MF Control"
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hexmask.long.word 0x34 16.--31. 1. "SPARE16,Software should not rely on the value of a reserved"
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newline
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abitfld.long 0x34 9.--15. "RCOSC_MF_CAP_ARRAY,Adjust RCOSC_MF capacitor" "0x00=nominal frequency 0.625pF,0x3F=lowest frequency 1.125pF,0x40=highest frequency 0.125pF"
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newline
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bitfld.long 0x34 8. "RCOSC_MF_REG_SEL,Choose regulator type.0: default1: alternate" "default,alternate"
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newline
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bitfld.long 0x34 6.--7. "RCOSC_MF_RES_COARSE,Select coarse resistor for frequency" "400kohms default,300kohms min,600kohms max,500kohms"
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newline
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bitfld.long 0x34 4.--5. "RCOSC_MF_RES_FINE,Select fine resistor for frequency" "11kohms minimum resistance max freq,13kohms,16kohms,20kohms max resistance min freq"
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newline
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bitfld.long 0x34 0.--3. "RCOSC_MF_BIAS_ADJ,Adjusts bias current to RCOSC_MF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x3C++0x0B
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line.long 0x00 "STAT0,Status 0This register contains status signals from OSC_DIG"
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bitfld.long 0x00 31. "RCOSC_LF_GOOD,RCOSC_LF_GOOD" "0,1"
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newline
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bitfld.long 0x00 29.--30. "SCLK_LF_SRC,Indicates source for the sclk_lf" "Low frequency clock derived from High Frequency..,Low frequency clock derived from High Frequency..,Low frequency RCOSC,Low frequency XOSC"
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newline
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bitfld.long 0x00 28. "SCLK_HF_SRC,Indicates source for the sclk_hf" "High frequency RCOSC clock,High frequency XOSC"
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newline
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bitfld.long 0x00 23.--27. "RESERVED23,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 22. "RCOSC_HF_EN,RCOSC_HF_EN" "0,1"
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newline
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bitfld.long 0x00 21. "RCOSC_LF_EN,RCOSC_LF_EN" "0,1"
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newline
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bitfld.long 0x00 20. "XOSC_LF_EN,XOSC_LF_EN" "0,1"
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newline
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bitfld.long 0x00 19. "CLK_DCDC_RDY,CLK_DCDC_RDY" "0,1"
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newline
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bitfld.long 0x00 18. "CLK_DCDC_RDY_ACK,CLK_DCDC_RDY_ACK" "0,1"
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newline
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bitfld.long 0x00 17. "SCLK_HF_LOSS,Indicates sclk_hf is lost" "0,1"
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newline
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bitfld.long 0x00 16. "SCLK_LF_LOSS,Indicates sclk_lf is lost" "0,1"
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newline
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bitfld.long 0x00 15. "XOSC_HF_EN,Indicates that XOSC_HF is enabled" "0,1"
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newline
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bitfld.long 0x00 14. "RESERVED14,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 13. "XB_48M_CLK_EN,Indicates that the 48MHz clock from the DOUBLER is enabled.It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal)" "0,1"
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newline
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bitfld.long 0x00 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 11. "XOSC_HF_LP_BUF_EN,XOSC_HF_LP_BUF_EN" "0,1"
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newline
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bitfld.long 0x00 10. "XOSC_HF_HP_BUF_EN,XOSC_HF_HP_BUF_EN" "0,1"
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newline
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bitfld.long 0x00 9. "RESERVED9,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 8. "ADC_THMET,ADC_THMET" "0,1"
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bitfld.long 0x00 7. "ADC_DATA_READY,indicates when adc_data is ready" "0,1"
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newline
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bitfld.long 0x00 1.--6. "ADC_DATA,adc_data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x00 0. "PENDINGSCLKHFSWITCHING,Indicates when SCLK_HF clock source is ready to be switched" "0,1"
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line.long 0x04 "STAT1,Status 1This register contains status signals from OSC_DIG"
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bitfld.long 0x04 28.--31. "RAMPSTATE,AMPCOMP FSM State" "RESET,INITIALIZATION,HPM_RAMP1,HPM_RAMP2,HPM_RAMP3,HPM_UPDATE,IDAC_INCREMENT,IBIAS_CAP_UPDATE,IBIAS_DECREMENT_WITH_MEASURE,LPM_UPDATE,IBIAS_INCREMENT,IDAC_DECREMENT_WITH_MEASURE,DUMMY_TO_INIT_1,FAST_START,FAST_START_SETTLE,?"
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newline
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bitfld.long 0x04 22.--27. "HPM_UPDATE_AMP,XOSC_HF amplitude during HPM_UPDATE state.When amplitude compensation of XOSC_HF is enabled in high performance mode this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC divided by 15 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x04 16.--21. "LPM_UPDATE_AMP,XOSC_HF amplitude during LPM_UPDATE stateWhen amplitude compensation of XOSC_HF is enabled in low power mode this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC divided by 15 mV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x04 15. "FORCE_RCOSC_HF,force_rcosc_hf" "0,1"
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newline
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bitfld.long 0x04 14. "SCLK_HF_EN,SCLK_HF_EN" "0,1"
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newline
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bitfld.long 0x04 13. "SCLK_MF_EN,SCLK_MF_EN" "0,1"
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newline
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bitfld.long 0x04 12. "ACLK_ADC_EN,ACLK_ADC_EN" "0,1"
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newline
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bitfld.long 0x04 11. "ACLK_TDC_EN,ACLK_TDC_EN" "0,1"
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newline
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bitfld.long 0x04 10. "ACLK_REF_EN,ACLK_REF_EN" "0,1"
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newline
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bitfld.long 0x04 9. "CLK_CHP_EN,CLK_CHP_EN" "0,1"
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newline
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bitfld.long 0x04 8. "CLK_DCDC_EN,CLK_DCDC_EN" "0,1"
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newline
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bitfld.long 0x04 7. "SCLK_HF_GOOD,SCLK_HF_GOOD" "0,1"
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newline
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bitfld.long 0x04 6. "SCLK_MF_GOOD,SCLK_MF_GOOD" "0,1"
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newline
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bitfld.long 0x04 5. "SCLK_LF_GOOD,SCLK_LF_GOOD" "0,1"
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newline
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bitfld.long 0x04 4. "ACLK_ADC_GOOD,ACLK_ADC_GOOD" "0,1"
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newline
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bitfld.long 0x04 3. "ACLK_TDC_GOOD,ACLK_TDC_GOOD" "0,1"
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newline
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bitfld.long 0x04 2. "ACLK_REF_GOOD,ACLK_REF_GOOD" "0,1"
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newline
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bitfld.long 0x04 1. "CLK_CHP_GOOD,CLK_CHP_GOOD" "0,1"
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newline
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bitfld.long 0x04 0. "CLK_DCDC_GOOD,CLK_DCDC_GOOD" "0,1"
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line.long 0x08 "STAT2,Status 2This register contains status signals from AMPCOMP FSM"
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bitfld.long 0x08 26.--31. "ADC_DCBIAS,DC Bias read by RADC during SAR modeThe value is an unsigned integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x08 25. "HPM_RAMP1_THMET,Indication of threshold is met for hpm_ramp1" "0,1"
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newline
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bitfld.long 0x08 24. "HPM_RAMP2_THMET,Indication of threshold is met for hpm_ramp2" "0,1"
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newline
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bitfld.long 0x08 23. "HPM_RAMP3_THMET,Indication of threshold is met for hpm_ramp3" "0,1"
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newline
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hexmask.long.byte 0x08 16.--22. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 12.--15. "RAMPSTATE,xosc_hf amplitude compensation FSMThis is identical to STAT1.RAMPSTATE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x08 4.--11. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 3. "AMPCOMP_REQ,ampcomp_req" "0,1"
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newline
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bitfld.long 0x08 2. "XOSC_HF_AMPGOOD,amplitude of xosc_hf is within the required threshold (set by DDI)" "0,1"
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newline
|
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bitfld.long 0x08 1. "XOSC_HF_FREQGOOD,frequency of xosc_hf is good to use for the digital clocks" "0,1"
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newline
|
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bitfld.long 0x08 0. "XOSC_HF_RF_FREQGOOD,frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations" "0,1"
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tree.end
|
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tree "AUX_EVCTL"
|
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base ad:0x400C5000
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rgroup.long 0x00++0x1B
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line.long 0x00 "EVSTAT0,Event Status 0Register holds events 0 thru 15 of the 64-bit event bus that is synchronous to AUX clock"
|
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hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x00 15. "AUXIO15,AUXIO15 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 7" "0,1"
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newline
|
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bitfld.long 0x00 14. "AUXIO14,AUXIO14 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 6" "0,1"
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newline
|
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bitfld.long 0x00 13. "AUXIO13,AUXIO13 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 5" "0,1"
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newline
|
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bitfld.long 0x00 12. "AUXIO12,AUXIO12 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 4" "0,1"
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newline
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bitfld.long 0x00 11. "AUXIO11,AUXIO11 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 3" "0,1"
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newline
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bitfld.long 0x00 10. "AUXIO10,AUXIO10 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 2" "0,1"
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newline
|
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bitfld.long 0x00 9. "AUXIO9,AUXIO9 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 1" "0,1"
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newline
|
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bitfld.long 0x00 8. "AUXIO8,AUXIO8 pin level read value corresponds to AUX_AIODIO1:GPIODIN bit 0" "0,1"
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newline
|
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bitfld.long 0x00 7. "AUXIO7,AUXIO7 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 7" "0,1"
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newline
|
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bitfld.long 0x00 6. "AUXIO6,AUXIO6 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 6" "0,1"
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newline
|
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bitfld.long 0x00 5. "AUXIO5,AUXIO5 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 5" "0,1"
|
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newline
|
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bitfld.long 0x00 4. "AUXIO4,AUXIO4 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 4" "0,1"
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newline
|
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bitfld.long 0x00 3. "AUXIO3,AUXIO3 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 3" "0,1"
|
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newline
|
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bitfld.long 0x00 2. "AUXIO2,AUXIO2 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 2" "0,1"
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newline
|
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bitfld.long 0x00 1. "AUXIO1,AUXIO1 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 1" "0,1"
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newline
|
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bitfld.long 0x00 0. "AUXIO0,AUXIO0 pin level read value corresponds to AUX_AIODIO0:GPIODIN bit 0" "0,1"
|
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line.long 0x04 "EVSTAT1,Event Status 1Register holds events 16 thru 31 of the 64-bit event bus that is synchronous to AUX clock"
|
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x04 15. "AUXIO31,AUXIO31 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 7" "0,1"
|
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newline
|
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bitfld.long 0x04 14. "AUXIO30,AUXIO30 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 6" "0,1"
|
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newline
|
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bitfld.long 0x04 13. "AUXIO29,AUXIO29 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 5" "0,1"
|
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newline
|
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bitfld.long 0x04 12. "AUXIO28,AUXIO28 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 4" "0,1"
|
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newline
|
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bitfld.long 0x04 11. "AUXIO27,AUXIO27 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 3" "0,1"
|
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newline
|
|
bitfld.long 0x04 10. "AUXIO26,AUXIO26 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 2" "0,1"
|
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newline
|
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bitfld.long 0x04 9. "AUXIO25,AUXIO25 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 1" "0,1"
|
|
newline
|
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bitfld.long 0x04 8. "AUXIO24,AUXIO24 pin level read value corresponds to AUX_AIODIO3:GPIODIN bit 0" "0,1"
|
|
newline
|
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bitfld.long 0x04 7. "AUXIO23,AUXIO23 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 7" "0,1"
|
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newline
|
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bitfld.long 0x04 6. "AUXIO22,AUXIO22 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 6" "0,1"
|
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newline
|
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bitfld.long 0x04 5. "AUXIO21,AUXIO21 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "AUXIO20,AUXIO20 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 4" "0,1"
|
|
newline
|
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bitfld.long 0x04 3. "AUXIO19,AUXIO19 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 3" "0,1"
|
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newline
|
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bitfld.long 0x04 2. "AUXIO18,AUXIO18 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 2" "0,1"
|
|
newline
|
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bitfld.long 0x04 1. "AUXIO17,AUXIO17 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 1" "0,1"
|
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newline
|
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bitfld.long 0x04 0. "AUXIO16,AUXIO16 pin level read value corresponds to AUX_AIODIO2:GPIODIN bit 0" "0,1"
|
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line.long 0x08 "EVSTAT2,Event Status 2Register holds events 32 thru 47 of the 64-bit event bus that is synchronous to AUX clock"
|
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
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newline
|
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bitfld.long 0x08 15. "AUX_COMPB,Comparator B output" "0,1"
|
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newline
|
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bitfld.long 0x08 14. "AUX_COMPA,Comparator A output" "0,1"
|
|
newline
|
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bitfld.long 0x08 13. "MCU_OBSMUX1,Observation input 1 from IOC" "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "MCU_OBSMUX0,Observation input 0 from IOC" "0,1"
|
|
newline
|
|
bitfld.long 0x08 11. "MCU_EV,Event from EVENT configured by EVENT:AUXSEL0" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. "ACLK_REF,TDC reference clock.It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ" "0,1"
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newline
|
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bitfld.long 0x08 9. "VDDR_RECHARGE,Event is high during VDDR recharge" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "MCU_ACTIVE,Event is high while system(MCU AUX or JTAG domains) is active or transitions to active (GLDO or DCDC power supply state)" "0,1"
|
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newline
|
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bitfld.long 0x08 7. "PWR_DWN,Event is high while system(MCU AUX or JTAG domains) is in powerdown (uLDO power supply)" "0,1"
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newline
|
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bitfld.long 0x08 6. "SCLK_LF,SCLK_LF clock" "0,1"
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newline
|
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bitfld.long 0x08 5. "AON_BATMON_TEMP_UPD,Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP" "0,1"
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newline
|
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bitfld.long 0x08 4. "AON_BATMON_BAT_UPD,Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT" "0,1"
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newline
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bitfld.long 0x08 3. "AON_RTC_4KHZ,AON_RTC:SUBSEC.VALUE bit" "0,1"
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newline
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bitfld.long 0x08 2. "AON_RTC_CH2_DLY,AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration" "0,1"
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newline
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bitfld.long 0x08 1. "AON_RTC_CH2,AON_RTC:EVFLAGS.CH2" "0,1"
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newline
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bitfld.long 0x08 0. "MANUAL_EV,Programmable event" "0,1"
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line.long 0x0C "EVSTAT3,Event Status 3Register holds events 48 thru 63 of the 64-bit event bus that is synchronous to AUX clock"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 15. "AUX_TIMER2_CLKSWITCH_RDY,AUX_SYSIF:TIMER2CLKSWITCH.RDY" "0,1"
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newline
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bitfld.long 0x0C 14. "AUX_DAC_HOLD_ACTIVE,AUX_ANAIF:DACSTAT.HOLD_ACTIVE" "0,1"
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newline
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bitfld.long 0x0C 13. "AUX_SMPH_AUTOTAKE_DONE,See AUX_SMPH:AUTOTAKE.SMPH_ID for description" "0,1"
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newline
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bitfld.long 0x0C 12. "AUX_ADC_FIFO_NOT_EMPTY,AUX_ANAIF:ADCFIFOSTAT.EMPTY negated" "0,1"
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newline
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bitfld.long 0x0C 11. "AUX_ADC_FIFO_ALMOST_FULL,AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL" "0,1"
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newline
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bitfld.long 0x0C 10. "AUX_ADC_IRQ,The logical function for this event is configurable.When DMACTL.EN =" "0,1"
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newline
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bitfld.long 0x0C 9. "AUX_ADC_DONE,AUX_ANAIF ADC conversion done event" "0,1"
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newline
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bitfld.long 0x0C 8. "AUX_ISRC_RESET_N,AUX_ANAIF:ISRCCTL.RESET_N" "0,1"
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newline
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bitfld.long 0x0C 7. "AUX_TDC_DONE,AUX_TDC:STAT.DONE" "0,1"
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newline
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bitfld.long 0x0C 6. "AUX_TIMER0_EV,AUX_TIMER0_EV event see AUX_TIMER01:T0TARGET for description" "0,1"
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newline
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bitfld.long 0x0C 5. "AUX_TIMER1_EV,AUX_TIMER1_EV event see AUX_TIMER01:T1TARGET for description" "0,1"
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newline
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bitfld.long 0x0C 4. "AUX_TIMER2_PULSE,AUX_TIMER2 pulse event" "0,1"
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newline
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bitfld.long 0x0C 3. "AUX_TIMER2_EV3,AUX_TIMER2 event output 3" "0,1"
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newline
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bitfld.long 0x0C 2. "AUX_TIMER2_EV2,AUX_TIMER2 event output 2" "0,1"
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newline
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bitfld.long 0x0C 1. "AUX_TIMER2_EV1,AUX_TIMER2 event output 1" "0,1"
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newline
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bitfld.long 0x0C 0. "AUX_TIMER2_EV0,AUX_TIMER2 event output 0" "0,1"
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line.long 0x10 "SCEWEVCFG0,Sensor Controller Engine Wait Event Configuration 0Configuration of this register and SCEWEVCFG1 controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS"
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hexmask.long 0x10 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 6. "COMB_EV_EN,Event combination control:0: Disable event combination.1: Enable event combination" "Disable event combination,Enable event combination"
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newline
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bitfld.long 0x10 0.--5. "EV0_SEL,Select the event source from the synchronous event bus to be used in event equation" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10 ,EVSTAT0.AUXIO11 ,EVSTAT0.AUXIO12 ,EVSTAT0.AUXIO13 ,EVSTAT0.AUXIO14 ,EVSTAT0.AUXIO15 ,EVSTAT1.AUXIO16 ,EVSTAT1.AUXIO17 ,EVSTAT1.AUXIO18 ,EVSTAT1.AUXIO19 ,EVSTAT1.AUXIO20 ,EVSTAT1.AUXIO21 ,EVSTAT1.AUXIO22 ,EVSTAT1.AUXIO23 ,EVSTAT1.AUXIO24 ,EVSTAT1.AUXIO25 ,EVSTAT1.AUXIO26 ,EVSTAT1.AUXIO27 ,EVSTAT1.AUXIO28 ,EVSTAT1.AUXIO29 ,EVSTAT1.AUXIO30 ,EVSTAT1.AUXIO31 ,Programmable delay event as described in PROGDLY,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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line.long 0x14 "SCEWEVCFG1,Sensor Controller Engine Wait Event Configuration 1See SCEWEVCFG0 for description"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 7. "EV0_POL,Polarity of SCEWEVCFG0.EV0_SEL event.When SCEWEVCFG0.COMB_EV_EN is" "Non-inverted,Inverted"
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newline
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bitfld.long 0x14 6. "EV1_POL,Polarity of EV1_SEL event.When SCEWEVCFG0.COMB_EV_EN is" "Non-inverted,Inverted"
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newline
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bitfld.long 0x14 0.--5. "EV1_SEL,Select the event source from the synchronous event bus to be used in event equation" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10 ,EVSTAT0.AUXIO11 ,EVSTAT0.AUXIO12 ,EVSTAT0.AUXIO13 ,EVSTAT0.AUXIO14 ,EVSTAT0.AUXIO15 ,EVSTAT1.AUXIO16 ,EVSTAT1.AUXIO17 ,EVSTAT1.AUXIO18 ,EVSTAT1.AUXIO19 ,EVSTAT1.AUXIO20 ,EVSTAT1.AUXIO21 ,EVSTAT1.AUXIO22 ,EVSTAT1.AUXIO23 ,EVSTAT1.AUXIO24 ,EVSTAT1.AUXIO25 ,EVSTAT1.AUXIO26 ,EVSTAT1.AUXIO27 ,EVSTAT1.AUXIO28 ,EVSTAT1.AUXIO29 ,EVSTAT1.AUXIO30 ,EVSTAT1.AUXIO31 ,Programmable delay event as described in PROGDLY,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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line.long 0x18 "DMACTL,Direct Memory Access Control"
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hexmask.long 0x18 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 2. "REQ_MODE,UDMA0 Request mode" "Burst requests are generated on UDMA0 channel 7..,Single requests are generated on UDMA0 channel 7.."
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newline
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bitfld.long 0x18 1. "EN,uDMA ADC interface enable.0: Disable UDMA0 interface to ADC.1: Enable UDMA0 interface to ADC" "Disable UDMA0 interface to ADC,Enable UDMA0 interface to ADC"
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newline
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bitfld.long 0x18 0. "SEL,Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data" "UDMA0 trigger event will be generated when there..,UDMA0 trigger event will be generated when the.."
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group.long 0x20++0x4B
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line.long 0x00 "SWEVSET,Software Event SetSet software event flags from AUX domain to AON and MCU domains"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 2. "SWEV2,Software event flag" "No effect,Set software event flag 2"
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newline
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bitfld.long 0x00 1. "SWEV1,Software event flag" "No effect,Set software event flag 1"
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newline
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bitfld.long 0x00 0. "SWEV0,Software event flag" "No effect,Set software event flag 0"
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line.long 0x04 "EVTOAONFLAGS,Events To AON FlagsThis register contains a collection of event flags routed to AON_EVENT"
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hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 8. "AUX_TIMER1_EV,This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV" "0,1"
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newline
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bitfld.long 0x04 7. "AUX_TIMER0_EV,This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV" "0,1"
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newline
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bitfld.long 0x04 6. "AUX_TDC_DONE,This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE" "0,1"
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newline
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bitfld.long 0x04 5. "AUX_ADC_DONE,This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE" "0,1"
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newline
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bitfld.long 0x04 4. "AUX_COMPB,This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB" "0,1"
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newline
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bitfld.long 0x04 3. "AUX_COMPA,This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA" "0,1"
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newline
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bitfld.long 0x04 2. "SWEV2,This event flag is set when software writes a 1 to SWEVSET.SWEV2" "0,1"
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newline
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bitfld.long 0x04 1. "SWEV1,This event flag is set when software writes a 1 to SWEVSET.SWEV1" "0,1"
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newline
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bitfld.long 0x04 0. "SWEV0,This event flag is set when software writes a 1 to SWEVSET.SWEV0" "0,1"
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line.long 0x08 "EVTOAONPOL,Events To AON PolarityEvent source polarity configuration for EVTOAONFLAGS"
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hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 8. "AUX_TIMER1_EV,Select the level of EVSTAT3.AUX_TIMER1_EV that sets EVTOAONFLAGS.AUX_TIMER1_EV" "High level,Low level"
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newline
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bitfld.long 0x08 7. "AUX_TIMER0_EV,Select the level of EVSTAT3.AUX_TIMER0_EV that sets EVTOAONFLAGS.AUX_TIMER0_EV" "High level,Low level"
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newline
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bitfld.long 0x08 6. "AUX_TDC_DONE,Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE" "High level,Low level"
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newline
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bitfld.long 0x08 5. "AUX_ADC_DONE,Select the level of EVSTAT3.AUX_ADC_DONE that sets EVTOAONFLAGS.AUX_ADC_DONE" "High level,Low level"
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newline
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bitfld.long 0x08 4. "AUX_COMPB,Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB" "Rising edge,Falling edge"
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newline
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bitfld.long 0x08 3. "AUX_COMPA,Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA" "Rising edge,Falling edge"
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newline
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rbitfld.long 0x08 0.--2. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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line.long 0x0C "EVTOAONFLAGSCLR,Events To AON ClearClear event flags in EVTOAONFLAGS"
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hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x0C 8. "AUX_TIMER1_EV,Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 7. "AUX_TIMER0_EV,Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 6. "AUX_TDC_DONE,Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x0C 5. "AUX_ADC_DONE,Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x0C 4. "AUX_COMPB,Write 1 to clear EVTOAONFLAGS.AUX_COMPB.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x0C 3. "AUX_COMPA,Write 1 to clear EVTOAONFLAGS.AUX_COMPA.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x0C 2. "SWEV2,Write 1 to clear EVTOAONFLAGS.SWEV2.Read value is 0" "0,1"
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newline
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bitfld.long 0x0C 1. "SWEV1,Write 1 to clear EVTOAONFLAGS.SWEV1.Read value is 0" "0,1"
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newline
|
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bitfld.long 0x0C 0. "SWEV0,Write 1 to clear EVTOAONFLAGS.SWEV0.Read value is 0" "0,1"
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line.long 0x10 "EVTOMCUFLAGS,Events to MCU FlagsThis register contains a collection of event flags routed to MCU domain"
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hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
|
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bitfld.long 0x10 15. "AUX_TIMER2_PULSE,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE occurs on EVSTAT3.AUX_TIMER2_PULSE" "0,1"
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newline
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bitfld.long 0x10 14. "AUX_TIMER2_EV3,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 occurs on EVSTAT3.AUX_TIMER2_EV3" "0,1"
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newline
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bitfld.long 0x10 13. "AUX_TIMER2_EV2,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 occurs on EVSTAT3.AUX_TIMER2_EV2" "0,1"
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newline
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bitfld.long 0x10 12. "AUX_TIMER2_EV1,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 occurs on EVSTAT3.AUX_TIMER2_EV1" "0,1"
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newline
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bitfld.long 0x10 11. "AUX_TIMER2_EV0,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 occurs on EVSTAT3.AUX_TIMER2_EV0" "0,1"
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newline
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bitfld.long 0x10 10. "AUX_ADC_IRQ,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs on EVSTAT3.AUX_ADC_IRQ" "0,1"
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|
newline
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bitfld.long 0x10 9. "MCU_OBSMUX0,This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT2.MCU_OBSMUX0" "0,1"
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newline
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bitfld.long 0x10 8. "AUX_ADC_FIFO_ALMOST_FULL,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL" "0,1"
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newline
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bitfld.long 0x10 7. "AUX_ADC_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs on EVSTAT3.AUX_ADC_DONE" "0,1"
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newline
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bitfld.long 0x10 6. "AUX_SMPH_AUTOTAKE_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE" "0,1"
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newline
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bitfld.long 0x10 5. "AUX_TIMER1_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV occurs on EVSTAT3.AUX_TIMER1_EV" "0,1"
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newline
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bitfld.long 0x10 4. "AUX_TIMER0_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV occurs on EVSTAT3.AUX_TIMER0_EV" "0,1"
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|
newline
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bitfld.long 0x10 3. "AUX_TDC_DONE,This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs on EVSTAT3.AUX_TDC_DONE" "0,1"
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newline
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bitfld.long 0x10 2. "AUX_COMPB,This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT2.AUX_COMPB" "0,1"
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|
newline
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bitfld.long 0x10 1. "AUX_COMPA,This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT2.AUX_COMPA" "0,1"
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|
newline
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bitfld.long 0x10 0. "AUX_WU_EV,This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on reduction-OR of the AUX_SYSIF:WUFLAGS register" "0,1"
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line.long 0x14 "EVTOMCUPOL,Event To MCU PolarityEvent source polarity configuration for EVTOMCUFLAGS"
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|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x14 15. "AUX_TIMER2_PULSE,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE" "High level,Low level"
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|
newline
|
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bitfld.long 0x14 14. "AUX_TIMER2_EV3,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3" "High level,Low level"
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|
newline
|
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bitfld.long 0x14 13. "AUX_TIMER2_EV2,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2" "High level,Low level"
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|
newline
|
|
bitfld.long 0x14 12. "AUX_TIMER2_EV1,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1" "High level,Low level"
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|
newline
|
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bitfld.long 0x14 11. "AUX_TIMER2_EV0,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0" "High level,Low level"
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|
newline
|
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bitfld.long 0x14 10. "AUX_ADC_IRQ,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ" "High level,Low level"
|
|
newline
|
|
bitfld.long 0x14 9. "MCU_OBSMUX0,Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0" "High level,Low level"
|
|
newline
|
|
bitfld.long 0x14 8. "AUX_ADC_FIFO_ALMOST_FULL,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL" "High level,Low level"
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newline
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bitfld.long 0x14 7. "AUX_ADC_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE" "High level,Low level"
|
|
newline
|
|
bitfld.long 0x14 6. "AUX_SMPH_AUTOTAKE_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE" "High level,Low level"
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newline
|
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bitfld.long 0x14 5. "AUX_TIMER1_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV" "High level,Low level"
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|
newline
|
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bitfld.long 0x14 4. "AUX_TIMER0_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV" "High level,Low level"
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newline
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bitfld.long 0x14 3. "AUX_TDC_DONE,Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE" "High level,Low level"
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newline
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bitfld.long 0x14 2. "AUX_COMPB,Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB" "Rising edge,Falling edge"
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newline
|
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bitfld.long 0x14 1. "AUX_COMPA,Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA" "Rising edge,Falling edge"
|
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newline
|
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bitfld.long 0x14 0. "AUX_WU_EV,Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV" "High level,Low level"
|
|
line.long 0x18 "EVTOMCUFLAGSCLR,Events To MCU Flags ClearClear event flags in EVTOMCUFLAGS"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 15. "AUX_TIMER2_PULSE,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE.Read value is 0" "0,1"
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|
newline
|
|
bitfld.long 0x18 14. "AUX_TIMER2_EV3,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "AUX_TIMER2_EV2,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "AUX_TIMER2_EV1,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "AUX_TIMER2_EV0,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 10. "AUX_ADC_IRQ,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "MCU_OBSMUX0,Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "AUX_ADC_FIFO_ALMOST_FULL,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "AUX_ADC_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "AUX_SMPH_AUTOTAKE_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "AUX_TIMER1_EV,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "AUX_TIMER0_EV,Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "AUX_TDC_DONE,Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "AUX_COMPB,Write 1 to clear EVTOMCUFLAGS.AUX_COMPB.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "AUX_COMPA,Write 1 to clear EVTOMCUFLAGS.AUX_COMPA.Read value is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "AUX_WU_EV,Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV.Read value is 0" "0,1"
|
|
line.long 0x1C "COMBEVTOMCUMASK,Combined Event To MCU MaskSelect event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU.The AUX_COMB event is high as long as one or more of the included event flags are set"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 15. "AUX_TIMER2_PULSE,EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 14. "AUX_TIMER2_EV3,EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 13. "AUX_TIMER2_EV2,EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 12. "AUX_TIMER2_EV1,EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 11. "AUX_TIMER2_EV0,EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 10. "AUX_ADC_IRQ,EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 9. "MCU_OBSMUX0,EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 8. "AUX_ADC_FIFO_ALMOST_FULL,EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 7. "AUX_ADC_DONE,EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 6. "AUX_SMPH_AUTOTAKE_DONE,EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 5. "AUX_TIMER1_EV,EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 4. "AUX_TIMER0_EV,EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 3. "AUX_TDC_DONE,EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 2. "AUX_COMPB,EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event.0: Exclude1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 1. "AUX_COMPA,EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
newline
|
|
bitfld.long 0x1C 0. "AUX_WU_EV,EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event.0: Exclude.1: Include" "Exclude,Include"
|
|
line.long 0x20 "EVOBSCFG,Event Observation Configuration"
|
|
hexmask.long 0x20 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--5. "EVOBS_SEL,Select which event from the asynchronous event bus that represents AUX_EV_OBS in AUX_AIODIOn" "EVSTAT0.AUXIO0 ,EVSTAT0.AUXIO1 ,EVSTAT0.AUXIO2 ,EVSTAT0.AUXIO3 ,EVSTAT0.AUXIO4 ,EVSTAT0.AUXIO5 ,EVSTAT0.AUXIO6 ,EVSTAT0.AUXIO7 ,EVSTAT0.AUXIO8 ,EVSTAT0.AUXIO9 ,EVSTAT0.AUXIO10,EVSTAT0.AUXIO11,EVSTAT0.AUXIO12,EVSTAT0.AUXIO13,EVSTAT0.AUXIO14,EVSTAT0.AUXIO15,EVSTAT1.AUXIO16,EVSTAT1.AUXIO17,EVSTAT1.AUXIO18,EVSTAT1.AUXIO19,EVSTAT1.AUXIO20,EVSTAT1.AUXIO21,EVSTAT1.AUXIO22,EVSTAT1.AUXIO23,EVSTAT1.AUXIO24,EVSTAT1.AUXIO25,EVSTAT1.AUXIO26,EVSTAT1.AUXIO27,EVSTAT1.AUXIO28,EVSTAT1.AUXIO29,EVSTAT1.AUXIO30,EVSTAT1.AUXIO31,EVSTAT2.MANUAL_EV,EVSTAT2.AON_RTC_CH2 ,EVSTAT2.AON_RTC_CH2_DLY ,EVSTAT2.AON_RTC_4KHZ ,EVSTAT2.AON_BATMON_BAT_UPD ,EVSTAT2.AON_BATMON_TEMP_UPD ,EVSTAT2.SCLK_LF ,EVSTAT2.PWR_DWN ,EVSTAT2.MCU_ACTIVE ,EVSTAT2.VDDR_RECHARGE ,EVSTAT2.ACLK_REF ,EVSTAT2.MCU_EV ,EVSTAT2.MCU_OBSMUX0 ,EVSTAT2.MCU_OBSMUX1 ,EVSTAT2.AUX_COMPA ,EVSTAT2.AUX_COMPB ,EVSTAT3.AUX_TIMER2_EV0 ,EVSTAT3.AUX_TIMER2_EV1 ,EVSTAT3.AUX_TIMER2_EV2 ,EVSTAT3.AUX_TIMER2_EV3 ,EVSTAT3.AUX_TIMER2_PULSE ,EVSTAT3.AUX_TIMER1_EV ,EVSTAT3.AUX_TIMER0_EV ,EVSTAT3.AUX_TDC_DONE ,EVSTAT3.AUX_ISRC_RESET_N ,EVSTAT3.AUX_ADC_DONE ,EVSTAT3.AUX_ADC_IRQ ,EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL ,EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY ,EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,EVSTAT3.AUX_DAC_HOLD_ACTIVE ,EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
|
|
line.long 0x24 "PROGDLY,Programmable Delay"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "VALUE,VALUE decrements to 0 at a rate of 1 MHz.The event AUX_PROG_DLY_IDLE is high when VALUE is 0 otherwise it is low"
|
|
line.long 0x28 "MANUAL,ManualProgrammable event"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0. "EV,This bit field sets the value of EVSTAT2.MANUAL_EV" "0,1"
|
|
line.long 0x2C "EVSTAT0L,Event Status 0 Low"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "ALIAS_EV,Alias of EVSTAT0 event 7 down to 0"
|
|
line.long 0x30 "EVSTAT0H,Event Status 0 High"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "ALIAS_EV,Alias of EVSTAT0 event 15 down to 8"
|
|
line.long 0x34 "EVSTAT1L,Event Status 1 Low"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "ALIAS_EV,Alias of EVSTAT1 event 7 down to 0"
|
|
line.long 0x38 "EVSTAT1H,Event Status 1 High"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "ALIAS_EV,Alias of EVSTAT1 event 15 down to 8"
|
|
line.long 0x3C "EVSTAT2L,Event Status 2 Low"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "ALIAS_EV,Alias of EVSTAT2 event 7 down to 0"
|
|
line.long 0x40 "EVSTAT2H,Event Status 2 High"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "ALIAS_EV,Alias of EVSTAT2 event 15 down to 8"
|
|
line.long 0x44 "EVSTAT3L,Event Status 3 Low"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "ALIAS_EV,Alias of EVSTAT3 event 7 down to 0"
|
|
line.long 0x48 "EVSTAT3H,Event Status 3 High"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "ALIAS_EV,Alias of EVSTAT3 event 15 down to 8"
|
|
tree.end
|
|
tree "AUX_MAC"
|
|
base ad:0x400C2000
|
|
wgroup.long 0x00++0x9F
|
|
line.long 0x00 "OP0S,Signed Operand 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "OP0_VALUE,Signed operand 0.Operand for multiply multiply-and-accumulate or 32-bit add operations"
|
|
line.long 0x04 "OP0U,Unsigned Operand 0"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x04 0.--15. 1. "OP0_VALUE,Unsigned operand 0.Operand for multiply multiply-and-accumulate or 32-bit add operations"
|
|
line.long 0x08 "OP1SMUL,Signed Operand 1 and Multiply"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x08 0.--15. 1. "OP1_VALUE,Signed operand 1 and multiplication trigger.Write OP1_VALUE to set signed operand 1 and trigger the following operation:When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * OP0S.OP0_VALUE.When operand 0 was written to.."
|
|
line.long 0x0C "OP1UMUL,Unsigned Operand 1 and Multiply"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x0C 0.--15. 1. "OP1_VALUE,Unsigned operand 1 and multiplication trigger.Write OP1_VALUE to set unsigned operand 1 and trigger the following operation:When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * OP0S.OP0_VALUE.When operand 0 was written to.."
|
|
line.long 0x10 "OP1SMAC,Signed Operand 1 and Multiply-Accumulate"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x10 0.--15. 1. "OP1_VALUE,Signed operand 1 and multiply-accumulation trigger.Write OP1_VALUE to set signed operand 1 and trigger the following operation:When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * OP0S.OP0_VALUE ).When operand 0 was written.."
|
|
line.long 0x14 "OP1UMAC,Unsigned Operand 1 and Multiply-Accumulate"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "OP1_VALUE,Unsigned operand 1 and multiply-accumulation trigger.Write OP1_VALUE to set unsigned operand 1 and trigger the following operation:When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * OP0S.OP0_VALUE ).When operand 0 was.."
|
|
line.long 0x18 "OP1SADD16,Signed Operand 1 and 16-bit Addition"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x18 0.--15. 1. "OP1_VALUE,Signed operand 1 and 16-bit addition trigger.Write OP1_VALUE to set signed operand 1 and trigger the following operation:ACC = ACC + OP1_VALUE"
|
|
line.long 0x1C "OP1UADD16,Unsigned Operand 1 and 16-bit Addition"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x1C 0.--15. 1. "OP1_VALUE,Unsigned operand 1 and 16-bit addition trigger.Write OP1_VALUE to set unsigned operand 1 and trigger the following operation:ACC = ACC + OP1_VALUE"
|
|
line.long 0x20 "OP1SADD32,Signed Operand 1 and 32-bit Addition"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x20 0.--15. 1. "OP1_VALUE,Upper half of signed 32-bit operand and addition trigger.Write OP1_VALUE to set upper half of signed 32-bit operand and trigger the following operation:When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + (( OP1_VALUE.."
|
|
line.long 0x24 "OP1UADD32,Unsigned Operand 1 and 32-bit Addition"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x24 0.--15. 1. "OP1_VALUE,Upper half of unsigned 32-bit operand and addition trigger.Write OP1_VALUE to set upper half of unsigned 32-bit operand and trigger the following operation:When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + ((.."
|
|
line.long 0x28 "CLZ,Count Leading Zero"
|
|
hexmask.long 0x28 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0.--5. "VALUE,Number of leading zero bits in" "0 leading zeros,1 leading zero,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,40 leading zeros (accumulator value is 0),?..."
|
|
line.long 0x2C "CLS,Count Leading Sign"
|
|
hexmask.long 0x2C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0.--5. "VALUE,Number of leading sign bits in the accumulator.When MSB of accumulator is 0 VALUE is number of leading zeros MSB included.When MSB of accumulator is 1 VALUE is number of leading ones MSB included.VALUE range is 1 thru 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x30 "ACCSHIFT,Accumulator Shift Only one shift operation can be triggered per register"
|
|
hexmask.long 0x30 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x30 2. "LSL1,Logic shift left by 1 bit.Write 1 to shift the accumulator one bit to the left 0 inserted at bit 0" "0,1"
|
|
bitfld.long 0x30 1. "LSR1,Logic shift right by 1 bit.Write 1 to shift the accumulator one bit to the right 0 inserted at bit 39" "0,1"
|
|
bitfld.long 0x30 0. "ASR1,Arithmetic shift right by 1 bit.Write 1 to shift the accumulator one bit to the right previous sign bit inserted at bit 39" "0,1"
|
|
line.long 0x34 "ACCRESET,Accumulator Reset"
|
|
hexmask.long.word 0x34 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x34 0.--15. 1. "TRG,Write any value to this register to trigger a reset of all bits in the accumulator"
|
|
line.long 0x38 "ACC15_0,Accumulator Bits 15:0"
|
|
hexmask.long.word 0x38 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x38 0.--15. 1. "VALUE,Value of the accumulator bits 15:0.Write VALUE to initialize bits 15:0 of accumulator"
|
|
line.long 0x3C "ACC16_1,Accumulator Bits 16:1"
|
|
hexmask.long.word 0x3C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x3C 0.--15. 1. "VALUE,Value of the accumulator bits 16:1"
|
|
line.long 0x40 "ACC17_2,Accumulator Bits 17:2"
|
|
hexmask.long.word 0x40 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x40 0.--15. 1. "VALUE,Value of the accumulator bits 17:2"
|
|
line.long 0x44 "ACC18_3,Accumulator Bits 18:3"
|
|
hexmask.long.word 0x44 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x44 0.--15. 1. "VALUE,Value of the accumulator bits 18:3"
|
|
line.long 0x48 "ACC19_4,Accumulator Bits 19:4"
|
|
hexmask.long.word 0x48 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x48 0.--15. 1. "VALUE,Value of the accumulator bits 19:4"
|
|
line.long 0x4C "ACC20_5,Accumulator Bits 20:5"
|
|
hexmask.long.word 0x4C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x4C 0.--15. 1. "VALUE,Value of the accumulator bits 20:5"
|
|
line.long 0x50 "ACC21_6,Accumulator Bits 21:6"
|
|
hexmask.long.word 0x50 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x50 0.--15. 1. "VALUE,Value of the accumulator bits 21:6"
|
|
line.long 0x54 "ACC22_7,Accumulator Bits 22:7"
|
|
hexmask.long.word 0x54 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x54 0.--15. 1. "VALUE,Value of the accumulator bits 22:7"
|
|
line.long 0x58 "ACC23_8,Accumulator Bits 23:8"
|
|
hexmask.long.word 0x58 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x58 0.--15. 1. "VALUE,Value of the accumulator bits 23:8"
|
|
line.long 0x5C "ACC24_9,Accumulator Bits 24:9"
|
|
hexmask.long.word 0x5C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x5C 0.--15. 1. "VALUE,Value of the accumulator bits 24:9"
|
|
line.long 0x60 "ACC25_10,Accumulator Bits 25:10"
|
|
hexmask.long.word 0x60 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x60 0.--15. 1. "VALUE,Value of the accumulator bits 25:10"
|
|
line.long 0x64 "ACC26_11,Accumulator Bits 26:11"
|
|
hexmask.long.word 0x64 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x64 0.--15. 1. "VALUE,Value of the accumulator bits 26:11"
|
|
line.long 0x68 "ACC27_12,Accumulator Bits 27:12"
|
|
hexmask.long.word 0x68 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x68 0.--15. 1. "VALUE,Value of the accumulator bits 27:12"
|
|
line.long 0x6C "ACC28_13,Accumulator Bits 28:13"
|
|
hexmask.long.word 0x6C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x6C 0.--15. 1. "VALUE,Value of the accumulator bits 28:13"
|
|
line.long 0x70 "ACC29_14,Accumulator Bits 29:14"
|
|
hexmask.long.word 0x70 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x70 0.--15. 1. "VALUE,Value of the accumulator bits 29:14"
|
|
line.long 0x74 "ACC30_15,Accumulator Bits 30:15"
|
|
hexmask.long.word 0x74 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x74 0.--15. 1. "VALUE,Value of the accumulator bits 30:15"
|
|
line.long 0x78 "ACC31_16,Accumulator Bits 31:16"
|
|
hexmask.long.word 0x78 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x78 0.--15. 1. "VALUE,Value of the accumulator bits 31:16.Write VALUE to initialize bits 31:16 of accumulator"
|
|
line.long 0x7C "ACC32_17,Accumulator Bits 32:17"
|
|
hexmask.long.word 0x7C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x7C 0.--15. 1. "VALUE,Value of the accumulator bits 32:17"
|
|
line.long 0x80 "ACC33_18,Accumulator Bits 33:18"
|
|
hexmask.long.word 0x80 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x80 0.--15. 1. "VALUE,Value of the accumulator bits 33:18"
|
|
line.long 0x84 "ACC34_19,Accumulator Bits 34:19"
|
|
hexmask.long.word 0x84 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x84 0.--15. 1. "VALUE,Value of the accumulator bits 34:19"
|
|
line.long 0x88 "ACC35_20,Accumulator Bits 35:20"
|
|
hexmask.long.word 0x88 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x88 0.--15. 1. "VALUE,Value of the accumulator bits 35:20"
|
|
line.long 0x8C "ACC36_21,Accumulator Bits 36:21"
|
|
hexmask.long.word 0x8C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x8C 0.--15. 1. "VALUE,Value of the accumulator bits 36:21"
|
|
line.long 0x90 "ACC37_22,Accumulator Bits 37:22"
|
|
hexmask.long.word 0x90 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x90 0.--15. 1. "VALUE,Value of the accumulator bits 37:22"
|
|
line.long 0x94 "ACC38_23,Accumulator Bits 38:23"
|
|
hexmask.long.word 0x94 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x94 0.--15. 1. "VALUE,Value of the accumulator bits 38:23"
|
|
line.long 0x98 "ACC39_24,Accumulator Bits 39:24"
|
|
hexmask.long.word 0x98 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x98 0.--15. 1. "VALUE,Value of the accumulator bits 39:24"
|
|
line.long 0x9C "ACC39_32,Accumulator Bits 39:32"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "VALUE,Value of the accumulator bits 39:32.Write VALUE to initialize bits 39:32 of accumulator"
|
|
tree.end
|
|
tree "AUX_SCE"
|
|
base ad:0x580E1000
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CTL,Internal"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FORCE_EV_LOW,Internal"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FORCE_EV_HIGH,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESET_VECTOR,Internal"
|
|
rbitfld.long 0x00 7. "RESERVED7,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "DBG_FREEZE_EN,Internal" "0,1"
|
|
bitfld.long 0x00 5. "FORCE_WU_LOW,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "FORCE_WU_HIGH,Internal" "0,1"
|
|
bitfld.long 0x00 3. "RESTART,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SINGLE_STEP,Internal" "0,1"
|
|
bitfld.long 0x00 1. "SUSPEND,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CLK_EN,Internal" "0,1"
|
|
line.long 0x04 "FETCHSTAT,Internal"
|
|
hexmask.long.word 0x04 16.--31. 1. "OPCODE,Internal"
|
|
hexmask.long.word 0x04 0.--15. 1. "PC,Internal"
|
|
line.long 0x08 "CPUSTAT,Internal"
|
|
hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED12,Internal"
|
|
bitfld.long 0x08 11. "BUS_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. "SLEEP,Internal" "0,1"
|
|
bitfld.long 0x08 9. "WEV,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "HALTED,Internal" "0,1"
|
|
bitfld.long 0x08 4.--7. "RESERVED4,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 3. "V_FLAG,Internal" "0,1"
|
|
bitfld.long 0x08 2. "C_FLAG,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "N_FLAG,Internal" "0,1"
|
|
bitfld.long 0x08 0. "Z_FLAG,Internal" "0,1"
|
|
line.long 0x0C "WUSTAT,Internal"
|
|
hexmask.long.word 0x0C 19.--31. 1. "RESERVED20,Internal"
|
|
bitfld.long 0x0C 16.--18. "EXC_VECTOR,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0C 9.--15. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x0C 8. "WU_SIGNAL,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV_SIGNALS,Internal"
|
|
line.long 0x10 "REG1_0,Internal"
|
|
hexmask.long.word 0x10 16.--31. 1. "REG1,Internal"
|
|
hexmask.long.word 0x10 0.--15. 1. "REG0,Internal"
|
|
line.long 0x14 "REG3_2,Internal"
|
|
hexmask.long.word 0x14 16.--31. 1. "REG3,Internal"
|
|
hexmask.long.word 0x14 0.--15. 1. "REG2,Internal"
|
|
line.long 0x18 "REG5_4,Internal"
|
|
hexmask.long.word 0x18 16.--31. 1. "REG5,Internal"
|
|
hexmask.long.word 0x18 0.--15. 1. "REG4,Internal"
|
|
line.long 0x1C "REG7_6,Internal"
|
|
hexmask.long.word 0x1C 16.--31. 1. "REG7,Internal"
|
|
hexmask.long.word 0x1C 0.--15. 1. "REG6,Internal"
|
|
line.long 0x20 "LOOPADDR,Internal"
|
|
hexmask.long.word 0x20 16.--31. 1. "STOP,Internal"
|
|
hexmask.long.word 0x20 0.--15. 1. "START,Internal"
|
|
line.long 0x24 "LOOPCNT,Internal"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED8,Internal"
|
|
hexmask.long.byte 0x24 0.--7. 1. "ITER_LEFT,Internal"
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "NONSECDDIACC$1,Non-Secure DDI Access 0When system is in secure state. AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED23,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 22. "RD_EN,Read Enable0: AUX_SCE is not allowed to read DDI half-word given by ADDR.1: AUX_SCE is allowed to read DDI half-word given by ADDR." "AUX_SCE is not allowed to read DDI half-word..,AUX_SCE is allowed to read DDI half-word given.."
|
|
newline
|
|
bitfld.long 0x00 16.--21. "ADDR,AddressAUX_SCE is allowed to update this DDI half-word using SET or CLR access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--15. 1. "WR_MASK,MaskAUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask"
|
|
repeat.end
|
|
tree.end
|
|
tree "AUX_SMPH"
|
|
base ad:0x400C8000
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SMPH$1,Semaphore 0"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Request or release of semaphore.Request by read:0: Semaphore not available.1: Semaphore granted.Release by write:0: Do not use.1: Release semaphore" "Do not use,Release semaphore"
|
|
repeat.end
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AUTOTAKE,Auto TakeSticky Request for Single Semaphore"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--2. "SMPH_ID,Write the semaphore ID 0x0-0x7 to SMPH_ID to request this semaphore until it is granted" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "AUX_SPIM"
|
|
base ad:0x400C1000
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "SPIMCFG,SPI Master ConfigurationWrite operation stalls until current transfer completes"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 2.--7. "DIV,SCLK divider.Peripheral clock frequency division gives the SCLK clock frequency" "Divide by 2,Divide by 4,Divide by 6,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 128"
|
|
bitfld.long 0x00 1. "PHA,Phase of the MOSI and MISO data signals.0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) edges of SCLK.1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) edges of SCLK." "Sample MISO at leading (odd) edges and shift..,Sample MISO at trailing (even) edges and shift.."
|
|
newline
|
|
bitfld.long 0x00 0. "POL,Polarity of the SCLK signal.0: SCLK is low when idle first clock edge rises.1: SCLK is high when idle first clock edge falls." "SCLK is low when idle first clock edge rises,SCLK is high when idle first clock edge falls"
|
|
line.long 0x04 "MISOCFG,MISO ConfigurationWrite operation stalls until current transfer completes"
|
|
hexmask.long 0x04 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0.--4. "AUXIO,AUXIO to MISO mux.Select the AUXIO pin that connects to MISO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "MOSICTL,MOSI ControlWrite operation stalls until current transfer completes"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "VALUE,MOSI level control.0: Set MOSI low.1: Set MOSI high" "Set MOSI low,Set MOSI high"
|
|
line.long 0x0C "TX8,Transmit 8 BitWrite operation stalls until current transfer completes"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "DATA,8 bit data transfer.Write DATA to start transfer MSB first"
|
|
line.long 0x10 "TX16,Transmit 16 BitWrite operation stalls until current transfer completes"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x10 0.--15. 1. "DATA,16 bit data transfer.Write DATA to start transfer MSB first"
|
|
line.long 0x14 "RX8,Receive 8 BitRead operation stalls until current transfer completes"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DATA,Latest 8 bits received on MISO"
|
|
line.long 0x18 "RX16,Receive 16 BitRead operation stalls until current transfer completes"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x18 0.--15. 1. "DATA,Latest 16 bits received on MISO"
|
|
line.long 0x1C "SCLKIDLE,SCLK IdleRead operation stalls until SCLK is idle with no remaining clock edges"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "STAT,Wait for SCLK idle.Read operation stalls until SCLK is idle with no remaining clock edges" "0,1"
|
|
line.long 0x20 "DATAIDLE,Data IdleRead operation stalls until current transfer completes"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT,Wait for data idle.Read operation stalls until the SCLK period associated with LSB transmission completes" "0,1"
|
|
tree.end
|
|
tree "AUX_SYSIF"
|
|
base ad:0x580C6000
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "OPMODEREQ,Operational Mode RequestAUX can operate in three operational modes"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "REQ,AUX operational mode request" "Active operational mode characterized by:-..,Lowpower operational mode characterized by:-..,Powerdown operational mode with wakeup to active..,Powerdown operational mode with wakeup to.."
|
|
line.long 0x04 "OPMODEACK,Operational Mode AcknowledgementAUX_SCE program must assume that the current operational mode is the one acknowledged"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "ACK,AUX operational mode acknowledgement" "Active operational mode is acknowledged.,Lowpower operational mode is acknowledged.,Powerdown operational mode with wakeup to active..,Powerdown operational mode with wakeup to.."
|
|
line.long 0x08 "PROGWU0CFG,Programmable Wakeup 0 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
|
|
newline
|
|
bitfld.long 0x08 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
|
|
line.long 0x0C "PROGWU1CFG,Programmable Wakeup 1 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
|
|
newline
|
|
bitfld.long 0x0C 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
|
|
newline
|
|
bitfld.long 0x0C 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x10 "PROGWU2CFG,Programmable Wakeup 2 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x10 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x10 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x14 "PROGWU3CFG,Programmable Wakeup 3 ConfigurationConfigure this register to enable a customized AUX wakeup flag"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 7. "POL,Polarity of WU_SRC" "The wakeup flag is set when WU_SRC is high or..,The wakeup flag is set when WU_SRC is low or.."
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newline
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bitfld.long 0x14 6. "EN,Programmable wakeup flag enable.0: Disable wakeup flag.1: Enable wakeup flag" "Disable wakeup flag,Enable wakeup flag"
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newline
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bitfld.long 0x14 0.--5. "WU_SRC,Wakeup source from the asynchronous AUX event bus.Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1.If you write a non-enumerated value the behavior is identical to NO_EVENT" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x18 "SWWUTRIG,Software Wakeup Triggers System CPU uses these wakeup flags to perform handshaking with AUX_SCE"
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hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 3. "SW_WU3,Software wakeup 3 trigger.0: No effect.1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU3 and.."
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newline
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bitfld.long 0x18 2. "SW_WU2,Software wakeup 2 trigger.0: No effect.1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU2 and.."
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newline
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bitfld.long 0x18 1. "SW_WU1,Software wakeup 1 trigger.0: No effect.1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU1 and.."
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newline
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bitfld.long 0x18 0. "SW_WU0,Software wakeup 0 trigger.0: No effect.1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup" "No effect,Set WUFLAGS.SW_WU0 and.."
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line.long 0x1C "WUFLAGS,Wakeup FlagsThis register holds the eight AUX wakeup flags"
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hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 7. "SW_WU3,Software wakeup 3 flag.0: Software wakeup 3 not triggered.1: Software wakeup 3 triggered" "Software wakeup 3 not triggered,Software wakeup 3 triggered"
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newline
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bitfld.long 0x1C 6. "SW_WU2,Software wakeup 2 flag.0: Software wakeup 2 not triggered.1: Software wakeup 2 triggered" "Software wakeup 2 not triggered,Software wakeup 2 triggered"
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newline
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bitfld.long 0x1C 5. "SW_WU1,Software wakeup 1 flag.0: Software wakeup 1 not triggered.1: Software wakeup 1 triggered" "Software wakeup 1 not triggered,Software wakeup 1 triggered"
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newline
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bitfld.long 0x1C 4. "SW_WU0,Software wakeup 0 flag.0: Software wakeup 0 not triggered.1: Software wakeup 0 triggered" "Software wakeup 0 not triggered,Software wakeup 0 triggered"
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newline
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bitfld.long 0x1C 3. "PROG_WU3,Programmable wakeup" "Programmable wakeup 3 not triggered,Programmable wakeup 3 triggered"
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newline
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bitfld.long 0x1C 2. "PROG_WU2,Programmable wakeup" "Programmable wakeup 2 not triggered,Programmable wakeup 2 triggered"
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newline
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bitfld.long 0x1C 1. "PROG_WU1,Programmable wakeup" "Programmable wakeup 1 not triggered,Programmable wakeup 1 triggered"
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newline
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bitfld.long 0x1C 0. "PROG_WU0,Programmable wakeup" "Programmable wakeup 0 not triggered,Programmable wakeup 0 triggered"
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line.long 0x20 "WUFLAGSCLR,Wakeup Flags ClearThis register clears AUX wakeup flags WUFLAGS"
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 7. "SW_WU3,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU3"
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newline
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bitfld.long 0x20 6. "SW_WU2,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU2"
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newline
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bitfld.long 0x20 5. "SW_WU1,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU1"
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newline
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bitfld.long 0x20 4. "SW_WU0,Clear software wakeup flag" "No effect,Clear WUFLAGS.SW_WU0"
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newline
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bitfld.long 0x20 3. "PROG_WU3,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU3"
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newline
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bitfld.long 0x20 2. "PROG_WU2,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU2"
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newline
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bitfld.long 0x20 1. "PROG_WU1,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU1"
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newline
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bitfld.long 0x20 0. "PROG_WU0,Programmable wakeup flag" "No effect,Clear WUFLAGS.PROG_WU0"
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line.long 0x24 "WUGATE,Wakeup GateYou must disable the AUX wakeup output:- Before you clear a programmable wakeup flag.- Before you change the value of [PROGWUnCFG.EN] or [PROGWUnCFG.WU_SRC].The AUX wakeup output must be re-enabled after clear operation or programmable.."
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hexmask.long 0x24 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 0. "EN,Wakeup output enable.0: Disable AUX wakeup output.1: Enable AUX wakeup output" "Disable AUX wakeup output,Enable AUX wakeup output"
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repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
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group.long ($2+0x28)++0x03
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line.long 0x00 "VECCFG$1,Vector Configuration 0AUX_SCE wakeup vector 0 configuration"
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hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--3. "VEC_EV,Select trigger event for vector 0.Non-enumerated values are treated as NONE" "Vector is disabled.,WUFLAGS.PROG_WU0,WUFLAGS.PROG_WU1,WUFLAGS.PROG_WU2,WUFLAGS.PROG_WU3,WUFLAGS.SW_WU0 ,WUFLAGS.SW_WU1 ,WUFLAGS.SW_WU2 ,WUFLAGS.SW_WU3 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY,?,?,?,?,?,?"
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repeat.end
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group.long 0x48++0x23
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line.long 0x00 "EVSYNCRATE,Event Synchronization Rate Configure synchronization rate for certain events to the synchronous AUX event bus.You must select SCE rate when AUX_SCE uses the event"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 2. "AUX_COMPA_SYNC_RATE,Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x00 1. "AUX_COMPB_SYNC_RATE,Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x00 0. "AUX_TIMER2_SYNC_RATE,Select synchronization rate for:- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3- AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE" "SCE rate,AUX bus rate"
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line.long 0x04 "PEROPRATE,Peripheral Operational Rate Some AUX peripherals are operated at either SCE or at AUX bus rate"
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hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 3. "ANAIF_DAC_OP_RATE,Select operational rate for AUX_ANAIF DAC sample clock state machine" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 2. "TIMER01_OP_RATE,Select operational rate for AUX_TIMER01" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 1. "SPIM_OP_RATE,Select operational rate for AUX_SPIM" "SCE rate,AUX bus rate"
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newline
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bitfld.long 0x04 0. "MAC_OP_RATE,Select operational rate for AUX_MAC" "SCE rate,AUX bus rate"
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line.long 0x08 "ADCCLKCTL,ADC Clock Control"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 1. "ACK,Clock acknowledgement.0: ADC clock is disabled.1: ADC clock is enabled" "ADC clock is disabled,ADC clock is enabled"
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newline
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bitfld.long 0x08 0. "REQ,ADC clock request.0: Disable ADC clock.1: Enable ADC clock.Only modify REQ when equal to ACK." "Disable ADC clock,Enable ADC clock.Only modify REQ when equal to ACK"
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line.long 0x0C "TDCCLKCTL,TDC Counter Clock ControlControls if the AUX_TDC counter clock source is enabled"
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hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 1. "ACK,TDC counter clock acknowledgement.0: TDC counter clock is disabled.1: TDC counter clock is enabled" "TDC counter clock is disabled,TDC counter clock is enabled"
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newline
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bitfld.long 0x0C 0. "REQ,TDC counter clock request.0: Disable TDC counter clock.1: Enable TDC counter clock.Only modify REQ when equal to ACK." "Disable TDC counter clock,Enable TDC counter clock.Only modify REQ when.."
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line.long 0x10 "TDCREFCLKCTL,TDC Reference Clock ControlControls if the AUX_TDC reference clock source is enabled"
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hexmask.long 0x10 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 1. "ACK,TDC reference clock acknowledgement.0: TDC reference clock is disabled.1: TDC reference clock is enabled" "TDC reference clock is disabled,TDC reference clock is enabled"
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newline
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bitfld.long 0x10 0. "REQ,TDC reference clock request.0: Disable TDC reference clock.1: Enable TDC reference clock.Only modify REQ when equal to ACK." "Disable TDC reference clock,Enable TDC reference clock.Only modify REQ when.."
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line.long 0x14 "TIMER2CLKCTL,AUX_TIMER2 Clock ControlAccess to AUX_TIMER2 is only possible when TIMER2CLKSTAT.STAT is different from NONE"
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hexmask.long 0x14 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 0.--2. "SRC,Select clock source for AUX_TIMER2.Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or TIMER2CLKSWITCH.RDY is 1.It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0" "no clock,SCLK_LF,SCLK_MF,?,SCLK_HF / 2,?,?,?"
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line.long 0x18 "TIMER2CLKSTAT,AUX_TIMER2 Clock Status"
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hexmask.long 0x18 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 0.--2. "STAT,AUX_TIMER2 clock source status" "No clock ,SCLK_LF,SCLK_MF,?,SCLK_HF / 2,?,?,?"
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line.long 0x1C "TIMER2CLKSWITCH,AUX_TIMER2 Clock Switch"
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hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 0. "RDY,Status of clock switcher.0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT.1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT.RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY" "TIMER2CLKCTL.SRC is different from..,TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT.RDY.."
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line.long 0x20 "TIMER2DBGCTL,AUX_TIMER2 Debug Control"
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hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 0. "DBG_FREEZE_EN,Debug freeze enable.0: AUX_TIMER2 does not halt when the system CPU halts in debug mode.1: Halt AUX_TIMER2 when the system CPU halts in debug mode" "AUX_TIMER2 does not halt when the system CPU..,Halt AUX_TIMER2 when the system CPU halts in.."
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group.long 0x70++0x27
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line.long 0x00 "CLKSHIFTDET,Clock Shift DetectionA transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF:- A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when.."
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "STAT,Clock shift detection.Write:0: Restart clock shift detection.1: Do not use.Read:0: MCU domain did not enter or exit active state since you wrote 0 to STAT" "MCU domain did not enter or exit active state..,MCU domain entered or exited active state since.."
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line.long 0x04 "RECHARGETRIG,VDDR Recharge Trigger"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "TRIG,Recharge trigger.0: No effect.1: Request VDDR recharge" "No effect,Request VDDR recharge"
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line.long 0x08 "RECHARGEDET,VDDR Recharge DetectionSome applications can be sensitive to power noise caused by recharge of VDDR"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 1. "STAT,VDDR recharge detector status.0: No recharge of VDDR has occurred since EN was set.1: Recharge of VDDR has occurred since EN was set" "No recharge of VDDR has occurred since EN was set,Recharge of VDDR has occurred since EN was set"
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newline
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bitfld.long 0x08 0. "EN,VDDR recharge detector enable.0: Disable recharge detection" "Disable recharge detection,Enable recharge detection"
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line.long 0x0C "RTCSUBSECINC0,Real Time Counter Sub Second Increment 0INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.AUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "INC15_0,New value for bits 15:0 in AON_RTC:SUBSECINC"
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line.long 0x10 "RTCSUBSECINC1,Real Time Counter Sub Second Increment 1INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.AUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "INC23_16,New value for bits 23:16 in AON_RTC:SUBSECINC"
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line.long 0x14 "RTCSUBSECINCCTL,Real Time Counter Sub Second Increment ControlAUX_SCE is not allowed to access this register when system state is secure"
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hexmask.long 0x14 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 1. "UPD_ACK,Update acknowledgement.0: AON_RTC has not acknowledged UPD_REQ" "AON_RTC has not acknowledged UPD_REQ,AON_RTC has acknowledged UPD_REQ"
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newline
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bitfld.long 0x14 0. "UPD_REQ,Request AON_RTC to update AON_RTC:SUBSECINC.0: Clear request to update.1: Set request to update.Only change UPD_REQ when it equals UPD_ACK" "Clear request to update,Set request to update.Only change UPD_REQ when.."
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line.long 0x18 "RTCSEC,Real Time Counter Second System CPU must not access this register"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "SEC,Bits 15:0 in AON_RTC:SEC.VALUE"
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line.long 0x1C "RTCSUBSEC,Real Time Counter Sub-Second System CPU must not access this register"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "SUBSEC,Bits 31:16 in AON_RTC:SUBSEC.VALUE"
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line.long 0x20 "RTCEVCLR,AON_RTC Event ClearRequest to clear events:- AON_RTC:EVFLAGS.CH2.- AON_RTC:EVFLAGS.CH2 delayed version.- AUX_EVCTL:EVSTAT2.AON_RTC_CH2.- AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY"
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hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 0. "RTC_CH2_EV_CLR,Clear events from AON_RTC channel 2.0: No effect" "No effect,Clear events from AON_RTC.."
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line.long 0x24 "BATMONBAT,AON_BATMON Battery Voltage ValueRead access to AON_BATMON:BAT"
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hexmask.long.tbyte 0x24 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 8.--10. "INT,See AON_BATMON:BAT.INT" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x24 0.--7. 1. "FRAC,See AON_BATMON:BAT.FRAC"
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rgroup.long 0x9C++0x07
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line.long 0x00 "BATMONTEMP,AON_BATMON Temperature ValueRead access to AON_BATMON:TEMP"
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hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 11.--15. "SIGN,Sign extension of INT.Follow this procedure to get the correct value:- Do two dummy reads of SIGN.- Then read SIGN until two consecutive reads are equal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.word 0x00 2.--10. 1. "INT,See AON_BATMON:TEMP.INT"
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newline
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bitfld.long 0x00 0.--1. "FRAC,See AON_BATMON:TEMP.FRAC" "0,1,2,3"
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line.long 0x04 "TIMERHALT,Timer HaltDebug register"
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hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 3. "PROGDLY,Halt programmable delay.0: AUX_EVCTL:PROGDLY.VALUE decrements as normal.1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation" "AUX_EVCTL,Halt AUX_EVCTL"
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newline
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bitfld.long 0x04 2. "AUX_TIMER2,Halt AUX_TIMER2.0: AUX_TIMER2 operates as normal.1: Halt AUX_TIMER2 operation" "AUX_TIMER2 operates as normal,Halt AUX_TIMER2 operation"
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newline
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bitfld.long 0x04 1. "AUX_TIMER1,Halt AUX_TIMER01 Timer" "AUX_TIMER01 Timer 1 operates as normal,Halt AUX_TIMER01 Timer 1 operation"
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newline
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bitfld.long 0x04 0. "AUX_TIMER0,Halt AUX_TIMER01 Timer" "AUX_TIMER01 Timer 0 operates as normal,Halt AUX_TIMER01 Timer 0 operation"
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rgroup.long 0xB0++0x07
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line.long 0x00 "TIMER2BRIDGE,AUX_TIMER2 Bridge"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "BUSY,Status of bus transactions to AUX_TIMER2.0: No unfinished bus transactions.1: A bus transaction is ongoing" "No unfinished bus transactions,A bus transaction is ongoing"
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line.long 0x04 "SWPWRPROF,Software Power Profiler"
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hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0.--2. "STAT,Software status bits that can be read by the power profiler" "0,1,2,3,4,5,6,7"
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tree.end
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tree "AUX_TDC"
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base ad:0x400C4000
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group.long 0x00++0x27
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line.long 0x00 "CTL,Control"
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hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--1. "CMD,TDC commands" "Clear STAT.SAT STAT.DONE and RESULT.VALUE..,Synchronous counter start.The counter looks..,Asynchronous counter start.The counter starts..,Force TDC state machine back to IDLE.."
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line.long 0x04 "STAT,Status"
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 7. "SAT,TDC measurement saturation flag.0: Conversion has not saturated.1: Conversion stopped due to saturation.This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD" "Conversion has not saturated,Conversion stopped due to saturation.This field.."
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newline
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bitfld.long 0x04 6. "DONE,TDC measurement complete flag.0: TDC measurement has not yet completed.1: TDC measurement has completed.This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD" "TDC measurement has not yet completed,TDC measurement has completed.This field clears.."
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newline
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bitfld.long 0x04 0.--5. "STATE,TDC state machine status" "Current state is TDC_STATE_WAIT_START. The..,?,?,?,Current state is..,?,Current state is TDC_STATE_IDLE. This is the..,Current state is TDC_STATE_CLRCNT. The..,Current state is TDC_STATE_WAIT_STOP.The state..,?,?,?,Current state is TDC_STATE_WAIT_STOPCNTDOWN.The..,?,Current state is TDC_STATE_GETRESULTS.The state..,Current state is TDC_STATE_POR. This is the..,?,?,?,?,?,?,Current state is TDC_STATE_WAIT_CLRCNT_DONE..,?,?,?,?,?,?,?,Current state is TDC_WAIT_STARTFALL. The..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Current state is TDC_FORCESTOP.You wrote ABORT..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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line.long 0x08 "RESULT,ResultResult of last TDC conversion"
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hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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newline
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hexmask.long 0x08 0.--24. 1. "VALUE,TDC conversion result.The result of the TDC conversion is given in number of clock edges of the clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL"
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line.long 0x0C "SATCFG,Saturation Configuration"
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hexmask.long 0x0C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 0.--3. "LIMIT,Saturation limit.The flag STAT.SAT is set when the TDC counter saturates.Values not enumerated are not supported" "?,?,?,Result bit 12: TDC conversion saturates and..,Result bit 13: TDC conversion saturates and..,Result bit 14: TDC conversion saturates and..,Result bit 15: TDC conversion saturates and..,Result bit 16: TDC conversion saturates and..,Result bit 17: TDC conversion saturates and..,Result bit 18: TDC conversion saturates and..,Result bit 19: TDC conversion saturates and..,Result bit 20: TDC conversion saturates and..,Result bit 21: TDC conversion saturates and..,Result bit 22: TDC conversion saturates and..,Result bit 23: TDC conversion saturates and..,Result bit 24: TDC conversion saturates and.."
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line.long 0x10 "TRIGSRC,Trigger SourceSelect source and polarity for TDC start and stop events"
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 14. "STOP_POL,Polarity of stop source.Change only while STAT.STATE is IDLE" "TDC conversion stops when high level is detected.,TDC conversion stops when low level is detected."
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newline
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bitfld.long 0x10 8.--13. "STOP_SRC,Select stop source from the asynchronous AUX event bus.Change only while STAT.STATE is IDLE" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,Select TDC Prescaler event which is generated by..,No event."
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newline
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rbitfld.long 0x10 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x10 6. "START_POL,Polarity of start source.Change only while STAT.STATE is IDLE" "TDC conversion starts when high level is detected.,TDC conversion starts when low level is detected."
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newline
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bitfld.long 0x10 0.--5. "START_SRC,Select start source from the asynchronous AUX event bus.Change only while STAT.STATE is IDLE" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,Select TDC Prescaler event which is generated by..,No event."
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line.long 0x14 "TRIGCNT,Trigger CounterStop-counter control and status"
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hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x14 0.--15. 1. "CNT,Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.Read CNT to get the remaining number of stop events to ignore during a TDC measurement"
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line.long 0x18 "TRIGCNTLOAD,Trigger Counter LoadStop-counter load"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "CNT,Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.To measure frequency of an event source: - Set start event equal to stop event.- Set CNT to number of periods to measure"
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line.long 0x1C "TRIGCNTCFG,Trigger Counter ConfigurationStop-counter configuration"
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hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 0. "EN,Enable stop-counter.0: Disable stop-counter.1: Enable stop-counter.Change only while STAT.STATE is IDLE" "Disable stop-counter,Enable stop-counter.Change only while STAT.STATE.."
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line.long 0x20 "PRECTL,Prescaler ControlThe prescaler can be used to count events that are faster than the AUX bus rate"
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 7. "RESET_N,Prescaler reset.0: Reset prescaler.1: Release reset of prescaler.AUX_TDC_PRE event becomes 0 when you reset the prescaler" "Reset prescaler,Release reset of prescaler.AUX_TDC_PRE.."
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newline
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bitfld.long 0x20 6. "RATIO,Prescaler ratio" "Prescaler divides input by 16. AUX_TDC_PRE..,Prescaler divides input by 64. AUX_TDC_PRE.."
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newline
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bitfld.long 0x20 0.--5. "SRC,Prescaler event source" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE ,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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line.long 0x24 "PRECNTR,Prescaler Counter"
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x24 0.--15. 1. "CNT,Prescaler counter value.Write a value to CNT to capture the value of the 16-bit prescaler counter into CNT"
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tree.end
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tree "AUX_TIMER01"
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base ad:0x400C7000
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group.long 0x00++0x1F
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line.long 0x00 "T0CFG,Timer 0 Configuration"
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hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 14. "TICK_SRC_POL,Tick source polarity for Timer 0" "Count on rising edges of TICK_SRC.,Count on falling edges of TICK_SRC."
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newline
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bitfld.long 0x00 8.--13. "TICK_SRC,Select Timer 0 tick source from the synchronous event bus" "AUX_EVCTL:EVSTAT0.AUXIO0..,AUX_EVCTL:EVSTAT0.AUXIO1..,AUX_EVCTL:EVSTAT0.AUXIO2..,AUX_EVCTL:EVSTAT0.AUXIO3..,AUX_EVCTL:EVSTAT0.AUXIO4..,AUX_EVCTL:EVSTAT0.AUXIO5..,AUX_EVCTL:EVSTAT0.AUXIO6..,AUX_EVCTL:EVSTAT0.AUXIO7..,AUX_EVCTL:EVSTAT0.AUXIO8..,AUX_EVCTL:EVSTAT0.AUXIO9..,AUX_EVCTL:EVSTAT0.AUXIO10..,AUX_EVCTL:EVSTAT0.AUXIO11..,AUX_EVCTL:EVSTAT0.AUXIO12..,AUX_EVCTL:EVSTAT0.AUXIO13..,AUX_EVCTL:EVSTAT0.AUXIO14..,AUX_EVCTL:EVSTAT0.AUXIO15..,AUX_EVCTL:EVSTAT1.AUXIO16..,AUX_EVCTL:EVSTAT1.AUXIO17..,AUX_EVCTL:EVSTAT1.AUXIO18..,AUX_EVCTL:EVSTAT1.AUXIO19..,AUX_EVCTL:EVSTAT1.AUXIO20..,AUX_EVCTL:EVSTAT1.AUXIO21..,AUX_EVCTL:EVSTAT1.AUXIO22..,AUX_EVCTL:EVSTAT1.AUXIO23..,AUX_EVCTL:EVSTAT1.AUXIO24..,AUX_EVCTL:EVSTAT1.AUXIO25..,AUX_EVCTL:EVSTAT1.AUXIO26..,AUX_EVCTL:EVSTAT1.AUXIO27..,AUX_EVCTL:EVSTAT1.AUXIO28..,AUX_EVCTL:EVSTAT1.AUXIO29..,AUX_EVCTL:EVSTAT1.AUXIO30..,AUX_EVCTL:EVSTAT1.AUXIO31..,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2..,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY..,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ..,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD..,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD..,AUX_EVCTL:EVSTAT2.SCLK_LF..,AUX_EVCTL:EVSTAT2.PWR_DWN..,AUX_EVCTL:EVSTAT2.MCU_ACTIVE..,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE..,AUX_EVCTL:EVSTAT2.ACLK_REF..,AUX_EVCTL:EVSTAT2.MCU_EV..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1..,AUX_EVCTL:EVSTAT2.AUX_COMPA..,AUX_EVCTL:EVSTAT2.AUX_COMPB..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE..,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV..,No event.,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N..,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE..,AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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newline
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bitfld.long 0x00 4.--7. "PRE,Prescaler division ratio is" "Divide by 1,Divide by 2,Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 32 768"
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newline
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rbitfld.long 0x00 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 1. "MODE,Timer 0 mode.Configure source for Timer 0 prescaler" "Use clock as source for prescaler. Note that..,Use event set by TICK_SRC as source for.."
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newline
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bitfld.long 0x00 0. "RELOAD,Timer 0 reload mode" "Manual mode.Timer 0 stops and T0CTL.EN becomes..,Continuous mode.Timer 0 restarts when the.."
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line.long 0x04 "T0CTL,Timer 0 Control"
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hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "EN,Timer 0 enable.0: Disable Timer" "Disable Timer 0,Enable Timer 0.The counter restarts from 0.."
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line.long 0x08 "T0TARGET,Timer 0 Target"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.word 0x08 0.--15. 1. "VALUE,Timer 0 target value.Manual Reload Mode:- Timer 0 increments until the counter value becomes equal to or greater than VALUE"
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line.long 0x0C "T0CNTR,Timer 0 Counter"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.word 0x0C 0.--15. 1. "VALUE,Timer 0 counter value"
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line.long 0x10 "T1CFG,Timer 1 Configuration"
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hexmask.long.tbyte 0x10 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 14. "TICK_SRC_POL,Tick source polarity for Timer 1" "Count on rising edges of TICK_SRC.,Count on falling edges of TICK_SRC."
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newline
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bitfld.long 0x10 8.--13. "TICK_SRC,Select Timer 1 tick source from the synchronous event bus" "AUX_EVCTL:EVSTAT0.AUXIO0..,AUX_EVCTL:EVSTAT0.AUXIO1..,AUX_EVCTL:EVSTAT0.AUXIO2..,AUX_EVCTL:EVSTAT0.AUXIO3..,AUX_EVCTL:EVSTAT0.AUXIO4..,AUX_EVCTL:EVSTAT0.AUXIO5..,AUX_EVCTL:EVSTAT0.AUXIO6..,AUX_EVCTL:EVSTAT0.AUXIO7..,AUX_EVCTL:EVSTAT0.AUXIO8..,AUX_EVCTL:EVSTAT0.AUXIO9..,AUX_EVCTL:EVSTAT0.AUXIO10..,AUX_EVCTL:EVSTAT0.AUXIO11..,AUX_EVCTL:EVSTAT0.AUXIO12..,AUX_EVCTL:EVSTAT0.AUXIO13..,AUX_EVCTL:EVSTAT0.AUXIO14..,AUX_EVCTL:EVSTAT0.AUXIO15..,AUX_EVCTL:EVSTAT1.AUXIO16..,AUX_EVCTL:EVSTAT1.AUXIO17..,AUX_EVCTL:EVSTAT1.AUXIO18..,AUX_EVCTL:EVSTAT1.AUXIO19..,AUX_EVCTL:EVSTAT1.AUXIO20..,AUX_EVCTL:EVSTAT1.AUXIO21..,AUX_EVCTL:EVSTAT1.AUXIO22..,AUX_EVCTL:EVSTAT1.AUXIO23..,AUX_EVCTL:EVSTAT1.AUXIO24..,AUX_EVCTL:EVSTAT1.AUXIO25..,AUX_EVCTL:EVSTAT1.AUXIO26..,AUX_EVCTL:EVSTAT1.AUXIO27..,AUX_EVCTL:EVSTAT1.AUXIO28..,AUX_EVCTL:EVSTAT1.AUXIO29..,AUX_EVCTL:EVSTAT1.AUXIO30..,AUX_EVCTL:EVSTAT1.AUXIO31..,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2..,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY..,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ..,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD..,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD..,AUX_EVCTL:EVSTAT2.SCLK_LF..,AUX_EVCTL:EVSTAT2.PWR_DWN..,AUX_EVCTL:EVSTAT2.MCU_ACTIVE..,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE..,AUX_EVCTL:EVSTAT2.ACLK_REF..,AUX_EVCTL:EVSTAT2.MCU_EV..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0..,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1..,AUX_EVCTL:EVSTAT2.AUX_COMPA..,AUX_EVCTL:EVSTAT2.AUX_COMPB..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE..,No event.,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV..,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N..,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE..,AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE..,AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY "
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newline
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bitfld.long 0x10 4.--7. "PRE,Prescaler division ratio is" "Divide by 1,Divide by 2,Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 32 768"
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newline
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rbitfld.long 0x10 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x10 1. "MODE,Timer 1 mode.Configure source for Timer 1 prescaler" "Use clock as source for prescaler. Note that..,Use event set by TICK_SRC as source for.."
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newline
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bitfld.long 0x10 0. "RELOAD,Timer 1 reload mode" "Manual mode.Timer 1 stops and T1CTL.EN becomes..,Continuous mode.Timer 1 restarts when the.."
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line.long 0x14 "T1CTL,Timer 1 Control"
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hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 0. "EN,Timer 1 enable.0: Disable Timer" "Disable Timer 1,Enable Timer 1.The counter restarts from 0.."
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line.long 0x18 "T1TARGET,Timer 1 TargetTimer 1 counter target value"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "VALUE,Timer 1 target value.Manual Reload Mode:- Timer 1 increments until the counter value becomes equal to or greater than VALUE"
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line.long 0x1C "T1CNTR,Timer 1 Counter"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "VALUE,Timer 1 counter value"
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tree.end
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tree "AUX_TIMER2"
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base ad:0x400C3000
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group.long 0x00++0x1B
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line.long 0x00 "CTL,Timer Control"
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hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 6. "CH3_RESET,Channel 3 reset.0: No effect.1: Reset CH3CC CH3PCC CH3EVCFG and CH3CCFG.Read returns 0" "No effect,Reset CH3CC CH3PCC.."
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newline
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bitfld.long 0x00 5. "CH2_RESET,Channel 2 reset.0: No effect.1: Reset CH2CC CH2PCC CH2EVCFG and CH2CCFG.Read returns 0" "No effect,Reset CH2CC CH2PCC.."
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newline
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bitfld.long 0x00 4. "CH1_RESET,Channel 1 reset.0: No effect.1: Reset CH1CC CH1PCC CH1EVCFG and CH1CCFG.Read returns 0" "No effect,Reset CH1CC CH1PCC.."
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newline
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bitfld.long 0x00 3. "CH0_RESET,Channel 0 reset.0: No effect.1: Reset CH0CC CH0PCC CH0EVCFG and CH0CCFG.Read returns 0" "No effect,Reset CH0CC CH0PCC.."
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newline
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bitfld.long 0x00 2. "TARGET_EN,Select counter target value.You must select TARGET to use shadow target functionality" "65535,TARGET.VALUE"
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newline
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bitfld.long 0x00 0.--1. "MODE,Timer mode control.The timer restarts from 0 when you set MODE to UP_ONCE UP_PER or UPDWN_PER" "Disable timer. Updates to counter channels and..,Count up once. The timer increments from 0 to..,Count up periodically. The timer increments from..,Count up and down periodically. The timer counts.."
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line.long 0x04 "TARGET,TargetUser defined counter target"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x04 0.--15. 1. "VALUE,16 bit user defined counter target value which is used when selected by CTL.TARGET_EN"
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line.long 0x08 "SHDWTARGET,Shadow Target"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x08 0.--15. 1. "VALUE,Target value for next counter period.The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0"
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line.long 0x0C "CNTR,Counter"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "VALUE,16 bit current counter value"
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line.long 0x10 "PRECFG,Clock Prescaler Configuration"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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abitfld.long 0x10 0.--7. "CLKDIV,Clock division.CLKDIV determines the timer clock frequency for counter synchronization and timer event updates" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
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line.long 0x14 "EVCTL,Event Control Set and clear individual events manually"
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hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 7. "EV3_SET,Set event 3.Write 1 to set event 3" "0,1"
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newline
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bitfld.long 0x14 6. "EV3_CLR,Clear event 3.Write 1 to clear event 3" "0,1"
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newline
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bitfld.long 0x14 5. "EV2_SET,Set event 2.Write 1 to set event 2" "0,1"
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newline
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bitfld.long 0x14 4. "EV2_CLR,Clear event 2.Write 1 to clear event 2" "0,1"
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newline
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bitfld.long 0x14 3. "EV1_SET,Set event 1.Write 1 to set event 1" "0,1"
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newline
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bitfld.long 0x14 2. "EV1_CLR,Clear event 1.Write 1 to clear event 1" "0,1"
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newline
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bitfld.long 0x14 1. "EV0_SET,Set event 0.Write 1 to set event 0" "0,1"
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newline
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bitfld.long 0x14 0. "EV0_CLR,Clear event 0.Write 1 to clear event 0" "0,1"
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line.long 0x18 "PULSETRIG,Pulse Trigger"
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hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 0. "TRIG,Pulse trigger.Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE" "0,1"
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group.long 0x80++0x3F
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line.long 0x00 "CH0EVCFG,Channel 0 Event ConfigurationThis register configures channel function and enables event outputs.Each channel has an edge-detection circuit with memory"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 7. "EV3_GEN,Event 3 enable.0: Channel 0 does not control event" "Channel 0 does not control event 3,Channel 0 controls event 3"
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newline
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bitfld.long 0x00 6. "EV2_GEN,Event 2 enable.0: Channel 0 does not control event" "Channel 0 does not control event 2,Channel 0 controls event 2"
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newline
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bitfld.long 0x00 5. "EV1_GEN,Event 1 enable.0: Channel 0 does not control event" "Channel 0 does not control event 1,Channel 0 controls event 1"
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newline
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bitfld.long 0x00 4. "EV0_GEN,Event 0 enable.0: Channel 0 does not control event" "Channel 0 does not control event 0,Channel 0 controls event 0"
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newline
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bitfld.long 0x00 0.--3. "CCACT,Capture-Compare action.Capture-Compare action defines 15 different channel functions that utilize capture compare and zero events" "Disable channel.,Set on capture and then disable..,Clear on zero toggle on compare and then..,Set on zero toggle on compare and then disable..,Clear on compare and then disable..,Set on compare and then disable..,Toggle on compare and then disable..,Pulse on compare and then disable..,Period and pulse width..,Set on capture repeatedly.Channel function..,Clear on zero toggle on compare repeatedly...,Set on zero toggle on compare..,Clear on compare repeatedly.Channel function..,Set on compare repeatedly.Channel function..,Toggle on compare repeatedly.Channel function..,Pulse on compare repeatedly. Channel function.."
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line.long 0x04 "CH0CCFG,Channel 0 Capture Configuration"
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hexmask.long 0x04 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 1.--6. "CAPT_SRC,Select capture signal source from the asynchronous AUX event bus" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,?,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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bitfld.long 0x04 0. "EDGE,Edge configuration.Channel captures counter value at selected edge on signal source selected by CAPT_SRC" "Capture CNTR.VALUE at falling edge of CAPT_SRC.,Capture CNTR.VALUE at rising edge of CAPT_SRC."
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line.long 0x08 "CH0PCC,Channel 0 Pipeline Capture Compare"
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hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x08 0.--15. 1. "VALUE,Pipeline Capture Compare value.16-bit user defined pipeline compare value or channel-updated capture value.Compare mode: An update of VALUE will be transferred to CH0CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS"
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line.long 0x0C "CH0CC,Channel 0 Capture Compare"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--15. 1. "VALUE,Capture Compare value.16-bit user defined compare value or channel-updated capture value.Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH0EVCFG.CCACT when these are equal"
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line.long 0x10 "CH1EVCFG,Channel 1 Event ConfigurationThis register configures channel function and enables event outputs.Each channel has an edge-detection circuit with memory"
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hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 7. "EV3_GEN,Event 3 enable.0: Channel 1 does not control event" "Channel 1 does not control event 3,Channel 1 controls event 3"
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newline
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bitfld.long 0x10 6. "EV2_GEN,Event 2 enable.0: Channel 1 does not control event" "Channel 1 does not control event 2,Channel 1 controls event 2"
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newline
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bitfld.long 0x10 5. "EV1_GEN,Event 1 enable.0: Channel 1 does not control event" "Channel 1 does not control event 1,Channel 1 controls event 1"
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newline
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bitfld.long 0x10 4. "EV0_GEN,Event 0 enable.0: Channel 1 does not control event" "Channel 1 does not control event 0,Channel 1 controls event 0"
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newline
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bitfld.long 0x10 0.--3. "CCACT,Capture-Compare action.Capture-Compare action defines 15 different channel functions that utilize capture compare and zero events" "Disable channel.,Set on capture and then disable..,Clear on zero toggle on compare and then..,Set on zero toggle on compare and then disable..,Clear on compare and then disable..,Set on compare and then disable..,Toggle on compare and then disable..,Pulse on compare and then disable..,Period and pulse width..,Set on capture repeatedly.Channel function..,Clear on zero toggle on compare repeatedly...,Set on zero toggle on compare..,Clear on compare repeatedly.Channel function..,Set on compare repeatedly.Channel function..,Toggle on compare repeatedly.Channel function..,Pulse on compare repeatedly. Channel function.."
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line.long 0x14 "CH1CCFG,Channel 1 Capture Configuration"
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hexmask.long 0x14 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 1.--6. "CAPT_SRC,Select capture signal source from the asynchronous AUX event bus" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,?,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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bitfld.long 0x14 0. "EDGE,Edge configuration.Channel captures counter value at selected edge on signal source selected by CAPT_SRC" "Capture CNTR.VALUE at falling edge of CAPT_SRC.,Capture CNTR.VALUE at rising edge of CAPT_SRC."
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line.long 0x18 "CH1PCC,Channel 1 Pipeline Capture Compare"
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hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x18 0.--15. 1. "VALUE,Pipeline Capture Compare value.16-bit user defined pipeline compare value or channel-updated capture value.Compare mode: An update of VALUE will be transferred to CH1CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS"
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line.long 0x1C "CH1CC,Channel 1 Capture Compare"
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "VALUE,Capture Compare value.16-bit user defined compare value or channel-updated capture value.Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH1EVCFG.CCACT when these are equal"
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line.long 0x20 "CH2EVCFG,Channel 2 Event ConfigurationThis register configures channel function and enables event outputs.Each channel has an edge-detection circuit with memory"
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x20 7. "EV3_GEN,Event 3 enable.0: Channel 2 does not control event" "Channel 2 does not control event 3,Channel 2 controls event 3"
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newline
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bitfld.long 0x20 6. "EV2_GEN,Event 2 enable.0: Channel 2 does not control event" "Channel 2 does not control event 2,Channel 2 controls event 2"
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newline
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bitfld.long 0x20 5. "EV1_GEN,Event 1 enable.0: Channel 2 does not control event" "Channel 2 does not control event 1,Channel 2 controls event 1"
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newline
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bitfld.long 0x20 4. "EV0_GEN,Event 0 enable.0: Channel 2 does not control event" "Channel 2 does not control event 0,Channel 2 controls event 0"
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newline
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bitfld.long 0x20 0.--3. "CCACT,Capture-Compare action.Capture-Compare action defines 15 different channel functions that utilize capture compare and zero events" "Disable channel.,Set on capture and then disable..,Clear on zero toggle on compare and then..,Set on zero toggle on compare and then disable..,Clear on compare and then disable..,Set on compare and then disable..,Toggle on compare and then disable..,Pulse on compare and then disable..,Period and pulse width..,Set on capture repeatedly.Channel function..,Clear on zero toggle on compare repeatedly...,Set on zero toggle on compare..,Clear on compare repeatedly.Channel function..,Set on compare repeatedly.Channel function..,Toggle on compare repeatedly.Channel function..,Pulse on compare repeatedly. Channel function.."
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line.long 0x24 "CH2CCFG,Channel 2 Capture Configuration"
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hexmask.long 0x24 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x24 1.--6. "CAPT_SRC,Select capture signal source from the asynchronous AUX event bus" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,?,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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bitfld.long 0x24 0. "EDGE,Edge configuration.Channel captures counter value at selected edge on signal source selected by CAPT_SRC" "Capture CNTR.VALUE at falling edge of CAPT_SRC.,Capture CNTR.VALUE at rising edge of CAPT_SRC."
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line.long 0x28 "CH2PCC,Channel 2 Pipeline Capture Compare"
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hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x28 0.--15. 1. "VALUE,Pipeline Capture Compare value.16-bit user defined pipeline compare value or channel-updated capture value.Compare mode: An update of VALUE will be transferred to CH2CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS"
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line.long 0x2C "CH2CC,Channel 2 Capture Compare"
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hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x2C 0.--15. 1. "VALUE,Capture Compare value.16-bit user defined compare value or channel-updated capture value.Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH2EVCFG.CCACT when these are equal"
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line.long 0x30 "CH3EVCFG,Channel 3 Event ConfigurationThis register configures channel function and enables event outputs.Each channel has an edge-detection circuit with memory"
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hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x30 7. "EV3_GEN,Event 3 enable.0: Channel 3 does not control event" "Channel 3 does not control event 3,Channel 3 controls event 3"
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newline
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bitfld.long 0x30 6. "EV2_GEN,Event 2 enable.0: Channel 3 does not control event" "Channel 3 does not control event 2,Channel 3 controls event 2"
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newline
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bitfld.long 0x30 5. "EV1_GEN,Event 1 enable.0: Channel 3 does not control event" "Channel 3 does not control event 1,Channel 3 controls event 1"
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newline
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bitfld.long 0x30 4. "EV0_GEN,Event 0 enable.0: Channel 3 does not control event" "Channel 3 does not control event 0,Channel 3 controls event 0"
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newline
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bitfld.long 0x30 0.--3. "CCACT,Capture-Compare action.Capture-Compare action defines 15 different channel functions that utilize capture compare and zero events" "Disable channel.,Set on capture and then disable..,Clear on zero toggle on compare and then..,Set on zero toggle on compare and then disable..,Clear on compare and then disable..,Set on compare and then disable..,Toggle on compare and then disable..,Pulse on compare and then disable..,Period and pulse width..,Set on capture repeatedly.Channel function..,Clear on zero toggle on compare repeatedly...,Set on zero toggle on compare..,Clear on compare repeatedly.Channel function..,Set on compare repeatedly.Channel function..,Toggle on compare repeatedly.Channel function..,Pulse on compare repeatedly. Channel function.."
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line.long 0x34 "CH3CCFG,Channel 3 Capture Configuration"
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hexmask.long 0x34 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x34 1.--6. "CAPT_SRC,Select capture signal source from the asynchronous AUX event bus" "AUX_EVCTL:EVSTAT0.AUXIO0 ,AUX_EVCTL:EVSTAT0.AUXIO1 ,AUX_EVCTL:EVSTAT0.AUXIO2 ,AUX_EVCTL:EVSTAT0.AUXIO3 ,AUX_EVCTL:EVSTAT0.AUXIO4 ,AUX_EVCTL:EVSTAT0.AUXIO5 ,AUX_EVCTL:EVSTAT0.AUXIO6 ,AUX_EVCTL:EVSTAT0.AUXIO7 ,AUX_EVCTL:EVSTAT0.AUXIO8 ,AUX_EVCTL:EVSTAT0.AUXIO9 ,AUX_EVCTL:EVSTAT0.AUXIO10 ,AUX_EVCTL:EVSTAT0.AUXIO11 ,AUX_EVCTL:EVSTAT0.AUXIO12 ,AUX_EVCTL:EVSTAT0.AUXIO13 ,AUX_EVCTL:EVSTAT0.AUXIO14 ,AUX_EVCTL:EVSTAT0.AUXIO15 ,AUX_EVCTL:EVSTAT1.AUXIO16 ,AUX_EVCTL:EVSTAT1.AUXIO17 ,AUX_EVCTL:EVSTAT1.AUXIO18 ,AUX_EVCTL:EVSTAT1.AUXIO19 ,AUX_EVCTL:EVSTAT1.AUXIO20 ,AUX_EVCTL:EVSTAT1.AUXIO21 ,AUX_EVCTL:EVSTAT1.AUXIO22 ,AUX_EVCTL:EVSTAT1.AUXIO23 ,AUX_EVCTL:EVSTAT1.AUXIO24 ,AUX_EVCTL:EVSTAT1.AUXIO25 ,AUX_EVCTL:EVSTAT1.AUXIO26 ,AUX_EVCTL:EVSTAT1.AUXIO27 ,AUX_EVCTL:EVSTAT1.AUXIO28 ,AUX_EVCTL:EVSTAT1.AUXIO29 ,AUX_EVCTL:EVSTAT1.AUXIO30 ,AUX_EVCTL:EVSTAT1.AUXIO31 ,AUX_EVCTL:EVSTAT2.MANUAL_EV,AUX_EVCTL:EVSTAT2.AON_RTC_CH2 ,AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY ,AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ ,AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD ,AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD ,AUX_EVCTL:EVSTAT2.SCLK_LF ,AUX_EVCTL:EVSTAT2.PWR_DWN ,AUX_EVCTL:EVSTAT2.MCU_ACTIVE ,AUX_EVCTL:EVSTAT2.VDDR_RECHARGE ,AUX_EVCTL:EVSTAT2.ACLK_REF ,AUX_EVCTL:EVSTAT2.MCU_EV ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 ,AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 ,AUX_EVCTL:EVSTAT2.AUX_COMPA ,AUX_EVCTL:EVSTAT2.AUX_COMPB ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 ,AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 ,?,AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV ,AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV ,AUX_EVCTL:EVSTAT3.AUX_TDC_DONE ,AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N ,AUX_EVCTL:EVSTAT3.AUX_ADC_DONE..,AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL..,AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY..,AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE ,?,No event."
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newline
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bitfld.long 0x34 0. "EDGE,Edge configuration.Channel captures counter value at selected edge on signal source selected by CAPT_SRC" "Capture CNTR.VALUE at falling edge of CAPT_SRC.,Capture CNTR.VALUE at rising edge of CAPT_SRC."
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line.long 0x38 "CH3PCC,Channel 3 Pipeline Capture Compare"
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hexmask.long.word 0x38 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x38 0.--15. 1. "VALUE,Pipeline Capture Compare value.16-bit user defined pipeline compare value or channel-updated capture value.Compare mode: An update of VALUE will be transferred to CH3CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS"
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line.long 0x3C "CH3CC,Channel 3 Capture Compare"
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hexmask.long.word 0x3C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x3C 0.--15. 1. "VALUE,Capture Compare value.16-bit user defined compare value or channel-updated capture value.Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH3EVCFG.CCACT when these are equal"
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tree.end
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tree.end
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tree "CCFG"
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base ad:0x50000000
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rgroup.long 0x00++0x47
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line.long 0x00 "SIZE_AND_DIS_FLAGS,CCFG Size and Disable Flags"
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hexmask.long.word 0x00 16.--31. 1. "SIZE_OF_CCFG,Total size of CCFG in bytes"
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newline
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hexmask.long.word 0x00 4.--15. 1. "DISABLE_FLAGS,Reserved for future use"
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newline
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bitfld.long 0x00 3. "DIS_TCXO,Deprecated" "0,1"
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newline
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bitfld.long 0x00 2. "DIS_GPRAM,Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).0: GPRAM is enabled and hence CACHE disabled.1: GPRAM is disabled and instead CACHE is enabled (default).Notes:- Disabling CACHE will reduce CPU execution speed (up to 60%).- GPRAM is 8.." "GPRAM is enabled and hence CACHE disabled,GPRAM is disabled and instead CACHE is enabled.."
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newline
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bitfld.long 0x00 1. "DIS_ALT_DCDC_SETTING,Disable alternate DC/DC settings" "Enable alternate DC/DC settings,Disable alternate DC/DC settings.See"
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newline
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bitfld.long 0x00 0. "DIS_XOSC_OVR,Disable XOSC override functionality.0: Enable XOSC override functionality.1: Disable XOSC override functionality.See:MODE_CONF_1.DELTA_IBIAS_INITMODE_CONF_1.DELTA_IBIAS_OFFSETMODE_CONF_1.XOSC_MAX_START" "Enable XOSC override functionality,Disable XOSC override functionality.See"
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line.long 0x04 "MODE_CONF,Mode Configuration 0"
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bitfld.long 0x04 28.--31. "VDDR_TRIM_SLEEP_DELTA,Signed delta value to apply to theVDDR_TRIM_SLEEP target minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x04 27. "DCDC_RECHARGE,DC/DC during recharge in powerdown.0: Use the DC/DC during recharge in powerdown.1: Do not use the DC/DC during recharge in powerdown (default).NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly.." "Use the DC/DC during recharge in powerdown,Do not use the DC/DC during recharge in.."
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newline
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bitfld.long 0x04 26. "DCDC_ACTIVE,DC/DC in active mode.0: Use the DC/DC during active mode.1: Do not use the DC/DC during active mode (default).NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled.." "Use the DC/DC during active mode,Do not use the DC/DC during active mode.."
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newline
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bitfld.long 0x04 25. "VDDR_EXT_LOAD,Reserved for future use" "0,1"
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newline
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bitfld.long 0x04 24. "VDDS_BOD_LEVEL,VDDS BOD level.0: VDDS BOD level is 2.0V (necessary for external load mode or for maximum PA output power on CC13xx).1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default)." "VDDS BOD level is 2.0V (necessary for external..,VDDS BOD level is 1.8V (or 1.65V for external.."
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newline
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bitfld.long 0x04 22.--23. "SCLK_LF_OPTION,Select source for SCLK_LF" "31.25kHz clock derived from 48MHz XOSC or HPOSC..,External low frequency clock on DIO defined by..,32.768kHz low frequency XOSC,Low frequency RCOSC (default)"
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newline
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bitfld.long 0x04 21. "VDDR_TRIM_SLEEP_TC," "0,1"
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newline
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bitfld.long 0x04 20. "RTC_COMP,Reserved for future use" "0,1"
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newline
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bitfld.long 0x04 18.--19. "XOSC_FREQ,Selects which high frequency oscillator is used (required for radio usage)" "External 48Mhz TCXO.Refer to..,Internal high precision oscillator.,48 MHz XOSC_HF,24 MHz XOSC_HF. Not supported."
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newline
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bitfld.long 0x04 17. "XOSC_CAP_MOD,Enable modification (delta) to XOSC cap-array" "Apply cap-array delta,Do not apply cap-array delta (default)"
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newline
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bitfld.long 0x04 16. "HF_COMP,Reserved for future use" "0,1"
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newline
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hexmask.long.byte 0x04 8.--15. 1. "XOSC_CAPARRAY_DELTA,Signed 8-bit value directly modifying trimmed XOSC cap-array step value"
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newline
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hexmask.long.byte 0x04 0.--7. 1. "VDDR_CAP,Unsigned 8-bit integer representing the minimum decoupling capacitance (worst case) on VDDR in units of 100nF"
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line.long 0x08 "MODE_CONF_1,Mode Configuration 1"
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bitfld.long 0x08 31. "TCXO_TYPE,Selects the TCXO type.0: CMOS type" "CMOS type,Clipped-sine type"
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newline
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hexmask.long.byte 0x08 24.--30. 1. "TCXO_MAX_START,Maximum TCXO startup time in units of 100us.Bit field value is only valid if MODE_CONF.XOSC_FREQ=0"
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newline
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bitfld.long 0x08 20.--23. "ALT_DCDC_VMIN,Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).Voltage = (28 + ALT_DCDC_VMIN) /" "1.75V,1.8125V,?,?,?,?,?,?,?,?,?,?,?,?,2.625V,2.6875VNOTE! The.."
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newline
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bitfld.long 0x08 19. "ALT_DCDC_DITHER_EN,Enable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).0: Dither disable1: Dither enable" "Dither disable,Dither enable"
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newline
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bitfld.long 0x08 16.--18. "ALT_DCDC_IPEAK,Inductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x08 12.--15. "DELTA_IBIAS_INIT,Signed delta value for IBIAS_INIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x08 8.--11. "DELTA_IBIAS_OFFSET,Signed delta value for IBIAS_OFFSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x08 0.--7. 1. "XOSC_MAX_START,Unsigned value of maximum XOSC startup time (worst case) in units of 100us"
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line.long 0x0C "VOLT_LOAD_0,Voltage Load 0Enabled by MODE_CONF.VDDR_EXT_LOAD"
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hexmask.long.byte 0x0C 24.--31. 1. "VDDR_EXT_TP45,Reserved for future use"
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newline
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hexmask.long.byte 0x0C 16.--23. 1. "VDDR_EXT_TP25,Reserved for future use"
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newline
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hexmask.long.byte 0x0C 8.--15. 1. "VDDR_EXT_TP5,Reserved for future use"
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newline
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hexmask.long.byte 0x0C 0.--7. 1. "VDDR_EXT_TM15,Reserved for future use"
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line.long 0x10 "VOLT_LOAD_1,Voltage Load 1Enabled by MODE_CONF.VDDR_EXT_LOAD"
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hexmask.long.byte 0x10 24.--31. 1. "VDDR_EXT_TP125,Reserved for future use"
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newline
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hexmask.long.byte 0x10 16.--23. 1. "VDDR_EXT_TP105,Reserved for future use"
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newline
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hexmask.long.byte 0x10 8.--15. 1. "VDDR_EXT_TP85,Reserved for future use"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "VDDR_EXT_TP65,Reserved for future use"
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line.long 0x14 "EXT_LF_CLK,Extern LF clock configuration"
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hexmask.long.byte 0x14 24.--31. 1. "DIO,Unsigned integer selecting the DIO to supply external 32kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL"
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newline
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hexmask.long.tbyte 0x14 0.--23. 1. "RTC_INCREMENT,Unsigned integer defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC"
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line.long 0x18 "IEEE_MAC_0,IEEE MAC Address 0"
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line.long 0x1C "IEEE_MAC_1,IEEE MAC Address 1"
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line.long 0x20 "IEEE_BLE_0,IEEE BLE Address 0"
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line.long 0x24 "IEEE_BLE_1,IEEE BLE Address 1"
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line.long 0x28 "BL_CONFIG,Bootloader ConfigurationConfigures the functionality of the ROM boot loader.If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the.."
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hexmask.long.byte 0x28 24.--31. 1. "BOOTLOADER_ENABLE,Bootloader enable"
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newline
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hexmask.long.byte 0x28 17.--23. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x28 16. "BL_LEVEL,Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field.0: Active low.1: Active high" "Active low,Active high"
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newline
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hexmask.long.byte 0x28 8.--15. 1. "BL_PIN_NUMBER,DIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field"
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newline
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hexmask.long.byte 0x28 0.--7. 1. "BL_ENABLE,Enables the boot loader"
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line.long 0x2C "ERASE_CONF,Erase Configuration"
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hexmask.long.tbyte 0x2C 9.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 8. "CHIP_ERASE_DIS_N,Chip erase.This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD.A successful chip erase operation will force the content of the flash main bank back to.." "Disable,Enable"
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newline
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hexmask.long.byte 0x2C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x2C 0. "BANK_ERASE_DIS_N,Bank erase.This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE).A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration.." "Disable the boot loader bank erase function,Enable the boot loader bank erase function"
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line.long 0x30 "ERASE_CONF_1,Erase Configuration 1"
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hexmask.long 0x30 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x30 0. "WEPROT_CCFG_N,WriteErase protect the CCFG sectorSetting this bit = 0 will set FLASH:WEPROT_AUX_BY1.WEPROT_B0_CCFG_BY1 = 1 during boot and hence WriteErase protect the CCFG" "0,1"
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line.long 0x34 "CCFG_TI_OPTIONS,TI Options"
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hexmask.long.word 0x34 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x34 8.--15. 1. "IDAU_CFG_ENABLE,IDAU"
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newline
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hexmask.long.byte 0x34 0.--7. 1. "TI_FA_ENABLE,TI Failure"
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line.long 0x38 "CCFG_TAP_DAP_0,Test Access Points Enable 0"
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hexmask.long.byte 0x38 24.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x38 16.--23. 1. "CPU_DAP_ENABLE,Enable CPU"
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newline
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hexmask.long.byte 0x38 8.--15. 1. "PWRPROF_TAP_ENABLE,Enable PWRPROF TAP.0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PWRPROF TAP access will remain disabled out of.."
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newline
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hexmask.long.byte 0x38 0.--7. 1. "TEST_TAP_ENABLE,Enable Test TAP.0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: TEST TAP access will remain disabled out of.."
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line.long 0x3C "CCFG_TAP_DAP_1,Test Access Points Enable 1"
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hexmask.long.byte 0x3C 24.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x3C 16.--23. 1. "PBIST2_TAP_ENABLE,Enable PBIST2 TAP.0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PBIST2 TAP access will remain disabled out of.."
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newline
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hexmask.long.byte 0x3C 8.--15. 1. "PBIST1_TAP_ENABLE,Enable PBIST1 TAP.0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: PBIST1 TAP access will remain disabled out of.."
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newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "AON_TAP_ENABLE,Enable AON TAP0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.Any other value: AON TAP access will remain disabled out of.."
|
|
line.long 0x40 "IMAGE_VALID_CONF,Image Valid"
|
|
line.long 0x44 "CCFG_WEPROT_31_0_BY2K,Protect Sectors 0-31Each bit write protects one 2KB flash sector from being both programmed and erased"
|
|
bitfld.long 0x44 31. "WEPROT_SEC_31_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 30. "WEPROT_SEC_30_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 29. "WEPROT_SEC_29_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 28. "WEPROT_SEC_28_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 27. "WEPROT_SEC_27_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 26. "WEPROT_SEC_26_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 25. "WEPROT_SEC_25_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 24. "WEPROT_SEC_24_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 23. "WEPROT_SEC_23_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 22. "WEPROT_SEC_22_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 21. "WEPROT_SEC_21_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 20. "WEPROT_SEC_20_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 19. "WEPROT_SEC_19_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 18. "WEPROT_SEC_18_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 17. "WEPROT_SEC_17_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 16. "WEPROT_SEC_16_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 15. "WEPROT_SEC_15_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 14. "WEPROT_SEC_14_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 13. "WEPROT_SEC_13_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 12. "WEPROT_SEC_12_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 11. "WEPROT_SEC_11_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 10. "WEPROT_SEC_10_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 9. "WEPROT_SEC_9_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 8. "WEPROT_SEC_8_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 7. "WEPROT_SEC_7_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 6. "WEPROT_SEC_6_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 5. "WEPROT_SEC_5_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 4. "WEPROT_SEC_4_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 3. "WEPROT_SEC_3_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 2. "WEPROT_SEC_2_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 1. "WEPROT_SEC_1_N," "0,1"
|
|
newline
|
|
bitfld.long 0x44 0. "WEPROT_SEC_0_N," "0,1"
|
|
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x48)++0x03
|
|
line.long 0x00 "CCFG_WEPROT_SPARE_$1,Spare register for WriteErase configuration"
|
|
repeat.end
|
|
rgroup.long 0x54++0x0B
|
|
line.long 0x00 "TRUSTZONE_FLASH_CFG,Trustzone configuration register for flash"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--16. 1. "NSADDR_BOUNDARY,Value will be written to PRCM:NVMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "NSCADDR_BOUNDARY,Value will be written to PRCM:NVMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
line.long 0x04 "TRUSTZONE_SRAM_CFG,Trustzone configuration register for MCU SRAM"
|
|
hexmask.long.word 0x04 18.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 9.--17. 1. "NSADDR_BOUNDARY,Value will be written to PRCM:SRAMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
newline
|
|
hexmask.long.word 0x04 0.--8. 1. "NSCADDR_BOUNDARY,Value will be written to PRCM:SRAMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5"
|
|
line.long 0x08 "SRAM_CFG,Configuration register for MCU SRAM"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "MEM_SEL,Value will be written to SRAM_MMR:MEM_CTL.MEM_SEL by ROM boot FW"
|
|
newline
|
|
hexmask.long.byte 0x08 1.--7. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "PARITY_DIS,Value will be inverted and then written to PRCM:MCUSRAMCFG.PARITY_EN by ROM boot FW" "0,1"
|
|
rgroup.long 0x64++0x07
|
|
line.long 0x00 "CPU_LOCK_CFG,Configuration register for MCU CPU lock options"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4. "LOCKNSVTOR_N,Value will be inverted and written to PRCM:CPULOCK.LOCKNSVTOR by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "LOCKSVTAIRCR_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSVTAIRCR by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "LOCKSAU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSAU by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKNSMPU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKNSMPU by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LOCKSMPU_N,Value will be inverted and written to PRCM:CPULOCK.LOCKSMPU by ROM boot FW" "0,1"
|
|
line.long 0x04 "DEB_AUTH_CFG,Configuration register for debug authentication"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 3. "INTSPNIDEN,Value will be written to CPU_DCB:DAUTHCTRL.INTSPNIDEN by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "SPNIDENSEL,Value will be written to CPU_DCB:DAUTHCTRL.SPNIDENSEL by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "INTSPIDEN,Value will be written to CPU_DCB:DAUTHCTRL.INTSPIDEN by ROM boot FW" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "SPIDENSEL,Value will be written to CPU_DCB:DAUTHCTRL.SPIDENSEL by ROM boot FW" "0,1"
|
|
tree.end
|
|
tree "CPU"
|
|
tree "CPU_CTI"
|
|
base ad:0xE0042000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTI Control Register"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "GLBEN,Enables or disables the CTI" "0,1"
|
|
group.long 0x10++0x2F
|
|
line.long 0x00 "CTIINTACK,CTI Interrupt Acknowledge Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INTACK,Acknowledges the corresponding ctitrigout output"
|
|
line.long 0x04 "CTIAPPSET,CTI Application Trigger Set Register"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0.--3. "APPSET,Setting a bit HIGH generates a channel event for the selected channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CTIAPPCLEAR,CTI Application Trigger Clear Register"
|
|
hexmask.long 0x08 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0.--3. "APPCLEAR,Sets the corresponding bits in the CTIAPPSET to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "CTIAPPPULSE,CTI Application Pulse Register"
|
|
hexmask.long 0x0C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0.--3. "APPULSE,Setting a bit HIGH generates a channel event pulse for the selected channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "CTIINEN0,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "CTIINEN1,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "CTIINEN2,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "CTIINEN3,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "CTIINEN4,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x20 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "CTIINEN5,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x24 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x28 "CTIINEN6,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x28 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "CTIINEN7,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x2C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA0++0x1F
|
|
line.long 0x00 "CTIOUTEN0,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--3. "TRIGOUTEN,Enables a cross trigger event to ctitrigout when the corresponding channel is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CTIOUTEN1,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0.--3. "TRIGOUTEN,Enables a cross trigger event to ctitrigout when the corresponding channel is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CTIOUTEN2,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x08 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0.--3. "TRIGOUTEN,Enables a cross trigger event to ctitrigout when the corresponding channel is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "CTIOUTEN3,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x0C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0.--3. "TRIGOUTEN,Enables a cross trigger event to ctitrigout when the corresponding channel is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "CTIOUTEN4,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0.--3. "TRIGOUTEN,Enables a cross trigger event to ctitrigout when the corresponding channel is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "CTIOUTEN5,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0.--3. "TRIGOUTEN,Enables a cross trigger event to ctitrigout when the corresponding channel is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "CTIOUTEN6,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0.--3. "TRIGOUTEN,Enables a cross trigger event to ctitrigout when the corresponding channel is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "CTIOUTEN7,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0.--3. "TRIGOUTEN,Enables a cross trigger event to ctitrigout when the corresponding channel is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x130++0x0B
|
|
line.long 0x00 "CTITRIGINSTATUS,CTI Trigger to Channel Enable Registers"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIGINSTATUS,Shows the status of the ctitrigin inputs"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTI Trigger In Status Register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "TRIGOUTSTATUS,Shows the status of the ctitrigout outputs"
|
|
line.long 0x08 "CTICHINSTATUS,CTI Channel In Status Register"
|
|
hexmask.long 0x08 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0.--3. "CTICHINSTATUS,Shows the status of the ctichin inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CTIGATE,Enable CTI Channel Gate register"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "CTIGATEEN3,Enable ctichout3" "0,1"
|
|
bitfld.long 0x00 2. "CTIGATEEN2,Enable ctichout2" "0,1"
|
|
bitfld.long 0x00 1. "CTIGATEEN1,Enable ctichout1" "0,1"
|
|
bitfld.long 0x00 0. "CTIGATEEN0,Enable ctichout0" "0,1"
|
|
line.long 0x04 "ASICCTL,External Multiplexer Control register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "ASICCTL,When external multiplexing is implemented for trigger signals then the number of multiplexed signals on each trigger must be shown in the Device ID Register"
|
|
group.long 0xEE4++0x07
|
|
line.long 0x00 "ITCHOUT,Integration Test Channel Output register"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--3. "CTCHOUT,Sets the value of the ctichout outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ITTRIGOUT,Integration Test Trigger Output register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "CTTRIGOUT,Sets the value of the ctitrigout outputs"
|
|
rgroup.long 0xEF4++0x03
|
|
line.long 0x00 "ITCHIN,Integration Test Channel Input register"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--3. "CTCHIN,Reads the value of the ctichin inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ITCTRL,Integration Mode Control register"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "IME,Integration Mode Enable" "0,1"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Device Architecture register"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Indicates the component"
|
|
bitfld.long 0x00 20. "PRESENT,Indicates whether the DEVARCH register is present: 0x1 Present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Indicates the architecture revision: 0x1 Revision 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARCHID,Indicates the component: 0x0A34 CoreSight GPR"
|
|
rgroup.long 0xFC8++0x0B
|
|
line.long 0x00 "DEVID,Device Configuration register"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16.--19. "NUMCH,Number of ECT channels available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. "NUMTRIG,Number of ECT triggers available"
|
|
bitfld.long 0x00 5.--7. "RESERVED5,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "EXTMUXNUM,Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DEVTYPE,Device Type Identifier register"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SUB,Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "MAJOR,Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR4,CoreSight Periperal ID4"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "SIZE,Always 0b0000" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. "DES_2,Together PIDR1.DES_0 PIDR2.DES_1 and PIDR4.DES_2 identify the designer of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,CoreSight Periperal ID5"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x1F
|
|
line.long 0x00 "PIDR0,CoreSight Periperal ID0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Bits[7:0] of the 12-bit part number of the component"
|
|
line.long 0x04 "PIDR1,CoreSight Periperal ID1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,Together PIDR1.DES_0 PIDR2.DES_1 and PIDR4.DES_2 identify the designer of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,Bits[11:8] of the 12-bit part number of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,CoreSight Periperal ID2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,0b0101 This device is at r1p0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,Always 1" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,Together PIDR1.DES_0 PIDR2.DES_1 and PIDR4.DES_2 identify the designer of the component" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,CoreSight Periperal ID3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,Indicates minor errata fixes specific to the revision of the component being used for example metal fixes after implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "CIDR0,CoreSight Component ID0"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble[0]"
|
|
line.long 0x14 "CIDR1,CoreSight Component ID1"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 4.--7. "CLASS,Class of the component for example whether the component is a ROM table or a generic CoreSight component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "CIDR2,CoreSight Component ID2"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble[2]"
|
|
line.long 0x1C "CIDR3,CoreSight Component ID3"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble[3]"
|
|
tree.end
|
|
tree "CPU_DCB"
|
|
base ad:0xE000EDE0
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "DHCSR,Controls halting debug"
|
|
rbitfld.long 0x00 27.--31. "RESERVED27,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 16.--31. 1. "DBGKEY,A debugger must write 0xA05F to this field to enable write access to the remaining bits otherwise the PE ignores the write access"
|
|
rbitfld.long 0x00 26. "S_RESTART_ST,Indicates the PE has processed a request to clear DHCSR.C_HALT to 0" "0,1"
|
|
rbitfld.long 0x00 25. "S_RESET_ST,Indicates whether the PE has been reset since the last read of the DHCSR" "0,1"
|
|
rbitfld.long 0x00 24. "S_RETIRE_ST,Set to 1 every time the PE retires one of more instructions" "0,1"
|
|
rbitfld.long 0x00 21.--23. "RESERVED21,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 20. "S_SDE,Indicates whether Secure invasive debug is allowed" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "S_LOCKUP,Indicates whether the PE is in Lockup state" "0,1"
|
|
rbitfld.long 0x00 18. "S_SLEEP,Indicates whether the PE is sleeping" "0,1"
|
|
rbitfld.long 0x00 17. "S_HALT,Indicates whether the PE is in Debug state" "0,1"
|
|
hexmask.long.word 0x00 6.--15. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 5. "C_SNAPSTALL,Allow imprecise entry to Debug state" "0,1"
|
|
rbitfld.long 0x00 4. "RESERVED4,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x00 3. "C_MASKINTS,When debug is enabled the debugger can write to this bit to mask PendSV SysTick and external configurable interrupts" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "C_STEP,Enable single instruction step" "0,1"
|
|
bitfld.long 0x00 1. "C_HALT,PE enter Debug state halt request" "0,1"
|
|
bitfld.long 0x00 0. "C_DEBUGEN,Enable Halting debug" "0,1"
|
|
line.long 0x04 "DCRSR,With the DCRDR. provides debug access to the general-purpose registers. special-purpose registers. and the FP extension registers"
|
|
hexmask.long.word 0x04 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 16. "REGWnR,Specifies the access type for the transfer" "0,1"
|
|
hexmask.long.word 0x04 7.--15. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--6. 1. "REGSEL,Specifies the general-purpose register special-purpose register or FP register to transfer"
|
|
line.long 0x08 "DCRDR,With the DCRSR. provides debug access to the general-purpose registers. special-purpose registers. and the FP Extension registers"
|
|
line.long 0x0C "DEMCR,Manages vector catch behavior and DebugMonitor handling when debugging"
|
|
hexmask.long.byte 0x0C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 24. "TRCENA,Global enable for all DWT and ITM features" "0,1"
|
|
rbitfld.long 0x0C 21.--23. "RESERVED21,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0C 20. "SDME,Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state" "0,1"
|
|
rbitfld.long 0x0C 19. "MON_REQ,DebugMonitor semaphore bit" "0,1"
|
|
rbitfld.long 0x0C 18. "MON_STEP,Enable DebugMonitor stepping" "0,1"
|
|
rbitfld.long 0x0C 17. "MON_PEND,Sets or clears the pending state of the DebugMonitor exception" "0,1"
|
|
newline
|
|
rbitfld.long 0x0C 16. "MON_EN,Enable the DebugMonitor exception" "0,1"
|
|
rbitfld.long 0x0C 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x0C 11. "VC_SFERR,SecureFault exception halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x0C 10. "VC_HARDERR,HardFault exception halting debug vector catch enable" "0,1"
|
|
rbitfld.long 0x0C 9. "VC_INTERR,Enable halting debug vector catch for faults during exception entry and return" "0,1"
|
|
rbitfld.long 0x0C 8. "VC_BUSERR,BusFault exception halting debug vector catch enable" "0,1"
|
|
rbitfld.long 0x0C 7. "VC_STATERR,Enable halting debug trap on a UsageFault exception caused by a state information error for example an Undefined Instruction exception" "0,1"
|
|
newline
|
|
rbitfld.long 0x0C 6. "VC_CHKERR,Enable halting debug trap on a UsageFault exception caused by a checking error for example an alignment check error" "0,1"
|
|
rbitfld.long 0x0C 5. "VC_NOCPERR,Enable halting debug trap on a UsageFault caused by an access to a coprocessor" "0,1"
|
|
rbitfld.long 0x0C 4. "VC_MMERR,Enable halting debug trap on a MemManage exception" "0,1"
|
|
rbitfld.long 0x0C 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 0. "VC_CORERESET,Enable Reset Vector Catch" "0,1"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "DAUTHCTRL,This register allows the external authentication interface to beoverridden from software"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x00 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
bitfld.long 0x00 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x00 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
line.long 0x04 "DSCSR,Provides control and status information for Secure debug"
|
|
hexmask.long.word 0x04 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 17. "CDSKEY,Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero" "0,1"
|
|
bitfld.long 0x04 16. "CDS,This field indicates the current Security state of the processor" "0,1"
|
|
hexmask.long.word 0x04 2.--15. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 1. "SBRSEL,If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger" "0,1"
|
|
bitfld.long 0x04 0. "SBRSELEN,Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger" "0,1"
|
|
tree.end
|
|
tree "CPU_DWT"
|
|
base ad:0xE0001000
|
|
rgroup.long 0x00++0x1F
|
|
line.long 0x00 "CTRL,Provides configuration and status information for the DWT unit. and used to control features of the unit"
|
|
bitfld.long 0x00 28.--31. "NUMCOMP,Number of DWT comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "NOTRCPKT,Indicates whether the implementation does not support trace" "0,1"
|
|
bitfld.long 0x00 26. "NOEXTTRIG,Reserved RAZ" "0,1"
|
|
bitfld.long 0x00 25. "NOCYCCNT,Indicates whether the implementation does not include a cycle counter" "0,1"
|
|
bitfld.long 0x00 24. "NOPRFCNT,Indicates whether the implementation does not include the profiling counters" "0,1"
|
|
bitfld.long 0x00 23. "CYCDISS,Controls whether the cycle counter is disabled in Secure state" "0,1"
|
|
bitfld.long 0x00 22. "CYCEVTENA,Enables Event Counter packet generation on POSTCNT underflow" "0,1"
|
|
bitfld.long 0x00 21. "FOLDEVTENA,Enables DWT_FOLDCNT counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LSUEVTENA,Enables DWT_LSUCNT counter" "0,1"
|
|
bitfld.long 0x00 19. "SLEEPEVTENA,Enable DWT_SLEEPCNT counter" "0,1"
|
|
bitfld.long 0x00 18. "EXCEVTENA,Enables DWT_EXCCNT counter" "0,1"
|
|
bitfld.long 0x00 17. "CPIEVTENA,Enables DWT_CPICNT counter" "0,1"
|
|
bitfld.long 0x00 16. "EXTTRCENA,Enables generation of Exception Trace packets" "0,1"
|
|
bitfld.long 0x00 13.--15. "RESERVED13,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. "PCSAMPLENA,Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation" "0,1"
|
|
bitfld.long 0x00 10.--11. "SYNCTAP,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "CYCTAP,Selects the position of the POSTCNT tap on the CYCCNT counter" "0,1"
|
|
bitfld.long 0x00 5.--8. "POSTINIT,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "POSTPRESET,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "CYCCNTENA,Enables CYCCNT" "0,1"
|
|
line.long 0x04 "CYCCNT,Shows or sets the value of the processor cycle counter. CYCCNT"
|
|
line.long 0x08 "CPICNT,CPI Count Register"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x08 0.--7. 1. "CPICNT,Counts one on each cycle when all of the following are true:- DWT_CTRL.CPIEVTENA == 1 and DEMCR.TRCENA == 1.- No instruction is executed.- No load-store operation is in progress see DWT_LSUCNT.- No exception-entry or exception-exit operation is.."
|
|
line.long 0x0C "EXCCNT,Counts the total cycles spent in exception processing"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EXCCNT,Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x10 "SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SLEEPCNT,Counts one on each cycle when all of the following are true:- DWT_CTRL.SLEEPEVTENA == 1 and DEMCR.TRCENA == 1.- No instruction is executed see DWT_CPICNT.- No load-store operation is in progress see DWT_LSUCNT.- No exception-entry or.."
|
|
line.long 0x14 "LSUCNT,Increments on the additional cycles required to execute all load or store instructions"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x14 0.--7. 1. "LSUCNT,Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x18 "FOLDCNT,Increments on the additional cycles required to execute all load or store instructions"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FOLDCNT,Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA =="
|
|
line.long 0x1C "PCSR,Program Counter Sample Register"
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x10 0x20 0x30 )
|
|
hgroup.long ($2+0x20)++0x03
|
|
hide.long 0x00 "COMP$1,Provides a reference value for use by watchpoint comparator 0"
|
|
repeat.end
|
|
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x10 0x20 0x30 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "FUNCTION$1,Controls the operation of watchpoint comparator 0"
|
|
rbitfld.long 0x00 27.--31. "ID,Identifies the capabilities for MATCH for comparator *n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 25.--26. "RESERVED25,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 24. "MATCHED,Set to 1 when the comparator matches" "0,1"
|
|
hexmask.long.word 0x00 12.--23. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 10.--11. "DATAVSIZE,Defines the size of the object being watched for by Data Value and Data Address comparators" "0,1,2,3"
|
|
rbitfld.long 0x00 6.--9. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--5. "ACTION,Defines the action on a match" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "MATCH,Controls the type of match generated by this comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the DWT"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the DWT"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_ETM"
|
|
base ad:0xE0041000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TRCPRGCTLR,Programming Control Register"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "EN,Trace Unit Enable" "0,1"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "TRCSTATR,The TRCSTATR indicates the ETM-Teal status"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "PMSTABLE,Indicates whether the ETM-Teal registers are stable and can be" "0,1"
|
|
bitfld.long 0x00 0. "IDLE,Indicates that the trace unit is inactive" "0,1"
|
|
line.long 0x04 "TRCCONFIGR,The TRCCONFIGR sets the basic tracing options for the trace unit"
|
|
hexmask.long.word 0x04 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 17. "DV,Reserved `ImpDefRES0" "0,1"
|
|
bitfld.long 0x04 16. "DA,Reserved `ImpDefRES0" "0,1"
|
|
bitfld.long 0x04 15. "RESERVED15,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x04 13.--14. "QE,Reserved `ImpDefRES0" "0,1,2,3"
|
|
bitfld.long 0x04 12. "RS,Reserved `ImpDefRES0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 11. "TS,Reserved `ImpDefRES0" "0,1"
|
|
bitfld.long 0x04 8.--10. "COND,Reserved `ImpDefRES0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 7. "VMID,Reserved `ImpDefRES0" "0,1"
|
|
bitfld.long 0x04 6. "CID,Reserved `ImpDefRES0" "0,1"
|
|
bitfld.long 0x04 5. "RESERVED5,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x04 4. "CCI,Reserved `ImpDefRES0" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "BB,Reserved `ImpDefRES0" "0,1"
|
|
bitfld.long 0x04 1.--2. "INSTP0,Reserved `ImpDefRES0" "0,1,2,3"
|
|
bitfld.long 0x04 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "TRCEVENTCTL0R,The TRCEVENTCTL0R controls the tracing of events in the trace stream"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 15. "TYPE1,Selects the resource type for event 1" "0,1"
|
|
rbitfld.long 0x00 11.--14. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--10. "SEL1,Selects the resource number based on the value of TYPE1: When TYPE1 is 0 selects a single selected resource from 0-15 defined by SEL1[2:0]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "TYPE0,Selects the resource type for event 0" "0,1"
|
|
rbitfld.long 0x00 3.--6. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "SEL0,Selects the resource number based on the value of TYPE0: When TYPE1 is 0 selects a single selected resource from 0-15 defined by SEL0[2:0]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "TRCEVENTCTL1R,The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave"
|
|
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 12. "LPOVERRIDE,Low power state behavior override" "0,1"
|
|
bitfld.long 0x04 11. "ATB,ATB enabled" "0,1"
|
|
hexmask.long.word 0x04 2.--10. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 1. "INSTEN1,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" "0,1"
|
|
bitfld.long 0x04 0. "INSTEN0,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" "0,1"
|
|
group.long 0x2C++0x0F
|
|
line.long 0x00 "TRCSTALLCTLR,The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 10. "INSTPRIORITY,Prioritize instruction trace if instruction trace buffer space is less than LEVEL" "0,1"
|
|
rbitfld.long 0x00 9. "RESERVED9,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x00 8. "ISTALL,Stall processor based on instruction trace buffer space" "0,1"
|
|
rbitfld.long 0x00 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "LEVEL,Threshold at which stalling becomes active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TRCTSCTLR,The TRCTSCTLR controls the insertion of global timestamps into the trace stream"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "EVENT,An event selector"
|
|
line.long 0x08 "TRCSYNCPR,The TRCSYNCPR specifies the period of trace synchronization of the trace streams"
|
|
hexmask.long 0x08 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0.--4. "PERIOD,Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "TRCCCCTLR,The TRCCCCTLR sets the threshold value for instruction trace cycle counting"
|
|
hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x0C 0.--11. 1. "THRESHOLD,Instruction trace cycle count threshold"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TRCVICTLR,The TRCVICTLR controls instruction trace filtering"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 19. "EXLEVEL_S3,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level" "0,1"
|
|
rbitfld.long 0x00 17.--18. "RESERVED17,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16. "EXLEVEL_S0,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level" "0,1"
|
|
rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "TRCERR,Selects whether a system error exception must always be traced" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TRCRESET,Selects whether a reset exception must always be traced" "0,1"
|
|
bitfld.long 0x00 9. "SSSTATUS,Indicates the current status of the start/stop logic" "0,1"
|
|
rbitfld.long 0x00 8. "RESERVED8,Software should not rely on the value of a reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EVENT,An event selector"
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x140)++0x03
|
|
line.long 0x00 "TRCCNTRLDVR$1,The TRCCNTRLDVR defines the reload value for the reduced function counter"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "VALUE,Defines the reload value for the counter"
|
|
repeat.end
|
|
rgroup.long 0x180++0x17
|
|
line.long 0x00 "TRCIDR8,TRCIDR8"
|
|
line.long 0x04 "TRCIDR9,TRCIDR9"
|
|
line.long 0x08 "TRCIDR10,TRCIDR10"
|
|
line.long 0x0C "TRCIDR11,TRCIDR11"
|
|
line.long 0x10 "TRCIDR12,TRCIDR12"
|
|
line.long 0x14 "TRCIDR13,TRCIDR13"
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x1C0)++0x03
|
|
line.long 0x00 "TRCIMSPEC$1,The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features. and enables any features that are provided"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--3. "SUPPORT,Set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
rgroup.long 0x1E0++0x17
|
|
line.long 0x00 "TRCIDR0,TRCIDR0"
|
|
bitfld.long 0x00 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x00 29. "COMMOPT,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x00 24.--28. "TSSIZE,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--23. "RESERVED18,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. "TRCEXDATA,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x00 15.--16. "QSUPP,reads as `ImpDef" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QFILT,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x00 12.--13. "CONDTYPE,reads as `ImpDef" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "NUMEVENT,reads as `ImpDef" "0,1,2,3"
|
|
bitfld.long 0x00 9. "RETSTACK,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x00 8. "RESERVED8,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x00 7. "TRCCCI,reads as `ImpDef" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TRCCOND,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x00 5. "TRCBB,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x00 3.--4. "TRCDATA,reads as `ImpDef" "0,1,2,3"
|
|
bitfld.long 0x00 1.--2. "INSTP0,reads as `ImpDef" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x04 "TRCIDR1,TRCIDR1"
|
|
hexmask.long.byte 0x04 24.--31. 1. "DESIGNER,reads as `ImpDef"
|
|
hexmask.long.byte 0x04 16.--23. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. "TRCARCHMAJ,reads as 0b0100" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. "TRCARCHMIN,reads as 0b0000" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "REVISION,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "TRCIDR2,TRCIDR2"
|
|
bitfld.long 0x08 29.--31. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 25.--28. "CCSIZE,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--24. "DVSIZE,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 15.--19. "DASIZE,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 10.--14. "VMIDSIZE,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 5.--9. "CIDSIZE,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 0.--4. "IASIZE,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "TRCIDR3,TRCIDR3"
|
|
bitfld.long 0x0C 31. "NOOVERFLOW,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x0C 28.--30. "NUMPROC,reads as `ImpDef" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 27. "SYSSTALL,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x0C 26. "STALLCTL,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x0C 25. "SYNCPR,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x0C 24. "TRCERR,reads as `ImpDef" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 20.--23. "EXLEVEL_NS,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--19. "EXLEVEL_S,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x0C 0.--11. 1. "CCITMIN,reads as `ImpDef"
|
|
line.long 0x10 "TRCIDR4,TRCIDR4"
|
|
bitfld.long 0x10 28.--31. "NUMVMIDC,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. "NUMCIDC,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. "NUMSSCC,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. "NUMRSPAIR,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 12.--15. "NUMPC,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 9.--11. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 8. "SUPPDAC,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x10 4.--7. "NUMDVC,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. "NUMACPAIRS,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "TRCIDR5,TRCIDR5"
|
|
bitfld.long 0x14 31. "REDFUNCNTR,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x14 28.--30. "NUMCNTR,reads as `ImpDef" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 25.--27. "NUMSEQSTATE,reads as `ImpDef" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24. "RESERVED24,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x14 23. "LPOVERRIDE,reads as `ImpDef" "0,1"
|
|
bitfld.long 0x14 22. "ATBTRIG,reads as `ImpDef" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16.--21. "TRACEIDSIZE,reads as 0x07" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 9.--11. "NUMEXTINSEL,reads as `ImpDef" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,reads as `ImpDef"
|
|
repeat 2. (list 6. 7. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x1F8)++0x03
|
|
line.long 0x00 "TRCIDR$1,TRCIDR6"
|
|
repeat.end
|
|
repeat 2. (list 2. 3. )(list 0x00 0x04 )
|
|
group.long ($2+0x208)++0x03
|
|
line.long 0x00 "TRCRSCTLR$1,The TRCRSCTLR controls the trace resources"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED22,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 21. "PAIRINV,Inverts the result of a combined pair of resources" "0,1"
|
|
bitfld.long 0x00 20. "INV,Inverts the selected resources" "0,1"
|
|
rbitfld.long 0x00 19. "RESERVED19,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x00 16.--18. "GROUP,Selects a group of resource" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SELECT,Selects one or more resources from the wanted group"
|
|
repeat.end
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x2A0)++0x03
|
|
line.long 0x00 "TRCSSCSR$1,Controls the corresponding single-shot comparator resource"
|
|
bitfld.long 0x00 31. "STATUS,Single-shot status bit" "0,1"
|
|
hexmask.long 0x00 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "PC,PE comparator input support" "0,1"
|
|
bitfld.long 0x00 2. "DV,Data value comparator support bit" "0,1"
|
|
bitfld.long 0x00 1. "DA,Data address comparator support bit" "0,1"
|
|
bitfld.long 0x00 0. "INST,Instruction address comparator support bit" "0,1"
|
|
repeat.end
|
|
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x2C0)++0x03
|
|
line.long 0x00 "TRCSSPCICR$1,Selects the PE comparator inputs for Single-shot control"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "PC1,Selects one or more PE comparator inputs for Single-shot control" "0,1"
|
|
bitfld.long 0x00 0. "PC0,Selects one or more PE comparator inputs for Single-shot control" "0,1"
|
|
repeat.end
|
|
group.long 0x310++0x07
|
|
line.long 0x00 "TRCPDCR,Requests the system to provide power to the trace unit"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "PU,Powerup request bit" "0,1"
|
|
rbitfld.long 0x00 0.--2. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "TRCPDSR,Returns the following information about the trace unit: - OS Lock status"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5. "OSLK,OS Lock status bit" "0,1"
|
|
bitfld.long 0x04 2.--4. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 1. "STICKYPD,Sticky powerdown status bit" "0,1"
|
|
bitfld.long 0x04 0. "POWER,Power status bit" "0,1"
|
|
group.long 0xEE4++0x03
|
|
line.long 0x00 "TRCITATBIDR,Trace Intergration ATB Identification Register"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--6. 1. "ID,Trace ID"
|
|
group.long 0xEF4++0x03
|
|
line.long 0x00 "TRCITIATBINR,Trace Integration Instruction ATB In Register"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFVALIDM,Integration Mode instruction AFVALIDM in" "0,1"
|
|
bitfld.long 0x00 0. "ATREADYM,Integration Mode instruction ATREADYM in" "0,1"
|
|
group.long 0xEFC++0x03
|
|
line.long 0x00 "TRCITIATBOUTR,Trace Integration Instruction ATB Out Register"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFREADY,Integration Mode instruction AFREADY out" "0,1"
|
|
bitfld.long 0x00 0. "ATVALID,Integration Mode instruction ATVALID out" "0,1"
|
|
group.long 0xFA0++0x07
|
|
line.long 0x00 "TRCCLAIMSET,Claim Tag Set Register"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "SET3,When a write to one of these bits occurs with the value" "0,1"
|
|
bitfld.long 0x00 2. "SET2,When a write to one of these bits occurs with the value" "0,1"
|
|
bitfld.long 0x00 1. "SET1,When a write to one of these bits occurs with the value" "0,1"
|
|
bitfld.long 0x00 0. "SET0,When a write to one of these bits occurs with the value" "0,1"
|
|
line.long 0x04 "TRCCLAIMCLR,Claim Tag Clear Register"
|
|
hexmask.long 0x04 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 3. "CLR3,When a write to one of these bits occurs with the value" "0,1"
|
|
bitfld.long 0x04 2. "CLR2,When a write to one of these bits occurs with the value" "0,1"
|
|
bitfld.long 0x04 1. "CLR1,When a write to one of these bits occurs with the value" "0,1"
|
|
bitfld.long 0x04 0. "CLR0,When a write to one of these bits occurs with the value" "0,1"
|
|
rgroup.long 0xFB8++0x07
|
|
line.long 0x00 "TRCAUTHSTATUS,Returns the level of tracing that the trace unit can support"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug" "0,1,2,3"
|
|
line.long 0x04 "TRCDEVARCH,TRCDEVARCH"
|
|
hexmask.long.word 0x04 21.--31. 1. "ARCHITECT,reads as 0b01000111011"
|
|
bitfld.long 0x04 20. "PRESENT,reads as 0b1" "0,1"
|
|
bitfld.long 0x04 16.--19. "REVISION,reads as 0b0000" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. "ARCHID,reads as 0b0100101000010011"
|
|
rgroup.long 0xFC8++0x0B
|
|
line.long 0x00 "TRCDEVID,TRCDEVID"
|
|
line.long 0x04 "TRCDEVTYPE,TRCDEVTYPE"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SUB,reads as 0b0001" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "MAJOR,reads as 0b0011" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "TRCPIDR4,TRCPIDR4"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "SIZE,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. "DES_2,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "TRCPIDR$1,TRCPIDR5"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "TRCPIDR0,TRCPIDR0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,reads as `ImpDef"
|
|
line.long 0x04 "TRCPIDR1,TRCPIDR1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_0,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "TRCPIDR2,TRCPIDR2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,reads as 0b1" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_0,reads as `ImpDef" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "TRCPIDR3,TRCPIDR3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,reads as `ImpDef" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "TRCCIDR$1,TRCCIDR0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,reads as 0b00001101"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "TRCCIDR1,TRCCIDR1"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,reads as 0b1001" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,reads as 0b0000" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_FPB"
|
|
base ad:0xE0002000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,Provides FPB implementation information. and the global enable for the FPB unit"
|
|
rbitfld.long 0x00 28.--31. "REV,Flash Patch and Breakpoint Unit architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 15.--27. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 12.--14. "NUM_CODE_14_12_,Indicates the number of implemented instruction address comparators" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--11. "NUM_LIT,Indicates the number of implemented literal address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 4.--7. "NUM_CODE_7_4_,Indicates the number of implemented instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "KEY,Writes to the FP_CTRL are ignored unless KEY is concurrently written to one" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the FPB" "0,1"
|
|
line.long 0x04 "REMAP,Indicates whether the implementation supports Flash Patch remap and. if it does. holds the target address for remap"
|
|
bitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x04 29. "RMPSPT,Indicates whether the FPB unit supports the Flash Patch remap function" "0,1"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. "REMAP,Holds the bits[28:5] of the Flash Patch remap address"
|
|
bitfld.long 0x04 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "COMP$1,Holds an address for comparison"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "BE,Selects between flashpatch and breakpoint functionality" "0,1"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the FPB"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the FPB"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the FP"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the FP"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_FPU"
|
|
base ad:0xE000EF30
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "FPCCR,Holds control data for the Floating-point extension"
|
|
bitfld.long 0x00 31. "ASPEN,When this bit is set to 1 execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "0,1"
|
|
bitfld.long 0x00 30. "LSPEN,Enables lazy context save of floating-point state" "0,1"
|
|
bitfld.long 0x00 29. "LSPENS,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "0,1"
|
|
bitfld.long 0x00 28. "CLRONRET,Clear floating-point caller saved registers on exception return" "0,1"
|
|
bitfld.long 0x00 27. "CLRONRETS,This bit controls whether the CLRONRET bit is writeable from the Non-secure state" "0,1"
|
|
bitfld.long 0x00 26. "TS,Treat floating-point registers as Secure enable" "0,1"
|
|
hexmask.long.word 0x00 11.--25. 1. "RESERVED11,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 10. "UFRDY,Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SPLIMVIOL,This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated" "0,1"
|
|
bitfld.long 0x00 8. "MONRDY,Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending" "0,1"
|
|
bitfld.long 0x00 7. "SFRDY,Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending" "0,1"
|
|
bitfld.long 0x00 6. "BFRDY,Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending" "0,1"
|
|
bitfld.long 0x00 5. "MMRDY,Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending" "0,1"
|
|
bitfld.long 0x00 4. "HFRDY,Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending" "0,1"
|
|
bitfld.long 0x00 3. "THREAD,Indicates the PE mode when it allocated the floating-point stack frame" "0,1"
|
|
bitfld.long 0x00 2. "S,Security status of the floating-point context" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "USER,Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame" "0,1"
|
|
bitfld.long 0x00 0. "LSPACT,Indicates whether lazy preservation of the floating-point state is active" "0,1"
|
|
line.long 0x04 "FPCAR,Holds the location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
hexmask.long 0x04 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
rbitfld.long 0x04 0.--2. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "FPDSCR,Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context"
|
|
rbitfld.long 0x08 27.--31. "RESERVED27,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 26. "AHP,Default value for FPSCR.AHP" "0,1"
|
|
bitfld.long 0x08 25. "DN,Default value for FPSCR.DN" "0,1"
|
|
bitfld.long 0x08 24. "FZ,Default value for FPSCR.FZ" "0,1"
|
|
bitfld.long 0x08 22.--23. "RMode,Default value for FPSCR.RMode" "0,1,2,3"
|
|
hexmask.long.tbyte 0x08 0.--21. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "MVFR0,Describes the features provided by the Floating-point Extension"
|
|
bitfld.long 0x0C 28.--31. "FPRound,Indicates the rounding modes supported by the FP Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 20.--23. "FPSqrt,Indicates the support for FP square root operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--19. "FPDivide,Indicates the support for FP divide operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. "FPDP,Indicates support for FP double-precision operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 4.--7. "FPSP,Indicates support for FP single-precision operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "SIMDReg,Indicates size of FP register file" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "MVFR1,Describes the features provided by the Floating-point Extension"
|
|
bitfld.long 0x10 28.--31. "FMAC,Indicates whether the FP Extension implements the fused multiply accumulate instructions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. "FPHP,Indicates whether the FP Extension implements half-precision FP conversion instructions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x10 8.--23. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 4.--7. "FPDNaN,Indicates whether the FP hardware implementation supports NaN propagation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. "FPFtZ,Indicates whether subnormals are always flushed-to-zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "MVFR2,Describes the features provided by the Floating-point Extension"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 4.--7. "FPMisc,Indicates support for miscellaneous FP features" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_ICB"
|
|
base ad:0xE000E000
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "ICTR,Provides information about the interrupt controller"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0.--3. "INTLINESNUM,Indicates the number of the highest implemented register in each of the NVIC control register sets or in the case of NVIC_IPR*n 4xINTLINESNUM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ACTLR,Provides IMPLEMENTATION DEFINED configuration and control options"
|
|
rbitfld.long 0x04 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x04 29. "EXTEXCLALL,External Exclusives Allowed with no MPU" "0,1"
|
|
hexmask.long.word 0x04 13.--28. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 12. "DISITMATBFLUSH,Disable ATB Flush" "0,1"
|
|
rbitfld.long 0x04 11. "RESERVED11,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x04 10. "FPEXCODIS,Disable FPU exception outputs" "0,1"
|
|
bitfld.long 0x04 9. "DISOOFP,Disable out-of-order FP instruction completion" "0,1"
|
|
newline
|
|
rbitfld.long 0x04 3.--8. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 2. "DISFOLD,Disable dual-issue" "0,1"
|
|
rbitfld.long 0x04 1. "RESERVED1,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x04 0. "DISMCYCINT,Disable dual-issue" "0,1"
|
|
tree.end
|
|
tree "CPU_ITM"
|
|
base ad:0xE0000000
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "STIM$1,Provides the interface for generating Instrumentation packets"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "DISABLED,Indicates whether the Stimulus Port is enabled or disabled" "0,1"
|
|
bitfld.long 0x00 0. "FIFOREADY,Indicates whether the Stimulus Port can accept data" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "STIM$1,Provides the interface for generating Instrumentation packets"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "DISABLED,Indicates whether the Stimulus Port is enabled or disabled" "0,1"
|
|
bitfld.long 0x00 0. "FIFOREADY,Indicates whether the Stimulus Port can accept data" "0,1"
|
|
repeat.end
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "TER0,Provide an individual enable bit for each ITM_STIM register"
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "TPR,Controls which stimulus ports can be accessed by unprivileged code"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "TCR,Configures and controls transfers through the ITM interface"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x00 23. "BUSY,Indicates whether the ITM is currently processing events" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "TraceBusID,Identifier for multi-source trace stream formatting"
|
|
rbitfld.long 0x00 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. "GTSFREQ,Defines how often the ITM generates a global timestamp based on the global timestamp clock frequency or disables generation of global timestamps" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. "TSPrescale,Local timestamp prescaler used with the trace packet reference clock" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x00 5. "STALLENA,Stall the PE to guarantee delivery of Data Trace packets" "0,1"
|
|
bitfld.long 0x00 4. "SWOENA,Enables asynchronous clocking of the timestamp counter" "0,1"
|
|
bitfld.long 0x00 3. "TXENA,Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU" "0,1"
|
|
bitfld.long 0x00 2. "SYNCENA,Enables Synchronization packet transmission for a synchronous TPIU" "0,1"
|
|
bitfld.long 0x00 1. "TSENA,Enables Local timestamp generation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ITMENA,Enables the ITM" "0,1"
|
|
rgroup.long 0xEF0++0x03
|
|
line.long 0x00 "INT_ATREADY,Integration Mode: Read ATB Ready"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFVALID,A read of this bit returns the value of AFVALID" "0,1"
|
|
bitfld.long 0x00 0. "ATREADY,A read of this bit returns the value of ATREADY" "0,1"
|
|
group.long 0xEF8++0x03
|
|
line.long 0x00 "INT_ATVALID,Integration Mode: Write ATB Valid"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "AFREADY,A write to this bit gives the value of AFREADY" "0,1"
|
|
bitfld.long 0x00 0. "ATREADY,A write to this bit gives the value of ATVALID" "0,1"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ITCTRL,Integration Mode Control Register"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "IME,Integration mode enable bit - The possible values are" "The trace unit is not in integration mode,The trace unit is in integration mode"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
|
|
bitfld.long 0x00 20. "PRESENT,Defines that the DEVARCH register is present" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,Defines the architecture revision of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "ARCHVER,Defines the architecture version of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. "ARCHPART,Defines the architecture of the component"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DEVTYPE,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "SUB,Component sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MAJOR,Component major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PIDR4,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SIZE,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "DES_2,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PIDR$1,Provides CoreSight discovery information for the ITM"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PIDR0,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,See CoreSight Architecture Specification"
|
|
line.long 0x04 "PIDR1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PIDR2,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,See CoreSight Architecture Specification" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PIDR3,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
|
|
rgroup.long ($2+0xFF0)++0x03
|
|
line.long 0x00 "CIDR$1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,See CoreSight Architecture Specification"
|
|
repeat.end
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CIDR1,Provides CoreSight discovery information for the ITM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 4.--7. "CLASS,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PRMBL_1,See CoreSight Architecture Specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "CPU_MPU"
|
|
base ad:0xE000EDC0
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MAIR0,Along with MPU_MAIR1. provides the memory attribute encodings corresponding to the AttrIndex values"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Attr3,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Attr2,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Attr1,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Attr0,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MAIR1,Along with MPU_MAIR0. provides the memory attribute encodings corresponding to the AttrIndex values"
|
|
hexmask.long.byte 0x04 24.--31. 1. "Attr7,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. "Attr6,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. "Attr5,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. "Attr4,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
tree.end
|
|
tree "CPU_MTB"
|
|
base ad:0xE0043000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "POSITION,The MTB_POSITION register contains the trace write pointer and the wrap bit"
|
|
hexmask.long 0x00 3.--31. 1. "POINTER,"
|
|
bitfld.long 0x00 2. "WRAP," "0,1"
|
|
rbitfld.long 0x00 0.--1. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
line.long 0x04 "MASTER,The MTB_MASTER register contains the main trace enable bit and other trace control fields"
|
|
bitfld.long 0x04 31. "EN," "0,1"
|
|
bitfld.long 0x04 30. "NSEN," "0,1"
|
|
hexmask.long.tbyte 0x04 10.--29. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 9. "HALTREQ," "0,1"
|
|
bitfld.long 0x04 8. "RAMPRIV," "0,1"
|
|
rbitfld.long 0x04 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x04 6. "TSTOPEN," "0,1"
|
|
bitfld.long 0x04 5. "TSTARTEN," "0,1"
|
|
newline
|
|
bitfld.long 0x04 0.--4. "MASK," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "FLOW,The MTB_FLOW register contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits"
|
|
hexmask.long 0x08 3.--31. 1. "WATERMARK,"
|
|
rbitfld.long 0x08 2. "RESERVED2,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x08 1. "AUTOHALT," "0,1"
|
|
bitfld.long 0x08 0. "AUTOSTOP," "0,1"
|
|
line.long 0x0C "BASE,The MTB_BASE register indicates where the SRAM is located in the processor memory map"
|
|
hexmask.long 0x0C 5.--31. 1. "BASE,"
|
|
bitfld.long 0x0C 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "TSTART,The MTB_TSTART register controls the trace start events using the DWT CMPMATCH feature"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x10 3. "CMPMATCH3,Reserved `ImpDefRES0" "0,1"
|
|
rbitfld.long 0x10 2. "CMPMATCH2,Reserved `ImpDefRES0" "0,1"
|
|
bitfld.long 0x10 1. "CMPMATCH1," "0,1"
|
|
bitfld.long 0x10 0. "CMPMATCH0," "0,1"
|
|
line.long 0x14 "TSTOP,The MTB_TSTOP register controls the trace stop events using the DWT CMPMATCH feature"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
rbitfld.long 0x14 3. "CMPMATCH3,Reserved `ImpDefRES0" "0,1"
|
|
rbitfld.long 0x14 2. "CMPMATCH2,Reserved `ImpDefRES0" "0,1"
|
|
bitfld.long 0x14 1. "CMPMATCH1," "0,1"
|
|
bitfld.long 0x14 0. "CMPMATCH0," "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SECURE,The MTB_SECURE register allows the SRAM region to be partitioned into two regions. with one region being defined as Secure and the other as Non-secure"
|
|
hexmask.long 0x00 5.--31. 1. "THRESHOLD,"
|
|
rbitfld.long 0x00 2.--4. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. "NS," "0,1"
|
|
bitfld.long 0x00 0. "THRSEN," "0,1"
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DEVARCH,MTB_DEVARCH"
|
|
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,reads as 0x23B"
|
|
bitfld.long 0x00 20. "PRESENT,reads as 0b1" "0,1"
|
|
bitfld.long 0x00 16.--19. "REVISION,reads as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "ARCHID,reads as 0x0A31"
|
|
rgroup.long 0xFC8++0x0B
|
|
line.long 0x00 "DEVID,MTB_DEVID"
|
|
line.long 0x04 "DEVTYPE,MTB_DEVTYPE"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "SUB,reads as 0x3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "MAJOR,reads as 0x1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PID4,MTB_PID4"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "SIZE,reads as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. "DES_2,reads as 0x4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xFD4)++0x03
|
|
line.long 0x00 "PID$1,MTB_PID5"
|
|
repeat.end
|
|
rgroup.long 0xFE0++0x1F
|
|
line.long 0x00 "PID0,MTB_PID0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,reads as 0x8E"
|
|
line.long 0x04 "PID1,MTB_PID1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 4.--7. "DES_0,reads as 0xB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "PART_1,reads as 0x9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PID2,MTB_PID2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 4.--7. "REVISION,reads as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. "JEDEC,reads as 0b1" "0,1"
|
|
bitfld.long 0x08 0.--2. "DES_1,reads as 0b011" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PID3,MTB_PID3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 4.--7. "REVAND,reads as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. "CMOD,reads as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "CID0,MTB_CID0"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,reads as 0x0D"
|
|
line.long 0x14 "CID1,MTB_CID1"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 4.--7. "CLASS,reads as 0x9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. "PRMBL_1,reads as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "CID2,MTB_CID2"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,reads as 0x05"
|
|
line.long 0x1C "CID3,MTB_CID3"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,reads as 0xB1"
|
|
tree.end
|
|
tree "CPU_NVIC"
|
|
base ad:0xE000E100
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "ISER$1,Enables or reads the enabled state of each group of 32 interrupts"
|
|
repeat.end
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x80)++0x03
|
|
line.long 0x00 "ICER$1,Clears or reads the enabled state of each group of 32 interrupts"
|
|
repeat.end
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x100)++0x03
|
|
line.long 0x00 "ISPR$1,Enables or reads the pending state of each group of 32 interrupts"
|
|
repeat.end
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x180)++0x03
|
|
line.long 0x00 "ICPR$1,Clears or reads the pending state of each group of 32 interrupts"
|
|
repeat.end
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x200)++0x03
|
|
line.long 0x00 "IABR$1,For each group of 32 interrupts. shows the active state of each interrupt"
|
|
repeat.end
|
|
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "ITNS$1,For each group of 32 interrupts. determines whether each interrupt targets Non-secure or Secure state"
|
|
repeat.end
|
|
group.long 0x300++0x147
|
|
line.long 0x00 "IPR0,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_N3,For register NVIC_IPR*0 `IAAMO the priority of interrupt number 4*0+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_N2,For register NVIC_IPR*0 `IAAMO the priority of interrupt number 4*0+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_N1,For register NVIC_IPR*0 `IAAMO the priority of interrupt number 4*0+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_N0,For register NVIC_IPR*0 `IAAMO the priority of interrupt number 4*0+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x04 "IPR1,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x04 24.--31. 1. "PRI_N3,For register NVIC_IPR*1 `IAAMO the priority of interrupt number 4*1+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x04 16.--23. 1. "PRI_N2,For register NVIC_IPR*1 `IAAMO the priority of interrupt number 4*1+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x04 8.--15. 1. "PRI_N1,For register NVIC_IPR*1 `IAAMO the priority of interrupt number 4*1+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x04 0.--7. 1. "PRI_N0,For register NVIC_IPR*1 `IAAMO the priority of interrupt number 4*1+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x08 "IPR2,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x08 24.--31. 1. "PRI_N3,For register NVIC_IPR*2 `IAAMO the priority of interrupt number 4*2+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x08 16.--23. 1. "PRI_N2,For register NVIC_IPR*2 `IAAMO the priority of interrupt number 4*2+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x08 8.--15. 1. "PRI_N1,For register NVIC_IPR*2 `IAAMO the priority of interrupt number 4*2+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PRI_N0,For register NVIC_IPR*2 `IAAMO the priority of interrupt number 4*2+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x0C "IPR3,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x0C 24.--31. 1. "PRI_N3,For register NVIC_IPR*3 `IAAMO the priority of interrupt number 4*3+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x0C 16.--23. 1. "PRI_N2,For register NVIC_IPR*3 `IAAMO the priority of interrupt number 4*3+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x0C 8.--15. 1. "PRI_N1,For register NVIC_IPR*3 `IAAMO the priority of interrupt number 4*3+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PRI_N0,For register NVIC_IPR*3 `IAAMO the priority of interrupt number 4*3+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x10 "IPR4,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x10 24.--31. 1. "PRI_N3,For register NVIC_IPR*4 `IAAMO the priority of interrupt number 4*4+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x10 16.--23. 1. "PRI_N2,For register NVIC_IPR*4 `IAAMO the priority of interrupt number 4*4+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x10 8.--15. 1. "PRI_N1,For register NVIC_IPR*4 `IAAMO the priority of interrupt number 4*4+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PRI_N0,For register NVIC_IPR*4 `IAAMO the priority of interrupt number 4*4+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x14 "IPR5,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x14 24.--31. 1. "PRI_N3,For register NVIC_IPR*5 `IAAMO the priority of interrupt number 4*5+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x14 16.--23. 1. "PRI_N2,For register NVIC_IPR*5 `IAAMO the priority of interrupt number 4*5+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x14 8.--15. 1. "PRI_N1,For register NVIC_IPR*5 `IAAMO the priority of interrupt number 4*5+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PRI_N0,For register NVIC_IPR*5 `IAAMO the priority of interrupt number 4*5+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x18 "IPR6,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x18 24.--31. 1. "PRI_N3,For register NVIC_IPR*6 `IAAMO the priority of interrupt number 4*6+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x18 16.--23. 1. "PRI_N2,For register NVIC_IPR*6 `IAAMO the priority of interrupt number 4*6+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x18 8.--15. 1. "PRI_N1,For register NVIC_IPR*6 `IAAMO the priority of interrupt number 4*6+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PRI_N0,For register NVIC_IPR*6 `IAAMO the priority of interrupt number 4*6+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x1C "IPR7,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "PRI_N3,For register NVIC_IPR*7 `IAAMO the priority of interrupt number 4*7+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "PRI_N2,For register NVIC_IPR*7 `IAAMO the priority of interrupt number 4*7+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "PRI_N1,For register NVIC_IPR*7 `IAAMO the priority of interrupt number 4*7+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PRI_N0,For register NVIC_IPR*7 `IAAMO the priority of interrupt number 4*7+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x20 "IPR8,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x20 24.--31. 1. "PRI_N3,For register NVIC_IPR*8 `IAAMO the priority of interrupt number 4*8+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x20 16.--23. 1. "PRI_N2,For register NVIC_IPR*8 `IAAMO the priority of interrupt number 4*8+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x20 8.--15. 1. "PRI_N1,For register NVIC_IPR*8 `IAAMO the priority of interrupt number 4*8+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x20 0.--7. 1. "PRI_N0,For register NVIC_IPR*8 `IAAMO the priority of interrupt number 4*8+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x24 "IPR9,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x24 24.--31. 1. "PRI_N3,For register NVIC_IPR*9 `IAAMO the priority of interrupt number 4*9+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x24 16.--23. 1. "PRI_N2,For register NVIC_IPR*9 `IAAMO the priority of interrupt number 4*9+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x24 8.--15. 1. "PRI_N1,For register NVIC_IPR*9 `IAAMO the priority of interrupt number 4*9+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PRI_N0,For register NVIC_IPR*9 `IAAMO the priority of interrupt number 4*9+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x28 "IPR10,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x28 24.--31. 1. "PRI_N3,For register NVIC_IPR*10 `IAAMO the priority of interrupt number 4*10+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x28 16.--23. 1. "PRI_N2,For register NVIC_IPR*10 `IAAMO the priority of interrupt number 4*10+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x28 8.--15. 1. "PRI_N1,For register NVIC_IPR*10 `IAAMO the priority of interrupt number 4*10+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x28 0.--7. 1. "PRI_N0,For register NVIC_IPR*10 `IAAMO the priority of interrupt number 4*10+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x2C "IPR11,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "PRI_N3,For register NVIC_IPR*11 `IAAMO the priority of interrupt number 4*11+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "PRI_N2,For register NVIC_IPR*11 `IAAMO the priority of interrupt number 4*11+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "PRI_N1,For register NVIC_IPR*11 `IAAMO the priority of interrupt number 4*11+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRI_N0,For register NVIC_IPR*11 `IAAMO the priority of interrupt number 4*11+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x30 "IPR12,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x30 24.--31. 1. "PRI_N3,For register NVIC_IPR*12 `IAAMO the priority of interrupt number 4*12+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x30 16.--23. 1. "PRI_N2,For register NVIC_IPR*12 `IAAMO the priority of interrupt number 4*12+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x30 8.--15. 1. "PRI_N1,For register NVIC_IPR*12 `IAAMO the priority of interrupt number 4*12+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PRI_N0,For register NVIC_IPR*12 `IAAMO the priority of interrupt number 4*12+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x34 "IPR13,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x34 24.--31. 1. "PRI_N3,For register NVIC_IPR*13 `IAAMO the priority of interrupt number 4*13+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x34 16.--23. 1. "PRI_N2,For register NVIC_IPR*13 `IAAMO the priority of interrupt number 4*13+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x34 8.--15. 1. "PRI_N1,For register NVIC_IPR*13 `IAAMO the priority of interrupt number 4*13+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x34 0.--7. 1. "PRI_N0,For register NVIC_IPR*13 `IAAMO the priority of interrupt number 4*13+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x38 "IPR14,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x38 24.--31. 1. "PRI_N3,For register NVIC_IPR*14 `IAAMO the priority of interrupt number 4*14+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x38 16.--23. 1. "PRI_N2,For register NVIC_IPR*14 `IAAMO the priority of interrupt number 4*14+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x38 8.--15. 1. "PRI_N1,For register NVIC_IPR*14 `IAAMO the priority of interrupt number 4*14+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x38 0.--7. 1. "PRI_N0,For register NVIC_IPR*14 `IAAMO the priority of interrupt number 4*14+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x3C "IPR15,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x3C 24.--31. 1. "PRI_N3,For register NVIC_IPR*15 `IAAMO the priority of interrupt number 4*15+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x3C 16.--23. 1. "PRI_N2,For register NVIC_IPR*15 `IAAMO the priority of interrupt number 4*15+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x3C 8.--15. 1. "PRI_N1,For register NVIC_IPR*15 `IAAMO the priority of interrupt number 4*15+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "PRI_N0,For register NVIC_IPR*15 `IAAMO the priority of interrupt number 4*15+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x40 "IPR16,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x40 24.--31. 1. "PRI_N3,For register NVIC_IPR*16 `IAAMO the priority of interrupt number 4*16+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x40 16.--23. 1. "PRI_N2,For register NVIC_IPR*16 `IAAMO the priority of interrupt number 4*16+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x40 8.--15. 1. "PRI_N1,For register NVIC_IPR*16 `IAAMO the priority of interrupt number 4*16+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x40 0.--7. 1. "PRI_N0,For register NVIC_IPR*16 `IAAMO the priority of interrupt number 4*16+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x44 "IPR17,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x44 24.--31. 1. "PRI_N3,For register NVIC_IPR*17 `IAAMO the priority of interrupt number 4*17+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x44 16.--23. 1. "PRI_N2,For register NVIC_IPR*17 `IAAMO the priority of interrupt number 4*17+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x44 8.--15. 1. "PRI_N1,For register NVIC_IPR*17 `IAAMO the priority of interrupt number 4*17+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x44 0.--7. 1. "PRI_N0,For register NVIC_IPR*17 `IAAMO the priority of interrupt number 4*17+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x48 "IPR18,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x48 24.--31. 1. "PRI_N3,For register NVIC_IPR*18 `IAAMO the priority of interrupt number 4*18+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x48 16.--23. 1. "PRI_N2,For register NVIC_IPR*18 `IAAMO the priority of interrupt number 4*18+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x48 8.--15. 1. "PRI_N1,For register NVIC_IPR*18 `IAAMO the priority of interrupt number 4*18+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x48 0.--7. 1. "PRI_N0,For register NVIC_IPR*18 `IAAMO the priority of interrupt number 4*18+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x4C "IPR19,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x4C 24.--31. 1. "PRI_N3,For register NVIC_IPR*19 `IAAMO the priority of interrupt number 4*19+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x4C 16.--23. 1. "PRI_N2,For register NVIC_IPR*19 `IAAMO the priority of interrupt number 4*19+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x4C 8.--15. 1. "PRI_N1,For register NVIC_IPR*19 `IAAMO the priority of interrupt number 4*19+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "PRI_N0,For register NVIC_IPR*19 `IAAMO the priority of interrupt number 4*19+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x50 "IPR20,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x50 24.--31. 1. "PRI_N3,For register NVIC_IPR*20 `IAAMO the priority of interrupt number 4*20+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x50 16.--23. 1. "PRI_N2,For register NVIC_IPR*20 `IAAMO the priority of interrupt number 4*20+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x50 8.--15. 1. "PRI_N1,For register NVIC_IPR*20 `IAAMO the priority of interrupt number 4*20+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x50 0.--7. 1. "PRI_N0,For register NVIC_IPR*20 `IAAMO the priority of interrupt number 4*20+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x54 "IPR21,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x54 24.--31. 1. "PRI_N3,For register NVIC_IPR*21 `IAAMO the priority of interrupt number 4*21+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x54 16.--23. 1. "PRI_N2,For register NVIC_IPR*21 `IAAMO the priority of interrupt number 4*21+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x54 8.--15. 1. "PRI_N1,For register NVIC_IPR*21 `IAAMO the priority of interrupt number 4*21+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x54 0.--7. 1. "PRI_N0,For register NVIC_IPR*21 `IAAMO the priority of interrupt number 4*21+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x58 "IPR22,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x58 24.--31. 1. "PRI_N3,For register NVIC_IPR*22 `IAAMO the priority of interrupt number 4*22+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x58 16.--23. 1. "PRI_N2,For register NVIC_IPR*22 `IAAMO the priority of interrupt number 4*22+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x58 8.--15. 1. "PRI_N1,For register NVIC_IPR*22 `IAAMO the priority of interrupt number 4*22+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x58 0.--7. 1. "PRI_N0,For register NVIC_IPR*22 `IAAMO the priority of interrupt number 4*22+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x5C "IPR23,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x5C 24.--31. 1. "PRI_N3,For register NVIC_IPR*23 `IAAMO the priority of interrupt number 4*23+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x5C 16.--23. 1. "PRI_N2,For register NVIC_IPR*23 `IAAMO the priority of interrupt number 4*23+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x5C 8.--15. 1. "PRI_N1,For register NVIC_IPR*23 `IAAMO the priority of interrupt number 4*23+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "PRI_N0,For register NVIC_IPR*23 `IAAMO the priority of interrupt number 4*23+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x60 "IPR24,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x60 24.--31. 1. "PRI_N3,For register NVIC_IPR*24 `IAAMO the priority of interrupt number 4*24+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x60 16.--23. 1. "PRI_N2,For register NVIC_IPR*24 `IAAMO the priority of interrupt number 4*24+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x60 8.--15. 1. "PRI_N1,For register NVIC_IPR*24 `IAAMO the priority of interrupt number 4*24+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x60 0.--7. 1. "PRI_N0,For register NVIC_IPR*24 `IAAMO the priority of interrupt number 4*24+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x64 "IPR25,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x64 24.--31. 1. "PRI_N3,For register NVIC_IPR*25 `IAAMO the priority of interrupt number 4*25+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x64 16.--23. 1. "PRI_N2,For register NVIC_IPR*25 `IAAMO the priority of interrupt number 4*25+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x64 8.--15. 1. "PRI_N1,For register NVIC_IPR*25 `IAAMO the priority of interrupt number 4*25+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x64 0.--7. 1. "PRI_N0,For register NVIC_IPR*25 `IAAMO the priority of interrupt number 4*25+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x68 "IPR26,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x68 24.--31. 1. "PRI_N3,For register NVIC_IPR*26 `IAAMO the priority of interrupt number 4*26+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x68 16.--23. 1. "PRI_N2,For register NVIC_IPR*26 `IAAMO the priority of interrupt number 4*26+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x68 8.--15. 1. "PRI_N1,For register NVIC_IPR*26 `IAAMO the priority of interrupt number 4*26+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x68 0.--7. 1. "PRI_N0,For register NVIC_IPR*26 `IAAMO the priority of interrupt number 4*26+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x6C "IPR27,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x6C 24.--31. 1. "PRI_N3,For register NVIC_IPR*27 `IAAMO the priority of interrupt number 4*27+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x6C 16.--23. 1. "PRI_N2,For register NVIC_IPR*27 `IAAMO the priority of interrupt number 4*27+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x6C 8.--15. 1. "PRI_N1,For register NVIC_IPR*27 `IAAMO the priority of interrupt number 4*27+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "PRI_N0,For register NVIC_IPR*27 `IAAMO the priority of interrupt number 4*27+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x70 "IPR28,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x70 24.--31. 1. "PRI_N3,For register NVIC_IPR*28 `IAAMO the priority of interrupt number 4*28+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x70 16.--23. 1. "PRI_N2,For register NVIC_IPR*28 `IAAMO the priority of interrupt number 4*28+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x70 8.--15. 1. "PRI_N1,For register NVIC_IPR*28 `IAAMO the priority of interrupt number 4*28+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x70 0.--7. 1. "PRI_N0,For register NVIC_IPR*28 `IAAMO the priority of interrupt number 4*28+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x74 "IPR29,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x74 24.--31. 1. "PRI_N3,For register NVIC_IPR*29 `IAAMO the priority of interrupt number 4*29+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x74 16.--23. 1. "PRI_N2,For register NVIC_IPR*29 `IAAMO the priority of interrupt number 4*29+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x74 8.--15. 1. "PRI_N1,For register NVIC_IPR*29 `IAAMO the priority of interrupt number 4*29+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x74 0.--7. 1. "PRI_N0,For register NVIC_IPR*29 `IAAMO the priority of interrupt number 4*29+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x78 "IPR30,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x78 24.--31. 1. "PRI_N3,For register NVIC_IPR*30 `IAAMO the priority of interrupt number 4*30+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x78 16.--23. 1. "PRI_N2,For register NVIC_IPR*30 `IAAMO the priority of interrupt number 4*30+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x78 8.--15. 1. "PRI_N1,For register NVIC_IPR*30 `IAAMO the priority of interrupt number 4*30+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x78 0.--7. 1. "PRI_N0,For register NVIC_IPR*30 `IAAMO the priority of interrupt number 4*30+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x7C "IPR31,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x7C 24.--31. 1. "PRI_N3,For register NVIC_IPR*31 `IAAMO the priority of interrupt number 4*31+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x7C 16.--23. 1. "PRI_N2,For register NVIC_IPR*31 `IAAMO the priority of interrupt number 4*31+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x7C 8.--15. 1. "PRI_N1,For register NVIC_IPR*31 `IAAMO the priority of interrupt number 4*31+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "PRI_N0,For register NVIC_IPR*31 `IAAMO the priority of interrupt number 4*31+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x80 "IPR32,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x80 24.--31. 1. "PRI_N3,For register NVIC_IPR*32 `IAAMO the priority of interrupt number 4*32+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x80 16.--23. 1. "PRI_N2,For register NVIC_IPR*32 `IAAMO the priority of interrupt number 4*32+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x80 8.--15. 1. "PRI_N1,For register NVIC_IPR*32 `IAAMO the priority of interrupt number 4*32+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x80 0.--7. 1. "PRI_N0,For register NVIC_IPR*32 `IAAMO the priority of interrupt number 4*32+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x84 "IPR33,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x84 24.--31. 1. "PRI_N3,For register NVIC_IPR*33 `IAAMO the priority of interrupt number 4*33+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x84 16.--23. 1. "PRI_N2,For register NVIC_IPR*33 `IAAMO the priority of interrupt number 4*33+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x84 8.--15. 1. "PRI_N1,For register NVIC_IPR*33 `IAAMO the priority of interrupt number 4*33+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x84 0.--7. 1. "PRI_N0,For register NVIC_IPR*33 `IAAMO the priority of interrupt number 4*33+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x88 "IPR34,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x88 24.--31. 1. "PRI_N3,For register NVIC_IPR*34 `IAAMO the priority of interrupt number 4*34+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x88 16.--23. 1. "PRI_N2,For register NVIC_IPR*34 `IAAMO the priority of interrupt number 4*34+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x88 8.--15. 1. "PRI_N1,For register NVIC_IPR*34 `IAAMO the priority of interrupt number 4*34+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x88 0.--7. 1. "PRI_N0,For register NVIC_IPR*34 `IAAMO the priority of interrupt number 4*34+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x8C "IPR35,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x8C 24.--31. 1. "PRI_N3,For register NVIC_IPR*35 `IAAMO the priority of interrupt number 4*35+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x8C 16.--23. 1. "PRI_N2,For register NVIC_IPR*35 `IAAMO the priority of interrupt number 4*35+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x8C 8.--15. 1. "PRI_N1,For register NVIC_IPR*35 `IAAMO the priority of interrupt number 4*35+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "PRI_N0,For register NVIC_IPR*35 `IAAMO the priority of interrupt number 4*35+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x90 "IPR36,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x90 24.--31. 1. "PRI_N3,For register NVIC_IPR*36 `IAAMO the priority of interrupt number 4*36+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x90 16.--23. 1. "PRI_N2,For register NVIC_IPR*36 `IAAMO the priority of interrupt number 4*36+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x90 8.--15. 1. "PRI_N1,For register NVIC_IPR*36 `IAAMO the priority of interrupt number 4*36+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x90 0.--7. 1. "PRI_N0,For register NVIC_IPR*36 `IAAMO the priority of interrupt number 4*36+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x94 "IPR37,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x94 24.--31. 1. "PRI_N3,For register NVIC_IPR*37 `IAAMO the priority of interrupt number 4*37+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x94 16.--23. 1. "PRI_N2,For register NVIC_IPR*37 `IAAMO the priority of interrupt number 4*37+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x94 8.--15. 1. "PRI_N1,For register NVIC_IPR*37 `IAAMO the priority of interrupt number 4*37+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x94 0.--7. 1. "PRI_N0,For register NVIC_IPR*37 `IAAMO the priority of interrupt number 4*37+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x98 "IPR38,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x98 24.--31. 1. "PRI_N3,For register NVIC_IPR*38 `IAAMO the priority of interrupt number 4*38+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x98 16.--23. 1. "PRI_N2,For register NVIC_IPR*38 `IAAMO the priority of interrupt number 4*38+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x98 8.--15. 1. "PRI_N1,For register NVIC_IPR*38 `IAAMO the priority of interrupt number 4*38+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x98 0.--7. 1. "PRI_N0,For register NVIC_IPR*38 `IAAMO the priority of interrupt number 4*38+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x9C "IPR39,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x9C 24.--31. 1. "PRI_N3,For register NVIC_IPR*39 `IAAMO the priority of interrupt number 4*39+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x9C 16.--23. 1. "PRI_N2,For register NVIC_IPR*39 `IAAMO the priority of interrupt number 4*39+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x9C 8.--15. 1. "PRI_N1,For register NVIC_IPR*39 `IAAMO the priority of interrupt number 4*39+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "PRI_N0,For register NVIC_IPR*39 `IAAMO the priority of interrupt number 4*39+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xA0 "IPR40,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xA0 24.--31. 1. "PRI_N3,For register NVIC_IPR*40 `IAAMO the priority of interrupt number 4*40+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA0 16.--23. 1. "PRI_N2,For register NVIC_IPR*40 `IAAMO the priority of interrupt number 4*40+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA0 8.--15. 1. "PRI_N1,For register NVIC_IPR*40 `IAAMO the priority of interrupt number 4*40+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA0 0.--7. 1. "PRI_N0,For register NVIC_IPR*40 `IAAMO the priority of interrupt number 4*40+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xA4 "IPR41,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xA4 24.--31. 1. "PRI_N3,For register NVIC_IPR*41 `IAAMO the priority of interrupt number 4*41+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA4 16.--23. 1. "PRI_N2,For register NVIC_IPR*41 `IAAMO the priority of interrupt number 4*41+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA4 8.--15. 1. "PRI_N1,For register NVIC_IPR*41 `IAAMO the priority of interrupt number 4*41+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "PRI_N0,For register NVIC_IPR*41 `IAAMO the priority of interrupt number 4*41+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xA8 "IPR42,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xA8 24.--31. 1. "PRI_N3,For register NVIC_IPR*42 `IAAMO the priority of interrupt number 4*42+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA8 16.--23. 1. "PRI_N2,For register NVIC_IPR*42 `IAAMO the priority of interrupt number 4*42+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA8 8.--15. 1. "PRI_N1,For register NVIC_IPR*42 `IAAMO the priority of interrupt number 4*42+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "PRI_N0,For register NVIC_IPR*42 `IAAMO the priority of interrupt number 4*42+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xAC "IPR43,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xAC 24.--31. 1. "PRI_N3,For register NVIC_IPR*43 `IAAMO the priority of interrupt number 4*43+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xAC 16.--23. 1. "PRI_N2,For register NVIC_IPR*43 `IAAMO the priority of interrupt number 4*43+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xAC 8.--15. 1. "PRI_N1,For register NVIC_IPR*43 `IAAMO the priority of interrupt number 4*43+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "PRI_N0,For register NVIC_IPR*43 `IAAMO the priority of interrupt number 4*43+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xB0 "IPR44,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xB0 24.--31. 1. "PRI_N3,For register NVIC_IPR*44 `IAAMO the priority of interrupt number 4*44+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB0 16.--23. 1. "PRI_N2,For register NVIC_IPR*44 `IAAMO the priority of interrupt number 4*44+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB0 8.--15. 1. "PRI_N1,For register NVIC_IPR*44 `IAAMO the priority of interrupt number 4*44+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "PRI_N0,For register NVIC_IPR*44 `IAAMO the priority of interrupt number 4*44+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xB4 "IPR45,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xB4 24.--31. 1. "PRI_N3,For register NVIC_IPR*45 `IAAMO the priority of interrupt number 4*45+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB4 16.--23. 1. "PRI_N2,For register NVIC_IPR*45 `IAAMO the priority of interrupt number 4*45+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB4 8.--15. 1. "PRI_N1,For register NVIC_IPR*45 `IAAMO the priority of interrupt number 4*45+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB4 0.--7. 1. "PRI_N0,For register NVIC_IPR*45 `IAAMO the priority of interrupt number 4*45+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xB8 "IPR46,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xB8 24.--31. 1. "PRI_N3,For register NVIC_IPR*46 `IAAMO the priority of interrupt number 4*46+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "PRI_N2,For register NVIC_IPR*46 `IAAMO the priority of interrupt number 4*46+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB8 8.--15. 1. "PRI_N1,For register NVIC_IPR*46 `IAAMO the priority of interrupt number 4*46+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xB8 0.--7. 1. "PRI_N0,For register NVIC_IPR*46 `IAAMO the priority of interrupt number 4*46+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xBC "IPR47,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xBC 24.--31. 1. "PRI_N3,For register NVIC_IPR*47 `IAAMO the priority of interrupt number 4*47+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xBC 16.--23. 1. "PRI_N2,For register NVIC_IPR*47 `IAAMO the priority of interrupt number 4*47+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xBC 8.--15. 1. "PRI_N1,For register NVIC_IPR*47 `IAAMO the priority of interrupt number 4*47+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xBC 0.--7. 1. "PRI_N0,For register NVIC_IPR*47 `IAAMO the priority of interrupt number 4*47+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xC0 "IPR48,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xC0 24.--31. 1. "PRI_N3,For register NVIC_IPR*48 `IAAMO the priority of interrupt number 4*48+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "PRI_N2,For register NVIC_IPR*48 `IAAMO the priority of interrupt number 4*48+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC0 8.--15. 1. "PRI_N1,For register NVIC_IPR*48 `IAAMO the priority of interrupt number 4*48+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC0 0.--7. 1. "PRI_N0,For register NVIC_IPR*48 `IAAMO the priority of interrupt number 4*48+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xC4 "IPR49,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xC4 24.--31. 1. "PRI_N3,For register NVIC_IPR*49 `IAAMO the priority of interrupt number 4*49+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC4 16.--23. 1. "PRI_N2,For register NVIC_IPR*49 `IAAMO the priority of interrupt number 4*49+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC4 8.--15. 1. "PRI_N1,For register NVIC_IPR*49 `IAAMO the priority of interrupt number 4*49+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC4 0.--7. 1. "PRI_N0,For register NVIC_IPR*49 `IAAMO the priority of interrupt number 4*49+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xC8 "IPR50,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xC8 24.--31. 1. "PRI_N3,For register NVIC_IPR*50 `IAAMO the priority of interrupt number 4*50+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "PRI_N2,For register NVIC_IPR*50 `IAAMO the priority of interrupt number 4*50+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC8 8.--15. 1. "PRI_N1,For register NVIC_IPR*50 `IAAMO the priority of interrupt number 4*50+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xC8 0.--7. 1. "PRI_N0,For register NVIC_IPR*50 `IAAMO the priority of interrupt number 4*50+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xCC "IPR51,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xCC 24.--31. 1. "PRI_N3,For register NVIC_IPR*51 `IAAMO the priority of interrupt number 4*51+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xCC 16.--23. 1. "PRI_N2,For register NVIC_IPR*51 `IAAMO the priority of interrupt number 4*51+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xCC 8.--15. 1. "PRI_N1,For register NVIC_IPR*51 `IAAMO the priority of interrupt number 4*51+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xCC 0.--7. 1. "PRI_N0,For register NVIC_IPR*51 `IAAMO the priority of interrupt number 4*51+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xD0 "IPR52,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xD0 24.--31. 1. "PRI_N3,For register NVIC_IPR*52 `IAAMO the priority of interrupt number 4*52+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "PRI_N2,For register NVIC_IPR*52 `IAAMO the priority of interrupt number 4*52+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD0 8.--15. 1. "PRI_N1,For register NVIC_IPR*52 `IAAMO the priority of interrupt number 4*52+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD0 0.--7. 1. "PRI_N0,For register NVIC_IPR*52 `IAAMO the priority of interrupt number 4*52+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xD4 "IPR53,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xD4 24.--31. 1. "PRI_N3,For register NVIC_IPR*53 `IAAMO the priority of interrupt number 4*53+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD4 16.--23. 1. "PRI_N2,For register NVIC_IPR*53 `IAAMO the priority of interrupt number 4*53+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD4 8.--15. 1. "PRI_N1,For register NVIC_IPR*53 `IAAMO the priority of interrupt number 4*53+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD4 0.--7. 1. "PRI_N0,For register NVIC_IPR*53 `IAAMO the priority of interrupt number 4*53+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xD8 "IPR54,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xD8 24.--31. 1. "PRI_N3,For register NVIC_IPR*54 `IAAMO the priority of interrupt number 4*54+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD8 16.--23. 1. "PRI_N2,For register NVIC_IPR*54 `IAAMO the priority of interrupt number 4*54+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD8 8.--15. 1. "PRI_N1,For register NVIC_IPR*54 `IAAMO the priority of interrupt number 4*54+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xD8 0.--7. 1. "PRI_N0,For register NVIC_IPR*54 `IAAMO the priority of interrupt number 4*54+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xDC "IPR55,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xDC 24.--31. 1. "PRI_N3,For register NVIC_IPR*55 `IAAMO the priority of interrupt number 4*55+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xDC 16.--23. 1. "PRI_N2,For register NVIC_IPR*55 `IAAMO the priority of interrupt number 4*55+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xDC 8.--15. 1. "PRI_N1,For register NVIC_IPR*55 `IAAMO the priority of interrupt number 4*55+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xDC 0.--7. 1. "PRI_N0,For register NVIC_IPR*55 `IAAMO the priority of interrupt number 4*55+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xE0 "IPR56,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xE0 24.--31. 1. "PRI_N3,For register NVIC_IPR*56 `IAAMO the priority of interrupt number 4*56+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE0 16.--23. 1. "PRI_N2,For register NVIC_IPR*56 `IAAMO the priority of interrupt number 4*56+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE0 8.--15. 1. "PRI_N1,For register NVIC_IPR*56 `IAAMO the priority of interrupt number 4*56+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE0 0.--7. 1. "PRI_N0,For register NVIC_IPR*56 `IAAMO the priority of interrupt number 4*56+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xE4 "IPR57,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xE4 24.--31. 1. "PRI_N3,For register NVIC_IPR*57 `IAAMO the priority of interrupt number 4*57+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE4 16.--23. 1. "PRI_N2,For register NVIC_IPR*57 `IAAMO the priority of interrupt number 4*57+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE4 8.--15. 1. "PRI_N1,For register NVIC_IPR*57 `IAAMO the priority of interrupt number 4*57+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE4 0.--7. 1. "PRI_N0,For register NVIC_IPR*57 `IAAMO the priority of interrupt number 4*57+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xE8 "IPR58,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xE8 24.--31. 1. "PRI_N3,For register NVIC_IPR*58 `IAAMO the priority of interrupt number 4*58+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE8 16.--23. 1. "PRI_N2,For register NVIC_IPR*58 `IAAMO the priority of interrupt number 4*58+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE8 8.--15. 1. "PRI_N1,For register NVIC_IPR*58 `IAAMO the priority of interrupt number 4*58+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xE8 0.--7. 1. "PRI_N0,For register NVIC_IPR*58 `IAAMO the priority of interrupt number 4*58+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xEC "IPR59,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xEC 24.--31. 1. "PRI_N3,For register NVIC_IPR*59 `IAAMO the priority of interrupt number 4*59+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xEC 16.--23. 1. "PRI_N2,For register NVIC_IPR*59 `IAAMO the priority of interrupt number 4*59+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xEC 8.--15. 1. "PRI_N1,For register NVIC_IPR*59 `IAAMO the priority of interrupt number 4*59+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xEC 0.--7. 1. "PRI_N0,For register NVIC_IPR*59 `IAAMO the priority of interrupt number 4*59+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xF0 "IPR60,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xF0 24.--31. 1. "PRI_N3,For register NVIC_IPR*60 `IAAMO the priority of interrupt number 4*60+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF0 16.--23. 1. "PRI_N2,For register NVIC_IPR*60 `IAAMO the priority of interrupt number 4*60+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF0 8.--15. 1. "PRI_N1,For register NVIC_IPR*60 `IAAMO the priority of interrupt number 4*60+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF0 0.--7. 1. "PRI_N0,For register NVIC_IPR*60 `IAAMO the priority of interrupt number 4*60+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xF4 "IPR61,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xF4 24.--31. 1. "PRI_N3,For register NVIC_IPR*61 `IAAMO the priority of interrupt number 4*61+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF4 16.--23. 1. "PRI_N2,For register NVIC_IPR*61 `IAAMO the priority of interrupt number 4*61+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF4 8.--15. 1. "PRI_N1,For register NVIC_IPR*61 `IAAMO the priority of interrupt number 4*61+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF4 0.--7. 1. "PRI_N0,For register NVIC_IPR*61 `IAAMO the priority of interrupt number 4*61+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xF8 "IPR62,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xF8 24.--31. 1. "PRI_N3,For register NVIC_IPR*62 `IAAMO the priority of interrupt number 4*62+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF8 16.--23. 1. "PRI_N2,For register NVIC_IPR*62 `IAAMO the priority of interrupt number 4*62+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF8 8.--15. 1. "PRI_N1,For register NVIC_IPR*62 `IAAMO the priority of interrupt number 4*62+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xF8 0.--7. 1. "PRI_N0,For register NVIC_IPR*62 `IAAMO the priority of interrupt number 4*62+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0xFC "IPR63,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0xFC 24.--31. 1. "PRI_N3,For register NVIC_IPR*63 `IAAMO the priority of interrupt number 4*63+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xFC 16.--23. 1. "PRI_N2,For register NVIC_IPR*63 `IAAMO the priority of interrupt number 4*63+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xFC 8.--15. 1. "PRI_N1,For register NVIC_IPR*63 `IAAMO the priority of interrupt number 4*63+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0xFC 0.--7. 1. "PRI_N0,For register NVIC_IPR*63 `IAAMO the priority of interrupt number 4*63+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x100 "IPR64,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x100 24.--31. 1. "PRI_N3,For register NVIC_IPR*64 `IAAMO the priority of interrupt number 4*64+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x100 16.--23. 1. "PRI_N2,For register NVIC_IPR*64 `IAAMO the priority of interrupt number 4*64+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x100 8.--15. 1. "PRI_N1,For register NVIC_IPR*64 `IAAMO the priority of interrupt number 4*64+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x100 0.--7. 1. "PRI_N0,For register NVIC_IPR*64 `IAAMO the priority of interrupt number 4*64+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x104 "IPR65,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x104 24.--31. 1. "PRI_N3,For register NVIC_IPR*65 `IAAMO the priority of interrupt number 4*65+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x104 16.--23. 1. "PRI_N2,For register NVIC_IPR*65 `IAAMO the priority of interrupt number 4*65+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x104 8.--15. 1. "PRI_N1,For register NVIC_IPR*65 `IAAMO the priority of interrupt number 4*65+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x104 0.--7. 1. "PRI_N0,For register NVIC_IPR*65 `IAAMO the priority of interrupt number 4*65+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x108 "IPR66,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x108 24.--31. 1. "PRI_N3,For register NVIC_IPR*66 `IAAMO the priority of interrupt number 4*66+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x108 16.--23. 1. "PRI_N2,For register NVIC_IPR*66 `IAAMO the priority of interrupt number 4*66+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x108 8.--15. 1. "PRI_N1,For register NVIC_IPR*66 `IAAMO the priority of interrupt number 4*66+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x108 0.--7. 1. "PRI_N0,For register NVIC_IPR*66 `IAAMO the priority of interrupt number 4*66+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x10C "IPR67,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x10C 24.--31. 1. "PRI_N3,For register NVIC_IPR*67 `IAAMO the priority of interrupt number 4*67+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x10C 16.--23. 1. "PRI_N2,For register NVIC_IPR*67 `IAAMO the priority of interrupt number 4*67+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x10C 8.--15. 1. "PRI_N1,For register NVIC_IPR*67 `IAAMO the priority of interrupt number 4*67+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x10C 0.--7. 1. "PRI_N0,For register NVIC_IPR*67 `IAAMO the priority of interrupt number 4*67+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x110 "IPR68,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x110 24.--31. 1. "PRI_N3,For register NVIC_IPR*68 `IAAMO the priority of interrupt number 4*68+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x110 16.--23. 1. "PRI_N2,For register NVIC_IPR*68 `IAAMO the priority of interrupt number 4*68+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x110 8.--15. 1. "PRI_N1,For register NVIC_IPR*68 `IAAMO the priority of interrupt number 4*68+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x110 0.--7. 1. "PRI_N0,For register NVIC_IPR*68 `IAAMO the priority of interrupt number 4*68+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x114 "IPR69,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x114 24.--31. 1. "PRI_N3,For register NVIC_IPR*69 `IAAMO the priority of interrupt number 4*69+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x114 16.--23. 1. "PRI_N2,For register NVIC_IPR*69 `IAAMO the priority of interrupt number 4*69+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x114 8.--15. 1. "PRI_N1,For register NVIC_IPR*69 `IAAMO the priority of interrupt number 4*69+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x114 0.--7. 1. "PRI_N0,For register NVIC_IPR*69 `IAAMO the priority of interrupt number 4*69+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x118 "IPR70,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x118 24.--31. 1. "PRI_N3,For register NVIC_IPR*70 `IAAMO the priority of interrupt number 4*70+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x118 16.--23. 1. "PRI_N2,For register NVIC_IPR*70 `IAAMO the priority of interrupt number 4*70+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x118 8.--15. 1. "PRI_N1,For register NVIC_IPR*70 `IAAMO the priority of interrupt number 4*70+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x118 0.--7. 1. "PRI_N0,For register NVIC_IPR*70 `IAAMO the priority of interrupt number 4*70+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x11C "IPR71,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x11C 24.--31. 1. "PRI_N3,For register NVIC_IPR*71 `IAAMO the priority of interrupt number 4*71+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x11C 16.--23. 1. "PRI_N2,For register NVIC_IPR*71 `IAAMO the priority of interrupt number 4*71+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x11C 8.--15. 1. "PRI_N1,For register NVIC_IPR*71 `IAAMO the priority of interrupt number 4*71+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x11C 0.--7. 1. "PRI_N0,For register NVIC_IPR*71 `IAAMO the priority of interrupt number 4*71+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x120 "IPR72,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x120 24.--31. 1. "PRI_N3,For register NVIC_IPR*72 `IAAMO the priority of interrupt number 4*72+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x120 16.--23. 1. "PRI_N2,For register NVIC_IPR*72 `IAAMO the priority of interrupt number 4*72+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x120 8.--15. 1. "PRI_N1,For register NVIC_IPR*72 `IAAMO the priority of interrupt number 4*72+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x120 0.--7. 1. "PRI_N0,For register NVIC_IPR*72 `IAAMO the priority of interrupt number 4*72+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x124 "IPR73,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x124 24.--31. 1. "PRI_N3,For register NVIC_IPR*73 `IAAMO the priority of interrupt number 4*73+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x124 16.--23. 1. "PRI_N2,For register NVIC_IPR*73 `IAAMO the priority of interrupt number 4*73+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x124 8.--15. 1. "PRI_N1,For register NVIC_IPR*73 `IAAMO the priority of interrupt number 4*73+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x124 0.--7. 1. "PRI_N0,For register NVIC_IPR*73 `IAAMO the priority of interrupt number 4*73+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x128 "IPR74,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x128 24.--31. 1. "PRI_N3,For register NVIC_IPR*74 `IAAMO the priority of interrupt number 4*74+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x128 16.--23. 1. "PRI_N2,For register NVIC_IPR*74 `IAAMO the priority of interrupt number 4*74+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x128 8.--15. 1. "PRI_N1,For register NVIC_IPR*74 `IAAMO the priority of interrupt number 4*74+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x128 0.--7. 1. "PRI_N0,For register NVIC_IPR*74 `IAAMO the priority of interrupt number 4*74+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x12C "IPR75,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x12C 24.--31. 1. "PRI_N3,For register NVIC_IPR*75 `IAAMO the priority of interrupt number 4*75+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x12C 16.--23. 1. "PRI_N2,For register NVIC_IPR*75 `IAAMO the priority of interrupt number 4*75+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x12C 8.--15. 1. "PRI_N1,For register NVIC_IPR*75 `IAAMO the priority of interrupt number 4*75+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x12C 0.--7. 1. "PRI_N0,For register NVIC_IPR*75 `IAAMO the priority of interrupt number 4*75+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x130 "IPR76,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x130 24.--31. 1. "PRI_N3,For register NVIC_IPR*76 `IAAMO the priority of interrupt number 4*76+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x130 16.--23. 1. "PRI_N2,For register NVIC_IPR*76 `IAAMO the priority of interrupt number 4*76+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x130 8.--15. 1. "PRI_N1,For register NVIC_IPR*76 `IAAMO the priority of interrupt number 4*76+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x130 0.--7. 1. "PRI_N0,For register NVIC_IPR*76 `IAAMO the priority of interrupt number 4*76+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x134 "IPR77,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x134 24.--31. 1. "PRI_N3,For register NVIC_IPR*77 `IAAMO the priority of interrupt number 4*77+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x134 16.--23. 1. "PRI_N2,For register NVIC_IPR*77 `IAAMO the priority of interrupt number 4*77+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x134 8.--15. 1. "PRI_N1,For register NVIC_IPR*77 `IAAMO the priority of interrupt number 4*77+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x134 0.--7. 1. "PRI_N0,For register NVIC_IPR*77 `IAAMO the priority of interrupt number 4*77+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x138 "IPR78,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x138 24.--31. 1. "PRI_N3,For register NVIC_IPR*78 `IAAMO the priority of interrupt number 4*78+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x138 16.--23. 1. "PRI_N2,For register NVIC_IPR*78 `IAAMO the priority of interrupt number 4*78+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x138 8.--15. 1. "PRI_N1,For register NVIC_IPR*78 `IAAMO the priority of interrupt number 4*78+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x138 0.--7. 1. "PRI_N0,For register NVIC_IPR*78 `IAAMO the priority of interrupt number 4*78+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x13C "IPR79,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x13C 24.--31. 1. "PRI_N3,For register NVIC_IPR*79 `IAAMO the priority of interrupt number 4*79+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x13C 16.--23. 1. "PRI_N2,For register NVIC_IPR*79 `IAAMO the priority of interrupt number 4*79+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x13C 8.--15. 1. "PRI_N1,For register NVIC_IPR*79 `IAAMO the priority of interrupt number 4*79+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x13C 0.--7. 1. "PRI_N0,For register NVIC_IPR*79 `IAAMO the priority of interrupt number 4*79+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x140 "IPR80,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x140 24.--31. 1. "PRI_N3,For register NVIC_IPR*80 `IAAMO the priority of interrupt number 4*80+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x140 16.--23. 1. "PRI_N2,For register NVIC_IPR*80 `IAAMO the priority of interrupt number 4*80+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x140 8.--15. 1. "PRI_N1,For register NVIC_IPR*80 `IAAMO the priority of interrupt number 4*80+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x140 0.--7. 1. "PRI_N0,For register NVIC_IPR*80 `IAAMO the priority of interrupt number 4*80+0 or is RES0 if the PE does not implement this interrupt"
|
|
line.long 0x144 "IPR81,Sets or reads interrupt priorities"
|
|
hexmask.long.byte 0x144 24.--31. 1. "PRI_N3,For register NVIC_IPR*81 `IAAMO the priority of interrupt number 4*81+3 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x144 16.--23. 1. "PRI_N2,For register NVIC_IPR*81 `IAAMO the priority of interrupt number 4*81+2 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x144 8.--15. 1. "PRI_N1,For register NVIC_IPR*81 `IAAMO the priority of interrupt number 4*81+1 or is RES0 if the PE does not implement this interrupt"
|
|
hexmask.long.byte 0x144 0.--7. 1. "PRI_N0,For register NVIC_IPR*81 `IAAMO the priority of interrupt number 4*81+0 or is RES0 if the PE does not implement this interrupt"
|
|
tree.end
|
|
tree "CPU_SAU"
|
|
base ad:0xE000EDD0
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "CTRL,Allows enabling of the Security Attribution Unit"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "ALLNS,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the SAU" "0,1"
|
|
line.long 0x04 "TYPE,Indicates the number of regions implemented by the Security Attribution Unit"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "SREGION,The number of implemented SAU regions"
|
|
line.long 0x08 "RNR,Selects the region currently accessed by SAU_RBAR and SAU_RLAR"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x08 0.--7. 1. "REGION,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
line.long 0x0C "RBAR,Provides indirect read and write access to the base address of the currently selected SAU region"
|
|
hexmask.long 0x0C 5.--31. 1. "BADDR,Holds bits [31:5] of the base address for the selected SAU region"
|
|
rbitfld.long 0x0C 0.--4. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "RLAR,Provides indirect read and write access to the limit address of the currently selected SAU region"
|
|
hexmask.long 0x10 5.--31. 1. "LADDR,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
rbitfld.long 0x10 2.--4. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. "NSC,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "0,1"
|
|
bitfld.long 0x10 0. "ENABLE,SAU region enable" "0,1"
|
|
line.long 0x14 "SFSR,Provides information about any security related faults"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 7. "LSERR,Sticky flag indicating that an error occurred during lazy state activation or deactivation" "0,1"
|
|
bitfld.long 0x14 6. "SFARVALID,This bit is set when the SFAR register contains a valid value" "0,1"
|
|
bitfld.long 0x14 5. "LSPERR,Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state" "0,1"
|
|
bitfld.long 0x14 4. "INVTRAN,Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory" "0,1"
|
|
bitfld.long 0x14 3. "AUVIOL,Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure" "0,1"
|
|
bitfld.long 0x14 2. "INVER,This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state" "0,1"
|
|
bitfld.long 0x14 1. "INVIS,This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation" "0,1"
|
|
bitfld.long 0x14 0. "INVEP,This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state" "0,1"
|
|
line.long 0x18 "SFAR,Shows the address of the memory location that caused a Security violation"
|
|
tree.end
|
|
tree "CPU_SIG"
|
|
base ad:0xE000EF00
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "STIR,Provides a mechanism for software to generate an interrupt"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Indicates the interrupt to be pended"
|
|
tree.end
|
|
tree "CPU_SYSTICK"
|
|
base ad:0xE000E010
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "CSR,Controls the SysTick timer and provides status data `FTSSS"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "COUNTFLAG,Indicates whether the counter has counted to zero since the last read of this register" "0,1"
|
|
hexmask.long.word 0x00 3.--15. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 2. "CLKSOURCE,Indicates the SysTick clock source" "0,1"
|
|
bitfld.long 0x00 1. "TICKINT,Indicates whether counting to 0 causes the status of the SysTick exception to change to pending" "0,1"
|
|
bitfld.long 0x00 0. "ENABLE,Indicates the enabled status of the SysTick counter" "0,1"
|
|
line.long 0x04 "RVR,Provides access SysTick timer counter reload value `FTSSS"
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. "RELOAD,The value to load into the SYST_CVR `FTSSS when the counter reaches 0"
|
|
line.long 0x08 "CVR,Reads or clears the SysTick timer current counter value `FTSSS"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. "CURRENT,Writing any value clears the SysTick timer counter `FTSSS to zero"
|
|
line.long 0x0C "CALIB,Reads the SysTick timer calibration value and parameters `FTSSS"
|
|
bitfld.long 0x0C 31. "NOREF,Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented" "0,1"
|
|
bitfld.long 0x0C 30. "SKEW,Indicates whether the 10ms calibration value is exact" "0,1"
|
|
bitfld.long 0x0C 24.--29. "RESERVED24,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. "TENMS,Optionally holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
tree.end
|
|
tree.end
|
|
tree "CRYPTO"
|
|
base ad:0x58024000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DMACH0CTL,Channel 0 ControlThis register is used for channel enabling and priority selection"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "PRIO,Channel priority0: Low1: HighIf both channels have the same priority access of the channels to the external port is arbitrated using the round robin scheme" "Low,HighIf.."
|
|
newline
|
|
bitfld.long 0x00 0. "EN,Channel enable0: Disabled1: EnableNote: Disabling an active channel interrupts the DMA operation" "Disabled,Enable"
|
|
line.long 0x04 "DMACH0EXTADDR,Channel 0 External Address"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMACH0LEN,Channel 0 DMA Length"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DMALEN,Channel DMA length in bytesDuring configuration this register contains the DMA transfer length in bytes"
|
|
rgroup.long 0x18++0x0F
|
|
line.long 0x00 "DMASTAT,DMAC StatusThis register provides the actual state of each DMA channel"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED18,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 17. "PORT_ERR,Reflects possible transfer errors on the AHB port" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--16. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_ACT,A value of 1 indicates that channel 1 is active (DMA transfer on-going)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CH0_ACT,A value of 1 indicates that channel 0 is active (DMA transfer on-going)" "0,1"
|
|
line.long 0x04 "DMASWRESET,DMAC Software ResetSoftware reset is used to reset the DMAC to stop all transfers and clears the port error status register"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "SWRES,Software reset enable0 : Disabled1 : Enabled (self-cleared to 0)Completion of the software reset must be checked through the DMASTAT" "Disabled,Enabled (self-cleared.."
|
|
line.long 0x08 "DMACH1CTL,Channel 1 ControlThis register is used for channel enabling and priority selection"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 1. "PRIO,Channel priority0: Low1: HighIf both channels have the same priority access of the channels to the external port is arbitrated using the round robin scheme" "Low,HighIf.."
|
|
newline
|
|
bitfld.long 0x08 0. "EN,Channel enable0: Disabled1: EnableNote: Disabling an active channel interrupts the DMA operation" "Disabled,Enable"
|
|
line.long 0x0C "DMACH1EXTADDR,Channel 1 External Address"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DMACH1LEN,Channel 1 DMA Length"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DMALEN,Channel DMA length in bytes.During configuration this register contains the DMA transfer length in bytes"
|
|
group.long 0x78++0x07
|
|
line.long 0x00 "DMABUSCFG,DMAC Master Run-time ParametersThis register defines all the run-time parameters for the AHB master interface port"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "AHB_MST1_BURST_SIZE,Maximum burst size that can be performed on the AHB bus" "?,?,4 bytes,8 bytes ,16 bytes ,32 bytes ,64 bytes ,?,?,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x00 11. "AHB_MST1_IDLE_EN,Idle insertion between consecutive burst transfers on AHB" "Do not insert idle transfers.,Idle transfer insertion enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "AHB_MST1_INCR_EN,Burst length type of AHB transfer" "Unspecified length burst transfers,Fixed length bursts or single transfers"
|
|
newline
|
|
bitfld.long 0x00 9. "AHB_MST1_LOCK_EN,Locked transform on AHB" "Transfers are not locked,Transfers are locked"
|
|
newline
|
|
bitfld.long 0x00 8. "AHB_MST1_BIGEND,Endianess for the AHB master" "Little Endian,Big Endian"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "DMAPORTERR,DMAC Port Error Raw StatusThis register provides the actual status of individual port errors"
|
|
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 12. "PORT1_AHB_ERROR,A value of 1 indicates that the EIP-101 has detected an AHB bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 9. "PORT1_CHANNEL,Indicates which channel has serviced last (channel 0 or channel 1) by AHB master port" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 0.--8. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "DMAHWVER,DMAC VersionThis register contains an indication (or signature) of the EIP type of this DMAC. as well as the hardware version/patch numbers"
|
|
bitfld.long 0x00 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "HW_MAJOR_VERSION,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "HW_MINOR_VERSION,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HW_PATCH_LEVEL,Patch levelStarts at 0 at first delivery of this version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "EIP_NUMBER_COMPL,Bit-by-bit complement of the EIP_NUMBER field bits"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EIP_NUMBER,Binary encoding of the EIP-number of this DMA controller (209)"
|
|
group.long 0x400++0x0F
|
|
line.long 0x00 "KEYWRITEAREA,Key Store Write AreaThis register defines where the keys should be written in the key store RAM"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "RAM_AREA7,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA7 is not selected to be written.1: RAM_AREA7 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA7 is not selected to be written,RAM_AREA7 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 6. "RAM_AREA6,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA6 is not selected to be written.1: RAM_AREA6 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA6 is not selected to be written,RAM_AREA6 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 5. "RAM_AREA5,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA5 is not selected to be written.1: RAM_AREA5 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA5 is not selected to be written,RAM_AREA5 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 4. "RAM_AREA4,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA4 is not selected to be written.1: RAM_AREA4 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA4 is not selected to be written,RAM_AREA4 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 3. "RAM_AREA3,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA3 is not selected to be written.1: RAM_AREA3 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA3 is not selected to be written,RAM_AREA3 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 2. "RAM_AREA2,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA2 is not selected to be written.1: RAM_AREA2 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA2 is not selected to be written,RAM_AREA2 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 1. "RAM_AREA1,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA1 is not selected to be written.1: RAM_AREA1 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA1 is not selected to be written,RAM_AREA1 is selected to be written.Writing to.."
|
|
newline
|
|
bitfld.long 0x00 0. "RAM_AREA0,Each RAM_AREAx represents an area of 128 bits.Select the key store RAM area(s) where the key(s) needs to be written0: RAM_AREA0 is not selected to be written.1: RAM_AREA0 is selected to be written.Writing to multiple RAM locations is possible.." "RAM_AREA0 is not selected to be written,RAM_AREA0 is selected to be written.Writing to.."
|
|
line.long 0x04 "KEYWRITTENAREA,Key Store Written AreaThis register shows which areas of the key store RAM contain valid written keys.When a new key needs to be written to the key store. on a location that is already occupied by a valid key. this key area must be.."
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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bitfld.long 0x04 7. "RAM_AREA_WRITTEN7,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 6. "RAM_AREA_WRITTEN6,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 5. "RAM_AREA_WRITTEN5,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 4. "RAM_AREA_WRITTEN4,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 3. "RAM_AREA_WRITTEN3,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 2. "RAM_AREA_WRITTEN2,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 1. "RAM_AREA_WRITTEN1,On read this bit returns the key area written status.This bit can be reset by writing a" "This RAM area is not written with valid key..,This RAM area is written with valid key.."
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bitfld.long 0x04 0. "RAM_AREA_WRITTEN0,On read this bit returns the key area written status.This bit can be reset by writing a" "0,1"
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line.long 0x08 "KEYSIZE,Key Store SizeThis register defines the size of the keys that are written with DMA"
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hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x08 0.--1. "SIZE,Key size:00: ReservedWhen writing this to this register the KEY_STORE_WRITTEN_AREA register is reset" "?,128 bits,192 bits,256 bits"
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line.long 0x0C "KEYREADAREA,Key Store Read AreaThis register selects the key store RAM area from where the key needs to be read that will be used for an AES operation"
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bitfld.long 0x0C 31. "BUSY,Key store operation busy status flag (read only):0: Operation is complete.1: Operation is not completed and the key store is busy" "Operation is complete,Operation is not completed and the key store is.."
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hexmask.long 0x0C 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 0.--3. "RAM_AREA,Selects the area of the key store RAM from where the key needs to be read that will be writen to the AES engineRAM_AREA:RAM areas RAM_AREA0 RAM_AREA2 RAM_AREA4 and RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes.Only RAM.." "RAM Area 0,RAM Area 1,RAM Area 2,RAM Area 3,RAM Area 4,RAM Area 5,RAM Area 6,RAM Area 7,No RAM,?,?,?,?,?,?,?"
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wgroup.long 0x500++0x03
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line.long 0x00 "AESKEY2,AES_KEY2_0 / AES_GHASH_H_IN_0Second Key / GHASH Key (internal. but clearable)The following registers are not accessible through the host for reading and writing"
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wgroup.long 0x510++0x03
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line.long 0x00 "AESKEY3,AES_KEY3_0 / AES_KEY2_4Third Key / Second Key (internal. but clearable)The following registers are not accessible through the host for reading and writing"
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group.long 0x540++0x03
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line.long 0x00 "AESIV,AES initialization vector registersThese registers are used to provide and read the IV from the AES engine"
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group.long 0x550++0x0F
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line.long 0x00 "AESCTL,AES ControlAES input/output buffer control and mode registerThis register specifies the AES mode of operation for the EIP-120t.Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0"
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rbitfld.long 0x00 31. "CONTEXT_READY,If 1 this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context" "0,1"
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bitfld.long 0x00 30. "SAVED_CONTEXT_RDY,If 1 this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the host to retrieve" "0,1"
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bitfld.long 0x00 29. "SAVE_CONTEXT,This bit indicates that an authentication TAG or result IV needs to be stored as a result context.Typically this bit must be set for authentication modes returning a TAG (CBC-MAC GCM and CCM) or for basic encryption modes that require.." "0,1"
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bitfld.long 0x00 28. "GCM_CCM_CONTINUE,Continue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase.Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation to continue processing from the.." "0,1"
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bitfld.long 0x00 27. "GET_DIGEST,Interrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation.Set this write-only signal to '1b' to interrupt GCM or CCM processing at the next full block (128 bits) boundary" "0,1"
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bitfld.long 0x00 26. "GCM_CCM_CONTINUE_AAD,Continue processing of an interrupted AES-GCM or AES-CCM operation in the AAD phase.Set this write-only signal to '1b' together with the regular mode bit settings for a GCM or CCM operation to continue processing from the next full.." "0,1"
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bitfld.long 0x00 25. "XCBC_MAC,Set to '1' to select AES-XCBC MAC mode.The direction bit must be set to '1' for this mode.Selecting this mode requires writing the length register" "0,1"
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bitfld.long 0x00 22.--24. "CCM_M,Defines M which indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one).Note: The EIP-120t always returns a 128-bit authentication field of which the M.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--21. "CCM_L,Defines L which indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 18. "CCM,If set to 1 AES-CCM is selectedAES-CCM is a combined mode using AES for authentication and encryption.Note: Selecting AES-CCM mode requires writing of the AAD length register after all other registers.Note: The CTR mode bit in this register must.." "0,1"
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bitfld.long 0x00 16.--17. "GCM,Set these bits to 11 to select AES-GCM mode.AES-GCM is a combined mode using the Galois field multiplier GF(2 to the power of 128) for authentication and AES-CTR mode for encryption.Note: The CTR mode bit in this register must also be set to 1 to.." "No GCM mode,Reserved do not select,?..."
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bitfld.long 0x00 15. "CBC_MAC,Set to 1 to select AES-CBC MAC mode.The direction bit must be set to 1 for this mode.Selecting this mode requires writing the length register after all other registers" "0,1"
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bitfld.long 0x00 9.--14. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7.--8. "CTR_WIDTH,Specifies the counter width for AES-CTR mode00 = 32-bit counter01 = 64-bit counter10 = 96-bit counter11 = 128-bit counter" "32-bit counter,64-bit counter,?..."
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bitfld.long 0x00 6. "CTR,If set to 1 AES counter mode (CTR) is selected.Note: This bit must also be set for GCM and CCM when encryption/decryption is required" "0,1"
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bitfld.long 0x00 5. "CBC,If set to 1 cipher-block-chaining (CBC) mode is selected" "0,1"
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bitfld.long 0x00 3.--4. "KEY_SIZE,This read-only field specifies the key size.The key size is automatically configured when a new key is loaded through the key store module.00 = N/A - Reserved01 =" "N/A - Reserved,128-bit,?..."
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bitfld.long 0x00 2. "DIR,If set to 1 an encrypt operation is performed.If set to 0 a decrypt operation is performed.This bit must be written with a 1 when CBC-MAC is selected" "0,1"
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bitfld.long 0x00 1. "INPUT_READY,If 1 this status bit indicates that the 16-byte AES input buffer is empty" "0,1"
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bitfld.long 0x00 0. "OUTPUT_READY,If 1 this status bit indicates that an AES output block is available to be retrieved by the host.Writing 0 clears the bit to 0 and indicates that output data is read by the host" "0,1"
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line.long 0x04 "AESDATALEN0,AES Crypto Length 0 (LSW)These registers are used to write the Length values to the EIP-120t"
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line.long 0x08 "AESDATALEN1,AES Crypto Length 1 (MSW)These registers are used to write the Length values to the EIP-120t"
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bitfld.long 0x08 29.--31. "RESERVED29,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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hexmask.long 0x08 0.--28. 1. "C_LENGTH,C_LENGTH[60:32]Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes"
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line.long 0x0C "AESAUTHLEN,AES Authentication Length"
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repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
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rgroup.long ($2+0x560)++0x03
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line.long 0x00 "AESDATAOUT$1,Data Input/Output"
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repeat.end
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repeat 2. (list 0. 1. )(list 0x00 0x04 )
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wgroup.long ($2+0x560)++0x03
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line.long 0x00 "AESDATAIN$1,AES Data Input_Output 0The data registers are typically accessed through the DMA and not with host writes and/or reads"
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repeat.end
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wgroup.long 0x568++0x0B
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line.long 0x00 "AESDATAIN2,AES Data Input_Output 2The data registers are typically accessed via DMA and not with host writes and/or reads"
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line.long 0x04 "AESDATAIN3,AES Data Input_Output 3The data registers are typically accessed via DMA and not with host writes and/or reads"
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line.long 0x08 "AESTAGOUT,AES Tag Out 0The tag registers can be accessed via DMA or directly with host reads.These registers buffer the TAG from the EIP-120t"
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group.long 0x5D4++0x0B
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line.long 0x00 "AESCCMALNWRD,This register needs to be read and stored when an AES-CCM operation is interrupted"
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line.long 0x04 "AESBLKCNT0,This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations"
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line.long 0x08 "AESBLKCNT1,This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations"
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hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
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hexmask.long 0x08 0.--24. 1. "AES_BLK_CNT_56_32,[56:32] of Internal block counter for AES GCM and CCM operations.These bits read the block count value that represents the number of blocks to go"
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repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
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wgroup.long ($2+0x604)++0x03
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line.long 0x00 "HASHDATAIN$1,HASH Data Input 1The data input registers should be used to provide input data to the hash module through the slave interface"
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repeat.end
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repeat 15. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
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wgroup.long ($2+0x644)++0x03
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line.long 0x00 "HASHDATAIN$1,HASH Data Input 17The data input registers should be used to provide input data to the hash module through the slave interface"
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repeat.end
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group.long 0x680++0x0F
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line.long 0x00 "HASHIOBUFCTRL,HASH Input_Output Buffer ControlThis register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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bitfld.long 0x00 7. "PAD_DMA_MESSAGE,Note: This bit must only be used when data is supplied through the DMA" "0,1"
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bitfld.long 0x00 6. "GET_DIGEST,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 5. "PAD_MESSAGE,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 3.--4. "RESERVED3,Write 0s and ignore on reading" "0,1,2,3"
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bitfld.long 0x00 2. "RFD_IN,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 1. "DATA_IN_AV,Note: The bit description below is only applicable when data is sent through the slave interface" "0,1"
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bitfld.long 0x00 0. "OUTPUT_FULL,Indicates that the output buffer registers (HASHDIGESTn) are available for reading by the host.When this bit reads 0 the output buffer registers are released; the hash engine is allowed to write new data to it" "0,1"
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line.long 0x04 "HASHMODE,HASH Mode"
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hexmask.long 0x04 7.--31. 1. "RESERVED7,Write 0s and ignore on reading"
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bitfld.long 0x04 6. "SHA384_MODE,The host must write this bit with 1 prior to processing a SHA 384 session" "0,1"
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bitfld.long 0x04 5. "SHA512_MODE,The host must write this bit with 1 prior to processing a SHA 512 session" "0,1"
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bitfld.long 0x04 4. "SHA224_MODE,The host must write this bit with 1 prior to processing a SHA 224 session" "0,1"
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bitfld.long 0x04 3. "SHA256_MODE,The host must write this bit with 1 prior to processing a SHA 256 session" "0,1"
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bitfld.long 0x04 1.--2. "RESERVED1,Write 0s and ignore on reading" "0,1,2,3"
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bitfld.long 0x04 0. "NEW_HASH,When set to 1 it indicates that the hash engine must start processing a new hash session" "0,1"
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line.long 0x08 "HASHINLENL,HASH Input Length LSB"
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line.long 0x0C "HASHINLENH,HASH Input Length MSB"
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group.long 0x6C0++0x47
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line.long 0x00 "HASHDIGESTA,HASH Digest AThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x04 "HASHDIGESTB,HASH Digest BThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x08 "HASHDIGESTC,HASH Digest CThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x0C "HASHDIGESTD,HASH Digest DThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x10 "HASHDIGESTE,HASH Digest EThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x14 "HASHDIGESTF,HASH Digest FThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x18 "HASHDIGESTG,HASH Digest GThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x1C "HASHDIGESTH,HASH Digest HThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x20 "HASHDIGESTI,HASH Digest IThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x24 "HASHDIGESTJ,HASH Digest JThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x28 "HASHDIGESTK,HASH Digest KThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x2C "HASHDIGESTL,HASH Digest LThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x30 "HASHDIGESTM,HASH Digest MThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x34 "HASHDIGESTN,HASH Digest NThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x38 "HASHDIGESTO,HASH Digest 0The hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x3C "HASHDIGESTP,HASH Digest PThe hash digest registers consist of eight 32-bit registers. named HASH_DIGEST_A to HASH_DIGEST_H"
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line.long 0x40 "ALGSEL,Algorithm SelectThis algorithm selection register configures the internal destination of the DMA controller"
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bitfld.long 0x40 31. "TAG,If this bit is cleared to 0 the DMA operation involves only data.If this bit is set the DMA operation includes a TAG (Authentication Result / Digest).For SHA-256 operation a DMA must be set up for both input data and TAG" "0,1"
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hexmask.long 0x40 4.--30. 1. "RESERVED4,Software should not rely on the value of a reserved"
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bitfld.long 0x40 3. "HASH_SHA_512,If set to one selects the hash engine in 512B mode as destination for the DMAThe maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out.." "0,1"
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bitfld.long 0x40 2. "HASH_SHA_256,If set to one selects the hash engine in 256B mode as destination for the DMAThe maximum transfer size to DMA engine is set to 64 bytes for reading and 32 bytes for writing (the latter is only applicable if the hash result is written out.." "0,1"
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bitfld.long 0x40 1. "AES,If set to one selects the AES engine as source/destination for the DMAThe read and write maximum transfer size to the DMA engine is set to 16 bytes" "0,1"
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bitfld.long 0x40 0. "KEY_STORE,If set to one selects the Key Store as destination for the DMAThe maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16 24 and 32 bytes are allowed)" "0,1"
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line.long 0x44 "DMAPROTCTL,DMA Protection ControlMaster PROT privileged access enableThis register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys.."
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hexmask.long 0x44 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x44 0. "PROT_EN,Select AHB transfer protection control for DMA transfers using the key store area as destination.0 : transfers use 'USER' type access.1 : transfers use 'PRIVILEGED' type access" "transfers use 'USER' type access,transfers use 'PRIVILEGED' type access"
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group.long 0x740++0x03
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line.long 0x00 "SWRESET,Software Reset"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x00 0. "SW_RESET,If this bit is set to 1 the following modules are reset: - Master control internal state is reset" "0,1"
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group.long 0x780++0x13
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line.long 0x00 "IRQTYPE,Control Interrupt Configuration"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x00 0. "LEVEL,If this bit is 0 the interrupt output is a pulse.If this bit is set to 1 the interrupt is a level interrupt that must be cleared by writing the interrupt clear register.This bit is applicable for both interrupt output signals" "0,1"
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line.long 0x04 "IRQEN,Control Interrupt Enable"
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hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 1. "DMA_IN_DONE,If this bit is set to 0 the DMA input done interrupt disabledIf this bit is set to 1 the DMA input done interrupt enabled." "0,1"
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bitfld.long 0x04 0. "RESULT_AVAIL,If this bit is set to 0 the Result Available interrupt is disabledIf this bit is set to 1 the Result Available interrupt is enabled." "0,1"
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line.long 0x08 "IRQCLR,Control Interrupt Clear"
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bitfld.long 0x08 31. "DMA_BUS_ERR,If 1 is written to this bit the DMA bus error status is cleared.Writing 0 has no effect" "0,1"
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bitfld.long 0x08 30. "KEY_ST_WR_ERR,If 1 is written to this bit the key store write error status is cleared.Writing 0 has no effect" "0,1"
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bitfld.long 0x08 29. "KEY_ST_RD_ERR,If 1 is written to this bit the key store read error status is cleared.Writing 0 has no effect" "0,1"
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hexmask.long 0x08 2.--28. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x08 1. "DMA_IN_DONE,If 1 is written to this bit the DMA in done interrupt status is cleared.Writing 0 has no effect.Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE)." "0,1"
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bitfld.long 0x08 0. "RESULT_AVAIL,If 1 is written to this bit the result available interrupt status is cleared.Writing 0 has no effect.Note that clearing an interrupt makes sense only if the interrupt output is programmed as level (refer to IRQTYPE)." "0,1"
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line.long 0x0C "IRQSET,Control Interrupt Set"
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hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 1. "DMA_IN_DONE,If 1 is written to this bit the DMA data in done interrupt is set.Writing 0 has no effect.If the interrupt configuration register is programmed to pulse clearing the DMA data in done interrupt is not needed" "0,1"
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|
|
bitfld.long 0x0C 0. "RESULT_AVAIL,If 1 is written to this bit the result available interrupt is setWriting 0 has no effect.If the interrupt configuration register is programmed to pulse clearing the result available interrupt is not needed" "0,1"
|
|
line.long 0x10 "IRQSTAT,Control Interrupt Status"
|
|
bitfld.long 0x10 31. "DMA_BUS_ERR,This bit is set when a DMA bus error is detected during a DMA operation" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "KEY_ST_WR_ERR,This bit is set when a write error is detected during the DMA write operation to the key store memory" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "KEY_ST_RD_ERR,This bit is set when a read error is detected during the read of a key from the key store while copying it to the AES core" "0,1"
|
|
newline
|
|
hexmask.long 0x10 2.--28. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 1. "DMA_IN_DONE,This read only bit returns the actual DMA data in done interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "RESULT_AVAIL,This read only bit returns the actual result available interrupt status" "0,1"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "HWVER,Hardware Version"
|
|
bitfld.long 0x00 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "HW_MAJOR_VER,Major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "HW_MINOR_VER,Minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "HW_PATCH_LVL,Patch levelStarts at 0 at first delivery of this version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "VER_NUM_COMPL,These bits simply contain the complement of bits [7:0] (0x87) used by a driver to ascertain that the EIP-120t register is indeed"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VER_NUM,These bits encode the EIP number for the EIP-120t this field contains the value 120 (decimal) or 0x78"
|
|
tree.end
|
|
tree "EVENT"
|
|
base ad:0x40083000
|
|
rgroup.long 0x00++0xAB
|
|
line.long 0x00 "CPUIRQSEL0,Output Selection for CPU Interrupt 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x04 "CPUIRQSEL1,Output Selection for CPU Interrupt 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x08 "CPUIRQSEL2,Output Selection for CPU Interrupt 2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "CPUIRQSEL3,Output Selection for CPU Interrupt 3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "CPUIRQSEL4,Output Selection for CPU Interrupt 4"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "CPUIRQSEL5,Output Selection for CPU Interrupt 5"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "CPUIRQSEL6,Output Selection for CPU Interrupt 6"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "CPUIRQSEL7,Output Selection for CPU Interrupt 7"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "CPUIRQSEL8,Output Selection for CPU Interrupt 8"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "CPUIRQSEL9,Output Selection for CPU Interrupt 9"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x28 "CPUIRQSEL10,Output Selection for CPU Interrupt 10"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x2C "CPUIRQSEL11,Output Selection for CPU Interrupt 11"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x30 "CPUIRQSEL12,Output Selection for CPU Interrupt 12"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x34 "CPUIRQSEL13,Output Selection for CPU Interrupt 13"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x38 "CPUIRQSEL14,Output Selection for CPU Interrupt 14"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x3C "CPUIRQSEL15,Output Selection for CPU Interrupt 15"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x40 "CPUIRQSEL16,Output Selection for CPU Interrupt 16"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x44 "CPUIRQSEL17,Output Selection for CPU Interrupt 17"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x48 "CPUIRQSEL18,Output Selection for CPU Interrupt 18"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x4C "CPUIRQSEL19,Output Selection for CPU Interrupt 19"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x50 "CPUIRQSEL20,Output Selection for CPU Interrupt 20"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x54 "CPUIRQSEL21,Output Selection for CPU Interrupt 21"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x58 "CPUIRQSEL22,Output Selection for CPU Interrupt 22"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x5C "CPUIRQSEL23,Output Selection for CPU Interrupt 23"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x60 "CPUIRQSEL24,Output Selection for CPU Interrupt 24"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x64 "CPUIRQSEL25,Output Selection for CPU Interrupt 25"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x68 "CPUIRQSEL26,Output Selection for CPU Interrupt 26"
|
|
hexmask.long.tbyte 0x68 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x68 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x6C "CPUIRQSEL27,Output Selection for CPU Interrupt 27"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x70 "CPUIRQSEL28,Output Selection for CPU Interrupt 28"
|
|
hexmask.long.tbyte 0x70 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x70 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x74 "CPUIRQSEL29,Output Selection for CPU Interrupt 29"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x78 "CPUIRQSEL30,Output Selection for CPU Interrupt 30"
|
|
hexmask.long.tbyte 0x78 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x78 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x7C "CPUIRQSEL31,Output Selection for CPU Interrupt 31"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x80 "CPUIRQSEL32,Output Selection for CPU Interrupt 32"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x84 "CPUIRQSEL33,Output Selection for CPU Interrupt 33"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x88 "CPUIRQSEL34,Output Selection for CPU Interrupt 34"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x8C "CPUIRQSEL35,Output Selection for CPU Interrupt 35"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x90 "CPUIRQSEL36,Output Selection for CPU Interrupt 36"
|
|
hexmask.long.tbyte 0x90 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x90 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x94 "CPUIRQSEL37,Output Selection for CPU Interrupt 37"
|
|
hexmask.long.tbyte 0x94 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x94 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x98 "CPUIRQSEL38,Output Selection for CPU Interrupt 38"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x9C "CPUIRQSEL39,Output Selection for CPU Interrupt 39"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA0 "CPUIRQSEL40,Output Selection for CPU Interrupt 40"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA4 "CPUIRQSEL41,Output Selection for CPU Interrupt 41"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA8 "CPUIRQSEL42,Output Selection for CPU Interrupt 42"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--7. 1. "EV,Read only selection value"
|
|
rgroup.long 0x100++0x27
|
|
line.long 0x00 "RFCSEL0,Output Selection for RFC Event 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x04 "RFCSEL1,Output Selection for RFC Event 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x08 "RFCSEL2,Output Selection for RFC Event 2"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "RFCSEL3,Output Selection for RFC Event 3"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "RFCSEL4,Output Selection for RFC Event 4"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "RFCSEL5,Output Selection for RFC Event 5"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "RFCSEL6,Output Selection for RFC Event 6"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "RFCSEL7,Output Selection for RFC Event 7"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "RFCSEL8,Output Selection for RFC Event 8"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "RFCSEL9,Output Selection for RFC Event 9"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "GPT0ACAPTSEL,Output Selection for GPT0 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT0BCAPTSEL,Output Selection for GPT0 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "GPT1ACAPTSEL,Output Selection for GPT1 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT1BCAPTSEL,Output Selection for GPT1 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "GPT2ACAPTSEL,Output Selection for GPT2 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x04 "GPT2BCAPTSEL,Output Selection for GPT2 1"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
rgroup.long 0x500++0x107
|
|
line.long 0x00 "UDMACH0SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "UDMACH0BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x08 "UDMACH1SSEL,Output Selection for DMA Channel 1 SREQ"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x0C "UDMACH1BSEL,Output Selection for DMA Channel 1 REQ"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x10 "UDMACH2SSEL,Output Selection for DMA Channel 2 SREQ"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x14 "UDMACH2BSEL,Output Selection for DMA Channel 2 REQ"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x18 "UDMACH3SSEL,Output Selection for DMA Channel 3 SREQ"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x1C "UDMACH3BSEL,Output Selection for DMA Channel 3 REQ"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x20 "UDMACH4SSEL,Output Selection for DMA Channel 4 SREQ"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x24 "UDMACH4BSEL,Output Selection for DMA Channel 4 REQ"
|
|
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x28 "UDMACH5SSEL,Output Selection for DMA Channel 5 SREQ"
|
|
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x2C "UDMACH5BSEL,Output Selection for DMA Channel 5 REQ"
|
|
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x30 "UDMACH6SSEL,Output Selection for DMA Channel 6 SREQ"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x34 "UDMACH6BSEL,Output Selection for DMA Channel 6 REQ"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x38 "UDMACH7SSEL,Output Selection for DMA Channel 7 SREQ"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x3C "UDMACH7BSEL,Output Selection for DMA Channel 7 REQ"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x40 "UDMACH8SSEL,Output Selection for DMA Channel 8 SREQSingle request is ignored for this channel"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x44 "UDMACH8BSEL,Output Selection for DMA Channel 8 REQ"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x48 "UDMACH9SSEL,Output Selection for DMA Channel 9 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x4C "UDMACH9BSEL,Output Selection for DMA Channel 9 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x50 "UDMACH10SSEL,Output Selection for DMA Channel 10 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x54 "UDMACH10BSEL,Output Selection for DMA Channel 10 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x58 "UDMACH11SSEL,Output Selection for DMA Channel 11 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x5C "UDMACH11BSEL,Output Selection for DMA Channel 11 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x60 "UDMACH12SSEL,Output Selection for DMA Channel 12 SREQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x64 "UDMACH12BSEL,Output Selection for DMA Channel 12 REQDMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x68 "UDMACH13SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x6C "UDMACH13BSEL,Output Selection for DMA Channel 13 REQ"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x70 "UDMACH14SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x74 "UDMACH14BSEL,Output Selection for DMA Channel 14 REQ"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x78 "UDMACH15SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x7C "UDMACH15BSEL,Output Selection for DMA Channel 15 REQ"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x80 "UDMACH16SSEL,Output Selection for DMA Channel 16 SREQ"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x84 "UDMACH16BSEL,Output Selection for DMA Channel 16 REQ"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x88 "UDMACH17SSEL,Output Selection for DMA Channel 17 SREQ"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x8C "UDMACH17BSEL,Output Selection for DMA Channel 17 REQ"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x90 "UDMACH18SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x94 "UDMACH18BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0x98 "UDMACH19SSEL,Output Selection for DMA Channel 19 SREQ"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x9C "UDMACH19BSEL,Output Selection for DMA Channel 19 REQ"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA0 "UDMACH20SSEL,Output Selection for DMA Channel 20 SREQ"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA4 "UDMACH20BSEL,Output Selection for DMA Channel 20 REQ"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xA8 "UDMACH21SSEL,Output Selection for DMA Channel 21 SREQ"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xAC "UDMACH21BSEL,Output Selection for DMA Channel 21 REQ"
|
|
hexmask.long.tbyte 0xAC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xAC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB0 "UDMACH22SSEL,Output Selection for DMA Channel 22 SREQ"
|
|
hexmask.long.tbyte 0xB0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB4 "UDMACH22BSEL,Output Selection for DMA Channel 22 REQ"
|
|
hexmask.long.tbyte 0xB4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xB8 "UDMACH23SSEL,Output Selection for DMA Channel 23 SREQ"
|
|
hexmask.long.tbyte 0xB8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xB8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xBC "UDMACH23BSEL,Output Selection for DMA Channel 23 REQ"
|
|
hexmask.long.tbyte 0xBC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC0 "UDMACH24SSEL,Output Selection for DMA Channel 24 SREQ"
|
|
hexmask.long.tbyte 0xC0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC4 "UDMACH24BSEL,Output Selection for DMA Channel 24 REQ"
|
|
hexmask.long.tbyte 0xC4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xC8 "UDMACH25SSEL,Output Selection for DMA Channel 25 SREQ"
|
|
hexmask.long.tbyte 0xC8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xC8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xCC "UDMACH25BSEL,Output Selection for DMA Channel 25 REQ"
|
|
hexmask.long.tbyte 0xCC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD0 "UDMACH26SSEL,Output Selection for DMA Channel 26 SREQ"
|
|
hexmask.long.tbyte 0xD0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xD0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD4 "UDMACH26BSEL,Output Selection for DMA Channel 26 REQ"
|
|
hexmask.long.tbyte 0xD4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xD4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xD8 "UDMACH27SSEL,Software should not rely on the value of a reserved"
|
|
line.long 0xDC "UDMACH27BSEL,Software should not rely on the value of a reserved"
|
|
line.long 0xE0 "UDMACH28SSEL,Output Selection for DMA Channel 28 SREQ"
|
|
hexmask.long.tbyte 0xE0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xE4 "UDMACH28BSEL,Output Selection for DMA Channel 28 REQ"
|
|
hexmask.long.tbyte 0xE4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xE8 "UDMACH29SSEL,Output Selection for DMA Channel 29 SREQ"
|
|
hexmask.long.tbyte 0xE8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xE8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xEC "UDMACH29BSEL,Output Selection for DMA Channel 29 REQ"
|
|
hexmask.long.tbyte 0xEC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xEC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF0 "UDMACH30SSEL,Output Selection for DMA Channel 30 SREQ"
|
|
hexmask.long.tbyte 0xF0 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF0 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF4 "UDMACH30BSEL,Output Selection for DMA Channel 30 REQ"
|
|
hexmask.long.tbyte 0xF4 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF4 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xF8 "UDMACH31SSEL,Output Selection for DMA Channel 31 SREQ"
|
|
hexmask.long.tbyte 0xF8 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xF8 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0xFC "UDMACH31BSEL,Output Selection for DMA Channel 31 REQ"
|
|
hexmask.long.tbyte 0xFC 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0xFC 0.--7. 1. "EV,Read only selection value"
|
|
line.long 0x100 "GPT3ACAPTSEL,Output Selection for GPT3 0"
|
|
hexmask.long.tbyte 0x100 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x100 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
line.long 0x104 "GPT3BCAPTSEL,Output Selection for GPT3 1"
|
|
hexmask.long.tbyte 0x104 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x104 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "AUXSEL0,Output Selection for AUX Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "CM3NMISEL0,Output Selection for NMI Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read only selection value"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "I2SSTMPSEL0,Output Selection for I2S Subscriber 0"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "FRZSEL0,Output Selection for FRZ SubscriberThe halted debug signal is passed to peripherals such as the General Purpose Timer. Sensor Controller with Digital and Analog Peripherals (AUX). Radio. and RTC"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EV,Read/write selection valueWriting any other value than values defined by a ENUM may result in undefined behavior."
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "SWEV,Set or Clear Software Events"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 24. "SWEV3,Writing '1' to this bit when the value is '0' triggers the Software 3 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "SWEV2,Writing '1' to this bit when the value is '0' triggers the Software 2 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "SWEV1,Writing '1' to this bit when the value is '0' triggers the Software 1 event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "SWEV0,Writing '1' to this bit when the value is '0' triggers the Software 0 event" "0,1"
|
|
tree.end
|
|
tree "FCFG1"
|
|
base ad:0x50000800
|
|
repeat 4. (list 0. 4. 140. 324. )(list 0x00 0x04 0x150 0x324 )
|
|
rgroup.long ($2+0x00)++0x03
|
|
line.long 0x00 "RESERVED_$1,Software should not rely on the value of a reserved"
|
|
repeat.end
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "MISC_CONF_1,Misc configurations"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DEVICE_MINOR_REV,HW minor revision number (a value of 0xFF shall be treated equally to 0x00).Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer.Value may change without warning"
|
|
line.long 0x04 "MISC_CONF_2,Internal"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "HPOSC_COMP_P3,Internal"
|
|
repeat 5. (list 5. 4. 3. 2. 1. )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
rgroup.long ($2+0xB0)++0x03
|
|
line.long 0x00 "HPOSC_MEAS_$1,Internal"
|
|
hexmask.long.word 0x00 16.--31. 1. "HPOSC_D5,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "HPOSC_T5,Internal"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "HPOSC_DT5,Internal"
|
|
repeat.end
|
|
rgroup.long 0xC4++0x1B
|
|
line.long 0x00 "CONFIG_CC26_FE,Internal"
|
|
bitfld.long 0x00 28.--31. "IFAMP_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "LNA_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19.--23. "IFAMP_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--18. "CTL_PA0_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13. "PATRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RSSITRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSSI_OFFSET,Internal"
|
|
line.long 0x04 "CONFIG_CC13_FE,Internal"
|
|
bitfld.long 0x04 28.--31. "IFAMP_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 24.--27. "LNA_IB,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 19.--23. "IFAMP_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 14.--18. "CTL_PA0_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 13. "PATRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12. "RSSITRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8.--11. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "RSSI_OFFSET,Internal"
|
|
line.long 0x08 "CONFIG_RF_COMMON,Internal"
|
|
bitfld.long 0x08 31. "DISABLE_CORNER_CAP,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25.--30. "SLDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 22.--24. "RESERVED,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 21. "PA20DBMTRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16.--20. "CTL_PA_20DBM_TRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x08 9.--15. 1. "RFLDO_TRIM_OUTPUT,Internal"
|
|
newline
|
|
bitfld.long 0x08 6.--8. "QUANTCTLTHRES,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 0.--5. "DACTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CONFIG_SYNTH_DIV2_CC26_2G4,Internal"
|
|
bitfld.long 0x0C 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x0C 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x0C 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "CONFIG_SYNTH_DIV2_CC13_2G4,Internal"
|
|
bitfld.long 0x10 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x10 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x10 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x10 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "CONFIG_SYNTH_DIV2_CC26_1G,Internal"
|
|
bitfld.long 0x14 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x14 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x14 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x14 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "CONFIG_SYNTH_DIV2_CC13_1G,Internal"
|
|
bitfld.long 0x18 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x18 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x18 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x18 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xE0)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV4_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 4. (list 5. 10. 15. 30. )(list 0x00 0x0C 0x18 0x1C )
|
|
rgroup.long ($2+0xE8)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xEC)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV6_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (list 26. 13. )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xF8)++0x03
|
|
line.long 0x00 "CONFIG_SYNTH_DIV12_CC$1,Internal"
|
|
bitfld.long 0x00 28.--31. "MIN_ALLOWED_RTRIM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "RFC_MDM_DEMIQMC0,Internal"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "LDOVCO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5. "RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RESERVED,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "IOCONF,IO Configuration"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "GPIO_CNT,Number of available DIOs."
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "USER_ID,User Identification.Reading this register and the FCFG1:ICEPICK_DEVICE_ID register is the only supported way of identifying a device.The value of this register will be written to AON_PMCTL:JTAGUSERCODE by boot FW while in safezone"
|
|
bitfld.long 0x00 28.--31. "PG_REV,Field used to distinguish revisions of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "VER,Version number.0x0: Bits [25:12] of this register has the stated meaning.Any other setting indicate a different encoding of these bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 25. "PA," "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED24,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CC13," "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "SEQUENCE,Sequence.Used to differentiate between marketing/orderable product where other fields of this register are the same (temp range flash size voltage range etc)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PKG,Package type.0x0: 4x4mm QFN (RHB) package0x1: 5x5mm QFN (RSM) package0x2: 7x7mm QFN (RGZ) package0x3: Wafer sale package (naked" "4x4mm QFN (RHB) package,5x5mm QFN (RSM) package,7x7mm QFN (RGZ) package,Wafer sale package (naked die),WCSP (YFV),7x7mm QFN package with Wettable FlanksOther..,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PROTOCOL,Protocols supported.0x1: BLE" "?,BLE,RF4CE,?,Zigbee/6lowpan,?,?,?,ProprietaryMore than..,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
rgroup.long 0x2B0++0x0B
|
|
line.long 0x00 "FLASH_OTP_DATA3,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FLASH_SIZE,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "ANA2_TRIM,Internal"
|
|
bitfld.long 0x04 31. "RCOSCHFCTRIMFRACT_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 26.--30. "RCOSCHFCTRIMFRACT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 25. "RESERVED0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 23.--24. "SET_RCOSC_HF_FINE_RESISTOR,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 22. "ATESTLF_UDIGLDO_IBIAS_TRIM,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 15.--21. 1. "NANOAMP_RES_TRIM,Internal"
|
|
newline
|
|
bitfld.long 0x04 12.--14. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 11. "DITHER_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 8.--10. "DCDC_IPEAK,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 6.--7. "DEAD_TIME_TRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 3.--5. "DCDC_LOW_EN_SEL,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "DCDC_HIGH_EN_SEL,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "LDO_TRIM,Internal"
|
|
bitfld.long 0x08 29.--31. "RESERVED4,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 24.--28. "VDDR_TRIM_SLEEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 19.--23. "RESERVED3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 16.--18. "GLDO_CURSRC,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 13.--15. "RESERVED2,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 11.--12. "ITRIM_DIGLDO_LOAD,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 8.--10. "ITRIM_UDIGLDO,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x08 3.--7. "RESERVED1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 0.--2. "VTRIM_DELTA,Internal" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2E8++0x0F
|
|
line.long 0x00 "MAC_BLE_0,MAC BLE Address 0"
|
|
line.long 0x04 "MAC_BLE_1,MAC BLE Address 1"
|
|
line.long 0x08 "MAC_15_4_0,MAC IEEE 802.15.4 Address 0"
|
|
line.long 0x0C "MAC_15_4_1,MAC IEEE 802.15.4 Address 1"
|
|
rgroup.long 0x30C++0x07
|
|
line.long 0x00 "MISC_TRIM,Miscellaneous Trim Parameters"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--16. "TRIM_RECHARGE_COMP_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TRIM_RECHARGE_COMP_REFLEVEL,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEMPVSLOPE,Signed byte value representing the TEMP slope with battery voltage in degrees C / V with four fractional bits"
|
|
line.long 0x04 "RCOSC_HF_TEMPCOMP,Internal"
|
|
hexmask.long.byte 0x04 24.--31. 1. "FINE_RESISTOR,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. "CTRIM,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "CTRIMFRACT_QUAD,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "CTRIMFRACT_SLOPE,Internal"
|
|
rgroup.long 0x318++0x0B
|
|
line.long 0x00 "ICEPICK_DEVICE_ID,IcePick Device IdentificationReading this register and the FCFG1:USER_ID register is the only supported way of identifying a device"
|
|
bitfld.long 0x00 28.--31. "PG_REV,Field used to distinguish revisions of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 12.--27. 1. "WAFER_ID,Field used to identify silicon die"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "MANUFACTURER_ID,Manufacturer"
|
|
line.long 0x04 "FCFG1_REVISION,Factory Configuration (FCFG1) Revision"
|
|
line.long 0x08 "MISC_OTP_DATA,Misc OTP Data"
|
|
bitfld.long 0x08 28.--31. "RCOSC_HF_ITUNE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x08 20.--27. 1. "RCOSC_HF_CRIM,Internal"
|
|
newline
|
|
bitfld.long 0x08 15.--19. "PER_M,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 12.--14. "PER_E,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
rgroup.long 0x34C++0x07
|
|
line.long 0x00 "CONFIG_IF_ADC,Internal"
|
|
bitfld.long 0x00 28.--31. "FF2ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FF3ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "INT3ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "FF1ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "AAFCAP,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--13. "INT2ADJ,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "IFDIGLDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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|
|
bitfld.long 0x00 0.--4. "IFANALDO_TRIM_OUTPUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CONFIG_OSC_TOP,Internal"
|
|
bitfld.long 0x04 30.--31. "RESERVED,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 26.--29. "XOSC_HF_ROW_Q12,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x04 10.--25. 1. "XOSC_HF_COLUMN_Q12,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 2.--9. 1. "RCOSCLF_CTUNE_TRIM,Internal"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RCOSCLF_RTUNE_TRIM,Internal" "0,1,2,3"
|
|
rgroup.long 0x35C++0x07
|
|
line.long 0x00 "SOC_ADC_ABS_GAIN,AUX_ADC Gain in Absolute Reference Mode"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "SOC_ADC_ABS_GAIN_TEMP1,SOC_ADC gain in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REL_GAIN,AUX_ADC Gain in Relative Reference Mode"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "SOC_ADC_REL_GAIN_TEMP1,SOC_ADC gain in relative reference mode at temperature 1 (30C)"
|
|
rgroup.long 0x368++0x17
|
|
line.long 0x00 "SOC_ADC_OFFSET_INT,AUX_ADC Temperature Offsets in Absolute Reference Mode"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "SOC_ADC_REL_OFFSET_TEMP1,SOC_ADC offset in relative reference mode at temperature 1 (30C)"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SOC_ADC_ABS_OFFSET_TEMP1,SOC_ADC offset in absolute reference mode at temperature 1 (30C)"
|
|
line.long 0x04 "SOC_ADC_REF_TRIM_AND_OFFSET_EXT,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--5. "SOC_ADC_REF_VOLTAGE_TRIM_TEMP1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "AMPCOMP_TH1,Internal"
|
|
hexmask.long.byte 0x08 24.--31. 1. "RESERVED1,Internal"
|
|
newline
|
|
bitfld.long 0x08 18.--23. "HPMRAMP3_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 16.--17. "RESERVED0,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 10.--15. "HPMRAMP3_HTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
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|
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bitfld.long 0x08 6.--9. "IBIASCAP_LPTOHP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x08 0.--5. "HPMRAMP1_TH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "AMPCOMP_TH2,Internal"
|
|
bitfld.long 0x0C 26.--31. "LPMUPDATE_LTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 24.--25. "RESERVED3,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 18.--23. "LPMUPDATE_HTM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x0C 16.--17. "RESERVED2,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 10.--15. "ADC_COMP_AMPTH_LPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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newline
|
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bitfld.long 0x0C 8.--9. "RESERVED1,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 2.--7. "ADC_COMP_AMPTH_HPM,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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newline
|
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bitfld.long 0x0C 0.--1. "RESERVED0,Internal" "0,1,2,3"
|
|
line.long 0x10 "AMPCOMP_CTRL1,Internal"
|
|
bitfld.long 0x10 31. "RESERVED1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "AMPCOMP_REQ_MODE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24.--29. "RESERVED0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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newline
|
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bitfld.long 0x10 20.--23. "IBIAS_OFFSET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. "IBIAS_INIT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "LPM_IBIAS_WAIT_CNT_FINAL,Internal"
|
|
newline
|
|
bitfld.long 0x10 4.--7. "CAP_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 0.--3. "IBIASCAP_HPTOLP_OL_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "ANABYPASS_VALUE2,Internal"
|
|
hexmask.long.tbyte 0x14 14.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.word 0x14 0.--13. 1. "XOSC_HF_IBIASTHERM,Internal"
|
|
rgroup.long 0x388++0x0B
|
|
line.long 0x00 "VOLT_TRIM,Internal"
|
|
bitfld.long 0x00 29.--31. "RESERVED3,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24.--28. "VDDR_TRIM_HH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 21.--23. "RESERVED2,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "VDDR_TRIM_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "VDDR_TRIM_SLEEP_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED0,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "TRIMBOD_H,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "OSC_CONF,OSC Configuration"
|
|
bitfld.long 0x04 30.--31. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 29. "ADC_SH_VBUF_EN,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x04 28. "ADC_SH_MODE_EN,Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x04 27. "ATESTLF_RCOSCLF_IBIAS_TRIM,Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM" "0,1"
|
|
newline
|
|
bitfld.long 0x04 25.--26. "XOSCLF_REGULATOR_TRIM,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 21.--24. "XOSCLF_CMIRRWR_RATIO,Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 19.--20. "XOSC_HF_FAST_START,Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 18. "XOSC_OPTION," "0,1"
|
|
newline
|
|
bitfld.long 0x04 17. "HPOSC_OPTION,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. "HPOSC_BIAS_HOLD_MODE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 12.--15. "HPOSC_CURRMIRR_RATIO,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. "HPOSC_BIAS_RES_SET,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 7. "HPOSC_FILTER_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 5.--6. "HPOSC_BIAS_RECHARGE_DELAY,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 3.--4. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 1.--2. "HPOSC_SERIES_CAP,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0. "HPOSC_DIV3_BYPASS,Internal" "0,1"
|
|
line.long 0x08 "FREQ_OFFSET,Internal"
|
|
hexmask.long.word 0x08 16.--31. 1. "HPOSC_COMP_P0,Internal"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. "HPOSC_COMP_P1,Internal"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "HPOSC_COMP_P2,Internal"
|
|
rgroup.long 0x398++0x03
|
|
line.long 0x00 "MISC_OTP_DATA_1,Internal"
|
|
bitfld.long 0x00 29.--31. "RESERVED,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "PEAK_DET_ITRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "HP_BUF_ITRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "LP_BUF_ITRIM,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DBLR_LOOP_FILTER_RESET_VOLTAGE,Internal" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "HPM_IBIAS_WAIT_CNT,Internal"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "LPM_IBIAS_WAIT_CNT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "IDAC_STEP,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x3D0++0x0F
|
|
line.long 0x00 "SHDW_DIE_ID_0,Shadow of DIE_ID_0 register in eFuse"
|
|
line.long 0x04 "SHDW_DIE_ID_1,Shadow of DIE_ID_1 register in eFuse"
|
|
line.long 0x08 "SHDW_DIE_ID_2,Shadow of DIE_ID_2 register in eFuse"
|
|
line.long 0x0C "SHDW_DIE_ID_3,Shadow of DIE_ID_3 register in eFuse"
|
|
rgroup.long 0x3F8++0x07
|
|
line.long 0x00 "SHDW_SCAN_MCU3_SEC,Internal"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SECURITY,Internal"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 11.--22. 1. "ULL_MCU_RAM_0_REP,Internal"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "ULL_MCU_RAM_1_REP_1,Internal"
|
|
line.long 0x04 "SHDW_SCAN_DATA1_CRC,Internal"
|
|
bitfld.long 0x04 31. "FLASH_RDY,Internal" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x04 9.--30. 1. "RESERVED,Internal"
|
|
newline
|
|
hexmask.long.byte 0x04 1.--8. 1. "CRC,Internal"
|
|
newline
|
|
bitfld.long 0x04 0. "TAP_DAP_LOCK_N,Internal" "0,1"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "DAC_BIAS_CNF,Internal"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED,Internal"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "LPM_TRIM_IOUT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "LPM_BIAS_WIDTH_TRIM,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "LPM_BIAS_BACKUP_EN,Internal" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED1,Internal"
|
|
rgroup.long 0x418++0x17
|
|
line.long 0x00 "TFW_PROBE,Internal"
|
|
line.long 0x04 "TFW_FT,Internal"
|
|
line.long 0x08 "DAC_CAL0,Internal"
|
|
hexmask.long.word 0x08 16.--31. 1. "SOC_DAC_VOUT_CAL_DECOUPLE_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "SOC_DAC_VOUT_CAL_DECOUPLE_C1,Internal"
|
|
line.long 0x0C "DAC_CAL1,Internal"
|
|
hexmask.long.word 0x0C 16.--31. 1. "SOC_DAC_VOUT_CAL_PRECH_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--15. 1. "SOC_DAC_VOUT_CAL_PRECH_C1,Internal"
|
|
line.long 0x10 "DAC_CAL2,Internal"
|
|
hexmask.long.word 0x10 16.--31. 1. "SOC_DAC_VOUT_CAL_ADCREF_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "SOC_DAC_VOUT_CAL_ADCREF_C1,Internal"
|
|
line.long 0x14 "DAC_CAL3,Internal"
|
|
hexmask.long.word 0x14 16.--31. 1. "SOC_DAC_VOUT_CAL_VDDS_C2,Internal"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "SOC_DAC_VOUT_CAL_VDDS_C1,Internal"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "RESERVED_N,Software should not rely on the value of a reserved"
|
|
tree.end
|
|
tree "FLASH"
|
|
base ad:0x58030000
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "WEPROT_B0_31_0_BY1,Internal"
|
|
line.long 0x04 "WEPROT_AUX_BY1,Internal"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x04 5. "WEPROT_B1_ENGR_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "WEPROT_B0_ENGR_BY1,Internal" "0,1"
|
|
bitfld.long 0x04 3. "WEPROT_B1_TRIM_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "WEPROT_B0_TRIM_BY1,Internal" "0,1"
|
|
bitfld.long 0x04 1. "WEPROT_B1_FCFG_BY1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "WEPROT_B0_CCFG_BY1,Internal" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STAT,NW and Efuse Status"
|
|
hexmask.long.word 0x00 17.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "STALLSTAT,An ocp1 or ocp3 read stall has occurred.0 : No stall or stall acknowledged by writing a" "No stall or stall acknowledged by writing a 1,Stall condition occurred/occurringThis is a.."
|
|
newline
|
|
bitfld.long 0x00 15. "EFUSE_BLANK,Efuse scanning detected if fuse ROM is blank:0 : Not blank1 : Blank" "Not blank,Blank"
|
|
bitfld.long 0x00 14. "EFUSE_TIMEOUT,Efuse scanning resulted in timeout error.0 : No Timeout error1 : Timeout Error" "No Timeout error,Timeout Error"
|
|
newline
|
|
bitfld.long 0x00 13. "SPRS_BYTE_NOT_OK,Efuse scanning resulted in scan chain Sparse byte error.0 : No Sparse error1 : Sparse Error" "No Sparse error,Sparse Error"
|
|
rbitfld.long 0x00 8.--12. "EFUSE_ERRCODE,Same as EFUSEERROR.CODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED7,Software should not rely on the value of a reserved bit" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "BUSY,NW FW_SMSTAT.CMD_IN_PROGRESS bit.This flag is valid immediately after the operation setting it" "Not busy,BusyBit 4 is for the..,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "READY1T,1T access readiness status indicator from NW" "FLASH banks are not ready for 1T accesses,FLASH banks are ready for 1T accesses"
|
|
bitfld.long 0x00 2. "READY2T,2T access readiness status indicator from NW1: FLASH banks are ready for 2T accesses0: FLASH banks are not ready for 2T accesses" "FLASH banks are not ready for 2T accesses,FLASH banks are ready for 2T accesses"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "POWER_MODE,Power state of each of the 2 flash arbiter FSM instances in the flash sub-system" "Active,Ready for Low..,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFG,Internal"
|
|
bitfld.long 0x00 31. "RESERVED31,Software should not rely on the value of a reserved" "0,1"
|
|
bitfld.long 0x00 30. "DIS_FWTEST,Internal" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 12.--29. 1. "RESERVED12,Internal"
|
|
bitfld.long 0x00 11. "MAIN_STICKY_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CCFG_STICKY_EN,Internal" "0,1"
|
|
bitfld.long 0x00 9. "FCFG_STICKY_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ENGR_TRIM_STICKY_EN,Internal" "0,1"
|
|
rbitfld.long 0x00 6.--7. "RESERVED6,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "DIS_EFUSECLK,Internal" "0,1"
|
|
bitfld.long 0x00 4. "DIS_READACCESS,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "RESERVED1,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "BP_TRIMCFG_EN,Internal" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FLASH_SIZE,Internal"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED10,Internal"
|
|
bitfld.long 0x00 7.--9. "SECTORS,Internal" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "RESERVED0,Internal"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "FWLOCK,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x00 0.--2. "FWLOCK,Internal" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FWFLAG,Internal"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Internal"
|
|
bitfld.long 0x04 0.--2. "FWFLAG,Internal" "0,1,2,3,4,5,6,7"
|
|
repeat 2. (list 3. 2. )(list 0x00 0x04 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "BANK0_TRIM_CFG_$1,Internal"
|
|
repeat.end
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "BANK0_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x00 28.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--27. "REDSWSELW3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "REDSWSELW2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. "REDSWSELW1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "REDSWSELW0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3. "REDSWENW3,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REDSWENW2,Internal" "0,1"
|
|
bitfld.long 0x00 1. "REDSWENW1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "REDSWENW0,Internal" "0,1"
|
|
line.long 0x04 "BANK0_TRIM_CFG_0,Internal"
|
|
repeat 2. (list 3. 2. )(list 0x00 0x04 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "BANK1_TRIM_CFG_$1,Internal"
|
|
repeat.end
|
|
group.long 0x68++0x13
|
|
line.long 0x00 "BANK1_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x00 28.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--27. "REDSWSELW3,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "REDSWSELW2,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--15. "REDSWSELW1,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--9. "REDSWSELW0,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 3. "REDSWENW3,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "REDSWENW2,Internal" "0,1"
|
|
bitfld.long 0x00 1. "REDSWENW1,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "REDSWENW0,Internal" "0,1"
|
|
line.long 0x04 "BANK1_TRIM_CFG_0,Internal"
|
|
line.long 0x08 "PUMP_TRIM_CFG_2,Internal"
|
|
bitfld.long 0x08 26.--31. "RESERVED6,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--25. "VWLCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x08 14.--19. "VSLCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 9.--13. "VREADCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 4.--8. "VINLOWCCORCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--3. "VINHICCORCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "PUMP_TRIM_CFG_1,Internal"
|
|
bitfld.long 0x0C 31. "VINHICCORCTLSB,Internal" "0,1"
|
|
bitfld.long 0x0C 25.--30. "VINHCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x0C 20.--24. "VCGCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 15.--19. "IREFVRDCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x0C 10.--14. "IREFTCCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 6.--9. "IREFCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 0.--5. "FOSCCT,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "PUMP_TRIM_CFG_0,Internal"
|
|
bitfld.long 0x10 30.--31. "RESERVED2,Internal" "0,1,2,3"
|
|
hexmask.long.word 0x10 20.--29. 1. "VHVCT_PV,Internal"
|
|
newline
|
|
hexmask.long.word 0x10 10.--19. 1. "VHVCT_PGM,Internal"
|
|
hexmask.long.word 0x10 0.--9. 1. "VHVCT_ERS,Internal"
|
|
group.long 0x1000++0x4F
|
|
line.long 0x00 "EFUSE,Internal"
|
|
rbitfld.long 0x00 29.--31. "RESERVED29,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "INSTRUCTION,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RESERVED16,Internal"
|
|
hexmask.long.word 0x00 0.--15. 1. "DUMPWORD,Internal"
|
|
line.long 0x04 "EFUSEADDR,Internal"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Internal"
|
|
bitfld.long 0x04 11.--15. "BLOCK,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x04 0.--10. 1. "ROW,Internal"
|
|
line.long 0x08 "DATAUPPER,Internal"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Internal"
|
|
bitfld.long 0x08 3.--7. "SPARE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "P,Internal" "0,1"
|
|
bitfld.long 0x08 1. "R,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "EEN,Internal" "0,1"
|
|
line.long 0x0C "DATALOWER,Internal"
|
|
line.long 0x10 "EFUSECFG,Internal"
|
|
hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED9,Internal"
|
|
bitfld.long 0x10 8. "IDLEGATING,Internal" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 5.--7. "RESERVED5,Internal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 3.--4. "SLAVEPOWER,Internal" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x10 1.--2. "RESERVED1,Internal" "0,1,2,3"
|
|
bitfld.long 0x10 0. "GATING,Internal" "0,1"
|
|
line.long 0x14 "EFUSESTAT,Internal"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x14 0. "RESETDONE,Internal" "0,1"
|
|
line.long 0x18 "ACC,Internal"
|
|
hexmask.long.byte 0x18 24.--31. 1. "RESERVED24,Internal"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "ACCUMULATOR,Internal"
|
|
line.long 0x1C "BOUNDARY,Internal"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "RESERVED24,Internal"
|
|
bitfld.long 0x1C 23. "DISROW0,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "SPARE,Internal" "0,1"
|
|
bitfld.long 0x1C 21. "EFC_SELF_TEST_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 20. "EFC_INSTRUCTION_INFO,Internal" "0,1"
|
|
bitfld.long 0x1C 19. "EFC_INSTRUCTION_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 18. "EFC_AUTOLOAD_ERROR,Internal" "0,1"
|
|
bitfld.long 0x1C 14.--17. "OUTPUTENABLE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 13. "SYS_ECC_SELF_TEST_EN,Internal" "0,1"
|
|
bitfld.long 0x1C 12. "SYS_ECC_OVERRIDE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "EFC_FDI,Internal" "0,1"
|
|
bitfld.long 0x1C 10. "SYS_DIEID_AUTOLOAD_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 8.--9. "SYS_REPAIR_EN,Internal" "0,1,2,3"
|
|
bitfld.long 0x1C 4.--7. "SYS_WS_READ_STATES,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 0.--3. "INPUTENABLE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "EFUSEFLAG,Internal"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Internal"
|
|
bitfld.long 0x20 0. "KEY,Internal" "0,1"
|
|
line.long 0x24 "EFUSEKEY,Internal"
|
|
line.long 0x28 "EFUSERELEASE,Internal"
|
|
hexmask.long.byte 0x28 25.--31. 1. "ODPYEAR,Internal"
|
|
bitfld.long 0x28 21.--24. "ODPMONTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x28 16.--20. "ODPDAY,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x28 9.--15. 1. "EFUSEYEAR,Internal"
|
|
newline
|
|
bitfld.long 0x28 5.--8. "EFUSEMONTH,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 0.--4. "EFUSEDAY,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "EFUSEPINS,Internal"
|
|
hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Internal"
|
|
bitfld.long 0x2C 15. "EFC_SELF_TEST_DONE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 14. "EFC_SELF_TEST_ERROR,Internal" "0,1"
|
|
bitfld.long 0x2C 13. "SYS_ECC_SELF_TEST_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 12. "EFC_INSTRUCTION_INFO,Internal" "0,1"
|
|
bitfld.long 0x2C 11. "EFC_INSTRUCTION_ERROR,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 10. "EFC_AUTOLOAD_ERROR,Internal" "0,1"
|
|
bitfld.long 0x2C 9. "SYS_ECC_OVERRIDE_EN,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 8. "EFC_READY,Internal" "0,1"
|
|
bitfld.long 0x2C 7. "EFC_FCLRZ,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 6. "SYS_DIEID_AUTOLOAD_EN,Internal" "0,1"
|
|
bitfld.long 0x2C 4.--5. "SYS_REPAIR_EN,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x2C 0.--3. "SYS_WS_READ_STATES,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "EFUSECRA,Internal"
|
|
hexmask.long 0x30 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x30 0.--5. "DATA,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x34 "EFUSEREAD,Internal"
|
|
hexmask.long.tbyte 0x34 10.--31. 1. "RESERVED10,Internal"
|
|
bitfld.long 0x34 8.--9. "DATABIT,Internal" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x34 4.--7. "READCLOCK,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 3. "DEBUG,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "SPARE,Internal" "0,1"
|
|
bitfld.long 0x34 0.--1. "MARGIN,Internal" "0,1,2,3"
|
|
line.long 0x38 "EFUSEPROGRAM,Internal"
|
|
rbitfld.long 0x38 31. "RESERVED31,Internal" "0,1"
|
|
bitfld.long 0x38 30. "COMPAREDISABLE,Internal" "0,1"
|
|
newline
|
|
hexmask.long.word 0x38 14.--29. 1. "CLOCKSTALL,Internal"
|
|
bitfld.long 0x38 13. "VPPTOVDD,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x38 9.--12. "ITERATIONS,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x38 0.--8. 1. "WRITECLOCK,Internal"
|
|
line.long 0x3C "EFUSEERROR,Internal"
|
|
hexmask.long 0x3C 6.--31. 1. "RESERVED6,Internal"
|
|
bitfld.long 0x3C 5. "DONE,Internal" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 0.--4. "CODE,Internal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x40 "SINGLEBIT,Internal"
|
|
hexmask.long 0x40 1.--31. 1. "FROMN,Internal"
|
|
bitfld.long 0x40 0. "FROM0,Internal" "0,1"
|
|
line.long 0x44 "TWOBIT,Internal"
|
|
hexmask.long 0x44 1.--31. 1. "FROMN,Internal"
|
|
bitfld.long 0x44 0. "FROM0,Internal" "0,1"
|
|
line.long 0x48 "SELFTESTCYC,Internal"
|
|
line.long 0x4C "SELFTESTSIGN,Internal"
|
|
tree.end
|
|
tree "GPIO"
|
|
base ad:0x40022000
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "DOUT3_0,Data Out 0 to 3Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 24. "DIO3,Sets the state of the pin that is configured as DIO#3 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 16. "DIO2,Sets the state of the pin that is configured as DIO#2 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "DIO1,Sets the state of the pin that is configured as DIO#1 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "DIO0,Sets the state of the pin that is configured as DIO#0 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x04 "DOUT7_4,Data Out 4 to 7Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x04 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 24. "DIO7,Sets the state of the pin that is configured as DIO#7 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 16. "DIO6,Sets the state of the pin that is configured as DIO#6 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 8. "DIO5,Sets the state of the pin that is configured as DIO#5 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x04 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "DIO4,Sets the state of the pin that is configured as DIO#4 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x08 "DOUT11_8,Data Out 8 to 11Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x08 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 24. "DIO11,Sets the state of the pin that is configured as DIO#11 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 16. "DIO10,Sets the state of the pin that is configured as DIO#10 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 8. "DIO9,Sets the state of the pin that is configured as DIO#9 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x08 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "DIO8,Sets the state of the pin that is configured as DIO#8 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x0C "DOUT15_12,Data Out 12 to 15Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x0C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 24. "DIO15,Sets the state of the pin that is configured as DIO#15 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 16. "DIO14,Sets the state of the pin that is configured as DIO#14 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 8. "DIO13,Sets the state of the pin that is configured as DIO#13 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "DIO12,Sets the state of the pin that is configured as DIO#12 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x10 "DOUT19_16,Data Out 16 to 19Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x10 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 24. "DIO19,Sets the state of the pin that is configured as DIO#19 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 16. "DIO18,Sets the state of the pin that is configured as DIO#18 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 8. "DIO17,Sets the state of the pin that is configured as DIO#17 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x10 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "DIO16,Sets the state of the pin that is configured as DIO#16 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x14 "DOUT23_20,Data Out 20 to 23Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x14 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 24. "DIO23,Sets the state of the pin that is configured as DIO#23 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 16. "DIO22,Sets the state of the pin that is configured as DIO#22 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 8. "DIO21,Sets the state of the pin that is configured as DIO#21 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x14 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "DIO20,Sets the state of the pin that is configured as DIO#20 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x18 "DOUT27_24,Data Out 24 to 27Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x18 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 24. "DIO27,Sets the state of the pin that is configured as DIO#27 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 16. "DIO26,Sets the state of the pin that is configured as DIO#26 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 8. "DIO25,Sets the state of the pin that is configured as DIO#25 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x18 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "DIO24,Sets the state of the pin that is configured as DIO#24 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x1C "DOUT31_28,Data Out 28 to 31Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x1C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 24. "DIO31,Sets the state of the pin that is configured as DIO#31 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 16. "DIO30,Sets the state of the pin that is configured as DIO#30 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 8. "DIO29,Sets the state of the pin that is configured as DIO#29 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x1C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "DIO28,Sets the state of the pin that is configured as DIO#28 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x20 "DOUT35_32,Data Out 35 to 32Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x20 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 24. "DIO35,Sets the state of the pin that is configured as DIO#35 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 16. "DIO34,Sets the state of the pin that is configured as DIO#34 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 8. "DIO33,Sets the state of the pin that is configured as DIO#33 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x20 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "DIO32,Sets the state of the pin that is configured as DIO#32 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x24 "DOUT39_36,Data Out 39 to 36Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x24 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 24. "DIO39,Sets the state of the pin that is configured as DIO#39 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 16. "DIO38,Sets the state of the pin that is configured as DIO#38 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 8. "DIO37,Sets the state of the pin that is configured as DIO#37 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x24 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0. "DIO36,Sets the state of the pin that is configured as DIO#36 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x28 "DOUT43_40,Data Out 43 to 40Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x28 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 24. "DIO43,Sets the state of the pin that is configured as DIO#43 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 16. "DIO42,Sets the state of the pin that is configured as DIO#42 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 8. "DIO41,Sets the state of the pin that is configured as DIO#41 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x28 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "DIO40,Sets the state of the pin that is configured as DIO#40 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
line.long 0x2C "DOUT47_44,Data Out 47 to 44Alias register for byte access to each bit in DOUT47_0"
|
|
hexmask.long.byte 0x2C 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 24. "DIO47,Sets the state of the pin that is configured as DIO#47 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 17.--23. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 16. "DIO46,Sets the state of the pin that is configured as DIO#46 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 8. "DIO45,Sets the state of the pin that is configured as DIO#45 if the corresponding DOE47_0 bitfield is set." "0,1"
|
|
hexmask.long.byte 0x2C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
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bitfld.long 0x2C 0. "DIO44,Sets the state of the pin that is configured as DIO#44 if the corresponding DOE47_0 bitfield is set." "0,1"
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group.long 0x80++0x07
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line.long 0x00 "DOUT31_0,Data Output for DIO 0 to 31"
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bitfld.long 0x00 31. "DIO31,Data output for DIO 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Data output for DIO 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Data output for DIO 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Data output for DIO 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Data output for DIO 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Data output for DIO 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Data output for DIO 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Data output for DIO 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Data output for DIO 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Data output for DIO 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Data output for DIO 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Data output for DIO 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Data output for DIO 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Data output for DIO 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Data output for DIO 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Data output for DIO 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Data output for DIO 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Data output for DIO 14" "0,1"
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newline
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bitfld.long 0x00 13. "DIO13,Data output for DIO 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Data output for DIO 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Data output for DIO 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Data output for DIO 10" "0,1"
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bitfld.long 0x00 9. "DIO9,Data output for DIO 9" "0,1"
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bitfld.long 0x00 8. "DIO8,Data output for DIO 8" "0,1"
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bitfld.long 0x00 7. "DIO7,Data output for DIO 7" "0,1"
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bitfld.long 0x00 6. "DIO6,Data output for DIO 6" "0,1"
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bitfld.long 0x00 5. "DIO5,Data output for DIO 5" "0,1"
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newline
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bitfld.long 0x00 4. "DIO4,Data output for DIO 4" "0,1"
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bitfld.long 0x00 3. "DIO3,Data output for DIO 3" "0,1"
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bitfld.long 0x00 2. "DIO2,Data output for DIO 2" "0,1"
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bitfld.long 0x00 1. "DIO1,Data output for DIO 1" "0,1"
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bitfld.long 0x00 0. "DIO0,Data output for DIO 0" "0,1"
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line.long 0x04 "DOUT47_32,Data Output for DIO 0 to 31"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "DIO47,Data output for DIO 47" "0,1"
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bitfld.long 0x04 14. "DIO46,Data output for DIO 46" "0,1"
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bitfld.long 0x04 13. "DIO45,Data output for DIO 45" "0,1"
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bitfld.long 0x04 12. "DIO44,Data output for DIO 44" "0,1"
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bitfld.long 0x04 11. "DIO43,Data output for DIO 43" "0,1"
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bitfld.long 0x04 10. "DIO42,Data output for DIO 42" "0,1"
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bitfld.long 0x04 9. "DIO41,Data output for DIO 41" "0,1"
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bitfld.long 0x04 8. "DIO40,Data output for DIO 40" "0,1"
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newline
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bitfld.long 0x04 7. "DIO39,Data output for DIO 39" "0,1"
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bitfld.long 0x04 6. "DIO38,Data output for DIO 38" "0,1"
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bitfld.long 0x04 5. "DIO37,Data output for DIO 37" "0,1"
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bitfld.long 0x04 4. "DIO36,Data output for DIO 36" "0,1"
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bitfld.long 0x04 3. "DIO35,Data output for DIO 35" "0,1"
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bitfld.long 0x04 2. "DIO34,Data output for DIO 34" "0,1"
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bitfld.long 0x04 1. "DIO33,Data output for DIO 33" "0,1"
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bitfld.long 0x04 0. "DIO32,Data output for DIO 32" "0,1"
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group.long 0x90++0x07
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line.long 0x00 "DOUTSET31_0,Data Out SetWriting 1 to a bit position sets the corresponding bit in the DOUT47_0 register"
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bitfld.long 0x00 31. "DIO31,Set bit 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Set bit 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Set bit 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Set bit 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Set bit 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Set bit 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Set bit 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Set bit 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Set bit 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Set bit 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Set bit 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Set bit 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Set bit 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Set bit 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Set bit 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Set bit 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Set bit 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Set bit 14" "0,1"
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newline
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bitfld.long 0x00 13. "DIO13,Set bit 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Set bit 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Set bit 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Set bit 10" "0,1"
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bitfld.long 0x00 9. "DIO9,Set bit 9" "0,1"
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bitfld.long 0x00 8. "DIO8,Set bit 8" "0,1"
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bitfld.long 0x00 7. "DIO7,Set bit 7" "0,1"
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bitfld.long 0x00 6. "DIO6,Set bit 6" "0,1"
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bitfld.long 0x00 5. "DIO5,Set bit 5" "0,1"
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newline
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bitfld.long 0x00 4. "DIO4,Set bit 4" "0,1"
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bitfld.long 0x00 3. "DIO3,Set bit 3" "0,1"
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bitfld.long 0x00 2. "DIO2,Set bit 2" "0,1"
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bitfld.long 0x00 1. "DIO1,Set bit 1" "0,1"
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bitfld.long 0x00 0. "DIO0,Set bit 0" "0,1"
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line.long 0x04 "DOUTSET47_32,Data Out SetWriting 1 to a bit position sets the corresponding bit in the DOUT47_0 register"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "DIO47,Set bit 47" "0,1"
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bitfld.long 0x04 14. "DIO46,Set bit 46" "0,1"
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bitfld.long 0x04 13. "DIO45,Set bit 45" "0,1"
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bitfld.long 0x04 12. "DIO44,Set bit 44" "0,1"
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bitfld.long 0x04 11. "DIO43,Set bit 43" "0,1"
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bitfld.long 0x04 10. "DIO42,Set bit 42" "0,1"
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bitfld.long 0x04 9. "DIO41,Set bit 41" "0,1"
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bitfld.long 0x04 8. "DIO40,Set bit 40" "0,1"
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newline
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bitfld.long 0x04 7. "DIO39,Set bit 39" "0,1"
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bitfld.long 0x04 6. "DIO38,Set bit 38" "0,1"
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bitfld.long 0x04 5. "DIO37,Set bit 37" "0,1"
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bitfld.long 0x04 4. "DIO36,Set bit 36" "0,1"
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bitfld.long 0x04 3. "DIO35,Set bit 35" "0,1"
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bitfld.long 0x04 2. "DIO34,Set bit 34" "0,1"
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bitfld.long 0x04 1. "DIO33,Set bit 33" "0,1"
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bitfld.long 0x04 0. "DIO32,Set bit 32" "0,1"
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group.long 0xA0++0x07
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line.long 0x00 "DOUTCLR31_0,Data Out ClearWriting 1 to a bit position clears the corresponding bit in the DOUT47_0 register"
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bitfld.long 0x00 31. "DIO31,Clears bit 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Clears bit 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Clears bit 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Clears bit 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Clears bit 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Clears bit 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Clears bit 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Clears bit 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Clears bit 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Clears bit 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Clears bit 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Clears bit 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Clears bit 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Clears bit 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Clears bit 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Clears bit 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Clears bit 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Clears bit 14" "0,1"
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newline
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bitfld.long 0x00 13. "DIO13,Clears bit 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Clears bit 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Clears bit 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Clears bit 10" "0,1"
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bitfld.long 0x00 9. "DIO9,Clears bit 9" "0,1"
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bitfld.long 0x00 8. "DIO8,Clears bit 8" "0,1"
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bitfld.long 0x00 7. "DIO7,Clears bit 7" "0,1"
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bitfld.long 0x00 6. "DIO6,Clears bit 6" "0,1"
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bitfld.long 0x00 5. "DIO5,Clears bit 5" "0,1"
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newline
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bitfld.long 0x00 4. "DIO4,Clears bit 4" "0,1"
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bitfld.long 0x00 3. "DIO3,Clears bit 3" "0,1"
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bitfld.long 0x00 2. "DIO2,Clears bit 2" "0,1"
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bitfld.long 0x00 1. "DIO1,Clears bit 1" "0,1"
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bitfld.long 0x00 0. "DIO0,Clears bit 0" "0,1"
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line.long 0x04 "DOUTCLR47_32,Data Out ClearWriting 1 to a bit position clears the corresponding bit in the DOUT47_0 register"
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hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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bitfld.long 0x04 15. "DIO47,Clears bit 47" "0,1"
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bitfld.long 0x04 14. "DIO46,Clears bit 46" "0,1"
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bitfld.long 0x04 13. "DIO45,Clears bit 45" "0,1"
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bitfld.long 0x04 12. "DIO44,Clears bit 44" "0,1"
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bitfld.long 0x04 11. "DIO43,Clears bit 43" "0,1"
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bitfld.long 0x04 10. "DIO42,Clears bit 42" "0,1"
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bitfld.long 0x04 9. "DIO41,Clears bit 41" "0,1"
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bitfld.long 0x04 8. "DIO40,Clears bit 40" "0,1"
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newline
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bitfld.long 0x04 7. "DIO39,Clears bit 39" "0,1"
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bitfld.long 0x04 6. "DIO38,Clears bit 38" "0,1"
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bitfld.long 0x04 5. "DIO37,Clears bit 37" "0,1"
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bitfld.long 0x04 4. "DIO36,Clears bit 36" "0,1"
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bitfld.long 0x04 3. "DIO35,Clears bit 35" "0,1"
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bitfld.long 0x04 2. "DIO34,Clears bit 34" "0,1"
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bitfld.long 0x04 1. "DIO33,Clears bit 33" "0,1"
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bitfld.long 0x04 0. "DIO32,Clears bit 32" "0,1"
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group.long 0xB0++0x07
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line.long 0x00 "DOUTTGL31_0,Data Out ToggleWriting 1 to a bit position will invert the corresponding DIO output"
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bitfld.long 0x00 31. "DIO31,Toggles bit 31" "0,1"
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bitfld.long 0x00 30. "DIO30,Toggles bit 30" "0,1"
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bitfld.long 0x00 29. "DIO29,Toggles bit 29" "0,1"
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bitfld.long 0x00 28. "DIO28,Toggles bit 28" "0,1"
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bitfld.long 0x00 27. "DIO27,Toggles bit 27" "0,1"
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bitfld.long 0x00 26. "DIO26,Toggles bit 26" "0,1"
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bitfld.long 0x00 25. "DIO25,Toggles bit 25" "0,1"
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bitfld.long 0x00 24. "DIO24,Toggles bit 24" "0,1"
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bitfld.long 0x00 23. "DIO23,Toggles bit 23" "0,1"
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newline
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bitfld.long 0x00 22. "DIO22,Toggles bit 22" "0,1"
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bitfld.long 0x00 21. "DIO21,Toggles bit 21" "0,1"
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bitfld.long 0x00 20. "DIO20,Toggles bit 20" "0,1"
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bitfld.long 0x00 19. "DIO19,Toggles bit 19" "0,1"
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bitfld.long 0x00 18. "DIO18,Toggles bit 18" "0,1"
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bitfld.long 0x00 17. "DIO17,Toggles bit 17" "0,1"
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bitfld.long 0x00 16. "DIO16,Toggles bit 16" "0,1"
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bitfld.long 0x00 15. "DIO15,Toggles bit 15" "0,1"
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bitfld.long 0x00 14. "DIO14,Toggles bit 14" "0,1"
|
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newline
|
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bitfld.long 0x00 13. "DIO13,Toggles bit 13" "0,1"
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bitfld.long 0x00 12. "DIO12,Toggles bit 12" "0,1"
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bitfld.long 0x00 11. "DIO11,Toggles bit 11" "0,1"
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bitfld.long 0x00 10. "DIO10,Toggles bit 10" "0,1"
|
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bitfld.long 0x00 9. "DIO9,Toggles bit 9" "0,1"
|
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bitfld.long 0x00 8. "DIO8,Toggles bit 8" "0,1"
|
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bitfld.long 0x00 7. "DIO7,Toggles bit 7" "0,1"
|
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bitfld.long 0x00 6. "DIO6,Toggles bit 6" "0,1"
|
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bitfld.long 0x00 5. "DIO5,Toggles bit 5" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "DIO4,Toggles bit 4" "0,1"
|
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bitfld.long 0x00 3. "DIO3,Toggles bit 3" "0,1"
|
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bitfld.long 0x00 2. "DIO2,Toggles bit 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Toggles bit 1" "0,1"
|
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bitfld.long 0x00 0. "DIO0,Toggles bit 0" "0,1"
|
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line.long 0x04 "DOUTTGL47_32,Data Out ToggleWriting 1 to a bit position will invert the corresponding DIO output"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Toggles bit 47" "0,1"
|
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bitfld.long 0x04 14. "DIO46,Toggles bit 46" "0,1"
|
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bitfld.long 0x04 13. "DIO45,Toggles bit 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Toggles bit 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Toggles bit 43" "0,1"
|
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bitfld.long 0x04 10. "DIO42,Toggles bit 42" "0,1"
|
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bitfld.long 0x04 9. "DIO41,Toggles bit 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Toggles bit 40" "0,1"
|
|
newline
|
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bitfld.long 0x04 7. "DIO39,Toggles bit 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Toggles bit 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Toggles bit 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Toggles bit 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Toggles bit 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Toggles bit 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Toggles bit 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Toggles bit 32" "0,1"
|
|
rgroup.long 0xC0++0x07
|
|
line.long 0x00 "DIN31_0,Data Input from DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data input from DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data input from DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data input from DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data input from DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data input from DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data input from DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data input from DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data input from DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data input from DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data input from DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data input from DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data input from DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data input from DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data input from DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data input from DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data input from DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data input from DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data input from DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data input from DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data input from DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data input from DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data input from DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data input from DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data input from DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data input from DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data input from DIO 6" "0,1"
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|
bitfld.long 0x00 5. "DIO5,Data input from DIO 5" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "DIO4,Data input from DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data input from DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data input from DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data input from DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data input from DIO 0" "0,1"
|
|
line.long 0x04 "DIN47_32,Data Input from DIO 32 to 47"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data input from DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data input from DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data input from DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data input from DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data input from DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data input from DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data input from DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data input from DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Data input from DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data input from DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data input from DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data input from DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data input from DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data input from DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data input from DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data input from DIO 32" "0,1"
|
|
group.long 0xD0++0x07
|
|
line.long 0x00 "DOE31_0,Data Output Enable for DIO 0 to 31"
|
|
bitfld.long 0x00 31. "DIO31,Data output enable for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Data output enable for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Data output enable for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Data output enable for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Data output enable for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Data output enable for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Data output enable for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Data output enable for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Data output enable for DIO 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DIO22,Data output enable for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Data output enable for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Data output enable for DIO 20" "0,1"
|
|
bitfld.long 0x00 19. "DIO19,Data output enable for DIO 19" "0,1"
|
|
bitfld.long 0x00 18. "DIO18,Data output enable for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Data output enable for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Data output enable for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Data output enable for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Data output enable for DIO 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DIO13,Data output enable for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Data output enable for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Data output enable for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Data output enable for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Data output enable for DIO 9" "0,1"
|
|
bitfld.long 0x00 8. "DIO8,Data output enable for DIO 8" "0,1"
|
|
bitfld.long 0x00 7. "DIO7,Data output enable for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Data output enable for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Data output enable for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Data output enable for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Data output enable for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Data output enable for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Data output enable for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Data output enable for DIO 0" "0,1"
|
|
line.long 0x04 "DOE47_32,Data Output Enable for DIO 32 to 47"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Data output enable for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Data output enable for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Data output enable for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Data output enable for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Data output enable for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Data output enable for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Data output enable for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Data output enable for DIO 40" "0,1"
|
|
newline
|
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bitfld.long 0x04 7. "DIO39,Data output enable for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Data output enable for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Data output enable for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Data output enable for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Data output enable for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Data output enable for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Data output enable for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Data output enable for DIO 32" "0,1"
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|
group.long 0xE0++0x07
|
|
line.long 0x00 "EVFLAGS31_0,Event Register for DIO 0 to 31Reading this registers will return 1 for triggered event and 0 for non-triggered events"
|
|
bitfld.long 0x00 31. "DIO31,Event for DIO 31" "0,1"
|
|
bitfld.long 0x00 30. "DIO30,Event for DIO 30" "0,1"
|
|
bitfld.long 0x00 29. "DIO29,Event for DIO 29" "0,1"
|
|
bitfld.long 0x00 28. "DIO28,Event for DIO 28" "0,1"
|
|
bitfld.long 0x00 27. "DIO27,Event for DIO 27" "0,1"
|
|
bitfld.long 0x00 26. "DIO26,Event for DIO 26" "0,1"
|
|
bitfld.long 0x00 25. "DIO25,Event for DIO 25" "0,1"
|
|
bitfld.long 0x00 24. "DIO24,Event for DIO 24" "0,1"
|
|
bitfld.long 0x00 23. "DIO23,Event for DIO 23" "0,1"
|
|
newline
|
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bitfld.long 0x00 22. "DIO22,Event for DIO 22" "0,1"
|
|
bitfld.long 0x00 21. "DIO21,Event for DIO 21" "0,1"
|
|
bitfld.long 0x00 20. "DIO20,Event for DIO 20" "0,1"
|
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bitfld.long 0x00 19. "DIO19,Event for DIO 19" "0,1"
|
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bitfld.long 0x00 18. "DIO18,Event for DIO 18" "0,1"
|
|
bitfld.long 0x00 17. "DIO17,Event for DIO 17" "0,1"
|
|
bitfld.long 0x00 16. "DIO16,Event for DIO 16" "0,1"
|
|
bitfld.long 0x00 15. "DIO15,Event for DIO 15" "0,1"
|
|
bitfld.long 0x00 14. "DIO14,Event for DIO 14" "0,1"
|
|
newline
|
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bitfld.long 0x00 13. "DIO13,Event for DIO 13" "0,1"
|
|
bitfld.long 0x00 12. "DIO12,Event for DIO 12" "0,1"
|
|
bitfld.long 0x00 11. "DIO11,Event for DIO 11" "0,1"
|
|
bitfld.long 0x00 10. "DIO10,Event for DIO 10" "0,1"
|
|
bitfld.long 0x00 9. "DIO9,Event for DIO 9" "0,1"
|
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bitfld.long 0x00 8. "DIO8,Event for DIO 8" "0,1"
|
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bitfld.long 0x00 7. "DIO7,Event for DIO 7" "0,1"
|
|
bitfld.long 0x00 6. "DIO6,Event for DIO 6" "0,1"
|
|
bitfld.long 0x00 5. "DIO5,Event for DIO 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIO4,Event for DIO 4" "0,1"
|
|
bitfld.long 0x00 3. "DIO3,Event for DIO 3" "0,1"
|
|
bitfld.long 0x00 2. "DIO2,Event for DIO 2" "0,1"
|
|
bitfld.long 0x00 1. "DIO1,Event for DIO 1" "0,1"
|
|
bitfld.long 0x00 0. "DIO0,Event for DIO 0" "0,1"
|
|
line.long 0x04 "EVFLAGS47_32,Event Register for DIO 32 to 47Reading this registers will return 1 for triggered event and 0 for non-triggered events"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 15. "DIO47,Event for DIO 47" "0,1"
|
|
bitfld.long 0x04 14. "DIO46,Event for DIO 46" "0,1"
|
|
bitfld.long 0x04 13. "DIO45,Event for DIO 45" "0,1"
|
|
bitfld.long 0x04 12. "DIO44,Event for DIO 44" "0,1"
|
|
bitfld.long 0x04 11. "DIO43,Event for DIO 43" "0,1"
|
|
bitfld.long 0x04 10. "DIO42,Event for DIO 42" "0,1"
|
|
bitfld.long 0x04 9. "DIO41,Event for DIO 41" "0,1"
|
|
bitfld.long 0x04 8. "DIO40,Event for DIO 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. "DIO39,Event for DIO 39" "0,1"
|
|
bitfld.long 0x04 6. "DIO38,Event for DIO 38" "0,1"
|
|
bitfld.long 0x04 5. "DIO37,Event for DIO 37" "0,1"
|
|
bitfld.long 0x04 4. "DIO36,Event for DIO 36" "0,1"
|
|
bitfld.long 0x04 3. "DIO35,Event for DIO 35" "0,1"
|
|
bitfld.long 0x04 2. "DIO34,Event for DIO 34" "0,1"
|
|
bitfld.long 0x04 1. "DIO33,Event for DIO 33" "0,1"
|
|
bitfld.long 0x04 0. "DIO32,Event for DIO 32" "0,1"
|
|
tree.end
|
|
tree "GPT"
|
|
repeat 4. (list 0. 1. 2. 3. )(list ad:0x40010000 ad:0x40011000 ad:0x40012000 ad:0x40013000 )
|
|
tree "GPT$1"
|
|
base $2
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CFG,Configuration"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CFG,GPT Configuration0x2" "32-bit timer configuration,?,?,?,16-bit timer configuration. Configure for two..,?,?,?"
|
|
line.long 0x04 "TAMR,Timer A Mode"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 13.--15. "TCACT,Timer Compare Action Select " "Disable compare operations,Toggle State on Time-Out,Clear CCP output pin on Time-Out,Set CCP output pin on Time-Out ,Set CCP output pin immediately and toggle on..,Clear CCP output pin immediately and toggle on..,Set CCP output pin immediately and clear on..,Clear CCP output pin immediately and set on.."
|
|
newline
|
|
bitfld.long 0x04 12. "TACINTD,One-Shot/Periodic Interrupt Disable" "Time-out interrupt function as normal,Time-out interrupt are disabled"
|
|
newline
|
|
bitfld.long 0x04 11. "TAPLO,GPTM Timer A PWM Legacy Operation0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0.1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0.This bit is only valid in.." "Legacy operation,CCP output pin is set to 1 on time-out"
|
|
newline
|
|
bitfld.long 0x04 10. "TAMRSU,Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated.If the timer is disabled (CTL.TAEN = 0) when this bit is set TAMATCHR and TAPR are updated when the timer is enabled.If the timer is stalled.." "Update TAMATCHR and TAPR if used on the next..,Update TAMATCHR and TAPR if used on the next.."
|
|
newline
|
|
bitfld.long 0x04 9. "TAPWMIE,GPTM Timer A PWM Interrupt EnableThis bit enables interrupts in PWM mode on rising falling or both edges of the CCP output as defined by the CTL.TAEVENTIn addition when this bit is set and a capture event occurs Timer Aautomatically generates.." "Interrupt is disabled. ,Interrupt is enabled. This bit is only valid in.."
|
|
newline
|
|
bitfld.long 0x04 8. "TAILD,GPT Timer A PWM Interval Load" "Update the TAR register with the value in the..,Update the TAR register with the value in the.."
|
|
newline
|
|
bitfld.long 0x04 7. "TASNAPS,GPT Timer A Snap-Shot Mode" "Snap-shot mode is disabled. ,If Timer A is configured in the periodic mode .."
|
|
newline
|
|
bitfld.long 0x04 6. "TAWOT,GPT Timer A Wait-On-Trigger" "Timer A begins counting as soon as it is enabled.,If Timer A is enabled (CTL.TAEN = 1) Timer A.."
|
|
newline
|
|
bitfld.long 0x04 5. "TAMIE,GPT Timer A Match Interrupt Enable" "The match interrupt is disabled for match..,An interrupt is generated when the match value.."
|
|
newline
|
|
bitfld.long 0x04 4. "TACDIR,GPT Timer A Count Direction" "The timer counts down. ,The timer counts up. When counting up the timer.."
|
|
newline
|
|
bitfld.long 0x04 3. "TAAMS,GPT Timer A Alternate Mode Note: To enable PWM mode you must also clear TACM and then configure TAMR field to 0x2" "Capture/Compare mode is enabled.,PWM mode is enabled"
|
|
newline
|
|
bitfld.long 0x04 2. "TACM,GPT Timer A Capture Mode" "Edge-Count mode,Edge-Time mode"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "TAMR,GPT Timer A Mode0x0 Reserved0x1 One-Shot Timer mode0x2 Periodic Timer mode0x3 Capture modeThe Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register" "?,One-Shot Timer mode,Periodic Timer mode ,Capture mode"
|
|
line.long 0x08 "TBMR,Timer B Mode"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 13.--15. "TCACT,Timer Compare Action Select" "Disable compare operations,Toggle State on Time-Out,Clear CCP output pin on Time-Out,Set CCP output pin on Time-Out ,Set CCP output pin immediately and toggle on..,Clear CCP output pin immediately and toggle on..,Set CCP output pin immediately and clear on..,Clear CCP output pin immediately and set on.."
|
|
newline
|
|
bitfld.long 0x08 12. "TBCINTD,One-Shot/Periodic Interrupt Mode" "Normal Time-Out Interrupt ,Mask Time-Out Interrupt"
|
|
newline
|
|
bitfld.long 0x08 11. "TBPLO,GPTM Timer B PWM Legacy Operation0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0.1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0.This bit is only valid in.." "Legacy operation,CCP output pin is set to 1 on time-out"
|
|
newline
|
|
bitfld.long 0x08 10. "TBMRSU,Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updatedIf the timer is disabled (CTL.TBEN is clear) when this bit is set TBMATCHR and TBPR are updated when the timer is enabled.If the timer is stalled.." "Update TBMATCHR and TBPR if used on the next..,Update TBMATCHR and TBPR if used on the next.."
|
|
newline
|
|
bitfld.long 0x08 9. "TBPWMIE,GPTM Timer B PWM Interrupt EnableThis bit enables interrupts in PWM mode on rising falling or both edges of the CCP output as defined by the CTL.TBEVENTIn addition when this bit is set and a capture event occurs Timer Aautomatically generates.." "Interrupt is disabled. ,Interrupt is enabled. This bit is only valid in.."
|
|
newline
|
|
bitfld.long 0x08 8. "TBILD,GPT Timer B PWM Interval Load" "Update the TBR register with the value in the..,Update the TBR register with the value in the.."
|
|
newline
|
|
bitfld.long 0x08 7. "TBSNAPS,GPT Timer B Snap-Shot Mode" "Snap-shot mode is disabled. ,If Timer B is configured in the periodic mode"
|
|
newline
|
|
bitfld.long 0x08 6. "TBWOT,GPT Timer B Wait-On-Trigger" "Timer B begins counting as soon as it is enabled. ,If Timer B is enabled (CTL.TBEN is set) Timer B.."
|
|
newline
|
|
bitfld.long 0x08 5. "TBMIE,GPT Timer B Match Interrupt Enable" "The match interrupt is disabled for match..,An interrupt is generated when the match value.."
|
|
newline
|
|
bitfld.long 0x08 4. "TBCDIR,GPT Timer B Count Direction" "The timer counts down. ,The timer counts up. When counting up the timer.."
|
|
newline
|
|
bitfld.long 0x08 3. "TBAMS,GPT Timer B Alternate Mode Note: To enable PWM mode you must also clear TBCM bit and configure TBMR field to 0x2" "Capture/Compare mode is enabled.,PWM mode is enabled"
|
|
newline
|
|
bitfld.long 0x08 2. "TBCM,GPT Timer B Capture Mode" "Edge-Count mode,Edge-Time mode"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "TBMR,GPT Timer B Mode0x0 Reserved0x1 One-Shot Timer mode0x2 Periodic Timer mode0x3 Capture modeThe Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register" "?,One-Shot Timer mode,Periodic Timer mode ,Capture mode"
|
|
line.long 0x0C "CTL,Control"
|
|
hexmask.long.tbyte 0x0C 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 14. "TBPWML,GPT Timer B PWM Output Level0: Output is unaffected" "Output is unaffected,Output is inverted"
|
|
newline
|
|
bitfld.long 0x0C 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 10.--11. "TBEVENT,GPT Timer B Event ModeThe values in this register are defined as follows:Value Description0x0 Positive edge0x1 Negative edge0x2 Reserved0x3 Both edgesNote: If PWM output inversion is enabled edge detection interruptbehavior is reversed" "Positive edge,Negative edge ,?,Both edges"
|
|
newline
|
|
bitfld.long 0x0C 9. "TBSTALL,GPT Timer B Stall Enable" "Timer B continues counting while the processor..,Timer B freezes counting while the processor is.."
|
|
newline
|
|
bitfld.long 0x0C 8. "TBEN,GPT Timer B Enable" "Timer B is disabled. ,Timer B is enabled and begins counting or the.."
|
|
newline
|
|
rbitfld.long 0x0C 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "TAPWML,GPT Timer A PWM Output Level" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x0C 4.--5. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 2.--3. "TAEVENT,GPT Timer A Event ModeThe values in this register are defined as follows:Value Description0x0 Positive edge0x1 Negative edge0x2 Reserved0x3 Both edgesNote: If PWM output inversion is enabled edge detection interruptbehavior is reversed" "Positive edge,Negative edge ,?,Both edges"
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|
newline
|
|
bitfld.long 0x0C 1. "TASTALL,GPT Timer A Stall Enable" "Timer A continues counting while the processor..,Timer A freezes counting while the processor is.."
|
|
newline
|
|
bitfld.long 0x0C 0. "TAEN,GPT Timer A Enable" "Timer A is disabled. ,Timer A is enabled and begins counting or the.."
|
|
line.long 0x10 "SYNC,Synch Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "SYNC3,Synchronize GPT Timer 3" "No Sync. GPT3 is not affected. ,A timeout event for Timer A of GPT3 is triggered,A timeout event for Timer B of GPT3 is triggered,A timeout event for both Timer A and Timer B of.."
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|
newline
|
|
bitfld.long 0x10 4.--5. "SYNC2,Synchronize GPT Timer 2" "No Sync. GPT2 is not affected. ,A timeout event for Timer A of GPT2 is triggered,A timeout event for Timer B of GPT2 is triggered,A timeout event for both Timer A and Timer B of.."
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|
newline
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bitfld.long 0x10 2.--3. "SYNC1,Synchronize GPT Timer 1" "No Sync. GPT1 is not affected. ,A timeout event for Timer A of GPT1 is triggered,A timeout event for Timer B of GPT1 is triggered,A timeout event for both Timer A and Timer B of.."
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newline
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bitfld.long 0x10 0.--1. "SYNC0,Synchronize GPT Timer 0" "No Sync. GPT0 is not affected. ,A timeout event for Timer A of GPT0 is triggered,A timeout event for Timer B of GPT0 is triggered,A timeout event for both Timer A and Timer B of.."
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group.long 0x18++0x3F
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line.long 0x00 "IMR,Interrupt MaskThis register is used to enable the interrupts.Associated registers:RIS. MIS. ICLR"
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|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 13. "DMABIM,Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS" "Disable Interrupt,Enable Interrupt"
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newline
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rbitfld.long 0x00 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 11. "TBMIM,Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 10. "CBEIM,Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 9. "CBMIM,Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 8. "TBTOIM,Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS" "Disable Interrupt,Enable Interrupt"
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newline
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rbitfld.long 0x00 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 5. "DMAAIM,Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 4. "TAMIM,Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x00 2. "CAEIM,Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 1. "CAMIM,Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS" "Disable Interrupt,Enable Interrupt"
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newline
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bitfld.long 0x00 0. "TATOIM,Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS" "Disable Interrupt,Enable Interrupt"
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line.long 0x04 "RIS,Raw Interrupt StatusAssociated registers:IMR. MIS. ICLR"
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hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 13. "DMABRIS,GPT Timer B DMA Done Raw Interrupt Status0: Transfer has not completed1: Transfer has completed" "Transfer has not completed,Transfer has completed"
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newline
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bitfld.long 0x04 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x04 11. "TBMRIS,GPT Timer B Match Raw Interrupt0: The match value has not been reached1: The match value is reached.TBMR.TBMIE is set and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode" "The match value has not been reached,The match value is reached.TBMR.TBMIE is set and.."
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newline
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bitfld.long 0x04 10. "CBERIS,GPT Timer B Capture Mode Event Raw Interrupt0: The event has not occured.1: The event has occured.This interrupt asserts when the subtimer is configured in Input Edge-Time mode" "The event has not occured,The event has occured.This interrupt asserts.."
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newline
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bitfld.long 0x04 9. "CBMRIS,GPT Timer B Capture Mode Match Raw Interrupt0: The capture mode match for Timer B has not occurred.1: A capture mode match has occurred for Timer B" "The capture mode match for Timer B has not..,A capture mode match has occurred for Timer B"
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newline
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bitfld.long 0x04 8. "TBTORIS,GPT Timer B Time-out Raw Interrupt0: Timer B has not timed out1: Timer B has timed out" "Timer B has not timed out,Timer B has timed out"
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newline
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bitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x04 5. "DMAARIS,GPT Timer A DMA Done Raw Interrupt Status0: Transfer has not completed1: Transfer has completed" "Transfer has not completed,Transfer has completed"
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newline
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bitfld.long 0x04 4. "TAMRIS,GPT Timer A Match Raw Interrupt0: The match value has not been reached1: The match value is reached.TAMR.TAMIE is set and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode" "The match value has not been reached,The match value is reached.TAMR.TAMIE is set and.."
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newline
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bitfld.long 0x04 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x04 2. "CAERIS,GPT Timer A Capture Mode Event Raw Interrupt0: The event has not occured.1: The event has occured.This interrupt asserts when the subtimer is configured in Input Edge-Time mode" "The event has not occured,The event has occured.This interrupt asserts.."
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newline
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bitfld.long 0x04 1. "CAMRIS,GPT Timer A Capture Mode Match Raw Interrupt0: The capture mode match for Timer A has not occurred.1: A capture mode match has occurred for Timer A" "The capture mode match for Timer A has not..,A capture mode match has occurred for Timer A"
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newline
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bitfld.long 0x04 0. "TATORIS,GPT Timer A Time-out Raw Interrupt0: Timer A has not timed out1: Timer A has timed out" "Timer A has not timed out,Timer A has timed out"
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line.long 0x08 "MIS,Masked Interrupt StatusValues are result of bitwise AND operation between RIS and IMRAssosciated clear register: ICLR"
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hexmask.long.tbyte 0x08 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 13. "DMABMIS," "0,1"
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newline
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bitfld.long 0x08 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x08 11. "TBMMIS," "0,1"
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newline
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bitfld.long 0x08 10. "CBEMIS," "0,1"
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newline
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bitfld.long 0x08 9. "CBMMIS," "0,1"
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newline
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bitfld.long 0x08 8. "TBTOMIS," "0,1"
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newline
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bitfld.long 0x08 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x08 5. "DMAAMIS," "0,1"
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newline
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bitfld.long 0x08 4. "TAMMIS," "0,1"
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newline
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bitfld.long 0x08 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x08 2. "CAEMIS," "0,1"
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newline
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bitfld.long 0x08 1. "CAMMIS," "0,1"
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newline
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bitfld.long 0x08 0. "TATOMIS," "0,1"
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line.long 0x0C "ICLR,Interrupt ClearThis register is used to clear status bits in the RIS and MIS registers"
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hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 13. "DMABINT," "0,1"
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newline
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bitfld.long 0x0C 12. "RESERVED12,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x0C 11. "TBMCINT," "0,1"
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newline
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bitfld.long 0x0C 10. "CBECINT," "0,1"
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newline
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bitfld.long 0x0C 9. "CBMCINT," "0,1"
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newline
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bitfld.long 0x0C 8. "TBTOCINT," "0,1"
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newline
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rbitfld.long 0x0C 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x0C 5. "DMAAINT," "0,1"
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newline
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bitfld.long 0x0C 4. "TAMCINT," "0,1"
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newline
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bitfld.long 0x0C 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x0C 2. "CAECINT," "0,1"
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newline
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bitfld.long 0x0C 1. "CAMCINT," "0,1"
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newline
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bitfld.long 0x0C 0. "TATOCINT," "0,1"
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line.long 0x10 "TAILR,Timer A Interval Load Register"
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line.long 0x14 "TBILR,Timer B Interval Load Register"
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line.long 0x18 "TAMATCHR,Timer A Match RegisterInterrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode.In Edge-Count mode. this register along with TAILR. determines how many edge events are counted.The total.."
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line.long 0x1C "TBMATCHR,Timer B Match Register When a GPT is configured to one of the 32-bit modes. the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR.Reads from this register return the current match value of Timer B and writes.."
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hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "TBMATCHR,GPT Timer B Match Register"
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line.long 0x20 "TAPR,Timer A Pre-scaleThis register allows software to extend the range of the timers when they are used individually.When in one-shot or periodic down count modes. this register acts as a true prescaler for the timer counter.When acting as a true.."
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hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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abitfld.long 0x20 0.--7. "TAPSR,Timer A Pre-scale.Prescaler ratio in one-shot and periodic count mode is TAPSR + 1 that is:0: Prescaler ratio =" "0x00=Prescaler ratio = 1,0x01=Prescaler ratio = 2,0x02=Prescaler ratio = 3,0xFF=Prescaler ratio = 256"
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line.long 0x24 "TBPR,Timer B Pre-scaleThis register allows software to extend the range of the timers when they are used individually.When in one-shot or periodic down count modes. this register acts as a true prescaler for the timer counter.When acting as a true.."
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hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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abitfld.long 0x24 0.--7. "TBPSR,Timer B Pre-scale.Prescale ratio in one-shot and periodic count mode is TBPSR + 1 that is:0: Prescaler ratio =" "0x00=Prescaler ratio = 1,0x01=Prescaler ratio = 2,0x02=Prescaler ratio = 3,0xFF=Prescaler ratio = 256"
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line.long 0x28 "TAPMR,Timer A Pre-scale MatchThis register allows software to extend the range of the TAMATCHR when used individually"
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hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x28 0.--7. 1. "TAPSMR,GPT Timer A Pre-scale Match"
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line.long 0x2C "TBPMR,Timer B Pre-scale MatchThis register allows software to extend the range of the TBMATCHR when used individually"
|
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hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x2C 0.--7. 1. "TBPSMR,GPT Timer B Pre-scale Match Register"
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line.long 0x30 "TAR,Timer A RegisterThis register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes"
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line.long 0x34 "TBR,Timer B RegisterThis register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes"
|
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line.long 0x38 "TAV,Timer A Value When read. this register shows the current. free-running value of Timer A in all modes"
|
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line.long 0x3C "TBV,Timer B Value When read. this register shows the current. free-running value of Timer B in all modes"
|
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rgroup.long 0x5C++0x13
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line.long 0x00 "TAPS,Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD. this register is updated with the value from TAPR register either on the next cycle or on the next timeout.This register shows the current value of the Timer A.."
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "PSS,GPT Timer A Pre-scaler"
|
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line.long 0x04 "TBPS,Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD. this register is updated with the value from TBPR register either on the next cycle or on the next timeout.This register shows the current value of the Timer B.."
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
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newline
|
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hexmask.long.byte 0x04 0.--7. 1. "PSS,GPT Timer B Pre-scaler"
|
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line.long 0x08 "TAPV,Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode"
|
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hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
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newline
|
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hexmask.long.byte 0x08 0.--7. 1. "PSV,GPT Timer A Pre-scaler Value"
|
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line.long 0x0C "TBPV,Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode"
|
|
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x0C 0.--7. 1. "PSV,GPT Timer B Pre-scaler Value"
|
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line.long 0x10 "DMAEV,DMA Event This register allows software to enable/disable GPT DMA trigger events"
|
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hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved field"
|
|
newline
|
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bitfld.long 0x10 11. "TBMDMAEN,GPT Timer B Match DMA Trigger Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 10. "CBEDMAEN,GPT Timer B Capture Event DMA Trigger Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 9. "CBMDMAEN,GPT Timer B Capture Match DMA Trigger Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 8. "TBTODMAEN,GPT Timer B Time-Out DMA Trigger Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 5.--7. "RESERVED5,Software should not rely on the value of a reserved field" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x10 4. "TAMDMAEN,GPT Timer A Match DMA Trigger Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
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bitfld.long 0x10 2. "CAEDMAEN,GPT Timer A Capture Event DMA Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CAMDMAEN,GPT Timer A Capture Match DMA Trigger Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 0. "TATODMAEN,GPT Timer A Time-Out DMA Trigger Enable" "0,1"
|
|
rgroup.long 0xFB0++0x07
|
|
line.long 0x00 "VERSION,Peripheral VersionThis register provides information regarding the GPT version"
|
|
line.long 0x04 "ANDCCP,Combined CCP OutputThis register is used to logically AND CCP output pairs for each timer"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 1. "LD_TO_EN,PWM assertion would happen at timeout0: PWM assertion happens when counter matches load value1: PWM assertion happens at timeout of the counter" "PWM assertion happens when counter matches load..,PWM assertion happens at timeout of the counter"
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|
newline
|
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bitfld.long 0x04 0. "CCP_AND_EN,Enables AND operation of the CCP outputs for timers A and B.0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers.1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals.." "PWM outputs of Timer A and Timer B are the..,PWM output of Timer A is ANDed version of Timer.."
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tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "Hidden"
|
|
base ad:0x00
|
|
rgroup.quad 0x00++0x07
|
|
line.quad 0x00 "JSTATE4,Digital JTAG State Register"
|
|
bitfld.quad 0x00 62. "MODACT10,CLK.I2C0" "0,1"
|
|
bitfld.quad 0x00 61. "MODACT11,CLK.I2S0" "0,1"
|
|
bitfld.quad 0x00 60. "MODACT12,CLK.DMA" "0,1"
|
|
bitfld.quad 0x00 59. "MODACT13,CLK.TRNG" "0,1"
|
|
bitfld.quad 0x00 58. "MODACT14,CLK.SEC" "0,1"
|
|
bitfld.quad 0x00 57. "MODACT15,CLK.PKA" "0,1"
|
|
bitfld.quad 0x00 56. "MODACT16,CLK.SSI0" "0,1"
|
|
bitfld.quad 0x00 55. "MODACT17,CLK.SSI1" "0,1"
|
|
bitfld.quad 0x00 54. "MODACT18,CLK.UART0" "0,1"
|
|
bitfld.quad 0x00 53. "MODACT19,CLK.UART1" "0,1"
|
|
newline
|
|
bitfld.quad 0x00 51.--52. "PWRSTATE0,CPU%CORTEXM_PM" "0,1,2,3"
|
|
bitfld.quad 0x00 49. "MODACT5,MCU.CPU_PD" "0,1"
|
|
bitfld.quad 0x00 48. "MODACT4,MCU.SERIAL_PD" "0,1"
|
|
bitfld.quad 0x00 47. "MODACT3,MCU.PERIPH_PD" "0,1"
|
|
bitfld.quad 0x00 46. "MODACT2,MCU.RFCORE_PD" "0,1"
|
|
bitfld.quad 0x00 45. "MODACT1,MCU.VIMS_PD" "0,1"
|
|
bitfld.quad 0x00 44. "MODACT0,MCU.MCU_CTL" "0,1"
|
|
bitfld.quad 0x00 43. "MODACT9,CLK.XOSC_EN" "0,1"
|
|
bitfld.quad 0x00 42. "MODACT8,CLK.SCLK_HF_SRC" "0,1"
|
|
bitfld.quad 0x00 36.--39. "PWRSTATE1,RF%LPRF_PM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 28.--35. 1. "MODACT7,PRCM:PWRPROFSTAT"
|
|
bitfld.quad 0x00 27. "MODACT20,PC_Error" "0,1"
|
|
hexmask.quad.tbyte 0x00 6.--26. 1. "PC,PC"
|
|
bitfld.quad 0x00 0.--5. "MODACT6,Interrupts%HWI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
tree.end
|
|
tree "I2C"
|
|
repeat 2. (list 0. 1. )(list ad:0x40002000 ad:0x4002A000 )
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SOAR,Slave Own AddressThis register consists of seven address bits that identify this I2C device on the I2C bus"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--6. 1. "OAR,I2C slave own addressThis field specifies bits a6 through a0 of the slave address"
|
|
line.long 0x04 "SSTAT,Slave Status Note: This register shares address with SCTL. meaning that this register functions as a control register when written. and a status register when"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 2. "FBR,First byte received0: The first byte has not been received.1: The first byte following the slave's own address has been received.This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the SDR.." "The first byte has not been received,The first byte following the slave's own address.."
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|
newline
|
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bitfld.long 0x04 1. "TREQ,Transmit request0: No outstanding transmit request.1: The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the SDR register" "No outstanding transmit request,The I2C controller has been addressed as a slave.."
|
|
bitfld.long 0x04 0. "RREQ,Receive request0: No outstanding receive data1: The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until data has been read from the SDR register." "No outstanding receive data,The I2C controller has outstanding receive data.."
|
|
wgroup.long 0x04++0x17
|
|
line.long 0x00 "SCTL,Slave ControlNote: This register shares address with SSTAT. meaning that this register functions as a control register when written. and a status register when"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved field"
|
|
bitfld.long 0x00 0. "DA,Device active0: Disables the I2C slave operation1: Enables the I2C slave operation" "Disables the I2C slave operation,Enables the I2C slave operation"
|
|
line.long 0x04 "SDR,Slave DataThis register contains the data to be transmitted when in the Slave Transmit state. and the data received when in the Slave Receive state"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "DATA,Data for transferThis field contains the data for transfer during a slave receive or transmit operation"
|
|
line.long 0x08 "SIMR,Slave Interrupt MaskThis register controls whether a raw interrupt is promoted to a controller interrupt"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 2. "STOPIM,Stop condition interrupt mask0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt controller." "The SRIS.STOPRIS interrupt is suppressed and not..,The SRIS.STOPRIS interrupt is enabled and sent.."
|
|
newline
|
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bitfld.long 0x08 1. "STARTIM,Start condition interrupt mask0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt controller." "The SRIS.STARTRIS interrupt is suppressed and..,The SRIS.STARTRIS interrupt is enabled and sent.."
|
|
bitfld.long 0x08 0. "DATAIM,Data interrupt mask0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt controller.1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt controller" "The SRIS.DATARIS interrupt is suppressed and not..,The SRIS.DATARIS interrupt is enabled and sent.."
|
|
line.long 0x0C "SRIS,Slave Raw Interrupt StatusThis register shows the unmasked interrupt status"
|
|
hexmask.long 0x0C 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 2. "STOPRIS,Stop condition raw interrupt status0: No interrupt1: A Stop condition interrupt is pending.This bit is cleared by writing a 1 to SICR.STOPIC" "No interrupt,A Stop condition interrupt is.."
|
|
newline
|
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bitfld.long 0x0C 1. "STARTRIS,Start condition raw interrupt status0: No interrupt1: A Start condition interrupt is pending.This bit is cleared by writing a 1 to SICR.STARTIC" "No interrupt,A Start condition interrupt is.."
|
|
bitfld.long 0x0C 0. "DATARIS,Data raw interrupt status0: No interrupt1: A data received or data requested interrupt is pending.This bit is cleared by writing a 1 to the SICR.DATAIC" "No interrupt,A data received or data requested.."
|
|
line.long 0x10 "SMIS,Slave Masked Interrupt StatusThis register show which interrupt is active (based on result from SRIS and SIMR)"
|
|
hexmask.long 0x10 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 2. "STOPMIS,Stop condition masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked Stop condition interrupt is pending.This bit is cleared by writing a 1 to the SICR.STOPIC" "An interrupt has not occurred or is..,An unmasked Stop condition interrupt is.."
|
|
newline
|
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bitfld.long 0x10 1. "STARTMIS,Start condition masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked Start condition interrupt is pending.This bit is cleared by writing a 1 to the SICR.STARTIC" "An interrupt has not occurred or is..,An unmasked Start condition interrupt is.."
|
|
bitfld.long 0x10 0. "DATAMIS,Data masked interrupt status0: An interrupt has not occurred or is masked/disabled.1: An unmasked data received or data requested interrupt is pending.This bit is cleared by writing a 1 to the SICR.DATAIC" "An interrupt has not occurred or is..,An unmasked data received or data requested.."
|
|
line.long 0x14 "SICR,Slave Interrupt ClearThis register clears the raw interrupt SRIS"
|
|
hexmask.long 0x14 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 2. "STOPIC,Stop condition interrupt clearWriting 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "STARTIC,Start condition interrupt clearWriting 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS" "0,1"
|
|
bitfld.long 0x14 0. "DATAIC,Data interrupt clearWriting 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS" "0,1"
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "MSA,Master Salve AddressThis register contains seven address bits of the slave to be accessed by the master (a6-a0). and an RS bit determining if the next operation is a receive or transmit"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 1.--7. 1. "SA,I2C master slave addressDefines which slave is addressed for the transaction in master mode"
|
|
newline
|
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bitfld.long 0x00 0. "RS,Receive or SendThis bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA" "Transmit/send data to slave,Receive data from slave"
|
|
line.long 0x04 "MSTAT,Master Status"
|
|
hexmask.long 0x04 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 6. "BUSBSY,Bus busy0: The I2C bus is idle.1: The I2C bus is busy.The bit changes based on the MCTRL.START and MCTRL.STOP conditions" "The I2C bus is idle,The I2C bus is busy.The bit changes based on the.."
|
|
newline
|
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bitfld.long 0x04 5. "IDLE,I2C idle0: The I2C controller is not idle.1: The I2C controller is idle" "The I2C controller is not idle,The I2C controller is idle"
|
|
bitfld.long 0x04 4. "ARBLST,Arbitration lost0: The I2C controller won arbitration.1: The I2C controller lost arbitration" "The I2C controller won arbitration,The I2C controller lost arbitration"
|
|
newline
|
|
bitfld.long 0x04 3. "DATACK_N,Data Was Not Acknowledge0: The transmitted data was acknowledged.1: The transmitted data was not acknowledged" "The transmitted data was acknowledged,The transmitted data was not acknowledged"
|
|
bitfld.long 0x04 2. "ADRACK_N,Address Was Not Acknowledge0: The transmitted address was acknowledged.1: The transmitted address was not acknowledged" "The transmitted address was acknowledged,The transmitted address was not acknowledged"
|
|
newline
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bitfld.long 0x04 1. "ERR,Error0: No error was detected on the last operation.1: An error occurred on the last operation" "No error was detected on the last operation,An error occurred on the last operation"
|
|
bitfld.long 0x04 0. "BUSY,I2C busy0: The controller is idle.1: The controller is busy.When this bit-field is set the other status bits are not valid.Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been.." "The controller is idle,The controller is busy.When this bit-field is.."
|
|
wgroup.long 0x804++0x1F
|
|
line.long 0x00 "MCTRL,Master ControlThis register accesses status bits when read and control bits when written"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 3. "ACK,Data acknowledge enable0: The received data byte is not acknowledged automatically by the master.1: The received data byte is acknowledged automatically by the master.This bit-field must be cleared when the I2C bus controller requires no further.." "The received data byte is not acknowledged..,The received data byte is acknowledged.."
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|
newline
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bitfld.long 0x00 2. "STOP,This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.0: The controller does not generate the Stop condition.1: The controller generates the Stop condition" "The controller does not generate the Stop..,The controller generates the Stop condition"
|
|
bitfld.long 0x00 1. "START,This bit-field generates the Start or Repeated Start condition" "The controller does not generate the Start..,The controller generates the Start condition"
|
|
newline
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bitfld.long 0x00 0. "RUN,I2C master enable0: The master is disabled.1: The master is enabled to transmit or receive data." "The master is disabled,The master is enabled to transmit or receive data"
|
|
line.long 0x04 "MDR,Master DataThis register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x04 0.--7. 1. "DATA,When Read: Last RX Data is returnedWhen Written: Data is transferred during TX transaction"
|
|
line.long 0x08 "MTPR,I2C Master Timer PeriodThis register specifies the period of the SCL clock"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 7. "TPR_7,Must be set to 0 to set TPR" "0,1"
|
|
newline
|
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hexmask.long.byte 0x08 0.--6. 1. "TPR,SCL clock periodThis field specifies the period of the SCL clock.SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRDwhere:SCL_PRD is the SCL line period (I2C clock).TPR is the timer period register value (range of 1 to 127)SCL_LP is the SCL low period.."
|
|
line.long 0x0C "MIMR,Master Interrupt MaskThis register controls whether a raw interrupt is promoted to a controller interrupt"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "IM,Interrupt mask0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt controller.1: The master interrupt is sent to the interrupt controller when the MRIS.RIS is set." "The MRIS.RIS interrupt is suppressed and not..,The master interrupt is sent to the interrupt.."
|
|
line.long 0x10 "MRIS,Master Raw Interrupt StatusThis register show the unmasked interrupt status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "RIS,Raw interrupt status0: No interrupt1: A master interrupt is pending.This bit is cleared by writing 1 to the MICR.IC bit" "No interrupt,A master interrupt is pending.This.."
|
|
line.long 0x14 "MMIS,Master Masked Interrupt StatusThis register show which interrupt is active (based on result from MRIS and MIMR)"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "MIS,Masked interrupt status0: An interrupt has not occurred or is masked.1: A master interrupt is pending.This bit is cleared by writing 1 to the MICR.IC bit" "An interrupt has not occurred or is masked,A master interrupt is pending.This bit is.."
|
|
line.long 0x18 "MICR,Master Interrupt ClearThis register clears the raw and masked interrupt"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "IC,Interrupt clearWriting 1 to this bit clears MRIS.RIS and MMIS.MIS .Reading this register returns no meaningful data" "0,1"
|
|
line.long 0x1C "MCR,Master ConfigurationThis register configures the mode (Master or Slave) and sets the interface for test mode loopback"
|
|
hexmask.long 0x1C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 5. "SFE,I2C slave function enable" "Slave mode is disabled.,Slave mode is enabled."
|
|
newline
|
|
bitfld.long 0x1C 4. "MFE,I2C master function enable" "Master mode is disabled.,Master mode is enabled."
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|
rbitfld.long 0x1C 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x1C 0. "LPBK,I2C loopback0: Normal operation1: Loopback operation (test mode)" "Normal operation,Loopback operation (test mode)"
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|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "I2S0"
|
|
base ad:0x40021000
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "AIFWCLKSRC,WCLK Source Selection"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 2. "WCLK_INV,Inverts WCLK source (pad or internal) when set.0: Not inverted1: Inverted" "Not inverted,Inverted"
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|
newline
|
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bitfld.long 0x00 0.--1. "WCLK_SRC,Selects WCLK source for AIF (should be the same as the BCLK source)" "None ('0'),External WCLK generator from pad,Internal WCLK generator from module PRCM,Not supported. Will give same WCLK as 'NONE'.."
|
|
line.long 0x04 "AIFDMACFG,DMA Buffer Size Configuration"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "END_FRAME_IDX,Defines the length of the DMA buffer"
|
|
line.long 0x08 "AIFDIRCFG,Pin Direction"
|
|
hexmask.long 0x08 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 4.--5. "AD1,Configures the AD1 audio data pin usage:0x3: Reserved" "Not in use (disabled),Input mode,Output mode,?"
|
|
newline
|
|
rbitfld.long 0x08 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "AD0,Configures the AD0 audio data pin usage:0x3: Reserved" "Not in use (disabled),Input mode,Output mode,?"
|
|
line.long 0x0C "AIFFMTCFG,Serial Interface Format Configuration"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
abitfld.long 0x0C 8.--15. "DATA_DELAY,The number of BCLK periods between a WCLK edge and MSB of the first word in a phase:0x00: LJF and DSP" "0x00=LJF and DSP format,0x01=I2S and DSP format,0x02=RJF format,0xFF=RJF format"
|
|
newline
|
|
bitfld.long 0x0C 7. "MEM_LEN_24,The size of each word stored to or loaded from memory" "16-bit (one 16 bit access per sample),24-bit (one 8 bit and one 16 bit locked access.."
|
|
newline
|
|
bitfld.long 0x0C 6. "SMPL_EDGE,On the serial audio interface data (and wclk) is sampled and clocked out on opposite edges of BCLK" "Data is sampled on the negative edge and clocked..,Data is sampled on the positive edge and clocked.."
|
|
newline
|
|
bitfld.long 0x0C 5. "DUAL_PHASE,Selects dual- or single-phase format.0: Single-phase: DSP format1" "Single-phase,Dual-phase"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. "WORD_LEN,Number of bits per word (8-24):In single-phase format this is the exact number of bits per word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "AIFWMASK0,Word Selection Bit Mask for Pin 0"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "MASK,Bit-mask indicating valid channels in a frame on AD0.In single-phase mode each bit represents one channel starting with LSB for the first word in the frame"
|
|
line.long 0x14 "AIFWMASK1,Word Selection Bit Mask for Pin 1"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "MASK,Bit-mask indicating valid channels in a frame on AD1.In single-phase mode each bit represents one channel starting with LSB for the first word in the frame"
|
|
line.long 0x18 "AIFWMASK2,Internal"
|
|
line.long 0x1C "AIFPWMVALUE,Audio Interface PWM Debug Value"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
abitfld.long 0x1C 0.--15. "PULSE_WIDTH,The value written to this register determines the width of the active high PWM pulse (pwm_debug) which starts together with MSB of the first output word in a DMA" "0x0000=Constant low,0x0001=Width of the pulse (number of BCLK cycles..,0xFFFE=Width of the pulse (number of BCLK cycles..,0xFFFF=Constant high"
|
|
line.long 0x20 "AIFINPTRNEXT,DMA Input Buffer Next Pointer"
|
|
line.long 0x24 "AIFINPTR,DMA Input Buffer Current Pointer"
|
|
line.long 0x28 "AIFOUTPTRNEXT,DMA Output Buffer Next Pointer"
|
|
line.long 0x2C "AIFOUTPTR,DMA Output Buffer Current Pointer"
|
|
group.long 0x34++0x37
|
|
line.long 0x00 "STMPCTL,Samplestamp Generator Control Register"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x00 2. "OUT_RDY,Low until the output pins are ready to be started by the samplestamp generator" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "IN_RDY,Low until the input pins are ready to be started by the samplestamp generator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STMP_EN,Enables the samplestamp generator" "0,1"
|
|
line.long 0x04 "STMPXCNTCAPT0,Captured XOSC Counter Value. Capture Channel 0"
|
|
hexmask.long.word 0x04 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. "CAPT_VALUE,The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0)"
|
|
line.long 0x08 "STMPXPER,XOSC Period Value"
|
|
hexmask.long.word 0x08 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 0.--15. 1. "VALUE,The number of 24 MHz clock cycles in the previous WCLK period (that is - the next value of the XOSC counter at the positive WCLK edge had it not been reset to 0).The value is cleared when STMPCTL.STMP_EN = 0."
|
|
line.long 0x0C "STMPWCNTCAPT0,Captured WCLK Counter Value. Capture Channel 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x0C 0.--15. 1. "CAPT_VALUE,The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel 0)"
|
|
line.long 0x10 "STMPWPER,WCLK Counter Period Value"
|
|
hexmask.long.word 0x10 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "VALUE,Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer"
|
|
line.long 0x14 "STMPINTRIG,WCLK Counter Trigger Value for Input Pins"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "IN_START_WCNT,Compare value used to start the incoming audio streams.This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very.."
|
|
line.long 0x18 "STMPOUTTRIG,WCLK Counter Trigger Value for Output Pins"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "OUT_START_WCNT,Compare value used to start the outgoing audio streams.This bit field must equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very.."
|
|
line.long 0x1C "STMPWSET,WCLK Counter Set Operation"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "VALUE,WCLK counter modification: Sets the running WCLK counter equal to the written value"
|
|
line.long 0x20 "STMPWADD,WCLK Counter Add Operation"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "VALUE_INC,WCLK counter modification: Adds the written value to the running WCLK counter"
|
|
line.long 0x24 "STMPXPERMIN,XOSC Minimum Period ValueMinimum Value of STMPXPER"
|
|
hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "VALUE,Each time STMPXPER is updated the value is also loaded into this register provided that the value is smaller than the current value in this register.When written the register is reset to 0xFFFF (65535) regardless of the value written.The minimum.."
|
|
line.long 0x28 "STMPWCNT,Current Value of WCNT"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "CURR_VALUE,Current value of the WCLK counter"
|
|
line.long 0x2C "STMPXCNT,Current Value of XCNT"
|
|
hexmask.long.word 0x2C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x2C 0.--15. 1. "CURR_VALUE,Current value of the XOSC counter latched when reading STMPWCNT"
|
|
line.long 0x30 "STMPXCNTCAPT1,Internal"
|
|
hexmask.long.word 0x30 16.--31. 1. "RESERVED16,Internal"
|
|
newline
|
|
hexmask.long.word 0x30 0.--15. 1. "CAPT_VALUE,Internal"
|
|
line.long 0x34 "STMPWCNTCAPT1,Internal"
|
|
hexmask.long.word 0x34 16.--31. 1. "RESERVED16,Internal"
|
|
newline
|
|
hexmask.long.word 0x34 0.--15. 1. "CAPT_VALUE,Internal"
|
|
group.long 0x70++0x0F
|
|
line.long 0x00 "IRQMASK,Interrupt Mask RegisterSelects mask states of the flags in IRQFLAGS that contribute to the I2S_IRQ event"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 5. "AIF_DMA_IN,IRQFLAGS.AIF_DMA_IN interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "AIF_DMA_OUT,IRQFLAGS.AIF_DMA_OUT interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "WCLK_TIMEOUT,IRQFLAGS.WCLK_TIMEOUT interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 2. "BUS_ERR,IRQFLAGS.BUS_ERR interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 1. "WCLK_ERR,IRQFLAGS.WCLK_ERR interrupt mask0: Disable1: Enable" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 0. "PTR_ERR,IRQFLAGS.PTR_ERR interrupt mask.0: Disable1: Enable" "Disable,Enable"
|
|
line.long 0x04 "IRQFLAGS,Raw Interrupt Status Register"
|
|
hexmask.long 0x04 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "AIF_DMA_IN,Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT) see description of AIFINPTRNEXT register for details" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. "AIF_DMA_OUT,Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTRNEXT) see description of AIFOUTPTRNEXT register for details" "0,1"
|
|
newline
|
|
bitfld.long 0x04 3. "WCLK_TIMEOUT,Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. "BUS_ERR,Set when a DMA operation is not completed in time (that is audio output buffer underflow or audio input buffer overflow)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. "WCLK_ERR,Set when: - An unexpected WCLK edge occurs during the data delay period of a phase" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "PTR_ERR,Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time" "0,1"
|
|
line.long 0x08 "IRQSET,Interrupt Set Register"
|
|
hexmask.long 0x08 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 5. "AIF_DMA_IN," "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "AIF_DMA_OUT," "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "WCLK_TIMEOUT," "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "BUS_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "WCLK_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "PTR_ERR," "0,1"
|
|
line.long 0x0C "IRQCLR,Interrupt Clear Register"
|
|
hexmask.long 0x0C 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 5. "AIF_DMA_IN," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "AIF_DMA_OUT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "WCLK_TIMEOUT," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "BUS_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "WCLK_ERR," "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "PTR_ERR," "0,1"
|
|
tree.end
|
|
tree "IOC"
|
|
base ad:0x40081000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IOCFG0,Configuration of DIO0"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO0Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO1"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO1Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
repeat 15. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO17"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO17Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
repeat 15. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "IOCFG$1,Configuration of DIO32"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "RESERVED19,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18. "EDGE_IRQ_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO32Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
repeat.end
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "IOCFG43,Configuration of DIO43"
|
|
bitfld.long 0x00 31. "IOEV_MCU_WU_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert MCU_WU event1: Input edge detection asserts MCU_WU event" "Input edge detection does not assert MCU_WU event,Input edge detection asserts MCU_WU event"
|
|
newline
|
|
bitfld.long 0x00 30. "HYST_EN," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IE," "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "WU_CFG,If DIO is configured GPIO or non-AON peripheral signals PORT_ID 0x00 or >0x08:00: No wake-up01: No wake-up10: Wakes up from shutdown if this pad is going low.11: Wakes up from shutdown if this pad is going high.If IO is configured for AON.." "No wake-up,Wakeup disabled10,?,Wakeup enabled Polarity is controlled.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IOMODE,IO Mode Not applicable for IO configured for AON periph" "?,?,Reserved,Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "IOEV_AON_PROG2_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG2 event1: Input edge detection asserts AON_PROG2 event" "Input edge detection does not assert AON_PROG2..,Input edge detection asserts AON_PROG2 event"
|
|
newline
|
|
bitfld.long 0x00 22. "IOEV_AON_PROG1_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG1 event1: Input edge detection asserts AON_PROG1 event" "Input edge detection does not assert AON_PROG1..,Input edge detection asserts AON_PROG1 event"
|
|
newline
|
|
bitfld.long 0x00 21. "IOEV_AON_PROG0_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert AON_PROG0 event1: Input edge detection asserts AON_PROG0 event" "Input edge detection does not assert AON_PROG0..,Input edge detection asserts AON_PROG0 event"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "EDGE_IRQ_EN,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "EDGE_DET,Enable generation of edge detection events on this IO " "No edge detection,Negative edge detection,Positive edge detection,Positive and negative edge detection"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PULL_CTL,Pull control" "?,Pull down,Pull up,No pull"
|
|
newline
|
|
bitfld.long 0x00 13. "SLEW_RED," "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "IOCURR,Selects IO current mode of this IO." "Low-Current (LC) mode: Min 2 mA when IOSTR is..,High-Current (HC) mode: Min 4 mA when IOSTR is..,Extended-Current (EC) mode: Min 8 mA for double..,?"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "IOSTR,Select source for drive strength control of this IO.This setting controls the drive strength of the Low-Current (LC) mode" "Automatic drive strength controlled by AON..,Minimum drive strength controlled by..,Medium drive strength controlled by..,Maximum drive strength controlled by.."
|
|
newline
|
|
bitfld.long 0x00 8. "IOEV_RTC_EN,Event asserted by this IO when edge detection is enabled0: Input edge detection does not assert RTC event1: Input edge detection asserts RTC event" "Input edge detection does not assert RTC event,Input edge detection asserts RTC event"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "PORT_ID,Selects usage for DIO43Note: This field should not be written other than the times when PORT_ID value is specifically required to change"
|
|
tree.end
|
|
tree "NVMNW"
|
|
base ad:0x58032000
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "CPU_CONNECT_0,Directly connect peripheral publisher port to application processor"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 1. "CPUSS0_CONN,CPUSS0 connect bit" "The CPU is not connected.,The CPU is connected."
|
|
rgroup.long 0x1020++0x03
|
|
line.long 0x00 "IIDX,Interrupt Index Register:The IIDX register provides the highest priority enabled interrupt index.PSD compliant register.Note that it is not recommended to use this register if the system clock isrunning at a slower clock frequency than the.."
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "STAT,Indicates which interrupt has fired" "No Interrupt Pending,DONE Interrupt Pending"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "IMASK,Interrupt Mask Register:The IMASK register holds the current interrupt mask settings"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
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bitfld.long 0x00 0. "DONE,Interrupt mask for DONE:0: Interrupt is disabled in MIS register1: Interrupt is enabled in MIS register" "Interrupt is disabled in MIS register,Interrupt is enabled in MIS register"
|
|
rgroup.long 0x1030++0x03
|
|
line.long 0x00 "RIS,Raw Interrupt Status Register:The RIS register reflects all pending interrupts. regardless of masking"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
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bitfld.long 0x00 0. "DONE,NoWrapper operation completed.This interrupt bit is set by firmware or the corresponding bit in the ISET register.It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority" "Interrupt did not occur,Interrupt occurred"
|
|
rgroup.long 0x1038++0x03
|
|
line.long 0x00 "MIS,Masked Interrupt Status Register:The MIS register is a bit-wise AND of the contents of the IMASK and RIS registers"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 0. "DONE,NoWrapper operation completed.This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits" "Masked interrupt did not occur,Masked interrupt occurred"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "ISET,Interrupt Set Register:The ISET register allows software to write a 1 to set corresponding interrupt"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
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bitfld.long 0x00 0. "DONE," "Writing a 0 has no effect,Set IPSTANDARD.RIS bit"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "ICLR,Interrupt Clear Register"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 0. "DONE," "Writing a 0 has no effect,Clear IPSTANDARD.RIS bit"
|
|
rgroup.long 0x10E0++0x03
|
|
line.long 0x00 "EVT_MODE,Event mode register"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
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bitfld.long 0x00 0.--1. "INT0_CFG,Event line mode select for peripheral event" "The interrupt or event line is disabled.,The interrupt or event line is in software mode..,The interrupt or event line is in hardware mode..,?"
|
|
rgroup.long 0x10FC++0x0F
|
|
line.long 0x00 "DESC,Hardware Version Description Register:This register identifies the NoWrapper hardware version and feature set used"
|
|
hexmask.long.word 0x00 16.--31. 1. "MODULEID,Module ID"
|
|
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bitfld.long 0x00 12.--15. "FEATUREVER,Feature set" "Minimum Value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum Value"
|
|
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bitfld.long 0x00 8.--11. "INSTNUM,Instance number" "Smallest value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Highest possible value"
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|
newline
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bitfld.long 0x00 4.--7. "MAJREV,Major Revision" "Smallest value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Highest possible value"
|
|
newline
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bitfld.long 0x00 0.--3. "MINREV,Minor Revision" "Smallest value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Highest possible value"
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line.long 0x04 "CMDEXEC,Command Execute Register:Initiates execution of the command specified in the CMDTYPE register.This register is blocked for writes after being written to 1 and prior to STATCMD.DONE being set by the NoWrapper hardware.NoWrapper hardware clears.."
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|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0. "VAL,Command Execute valueInitiates execution of the command specified in the CMDTYPE register" "Command will not execute or is not executing in..,Command will execute or is executing in NoWrapper"
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|
line.long 0x08 "CMDTYPE,Command Type RegisterThis register specifies the type of command to be executed by the NoWrapper hardware.This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that.."
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|
bitfld.long 0x08 4.--6. "SIZE,Command size" "Operate on 1 flash word,Operate on 2 flash words,Operate on 4 flash words,Operate on 8 flash words,Operate on a flash sector,Operate on an entire flash bank,?,?"
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rbitfld.long 0x08 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x08 0.--2. "COMMAND,Command type" "No Operation,Program,Erase,Read Verify - Perform a standalone read verify..,Mode Change - Perform a mode change only no..,Clear Status - Clear status bits in FW_SMSTAT..,Blank Verify - Check whether a flash word is in..,?"
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line.long 0x0C "CMDCTL,Command Control RegisterThis register configures specific capabilities of the state machine for related tothe execution of a command.This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the.."
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hexmask.long.word 0x0C 22.--31. 1. "RESERVED22,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 21. "DATAVEREN,Enable invalid data verify" "Disable,Enable"
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newline
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bitfld.long 0x0C 20. "SSERASEDIS,Disable Stair-Step Erase" "Enable,Disable"
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|
newline
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bitfld.long 0x0C 19. "ERASEMASKDIS,Disable use of erase mask for eraseBit masking will not be used during erase verify" "Enable,Disable"
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newline
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bitfld.long 0x0C 18. "PROGMASKDIS,Disable use of program mask for programming.Bit masking will not be used during program verify" "Enable,Disable"
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|
newline
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bitfld.long 0x0C 17. "ECCGENOVR,Override hardware generation of ECC data for program" "Do not override,Override"
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|
newline
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bitfld.long 0x0C 16. "ADDRXLATEOVR,Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID" "Do not override,Override"
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newline
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bitfld.long 0x0C 15. "POSTVEREN,Enable verify after program or erase" "Disable,Enable"
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|
newline
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bitfld.long 0x0C 14. "PREVEREN,Enable verify before program or erase" "Disable,Enable"
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|
newline
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rbitfld.long 0x0C 13. "RESERVED13,Software should not rely on the value of a reserved" "0,1"
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|
newline
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bitfld.long 0x0C 9.--12. "REGIONSEL,Bank RegionA specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set" "?,Main Region,Non-Main Region,?,Trim Region,?,?,?,Engr Region,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x0C 4. "BANKSEL,Bank SelectA specific Bank ID can be written to this field to indicate to which bank an operation should be applied if CMDCTL.ADDRXLATEOVR is set" "?,Bank 0"
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newline
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bitfld.long 0x0C 0.--3. "MODESEL,ModeThis field is only used for the Mode Change command type" "Read Mode,?,Read Margin 0 Mode,?,Read Margin 1 Mode,?,Read Margin 0B Mode,Read Margin 1B Mode,?,Program Verify Mode,Program Single Word,Erase Verify Mode,Erase Sector,?,Program Multiple Word,Erase Bank"
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group.long 0x1120++0x07
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line.long 0x00 "CMDADDR,Command Address Register:This register forms the target address of a command"
|
|
line.long 0x04 "CMDBYTEN,Command Program Byte Enable Register:This register forms a per-byte enable for programming data"
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hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
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|
newline
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hexmask.long.byte 0x04 0.--7. 1. "VAL,Command Byte Enable value.A 1-bit per flash word byte value is placed in this register."
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|
group.long 0x112C++0x03
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line.long 0x00 "CMDDATAINDEX,Command Program Data Index Register:When multiple data registers are available for multi-word program. this registercan be written with an index which points to one of the data registers"
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hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--2. "VAL,Data register index" "Minimum value of VAL,?,?,?,?,?,?,Maximum value of VAL"
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|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
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group.long ($2+0x1130)++0x03
|
|
line.long 0x00 "CMDDATA$1,Command Data Register 0This register forms the data for a command"
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repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
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group.long ($2+0x1170)++0x03
|
|
line.long 0x00 "CMDDATA$1,Command Data Register 16This register forms the data for a command"
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|
repeat.end
|
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repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
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|
group.long ($2+0x11B0)++0x03
|
|
line.long 0x00 "CMDDATAECC$1,Command Data Register 0This register forms the ECC portion of the data for a command"
|
|
hexmask.long.byte 0x00 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here"
|
|
repeat.end
|
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group.long 0x11D0++0x0B
|
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line.long 0x00 "CMDWEPROTA,Command WriteErase Protect A RegisterThis register allows the first 32 sectors of the main region to be protected fromprogram or erase. with 1 bit protecting each sector"
|
|
line.long 0x04 "CMDWEPROTB,Command WriteErase Protect B RegisterThis register allows main region sectors to be protected from program anderase"
|
|
line.long 0x08 "CMDWEPROTC,Command WriteErase Protect C RegisterThis register allows main region sectors to be protected from program anderase"
|
|
group.long 0x1210++0x0B
|
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line.long 0x00 "CMDWEPROTNM,Command WriteErase Protect Non-Main RegisterThis register allows non-main region region sectors to be protectedfrom program and erase"
|
|
line.long 0x04 "CMDWEPROTTR,Command WriteErase Protect Trim RegisterThis register allows trim region sectors to be protectedfrom program and erase"
|
|
line.long 0x08 "CMDWEPROTEN,Command WriteErase Protect Engr RegisterThis register allows engr region sectors to be protectedfrom program and erase"
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|
group.long 0x13B0++0x07
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line.long 0x00 "CFGCMD,Command Configuration RegisterThis register configures specific capabilities of the state machine for related tothe execution of a command.This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by.."
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bitfld.long 0x00 6. "HOLDCLKSTREN,Enable pulse stretching for the clocking of the hold latches for inputs to theflash bank" "Disable,Enable"
|
|
newline
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bitfld.long 0x00 5. "CTRLCLKSTREN,Enable pulse stretching when generating a control clock to the flash bank from theNoWrapper" "Disable,Enable"
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|
newline
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bitfld.long 0x00 4. "RDCLKSTREN,Enable pulse stretching when generating a read clock to the flash bank from theNoWrapper" "Disable,Enable"
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|
newline
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bitfld.long 0x00 0.--3. "WAITSTATE,Wait State setting for program verify erase verify and read verify" "Minimum value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value"
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line.long 0x04 "CFGPCNT,Pulse Counter Configuration RegisterThis register allows further configuration of maximum pulse counts for program and erase operations.This register is blocked for writes after a 1 is written to the CMDEXECregister and prior to STATCMD.DONE.."
|
|
hexmask.long.word 0x04 20.--31. 1. "MAXERSPCNTVAL,Override maximum pulse count for erase with this value"
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|
newline
|
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rbitfld.long 0x04 17.--19. "RESERVED17,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x04 16. "MAXERSPCNTOVR,Override hard-wired maximum pulse count for erase" "Use hard-wired (default) value for maximum pulse..,Use value from MAXERSPCNTVAL field as maximum.."
|
|
newline
|
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hexmask.long.byte 0x04 4.--11. 1. "MAXPCNTVAL,Override maximum pulse counter with this value"
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|
newline
|
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rbitfld.long 0x04 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x04 0. "MAXPCNTOVR,Override hard-wired maximum pulse count" "Use hard-wired (default) value for maximum pulse..,Use value from MAXPCNTVAL field as maximum puse.."
|
|
rgroup.long 0x13D0++0x0F
|
|
line.long 0x00 "STATCMD,Command Status RegisterThis register contains status regarding completion and errors of commandexecution"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED13,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x00 12. "FAILMISC,Command failed due to error other than write/erase protect violation or verifyerror" "No Fail,Fail"
|
|
newline
|
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bitfld.long 0x00 8. "FAILINVDATA,Program command failed because an attempt was made to program a stored0 value to a 1" "No Fail,Fail"
|
|
newline
|
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bitfld.long 0x00 7. "FAILMODE,Command failed because a bank has been set to a mode other than READ.Program and Erase commands cannot be initiated unless all banks are in READmode" "No Fail,Fail"
|
|
newline
|
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bitfld.long 0x00 6. "FAILILLADDR,Command failed due to the use of an illegal address" "No Fail,Fail"
|
|
newline
|
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bitfld.long 0x00 5. "FAILVERIFY,Command failed due to verify error" "No Fail,Fail"
|
|
newline
|
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bitfld.long 0x00 4. "FAILWEPROT,Command failed due to Write/Erase Protect Sector Violation" "No Fail,Fail"
|
|
newline
|
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bitfld.long 0x00 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CMDINPROGRESS,Command In Progress" "Complete,In Progress"
|
|
newline
|
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bitfld.long 0x00 1. "CMDPASS,Command Pass - valid when CMD_DONE field is 1" "Fail,Pass"
|
|
newline
|
|
bitfld.long 0x00 0. "CMDDONE,Command Done" "Not Done,Done"
|
|
line.long 0x04 "STATADDR,Current Address Counter ValueRead only register giving read access to the state machine current address.A bank id. region id and address are stored in this register and are incremented asnecessary during execution of a command."
|
|
bitfld.long 0x04 26.--31. "RESERVED26,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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bitfld.long 0x04 21.--25. "BANKID,Current Bank IDA bank indicator is stored in this register which represents the current bank onwhich the state machine is operating" "?,Bank 0,Bank 1,?,Bank 2,?,?,?,Bank 3,?,?,?,?,?,?,?,Bank 4,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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|
newline
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bitfld.long 0x04 16.--20. "REGIONID,Current Region IDA region indicator is stored in this register which represents the current flash region on which the state machine is operating" "?,Main Region,Non-Main Region,?,Trim Region,?,?,?,Engr Region,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
newline
|
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hexmask.long.word 0x04 0.--15. 1. "BANKADDR,Current Bank AddressA bank offset address is stored in this register"
|
|
line.long 0x08 "STATPCNT,Current Pulse Count Register:Read only register giving read access to the state machine current pulse countvalue for program/erase operations."
|
|
hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.word 0x08 0.--11. 1. "PULSECNT,Current Pulse Counter Value"
|
|
line.long 0x0C "STATMODE,Mode Status RegisterIndicates any banks which not in READ mode. and it indicates the modewhich the bank(s) are in."
|
|
bitfld.long 0x0C 17. "BANK1TRDY,Bank 1T Ready.Bank(s) are ready for 1T access" "Not ready,Ready"
|
|
newline
|
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bitfld.long 0x0C 16. "BANK2TRDY,Bank 2T Ready.Bank(s) are ready for 2T access" "Not ready,Ready"
|
|
newline
|
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bitfld.long 0x0C 8.--11. "BANKMODE,Indicates mode of bank(s) that are not in READ mode" "Read Mode,?,Read Margin 0 Mode,?,Read Margin 1 Mode,?,Read Margin 0B Mode,Read Margin 1B Mode,?,Program Verify Mode,Program Single Word,Erase Verify Mode,Erase Sector,?,Program Multiple Word,Erase Bank"
|
|
newline
|
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hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x0C 0. "BANKNOTINRD,Bank not in read mode.Indicates which banks are not in READ mode" "?,Bank 0"
|
|
rgroup.long 0x13F0++0x0B
|
|
line.long 0x00 "GBLINFO0,Global Info 0 RegisterRead only register detailing information about sector size and number of bankspresent."
|
|
bitfld.long 0x00 16.--18. "NUMBANKS,Number of banks instantiatedMinimum:1Maximum:5" "?,Minimum value,?,?,?,Maximum value,?,?"
|
|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "SECTORSIZE,Sector size in bytes"
|
|
line.long 0x04 "GBLINFO1,Global Info 1 RegisterRead only register detailing information about data. ecc and redundant datawidths in bits."
|
|
hexmask.long.word 0x04 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x04 16.--18. "REDWIDTH,Redundant data width in bits" "Redundant data width is 0. Redundancy/Repair..,?,Redundant data width is 2 bits,?,Redundant data width is 4 bits,?,?,?"
|
|
newline
|
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bitfld.long 0x04 8.--12. "ECCWIDTH,ECC data width in bits" "ECC data width is 0. ECC not used.,?,?,?,?,?,?,?,ECC data width is 8 bits,?,?,?,?,?,?,?,ECC data width is 16 bits,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
|
|
newline
|
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hexmask.long.byte 0x04 0.--7. 1. "DATAWIDTH,Data width in bits"
|
|
line.long 0x08 "GBLINFO2,Global Info 2 RegisterRead only register detailing information about the number of data registerspresent."
|
|
hexmask.long 0x08 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x08 0.--3. "DATAREGISTERS,Number of data registers present" "?,Minimum value of DATAREGISTERS,?,?,?,?,?,?,Maximum value of DATAREGISTERS,?,?,?,?,?,?,?"
|
|
rgroup.long 0x1400++0x07
|
|
line.long 0x00 "BANK0INFO0,Bank Info 0 Register for bank 0.Read only register detailing information about Main region size in the bank."
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "MAINSIZE,Main region size in sectorsMinimum:0x8 (8)Maximum:0x200 (512)"
|
|
line.long 0x04 "BANK0INFO1,Bank Info1 Register for bank 0.Read only register detailing information about Non-Main. Trim. and Engrregion sizes in the bank."
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. "ENGRSIZE,Engr region size in sectorsMinimum:0x0 (0)Maximum:0x10 (16)"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "TRIMSIZE,Trim region size in sectorsMinimum:0x0 (0)Maximum:0x10 (16)"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "NONMAINSIZE,Non-main region size in sectorsMinimum:0x0 (0)Maximum:0x10 (16)"
|
|
rgroup.long 0x1410++0x07
|
|
line.long 0x00 "BANK1INFO0,Bank Info 0 Register for bank 1.Read only register detailing information about Main region size in the bank."
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "MAINSIZE,Main region size in sectorsMinimum:0x8 (8)Maximum:0x200 (512)"
|
|
line.long 0x04 "BANK1INFO1,Bank Info1 Register for bank 1.Read only register detailing information about Non-Main. Trim. and Engrregion sizes in the bank."
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. "ENGRSIZE,Engr region size in sectorsMinimum:0x0 (0)Maximum:0x10 (16)"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "TRIMSIZE,Trim region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors"
|
|
rgroup.long 0x1420++0x07
|
|
line.long 0x00 "BANK2INFO0,Bank Info 0 Register for bank 2.Read only register detailing information about Main region size in the bank."
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "MAINSIZE,Main region size in sectorsMinimum:0x8 (8)Maximum:0x200 (512)"
|
|
line.long 0x04 "BANK2INFO1,Bank Info1 Register for bank 2.Read only register detailing information about Non-Main. Trim. and Engrregion sizes in the bank."
|
|
hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
newline
|
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hexmask.long.byte 0x04 16.--23. 1. "ENGRSIZE,Engr region size in sectors"
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hexmask.long.byte 0x04 8.--15. 1. "TRIMSIZE,Trim region size in sectors"
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hexmask.long.byte 0x04 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors"
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rgroup.long 0x1430++0x07
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line.long 0x00 "BANK3INFO0,Bank Info 0 Register for bank 3.Read only register detailing information about Main region size in the bank."
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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hexmask.long.word 0x00 0.--11. 1. "MAINSIZE,Main region size in sectors"
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line.long 0x04 "BANK3INFO1,Bank Info1 Register for bank 3.Read only register detailing information about Non-Main. Trim. and Engrregion sizes in the bank."
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hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x04 16.--23. 1. "ENGRSIZE,Engr region size in sectors"
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hexmask.long.byte 0x04 8.--15. 1. "TRIMSIZE,Trim region size in sectors"
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hexmask.long.byte 0x04 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors"
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rgroup.long 0x1440++0x07
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line.long 0x00 "BANK4INFO0,Bank Info 0 Register for bank 4.Read only register detailing information about Main region size in the bank."
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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hexmask.long.word 0x00 0.--11. 1. "MAINSIZE,Main region size in sectors"
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line.long 0x04 "BANK4INFO1,Bank Info1 Register for bank 4.Read only register detailing information about Non-Main. Trim. and Engrregion sizes in the bank."
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hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.byte 0x04 16.--23. 1. "ENGRSIZE,Engr region size in sectors"
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hexmask.long.byte 0x04 8.--15. 1. "TRIMSIZE,Trim region size in sectors"
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hexmask.long.byte 0x04 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors"
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group.long 0x1500++0x17
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line.long 0x00 "DFTEN,DFT Enable RegisterAllows control of NoWrapper test features"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x00 0. "ENABLE,Enable Test Features" "Command,Command"
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line.long 0x04 "DFTCMDCTL,DFT Command Control RegisterThis register configures specific capabilities for test.This register is only writable when DFTEN.ENABLE is set.This register is blocked for writes after a 1 is written to the CMDEXECregister and prior to.."
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bitfld.long 0x04 28.--31. "DTBMUXSEL,DTB Mux SelectThis field will form the select for the primary DTB mux" "Minimum value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value"
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bitfld.long 0x04 27. "DTB16MUXSEL,DTB16 Mux SelectThis bit is valid when the NoWrapper DTB output bus width is less than 32 bits.Specifically this bit is valid when the DTB width is 16 bits or less" "Select lower 16 bits of 32-bit DTB,Select upper 16 bits of 32-bit DTB"
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bitfld.long 0x04 26. "DTB8MUXSEL,DTB8 Mux SelectThis bit is valid when the NoWrapper DTB output bus width is less than 32 bits.Specifically this bit is valid when the DTB width is 8 bits" "Select lower 8 bits of 16-bit DTB,Select upper 8 bits of 16-bit DTB"
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rbitfld.long 0x04 25. "RESERVED25,Software should not rely on the value of a reserved" "0,1"
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bitfld.long 0x04 24. "ERASEMASKDIS,Disable use of erase mask for eraseBit masking will not be used during erase verify" "Enable,Disable"
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newline
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bitfld.long 0x04 23. "PROGMASKDIS,Disable use of program mask for programming.Bit masking will not be used during program verify" "Enable,Disable"
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bitfld.long 0x04 22. "POSTVEREN,Enable verify after program or erase" "Disable,Enable"
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bitfld.long 0x04 21. "PREVEREN,Enable verify before program or erase" "Disable,Enable"
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bitfld.long 0x04 20. "STOPVERONFAIL,Stop read verify on fail" "Disable,Enable"
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bitfld.long 0x04 18. "ODDROWINVDATA,Invert data at odd row addresses for program or verify" "Use true data,Use inverted data"
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bitfld.long 0x04 17. "ODDWORDINVDATA,Invert data at odd bank addresses for program or verify" "Use true data,Use inverted data"
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bitfld.long 0x04 16. "ALWAYSINVDATA,Invert data always for program or verify" "Use true data,Use inverted data"
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bitfld.long 0x04 13.--15. "DATAPATSEL,Select data pattern" "Set to all 0,Set to all 1,Set to logical checkerboard (0x01010101...),?,?,?,?,?"
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bitfld.long 0x04 12. "DATAPATEN,Enable data pattern" "Disable,Enable"
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rbitfld.long 0x04 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x04 9. "PULSECNTLDDIS,Override pulse counter enable" "Enable,Disable"
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bitfld.long 0x04 8. "ADDRCNTLDDIS,Override address counter enable" "Enable,Disable"
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rbitfld.long 0x04 6.--7. "RESERVED6,Software should not rely on the value of a reserved" "0,1,2,3"
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bitfld.long 0x04 5. "REDMATCHFORCE,Force redundancy match" "Disable,Enable"
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newline
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bitfld.long 0x04 4. "REDMATCHDIS,Disable redundancy matching" "Enable,Disable"
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rbitfld.long 0x04 3. "RESERVED3,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x04 2. "AMX2TDIS,2T address mux disable control" "Enable,Disable"
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newline
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bitfld.long 0x04 1. "FORCE2TEN,Force 2T Enable - Force 2T access to regions that are designated as 1T" "Disable,Enable"
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newline
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bitfld.long 0x04 0. "FORCE1TEN,Force 1T Enable - Force 1T access to regions that are designated as 2T" "Disable,Enable"
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line.long 0x08 "DFTTIMERCTL,DFT Timer Control RegisterThis allows some configuration of timing values for various phases of flashoperations for test"
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rbitfld.long 0x08 31. "RESERVED31,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x08 28.--30. "TIMERCLOCKOVR,Override Timer clock frequency using an ICG-based clock divide mechanism" "No divide on timer clock.,Divide timer clock by 2,Divide timer clock by 3,Divide timer clock by 4,Divide timer clock by 5,Divide timer clock by 6,Divide timer clock by 7,Divide timer clock by 8"
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hexmask.long.word 0x08 12.--27. 1. "PEPULSETIMEVAL,Program/Erase Pulse Time ValueIf operation is a program this value gets loaded into bits [15:0] of the timerwhen the PEPULSETIMEVALOVR field is set to 1.If operation is an erase this value gets loaded into bits [19:4] of the timerwhen the.."
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rbitfld.long 0x08 9.--11. "RESERVED9,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x08 8. "PEPULSETIMEOVR,Override Program/Erase Pulse TimeIf set this will force the program or erase pulse time to be overridden with thevalue in the PEPULSETIMEVAL field" "Use hard-wired (Functional) timer value,Use value from the PE_PULSE_TIME field for time.."
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newline
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bitfld.long 0x08 7. "READMODETIME,Read Mode Change Time" "Use hard-wired (Functional) timer value,Use 2x the hard-wired (functional) time value"
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newline
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bitfld.long 0x08 6. "PEVHOLDTIME,Program/Erase Verify Hold Time" "Use hard-wired (Functional) timer value,Use 2x the hard-wired (functional) time value"
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newline
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bitfld.long 0x08 5. "PEVSETUPTIME,Program/Erase Verify Setup Time" "Use hard-wired (Functional) timer value,Use 2x the hard-wired (functional) time value"
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newline
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bitfld.long 0x08 4. "PEVMODETIME,Program/Erase Verify Mode Change Time" "Use hard-wired (Functional) timer value,Use 2x the hard-wired (functional) time value"
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newline
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bitfld.long 0x08 3. "PEHOLDTIME,Program/Erase Hold Time" "Use hard-wired (Functional) timer value,Use 2x the hard-wired (functional) time value"
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newline
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bitfld.long 0x08 2. "PPVWORDLINETIME,Program and Program Verify Wordline Switching Time" "Use hard-wired (Functional) timer value,Use 2x the hard-wired (functional) time value"
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newline
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bitfld.long 0x08 1. "PVHVSETUPTIME,Program VHV Setup Time" "Use hard-wired (Functional) timer value,Use 2x the hard-wired (functional) time value"
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newline
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bitfld.long 0x08 0. "PESETUPTIME,Program/Erase Setup Time" "Use hard-wired (Functional) timer value,Use 2x the hard-wired (functional) time value"
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line.long 0x0C "DFTEXECZCTL,DFT EXECUTEZ control register"
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bitfld.long 0x0C 1. "EXEZ_OVR,Override value to be applied to EXECUTEZ" "Set EXECUTEZ to 0,Set EXECUTEZ to 1"
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newline
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bitfld.long 0x0C 0. "EXEZOVREN,Enable override of EXECUTEZNote that when this bit is set NoWrapper has control of the bank pins" "Disable,Enable"
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line.long 0x10 "DFTPCLKTESTCTL,DFT Pump Clock Test Control Register"
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hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 0. "ENABLE,Enable the state machine which sequences measurement of pump clock frequency." "Disable,Enable"
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line.long 0x14 "DFTPCLKTESTSTAT,DFT Pump Clock Test Status Register"
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hexmask.long.word 0x14 4.--15. 1. "CLOCKCNT,Indicates the core clock count captured during the pump clock measurement"
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newline
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bitfld.long 0x14 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x14 0. "BUSY,Indicates that a pump clock measurement is in progress" "Indicates test complete,Indicates test in progress"
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repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
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group.long ($2+0x1540)++0x03
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line.long 0x00 "DFTDATARED$1,DFT Redundancy Data Register 0This register is used when testing the redundant columns in the flash"
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hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0.--3. "VAL,Data for redundant bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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repeat.end
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group.long 0x1560++0x07
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line.long 0x00 "DFTPUMPCTL,DFT Pump Control RegisterThis allows some configuration of pump parameters during test.This register is only writable when DFTEN.ENABLE is set.This register is blocked for writes after a 1 is written to the CMDEXECregister and prior to.."
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hexmask.long.word 0x00 19.--31. 1. "RESERVED19,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 16.--18. "IREFEVCTL,IREFEV control IREFVRD REFTC IREFCONST IREFCCOR blocks in IREFEV" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 12.--15. "CONFIGPMP,Pump configuration control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 9. "SSEN,Dither control for oscillatorEnumeration:0: Disable" "Disable Dither,Enable Dither"
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newline
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bitfld.long 0x00 8. "PUMPCLKEN,Allows direct control of the pump oscillator which is used to generate pumpclk.Normally enable/disable of pumpclk is under NoWrapper state machinecontrol" "Allow pump clock oscillator to be controlled by..,Force pump clock oscillator to be enabled."
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newline
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rbitfld.long 0x00 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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hexmask.long.byte 0x00 0.--6. 1. "TCR,TCR test mode to be applied to the pump"
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line.long 0x04 "DFTBANKCTL,DFT Bank Control RegisterThis allows some configuration of bank parameters during test.This register is only writable when DFTEN.ENABLE is set.This register is blocked for writes after a 1 is written to the CMDEXECregister and prior to.."
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bitfld.long 0x04 8. "TEZ,When set TEZ is asserted to the flash banks" "Assert TEZ,Do not assert TEZ"
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newline
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rbitfld.long 0x04 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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hexmask.long.byte 0x04 0.--6. 1. "TCR,TCR test mode to be applied to the bank"
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group.long 0x1600++0x0B
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line.long 0x00 "TRIMCTL,Allows control of the application of bank/pump trim values"
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hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 0. "ENABLE,Indicate that Bank and Pump trim values are valid" "Trim data is not valid,Trim data is valid"
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line.long 0x04 "TRIMLOCK,Trim Lock RegisterWhen set PUMPTRIM* and BANK*TRIM* registers are locked and cannot bewritten"
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bitfld.long 0x04 1. "TRIMLOCKOTHER,This bit controls the PUMPTRIM and BANK*TRIM registers" "*TRIM registers are open for write.,*TRIM registers are locked from write"
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newline
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bitfld.long 0x04 0. "TRIMLOCKREAD,This bit controls the PUMPTRIMREAD and BANK*TRIMREAD registers" "*TRIMREAD registers are open for write.,*TRIMREAD registers are locked from write"
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line.long 0x08 "TRIMCOMMIT,Trim Commit RegisterWhen bits in this register are set. all associated trim registers (including TRIMCTL. TRIMLOCK and this register) are locked from update"
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bitfld.long 0x08 1. "TRIMCOMMITOTHER,This bit controls the PUMPTRIM and BANK*TRIM registers" "*TRIM registers are not committed.,*TRIM registers are committed"
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newline
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bitfld.long 0x08 0. "TRIMCOMMITREAD,This bit controls the PUMPTRIMREAD and BANK*TRIMREAD registers" "*TRIMREAD registers are not committed.,*TRIMREAD registers are committed"
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group.long 0x1610++0x0F
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line.long 0x00 "PUMPTRIM0,Pump Trim 0 Register.This register contains pump trim values associated with program and erase."
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hexmask.long.word 0x00 16.--25. 1. "PUMPVHVCTPV,VHVCT pump trim value for program verify"
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newline
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rbitfld.long 0x00 10.--15. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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hexmask.long.word 0x00 0.--9. 1. "PUMPVHVCTERS,VHVCT pump trim value for erase"
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line.long 0x04 "PUMPTRIM1,Pump Trim 1 Register.This register contains pump trim values associated with program and erase."
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bitfld.long 0x04 21.--26. "PUMPVINHCT,VINHCT pump trim value" "Minimum value of PUMPVINHCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPVINHCT"
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newline
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bitfld.long 0x04 16.--20. "PUMPIREFVRDCT,IREFVRDCT pump trim value" "Minimum value of PUMPIREFVRDCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPIREFVRDCT"
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newline
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bitfld.long 0x04 10.--14. "PUMPIREFTCCT,IREFTCCT pump trim value" "Minimum value of PUMPIREFTCCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPIREFTCCT"
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newline
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hexmask.long.word 0x04 0.--9. 1. "PUMPVHVCTPGM,VHVCT pump trim value for program"
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line.long 0x08 "PUMPTRIM2,Pump Trim 2 Register.This register contains pump trim values associated with program and erase."
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rbitfld.long 0x08 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x08 22.--27. "PUMPFOSCCT,FOSCCT pump trim value" "Minimum value of PUMPFOSCCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPFOSCCT"
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newline
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bitfld.long 0x08 16.--21. "PUMPVWLCT,VWLCT pump trim value" "Minimum value of PUMPVWLCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPVWLCT"
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newline
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bitfld.long 0x08 10.--15. "PUMPVSLCT,VSLCT pump trim value" "Minimum value of PUMPVSLCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPVSLCT"
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newline
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bitfld.long 0x08 5.--9. "PUMPVINLOWCCORCT,VINLOWCCORCT pump trim value" "Minimum value of PUMPVINLOWCCORCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPVINLOWCCORCT"
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newline
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bitfld.long 0x08 0.--4. "PUMPVINHHICCORCT,VINHHICCORCT pump trim value" "Minimum value of PUMPVINHHICCORCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPVINHHICCORCT"
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line.long 0x0C "PUMPTRIMREAD,Pump Read Trim Register.This register contains pump trim values which apply to flash reads."
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hexmask.long.tbyte 0x0C 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 9.--13. "PUMPVCGCT,VCGCT pump trim value" "Minimum value of PUMPVCGCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPVCGCT"
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newline
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bitfld.long 0x0C 4.--8. "PUMPVREADCT,VREADCT pump trim value" "Minimum value of PUMPVREADCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPVREADCT"
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newline
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bitfld.long 0x0C 0.--3. "PUMPIREFCT,IREFCT pump trim value" "Minimum value of PUMPIREFCT,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of PUMPIREFCT"
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group.long 0x1630++0x07
|
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line.long 0x00 "BANK0TRIM0,Bank 0 Trim 0 Register.Contains bits [31:0] of the bank 0 trim."
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bitfld.long 0x00 29.--31. "ERASEGPULSECFG,Configures the length of the erase pulse" "Use 100ms for the erase pulse time,Use 200ms for the erase pulse time,Use 300ms for the erase pulse time,Use 400ms for the erase pulse time,Use 500ms for the erase pulse time,Use 700ms for the erase pulse time,Use 25ms for the erase pulse time,Use 50ms for the erase pulse time"
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newline
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bitfld.long 0x00 26.--28. "PROGPULSECFG,Configures the length of the program pulse" "Use 1.5 X the default fixed program pulse time,Use 2.0 X the default fixed program pulse time,Use 2.5 X the default fixed program pulse time,Use 3.0 X the default fixed program pulse time,Use 4.0 X the default fixed program pulse time,Use 5.0 X the default fixed program pulse time,Use 0.5 X the default fixed program pulse time,Use 1.0 X the default fixed program pulse time"
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newline
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bitfld.long 0x00 25. "IREFCFGEN,Enables override of IREF configuration" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 20.--24. "IREFCFG,Configures IREF used for read operation" "Uses default IREF on the reference side,Adds 0.25*IREF (nominally 4uA to bank) to the..,Adds 0.50*IREF (nominally 4uA to bank) to the..,?,Adds 1.00*IREF (nominally 4uA to bank) to the..,?,?,?,Adds 2.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,Adds 3.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x00 19. "NOERSPOSTVERIFY,Do not do a post verify after erase" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 18. "RDERSPOSTVERIFY,Use READ mode for erase verify operations" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 17. "EVENCGSTRESSEN,Even control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 16. "ODDCGSTRESSEN,Odd control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 15. "EVENBLSTRESSEN,Even bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 14. "ODDBLSTRESSEN,Odd bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 13. "EVENWLSTRESSEN,Even word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 12. "ODDWLSTRESSEN,Odd word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 11. "NOPRGPOSTVERIFY,Do not do a post verify after program" "Feature disabled,Feature enabled"
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line.long 0x04 "BANK0TRIMREAD,Bank 0 Read Trim Register.Contains repair trim bits for bank 0."
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bitfld.long 0x04 22.--27. "REPAIRCFG3,Repair Configure 3Configures repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Minimum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 16.--21. "REPAIRCFG2,Repair Configure 2Configures repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Minimum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 10.--15. "REPAIRCFG1,Repair Configure 1Configures repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Minimum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 4.--9. "REPAIRCFG0,Repair Configure 0Configures repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Minimum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 3. "REPAIREN3,Repair Enable 3Enables repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 2. "REPAIREN2,Repair Enable 2Enables repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 1. "REPAIREN1,Repair Enable 1Enables repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 0. "REPAIREN0,Repair Enable 0Enables repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Disable,Enable"
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group.long 0x1640++0x07
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line.long 0x00 "BANK1TRIM0,Bank 1 Trim 0 Register.Contains bits [31:0] of the bank 0 trim."
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bitfld.long 0x00 29.--31. "ERASEGPULSECFG,Configures the length of the erase pulse" "Use 100ms for the erase pulse time,Use 200ms for the erase pulse time,Use 300ms for the erase pulse time,Use 400ms for the erase pulse time,Use 500ms for the erase pulse time,Use 700ms for the erase pulse time,Use 25ms for the erase pulse time,Use 50ms for the erase pulse time"
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newline
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bitfld.long 0x00 26.--28. "PROGPULSECFG,Configures the length of the program pulse" "Use 1.5 X the default fixed program pulse time,Use 2.0 X the default fixed program pulse time,Use 2.5 X the default fixed program pulse time,Use 3.0 X the default fixed program pulse time,Use 4.0 X the default fixed program pulse time,Use 5.0 X the default fixed program pulse time,Use 0.5 X the default fixed program pulse time,Use 1.0 X the default fixed program pulse time"
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newline
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bitfld.long 0x00 25. "IREFCFGEN,Enables override of IREF configuration" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 20.--24. "IREFCFG,Configures IREF used for read operation" "Uses default IREF on the reference side,Adds 0.25*IREF (nominally 4uA to bank) to the..,Adds 0.50*IREF (nominally 4uA to bank) to the..,?,Adds 1.00*IREF (nominally 4uA to bank) to the..,?,?,?,Adds 2.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,Adds 3.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x00 19. "NOERSPOSTVERIFY,Do not do a post verify after erase" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 18. "RDERSPOSTVERIFY,Use READ mode for erase verify operations" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 17. "EVENCGSTRESSEN,Even control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 16. "ODDCGSTRESSEN,Odd control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 15. "EVENBLSTRESSEN,Even bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 14. "ODDBLSTRESSEN,Odd bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 13. "EVENWLSTRESSEN,Even word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 12. "ODDWLSTRESSEN,Odd word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 11. "NOPRGPOSTVERIFY,Do not do a post verify after program" "Feature disabled,Feature enabled"
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line.long 0x04 "BANK1TRIMREAD,Bank 1 Read Trim Register.Contains repair trim bits for bank 1."
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bitfld.long 0x04 22.--27. "REPAIRCFG3,Repair Configure 3Configures repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Minimum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 16.--21. "REPAIRCFG2,Repair Configure 2Configures repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Minimum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 10.--15. "REPAIRCFG1,Repair Configure 1Configures repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Minimum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 4.--9. "REPAIRCFG0,Repair Configure 0Configures repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Minimum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 3. "REPAIREN3,Repair Enable 3Enables repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 2. "REPAIREN2,Repair Enable 2Enables repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 1. "REPAIREN1,Repair Enable 1Enables repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 0. "REPAIREN0,Repair Enable 0Enables repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Disable,Enable"
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group.long 0x1650++0x07
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line.long 0x00 "BANK2TRIM0,Bank 2 Trim 0 Register.Contains bits [31:0] of the bank 2 trim."
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bitfld.long 0x00 29.--31. "ERASEGPULSECFG,Configures the length of the erase pulse" "Use 100ms for the erase pulse time,Use 200ms for the erase pulse time,Use 300ms for the erase pulse time,Use 400ms for the erase pulse time,Use 500ms for the erase pulse time,Use 700ms for the erase pulse time,Use 25ms for the erase pulse time,Use 50ms for the erase pulse time"
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newline
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bitfld.long 0x00 26.--28. "PROGPULSECFG,Configures the length of the program pulse" "Use 1.5 X the default fixed program pulse time,Use 2.0 X the default fixed program pulse time,Use 2.5 X the default fixed program pulse time,Use 3.0 X the default fixed program pulse time,Use 4.0 X the default fixed program pulse time,Use 5.0 X the default fixed program pulse time,Use 0.5 X the default fixed program pulse time,Use 1.0 X the default fixed program pulse time"
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newline
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bitfld.long 0x00 25. "IREFCFGEN,Enables override of IREF configuration" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 20.--24. "IREFCFG,Configures IREF used for read operation" "Uses default IREF on the reference side,Adds 0.25*IREF (nominally 4uA to bank) to the..,Adds 0.50*IREF (nominally 4uA to bank) to the..,?,Adds 1.00*IREF (nominally 4uA to bank) to the..,?,?,?,Adds 2.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,Adds 3.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x00 19. "NOERSPOSTVERIFY,Do not do a post verify after erase" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 18. "RDERSPOSTVERIFY,Use READ mode for erase verify operations" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 17. "EVENCGSTRESSEN,Even control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 16. "ODDCGSTRESSEN,Odd control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 15. "EVENBLSTRESSEN,Even bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 14. "ODDBLSTRESSEN,Odd bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 13. "EVENWLSTRESSEN,Even word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 12. "ODDWLSTRESSEN,Odd word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 11. "NOPRGPOSTVERIFY,Do not do a post verify after program" "Feature disabled,Feature enabled"
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line.long 0x04 "BANK2TRIMREAD,Bank 2 Read Trim Register.Contains repair trim bits for bank 2."
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bitfld.long 0x04 22.--27. "REPAIRCFG3,Repair Configure 3Configures repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Minimum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 16.--21. "REPAIRCFG2,Repair Configure 2Configures repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Minimum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 10.--15. "REPAIRCFG1,Repair Configure 1Configures repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Minimum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 4.--9. "REPAIRCFG0,Repair Configure 0Configures repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Minimum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 3. "REPAIREN3,Repair Enable 3Enables repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 2. "REPAIREN2,Repair Enable 2Enables repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 1. "REPAIREN1,Repair Enable 1Enables repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 0. "REPAIREN0,Repair Enable 0Enables repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Disable,Enable"
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group.long 0x1660++0x07
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line.long 0x00 "BANK3TRIM0,Bank 3 Trim 0 Register.Contains bits [31:0] of the bank 3 trim."
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bitfld.long 0x00 29.--31. "ERASEGPULSECFG,Configures the length of the erase pulse" "Use 100ms for the erase pulse time,Use 200ms for the erase pulse time,Use 300ms for the erase pulse time,Use 400ms for the erase pulse time,Use 500ms for the erase pulse time,Use 700ms for the erase pulse time,Use 25ms for the erase pulse time,Use 50ms for the erase pulse time"
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newline
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bitfld.long 0x00 26.--28. "PROGPULSECFG,Configures the length of the program pulse" "Use 1.5 X the default fixed program pulse time,Use 2.0 X the default fixed program pulse time,Use 2.5 X the default fixed program pulse time,Use 3.0 X the default fixed program pulse time,Use 4.0 X the default fixed program pulse time,Use 5.0 X the default fixed program pulse time,Use 0.5 X the default fixed program pulse time,Use 1.0 X the default fixed program pulse time"
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newline
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bitfld.long 0x00 25. "IREFCFGEN,Enables override of IREF configuration" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 20.--24. "IREFCFG,Configures IREF used for read operation" "Uses default IREF on the reference side,Adds 0.25*IREF (nominally 4uA to bank) to the..,Adds 0.50*IREF (nominally 4uA to bank) to the..,?,Adds 1.00*IREF (nominally 4uA to bank) to the..,?,?,?,Adds 2.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,Adds 3.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x00 19. "NOERSPOSTVERIFY,Do not do a post verify after erase" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 18. "RDERSPOSTVERIFY,Use READ mode for erase verify operations" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 17. "EVENCGSTRESSEN,Even control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 16. "ODDCGSTRESSEN,Odd control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 15. "EVENBLSTRESSEN,Even bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 14. "ODDBLSTRESSEN,Odd bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 13. "EVENWLSTRESSEN,Even word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 12. "ODDWLSTRESSEN,Odd word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 11. "NOPRGPOSTVERIFY,Do not do a post verify after program" "Feature disabled,Feature enabled"
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line.long 0x04 "BANK3TRIMREAD,Bank 3 Read Trim Register.Contains repair trim bits for bank 3."
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bitfld.long 0x04 22.--27. "REPAIRCFG3,Repair Configure 3Configures repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Minimum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 16.--21. "REPAIRCFG2,Repair Configure 2Configures repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Minimum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 10.--15. "REPAIRCFG1,Repair Configure 1Configures repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Minimum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 4.--9. "REPAIRCFG0,Repair Configure 0Configures repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Minimum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 3. "REPAIREN3,Repair Enable 3Enables repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 2. "REPAIREN2,Repair Enable 2Enables repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 1. "REPAIREN1,Repair Enable 1Enables repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Disable,Enable"
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newline
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bitfld.long 0x04 0. "REPAIREN0,Repair Enable 0Enables repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Disable,Enable"
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group.long 0x1670++0x07
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line.long 0x00 "BANK4TRIM0,Bank 4 Trim 0 Register.Contains bits [31:0] of the bank 4 trim."
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bitfld.long 0x00 29.--31. "ERASEGPULSECFG,Configures the length of the erase pulse" "Use 100ms for the erase pulse time,Use 200ms for the erase pulse time,Use 300ms for the erase pulse time,Use 400ms for the erase pulse time,Use 500ms for the erase pulse time,Use 700ms for the erase pulse time,Use 25ms for the erase pulse time,Use 50ms for the erase pulse time"
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newline
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bitfld.long 0x00 26.--28. "PROGPULSECFG,Configures the length of the program pulse" "Use 1.5 X the default fixed program pulse time,Use 2.0 X the default fixed program pulse time,Use 2.5 X the default fixed program pulse time,Use 3.0 X the default fixed program pulse time,Use 4.0 X the default fixed program pulse time,Use 5.0 X the default fixed program pulse time,Use 0.5 X the default fixed program pulse time,Use 1.0 X the default fixed program pulse time"
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newline
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bitfld.long 0x00 25. "IREFCFGEN,Enables override of IREF configuration" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 20.--24. "IREFCFG,Configures IREF used for read operation" "Uses default IREF on the reference side,Adds 0.25*IREF (nominally 4uA to bank) to the..,Adds 0.50*IREF (nominally 4uA to bank) to the..,?,Adds 1.00*IREF (nominally 4uA to bank) to the..,?,?,?,Adds 2.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,Adds 3.00*IREF (nominally 4uA to bank) to the..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x00 19. "NOERSPOSTVERIFY,Do not do a post verify after erase" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 18. "RDERSPOSTVERIFY,Use READ mode for erase verify operations" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 17. "EVENCGSTRESSEN,Even control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 16. "ODDCGSTRESSEN,Odd control gate stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 15. "EVENBLSTRESSEN,Even bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 14. "ODDBLSTRESSEN,Odd bit line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 13. "EVENWLSTRESSEN,Even word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 12. "ODDWLSTRESSEN,Odd word line stress enable" "Feature disabled,Feature enabled"
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newline
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bitfld.long 0x00 11. "NOPRGPOSTVERIFY,Do not do a post verify after program" "Feature disabled,Feature enabled"
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line.long 0x04 "BANK4TRIMREAD,Bank 4 Read Trim Register.Contains repair trim bits for bank 4."
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bitfld.long 0x04 22.--27. "REPAIRCFG3,Repair Configure 3Configures repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Minimum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG3,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 16.--21. "REPAIRCFG2,Repair Configure 2Configures repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Minimum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 10.--15. "REPAIRCFG1,Repair Configure 1Configures repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Minimum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 4.--9. "REPAIRCFG0,Repair Configure 0Configures repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Minimum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Maximum value of REPAIRCFG0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x04 3. "REPAIREN3,Repair Enable 3Enables repair for bank data bits 143:108 (if ecc) or 127:96 (if no ecc)" "Disable,Enable"
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bitfld.long 0x04 2. "REPAIREN2,Repair Enable 2Enables repair for bank data bits 107:72 (if ecc) or 95:64 (if no ecc)" "Disable,Enable"
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bitfld.long 0x04 1. "REPAIREN1,Repair Enable 1Enables repair for bank data bits 71:36 (if ecc) or 63:32 (if no ecc)" "Disable,Enable"
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bitfld.long 0x04 0. "REPAIREN0,Repair Enable 0Enables repair for bank data bits 35:0 (if ecc) or 31:0 (if no ecc)" "Disable,Enable"
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tree.end
|
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tree "PKA"
|
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base ad:0x58025000
|
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group.long 0x00++0x2B
|
|
line.long 0x00 "APTR,PKA Vector A AddressDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
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hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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hexmask.long.word 0x00 0.--10. 1. "APTR,This register specifies the location of vector A within the PKA RAM"
|
|
line.long 0x04 "BPTR,PKA Vector B AddressDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
|
hexmask.long.tbyte 0x04 11.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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hexmask.long.word 0x04 0.--10. 1. "BPTR,This register specifies the location of vector B within the PKA RAM"
|
|
line.long 0x08 "CPTR,PKA Vector C AddressDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
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hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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hexmask.long.word 0x08 0.--10. 1. "CPTR,This register specifies the location of vector C within the PKA RAM"
|
|
line.long 0x0C "DPTR,PKA Vector D AddressDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
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hexmask.long.tbyte 0x0C 11.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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hexmask.long.word 0x0C 0.--10. 1. "DPTR,This register specifies the location of vector D within the PKA RAM"
|
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line.long 0x10 "ALENGTH,PKA Vector A LengthDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
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hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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hexmask.long.word 0x10 0.--8. 1. "ALENGTH,This register specifies the length (in 32-bit words) of Vector A"
|
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line.long 0x14 "BLENGTH,PKA Vector B LengthDuring execution of basic PKCP operations. this register is double buffered and can be written with a new value for the next operation; when not written. the value remains intact"
|
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hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED11,Set to zero on write ignore on read"
|
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hexmask.long.word 0x14 0.--8. 1. "BLENGTH,This register specifies the length (in 32-bit words) of Vector B"
|
|
line.long 0x18 "SHIFT,PKA Bit Shift ValueFor basic PKCP operations. modifying the contents of this register is made impossible while the operation is being performed"
|
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hexmask.long 0x18 5.--31. 1. "RESERVED11,Set to zero on write ignore on read"
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bitfld.long 0x18 0.--4. "NUM_BITS_TO_SHIFT,This register specifies the number of bits to shift the input vector (in the range 0-31) during a Rshift or Lshift operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "FUNCTION,PKA FunctionThis register contains the control bits to start basic PKCP as well as complex sequencer operations"
|
|
hexmask.long.byte 0x1C 25.--31. 1. "RESERVED25,Set to zero on write ignore on read"
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bitfld.long 0x1C 24. "STALL_RESULT,When written with a 1b updating of the COMPARE bit MSW and DIVMSW registers as well as resetting the run bit is stalled beyond the point that a running operation is actually finished" "0,1"
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hexmask.long.byte 0x1C 16.--23. 1. "RESERVED16,Set to zero on write ignore on read"
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bitfld.long 0x1C 15. "RUN,The host sets this bit to instruct the PKA module to begin processing the basic PKCP or complex sequencer operation" "0,1"
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|
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bitfld.long 0x1C 12.--14. "SEQUENCER_OPERATIONS,These bits select the complex sequencer operation to perform" "None,ExpMod-CRT,ECmontMUL,ECC-ADD (if available in firmware otherwise..,ExpMod-ACT2,ECC-MUL (if available in firmware otherwise..,ExpMod-variable,ModInv (if available in firmware otherwise.."
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bitfld.long 0x1C 11. "COPY,Perform copy operation" "0,1"
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|
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bitfld.long 0x1C 10. "COMPARE,Perform compare operation" "0,1"
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|
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bitfld.long 0x1C 9. "MODULO,Perform modulo operation" "0,1"
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bitfld.long 0x1C 8. "DIVIDE,Perform divide operation" "0,1"
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|
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bitfld.long 0x1C 7. "LSHIFT,Perform left shift operation" "0,1"
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|
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bitfld.long 0x1C 6. "RSHIFT,Perform right shift operation" "0,1"
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|
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bitfld.long 0x1C 5. "SUBTRACT,Perform subtract operation" "0,1"
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|
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bitfld.long 0x1C 4. "ADD,Perform add operation" "0,1"
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|
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bitfld.long 0x1C 3. "MS_ONE,Loads the location of the Most Significant one bit within the result word indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS register - can only be used with basic PKCP operations except for Divide Modulo and Compare" "0,1"
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bitfld.long 0x1C 2. "RESERVED2,Set to zero on write ignore on read" "0,1"
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|
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bitfld.long 0x1C 1. "ADDSUB,Perform combined add/subtract operation" "0,1"
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bitfld.long 0x1C 0. "MULTIPLY,Perform multiply operation" "0,1"
|
|
line.long 0x20 "COMPARE,PKA compare resultThis register provides the result of a basic PKCP compare operation"
|
|
hexmask.long 0x20 3.--31. 1. "RESERVED3,Ignore on read"
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|
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bitfld.long 0x20 2. "A_GREATER_THAN_B,Vector_A is greater than Vector_B" "0,1"
|
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|
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bitfld.long 0x20 1. "A_LESS_THAN_B,Vector_A is less than Vector_B" "0,1"
|
|
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|
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bitfld.long 0x20 0. "A_EQUALS_B,Vector_A is equal to Vector_B" "0,1"
|
|
line.long 0x24 "MSW,PKA most-significant-word of result vectorThis register indicates the (word) address in the PKA RAM where the most significant nonzero 32-bit word of the result is stored"
|
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hexmask.long.word 0x24 16.--31. 1. "RESERVED16,Ignore on read"
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bitfld.long 0x24 15. "RESULT_IS_ZERO,The result vector is all zeroes ignore the address returned in bits [10:0]" "0,1"
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bitfld.long 0x24 11.--14. "RESERVED11,Ignore on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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hexmask.long.word 0x24 0.--10. 1. "MSW_ADDRESS,Address of the most-significant nonzero 32-bit word of the result vector in PKA RAM"
|
|
line.long 0x28 "DIVMSW,PKA most-significant-word of divide remainderThis register indicates the (32-bit word) address in the PKA RAM where the most significant nonzero 32-bit word of the remainder result for the basic divide and modulo operations is stored"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Ignore on read"
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|
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|
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bitfld.long 0x28 15. "RESULT_IS_ZERO,The result vector is all zeroes ignore the address returned in bits [10:0]" "0,1"
|
|
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|
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bitfld.long 0x28 11.--14. "RESERVED11,Ignore on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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hexmask.long.word 0x28 0.--10. 1. "MSW_ADDRESS,Address of the most significant nonzero 32-bit word of the remainder result vector in PKA RAM"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "SEQCTRL,PKA sequencer control and status registerThe sequencer is interfaced with the outside world through a single control and status register"
|
|
bitfld.long 0x00 31. "RESET,Option program ROM: Reset value = 0" "0,1"
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|
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|
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hexmask.long.word 0x00 16.--30. 1. "RESERVED16,Set to zero on write ignore on read"
|
|
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|
|
hexmask.long.byte 0x00 8.--15. 1. "SEQUENCER_STAT,These read-only bits can be used by the sequencer to communicate status to the outside world"
|
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|
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hexmask.long.byte 0x00 0.--7. 1. "SW_CONTROL_STAT,These bits can be used by software to trigger sequencer operations"
|
|
rgroup.long 0xF4++0x0B
|
|
line.long 0x00 "OPTIONS,PKA hardware options registerThis register provides the host with a means to determine the hardware configuration implemented in this PKA engine. focused on options that have an effect on software interacting with the module."
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Ignore on read"
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|
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|
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bitfld.long 0x00 11. "INT_MASKING,Interrupt Masking" "indicates that the main interrupt output (bit..,indicates that interrupt masking logic is.."
|
|
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|
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bitfld.long 0x00 8.--10. "PROTECTION_OPTION,Protection Option" "indicates no additional protection against side..,indicates the SCAP option,Reserved,indicates the PROT option;,?..."
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|
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bitfld.long 0x00 7. "PROGRAM_RAM,Program RAM" "indicates sequencer program storage in ROM,indicates sequencer program storage in RAM"
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|
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|
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bitfld.long 0x00 5.--6. "SEQUENCER_CONFIGURATION,Sequencer Configuration" "Reserved,Indicates a standard..,Reserved,Reserved"
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|
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|
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bitfld.long 0x00 2.--4. "RESERVED2,Ignore on read" "0,1,2,3,4,5,6,7"
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|
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|
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bitfld.long 0x00 0.--1. "PKCP_CONFIGURATION,PKCP Configuration" "Reserved,Indicates a PKCP with a 16x16 multiplier,indicates a PKCP with a 32x32 multiplier,Reserved"
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line.long 0x04 "FWREV,PKA firmware revision and capabilities registerThis register allows the host access to the internal firmware revision number of the PKA Engine for software driver matching and diagnostic purposes"
|
|
bitfld.long 0x04 28.--31. "FW_CAPABILITIES,Firmware Capabilities 4-bit binary encoding for the functionality implemented in the firmware" "indicates basic ModExp with/without CRT,adds Modular Inversion,value 2 adds Modular Inversion and ECC operations,?..."
|
|
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|
|
bitfld.long 0x04 24.--27. "MAJOR_FW_REVISION,4-bit binary encoding of the major firmware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x04 20.--23. "MINOR_FW_REVISION,4-bit binary encoding of the minor firmware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x04 16.--19. "FW_PATCH_LEVEL,4-bit binary encoding of the firmware patch level initial release will carry value zeroPatches are used to remove bugs without changing the functionality or interface of a module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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hexmask.long.word 0x04 0.--15. 1. "RESERVED0,Ignore on read"
|
|
line.long 0x08 "HWREV,PKA hardware revision registerThis register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes"
|
|
bitfld.long 0x08 28.--31. "RESERVED28,Ignore on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x08 24.--27. "MAJOR_HW_REVISION,4-bit binary encoding of the major hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
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bitfld.long 0x08 20.--23. "MINOR_HW_REVISION,4-bit binary encoding of the minor hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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|
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bitfld.long 0x08 16.--19. "HW_PATCH_LEVEL,4-bit binary encoding of the hardware patch level initial release will carry value zeroPatches are used to remove bugs without changing the functionality or interface of a module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
hexmask.long.byte 0x08 8.--15. 1. "COMPLEMENT_OF_BASIC_EIP_NUMBER,Bit-by-bit logic complement of bits [7:0] EIP-28 gives 0xE3"
|
|
newline
|
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hexmask.long.byte 0x08 0.--7. 1. "BASIC_EIP_NUMBER,8-bit binary encoding of the EIP number EIP-28 gives 0x1C"
|
|
tree.end
|
|
tree "PKA_INT"
|
|
base ad:0x58027000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RESERVED_0,Software should not rely on the value of a reserved"
|
|
group.long 0xFF8++0x07
|
|
line.long 0x00 "OPTIONS,PKA Options register"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "RESERVED11,Ignore on read"
|
|
rbitfld.long 0x00 10. "AIC_PRESENT,When set to '1' indicates that an EIP201 AIC is included in the EIP150" "0,1"
|
|
rbitfld.long 0x00 9. "EIP76_PRESENT,When set to '1' indicates that the EIP76 TRNG is included in the EIP150" "0,1"
|
|
rbitfld.long 0x00 8. "EIP28_PRESENT,When set to '1' indicates that the EIP28 PKA is included in the EIP150" "0,1"
|
|
rbitfld.long 0x00 4.--7. "RESERVED4,Ignore on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 3. "AXI_INTERFACE,When set to '1' indicates that the EIP150 is equipped with a AXI interface" "0,1"
|
|
rbitfld.long 0x00 2. "AHB_IS_ASYNC,When set to '1' indicates that AHB interface is asynchronous Only applicable when AHB_INTERFACE is 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AHB_INTERFACE,When set to '1' indicates that the EIP150 is equipped with a AHB interface" "0,1"
|
|
bitfld.long 0x00 0. "PLB_INTERFACE,When set to '1' indicates that the EIP150 is equipped with a PLB interface" "0,1"
|
|
line.long 0x04 "REVISION,PKA hardware revision registerThis register allows the host access to the hardware revision number of the PKA engine for software driver matching and diagnostic purposes"
|
|
bitfld.long 0x04 28.--31. "RESERVED28,These bits should be ignored on read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. "MAJOR_REVISION,These bits encode the major version number for this module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. "MINOR_REVISION,These bits encode the minor version number for this module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. "PATCH_LEVEL,These bits encode the hardware patch level for this module they start at value 0 on the first release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 8.--15. 1. "COMP_EIP_NUM,These bits simply contain the complement of bits [7:0] used by a driver to ascertain that the EIP150 revision register is indeed"
|
|
hexmask.long.byte 0x04 0.--7. 1. "EIP_NUM,These bits encode the AuthenTec EIP number for the EIP150"
|
|
tree.end
|
|
tree "PRCM"
|
|
base ad:0x58082000
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "INFRCLKDIVR,Infrastructure Clock Division Factor For Run Mode"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x04 "INFRCLKDIVS,Infrastructure Clock Division Factor For Sleep Mode"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x08 "INFRCLKDIVDS,Infrastructure Clock Division Factor For DeepSleep Mode"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "RATIO,Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode" "Divide by 1,Divide by 2,Divide by 8,Divide by 32"
|
|
line.long 0x0C "VDCTL,MCU Voltage Domain Control"
|
|
hexmask.long 0x0C 1.--31. 1. "SPARE1,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x0C 0. "ULDO,Request PMCTL to switch to uLDO.0: No request1: Assert request when possibleThe bit will have no effect before the following requirements are met:1" "No request,Assert request when.."
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "CLKLOADCTL,Load PRCM Settings To CLKCTRL Power Domain"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 1. "LOAD_DONE,Status of LOAD" "One or more registers have been write accessed..,No registers are write accessed after last LOAD"
|
|
newline
|
|
bitfld.long 0x00 0. "LOAD," "No action,Load settings to CLKCTRL"
|
|
line.long 0x04 "RFCCLKG,RFC Clock Gate"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "CLK_EN," "Disable Clock,Enable clock if RFC power domain is.."
|
|
line.long 0x08 "VIMSCLKG,VIMS Clock Gate"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "CLK_EN," "0,1,2,3"
|
|
group.long 0x3C++0x53
|
|
line.long 0x00 "SECDMACLKGR,SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED25,Software should not rely on the value of a reserved"
|
|
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|
|
bitfld.long 0x00 24. "DMA_AM_CLK_EN," "No force,Force clock on for all.."
|
|
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|
|
rbitfld.long 0x00 20.--23. "RESERVED20,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
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|
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bitfld.long 0x00 19. "PKA_ZERIOZE_RESET_N,Zeroization logic hardware reset.0: pka_zeroize logic inactive.1: pka_zeroize of memory is enabled" "pka_zeroize logic inactive,pka_zeroize of memory is enabled"
|
|
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|
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bitfld.long 0x00 18. "PKA_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
bitfld.long 0x00 17. "TRNG_AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
bitfld.long 0x00 16. "CRYPTO_AM_CLK_EN," "No force,Force clock on for all.."
|
|
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|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
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|
|
bitfld.long 0x00 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
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|
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rbitfld.long 0x00 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x00 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x00 1. "TRNG_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
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bitfld.long 0x00 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x04 "SECDMACLKGS,SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode"
|
|
hexmask.long.tbyte 0x04 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
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|
|
bitfld.long 0x04 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x04 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x04 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x04 1. "TRNG_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x04 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x08 "SECDMACLKGDS,SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode"
|
|
hexmask.long.tbyte 0x08 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 8. "DMA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
rbitfld.long 0x08 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x08 2. "PKA_CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
newline
|
|
bitfld.long 0x08 1. "TRNG_CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
newline
|
|
bitfld.long 0x08 0. "CRYPTO_CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
line.long 0x0C "GPIOCLKGR,GPIO Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 8. "AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x0C 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x10 "GPIOCLKGS,GPIO Clock Gate For Sleep Mode"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x14 "GPIOCLKGDS,GPIO Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x18 "GPTCLKGR,GPT Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 8.--11. "AM_CLK_EN,Each bit below has the following meaning:0: No force1: Force clock on for all modes (Run Sleep and Deep Sleep)Overrides CLK_EN GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled.ENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD.." "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x18 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clock Can be forced on by AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clock Can be forced on by..,?..."
|
|
line.long 0x1C "GPTCLKGS,GPT Clock Gate For Sleep Mode"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clockCan be forced on by GPTCLKGR.AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x20 "GPTCLKGDS,GPT Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x20 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 0.--3. "CLK_EN,Each bit below has the following meaning:0: Disable clock1: Enable clockCan be forced on by GPTCLKGR.AM_CLK_ENENUMs can be combinedFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x24 "I2CCLKGR,I2C Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 8.--9. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x24 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x24 0.--1. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x28 "I2CCLKGS,I2C Clock Gate For Sleep Mode"
|
|
hexmask.long 0x28 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x28 0.--1. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x2C "I2CCLKGDS,I2C Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x2C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x2C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x30 "UARTCLKGR,UART Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x30 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x30 8.--11. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x30 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x30 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x34 "UARTCLKGS,UART Clock Gate For Sleep Mode"
|
|
hexmask.long 0x34 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x34 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x38 "UARTCLKGDS,UART Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x38 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x38 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x3C "SSICLKGR,SSI Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x3C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x3C 8.--11. "AM_CLK_EN," "No force,Force clock on for all..,?..."
|
|
newline
|
|
rbitfld.long 0x3C 4.--7. "RESERVED4,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x3C 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x40 "SSICLKGS,SSI Clock Gate For Sleep Mode"
|
|
hexmask.long 0x40 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x40 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x44 "SSICLKGDS,SSI Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x44 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x44 0.--3. "CLK_EN," "Disable clock,Enable clockCan be forced on by..,?..."
|
|
line.long 0x48 "I2SCLKGR,I2S Clock Gate For Run And All Modes"
|
|
hexmask.long.tbyte 0x48 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x48 8. "AM_CLK_EN," "No force,Force clock on for all.."
|
|
newline
|
|
hexmask.long.byte 0x48 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x48 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x4C "I2SCLKGS,I2S Clock Gate For Sleep Mode"
|
|
hexmask.long 0x4C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x4C 0. "CLK_EN," "Disable clock,Enable clockCan be forced on by.."
|
|
line.long 0x50 "I2SCLKGDS,I2S Clock Gate For Deep Sleep Mode"
|
|
hexmask.long 0x50 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x50 0. "CLK_EN," "Disable clock,Enable clockSYSBUS clock will always.."
|
|
group.long 0xB4++0x2B
|
|
line.long 0x00 "SYSBUSCLKDIV,Internal"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Internal"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?"
|
|
line.long 0x04 "CPUCLKDIV,Internal"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Internal"
|
|
newline
|
|
bitfld.long 0x04 0. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API."
|
|
line.long 0x08 "PERBUSCPUCLKDIV,Internal"
|
|
hexmask.long 0x08 4.--31. 1. "RESERVED4,Internal"
|
|
newline
|
|
bitfld.long 0x08 0.--3. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.long 0x0C "PERBUSDMACLKDIV,Internal"
|
|
line.long 0x10 "PERDMACLKDIV,Internal"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Internal"
|
|
newline
|
|
bitfld.long 0x10 0.--3. "RATIO,Internal" "Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,Internal. Only to be used through TI provided API.,?,?,?,?,?,?,?"
|
|
line.long 0x14 "I2SBCLKSEL,I2S Clock Control"
|
|
hexmask.long 0x14 1.--31. 1. "SPARE1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 0. "SRC,BCLK source selector0: Use external BCLK1: Use internally generated clockFor changes to take effect CLKLOADCTL.LOAD needs to be written" "Use external BCLK,Use internally generated clockFor changes to.."
|
|
line.long 0x18 "GPTCLKDIV,GPT Scalar"
|
|
hexmask.long 0x18 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 0.--3. "RATIO,Scalar used for GPTs" "Divide by 1,Divide by 2,Divide by 4,Divide by 8,Divide by 16,Divide by 32,Divide by 64,Divide by 128,Divide by 256,?,?,?,?,?,?,?"
|
|
line.long 0x1C "I2SCLKCTL,I2S Clock Control"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 3. "SMPL_ON_POSEDGE,On the I2S serial interface data and WCLK is sampled and clocked out on opposite edges of BCLK" "data and WCLK are sampled on the negative edge..,data and WCLK are sampled on the positive edge.."
|
|
newline
|
|
bitfld.long 0x1C 1.--2. "WCLK_PHASE,Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV)" "Single phase,Dual phase,User Defined,Reserved/UndefinedFor changes to.."
|
|
newline
|
|
bitfld.long 0x1C 0. "EN," "MCLK BCLK and WCLK will be static low,Enables the generation of MCLK BCLK and WCLKFor.."
|
|
line.long 0x20 "I2SMCLKDIV,MCLK Division Ratio"
|
|
hexmask.long.tbyte 0x20 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--9. 1. "MDIV,An unsigned factor of the division ratio used to generate MCLK [2-1024]:MCLK = MCUCLK/MDIV[Hz]MCUCLK is 48MHz.A value of 0 is interpreted as 1024.A value of 1 is invalid.If MDIV is odd the low phase of the clock is one MCUCLK period longer than the.."
|
|
line.long 0x24 "I2SBCLKDIV,BCLK Division Ratio"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED10,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x24 0.--9. 1. "BDIV,An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]:BCLK = MCUCLK/BDIV[Hz]MCUCLK is 48MHz.A value of 0 is interpreted as 1024.A value of 1 is invalid.If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0 the low phase of the.."
|
|
line.long 0x28 "I2SWCLKDIV,WCLK Division Ratio"
|
|
hexmask.long.word 0x28 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "WDIV,If I2SCLKCTL.WCLK_PHASE = 0 Single phase.WCLK is high one BCLK period and low WDIV[9:0] (unsigned [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]MCUCLK is 48MHz.If I2SCLKCTL.WCLK_PHASE = 1 Dual phase.Each phase on WCLK (50% duty.."
|
|
group.long 0xF0++0x1B
|
|
line.long 0x00 "RESETSECDMA,RESET For SEC (PKA And TRNG And CRYPTO) And UDMA"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA,Write 1 to reset" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 3.--7. "RESERVED3,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "PKA,Write 1 to reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRNG,Write 1 to reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CRYPTO,Write 1 to reset" "0,1"
|
|
line.long 0x04 "RESETGPIO,RESET For GPIO IPs"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "GPIO," "No action,Reset GPIO"
|
|
line.long 0x08 "RESETGPT,RESET For GPT Ips"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "GPT," "No action,Reset all GPTs"
|
|
line.long 0x0C "RESETI2C,RESET For I2C IPs"
|
|
hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 1. "I2C1," "No action,Reset I2C1"
|
|
newline
|
|
bitfld.long 0x0C 0. "I2C0," "No action,Reset I2C0"
|
|
line.long 0x10 "RESETUART,RESET For UART IPs"
|
|
hexmask.long 0x10 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 3. "UART3," "No action,Reset UART3"
|
|
newline
|
|
bitfld.long 0x10 2. "UART2," "No action,Reset UART2"
|
|
newline
|
|
bitfld.long 0x10 1. "UART1," "No action,Reset UART1"
|
|
newline
|
|
bitfld.long 0x10 0. "UART0," "No action,Reset UART0"
|
|
line.long 0x14 "RESETSSI,RESET For SSI IPs"
|
|
hexmask.long 0x14 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 3. "SSI3," "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "SSI2," "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "SSI1," "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SSI0," "0,1"
|
|
line.long 0x18 "RESETI2S,RESET For I2S IP"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x18 0. "I2S," "No action,Reset module"
|
|
group.long 0x12C++0x0F
|
|
line.long 0x00 "PDCTL0,Power Domain Control"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "PERIPH_ON,PERIPH Power domain.0: PERIPH power domain is powered down1: PERIPH power domain is powered up" "PERIPH power domain is powered down,PERIPH power domain is powered up"
|
|
newline
|
|
bitfld.long 0x00 1. "SERIAL_ON,SERIAL Power domain.0: SERIAL power domain is powered down1: SERIAL power domain is powered up" "SERIAL power domain is powered down,SERIAL power domain is powered up"
|
|
newline
|
|
bitfld.long 0x00 0. "RFC_ON," "RFC power domain powered off if also..,RFC power domain powered on"
|
|
line.long 0x04 "PDCTL0RFC,RFC Power Domain Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,Alias for PDCTL0.RFC_ON" "0,1"
|
|
line.long 0x08 "PDCTL0SERIAL,SERIAL Power Domain Control"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,Alias for PDCTL0.SERIAL_ON" "0,1"
|
|
line.long 0x0C "PDCTL0PERIPH,PERIPH Power Domain Control"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,Alias for PDCTL0.PERIPH_ON" "0,1"
|
|
rgroup.long 0x140++0x0F
|
|
line.long 0x00 "PDSTAT0,Power Domain Status"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 2. "PERIPH_ON,PERIPH Power domain.0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
newline
|
|
bitfld.long 0x00 1. "SERIAL_ON,SERIAL Power domain.0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
newline
|
|
bitfld.long 0x00 0. "RFC_ON,RFC Power domain0: Domain may be powered down1: Domain powered up (guaranteed)" "Domain may be powered down,Domain powered up (guaranteed)"
|
|
line.long 0x04 "PDSTAT0RFC,RFC Power Domain Status"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,Alias for PDSTAT0.RFC_ON" "0,1"
|
|
line.long 0x08 "PDSTAT0SERIAL,SERIAL Power Domain Status"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,Alias for PDSTAT0.SERIAL_ON" "0,1"
|
|
line.long 0x0C "PDSTAT0PERIPH,PERIPH Power Domain Status"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,Alias for PDSTAT0.PERIPH_ON" "0,1"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "PDCTL1,Power Domain Control"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "VIMS_MODE," "VIMS power domain is only powered when CPU power..,VIMS power domain is powered whenever the BUS..,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "RFC_ON," "RFC power domain powered off if also..,RFC power domain powered on Bit shall be used by.."
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_ON," "Causes a power down of the CPU power domain when..,Initiates power-on of the CPU power domain.This.."
|
|
newline
|
|
rbitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
group.long 0x184++0x0B
|
|
line.long 0x00 "PDCTL1CPU,CPU Power Domain Direct Control"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0. "ON,This is an alias for PDCTL1.CPU_ON" "0,1"
|
|
line.long 0x04 "PDCTL1RFC,RFC Power Domain Direct Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,This is an alias for PDCTL1.RFC_ON" "0,1"
|
|
line.long 0x08 "PDCTL1VIMS,VIMS Mode Direct Control"
|
|
hexmask.long 0x08 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0.--1. "MODE,This is an alias for PDCTL1.VIMS_MODE" "0,1,2,3"
|
|
rgroup.long 0x194++0x13
|
|
line.long 0x00 "PDSTAT1,Power Manager Status"
|
|
hexmask.long 0x00 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4. "BUS_ON," "BUS domain not accessible,BUS domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 3. "VIMS_ON," "VIMS domain not accessible,VIMS domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 2. "RFC_ON," "RFC domain not accessible,RFC domain is currently accessible"
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_ON," "CPU and BUS domain not accessible,CPU and BUS domains are both currently accessible"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x04 "PDSTAT1BUS,BUS Power Domain Direct Read Status"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0. "ON,This is an alias for PDSTAT1.BUS_ON" "0,1"
|
|
line.long 0x08 "PDSTAT1RFC,RFC Power Domain Direct Read Status"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 0. "ON,This is an alias for PDSTAT1.RFC_ON" "0,1"
|
|
line.long 0x0C "PDSTAT1CPU,CPU Power Domain Direct Read Status"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 0. "ON,This is an alias for PDSTAT1.CPU_ON" "0,1"
|
|
line.long 0x10 "PDSTAT1VIMS,VIMS Mode Direct Read Status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x10 0. "ON,This is an alias for PDSTAT1.VIMS_ON" "0,1"
|
|
group.long 0x1CC++0x0B
|
|
line.long 0x00 "RFCBITS,Control To RFC"
|
|
line.long 0x04 "RFCMODESEL,Selected RFC Mode"
|
|
hexmask.long 0x04 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 0.--2. "CURR,Selects the set of commands that the RFC will accept" "Select Mode 0,Select Mode 1,Select Mode 2,Select Mode 3,Select Mode 4,Select Mode 5,Select Mode 6,Select Mode 7"
|
|
line.long 0x08 "RFCMODEHWOPT,Allowed RFC Modes"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. "AVAIL,Permitted RFC modes"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "PWRPROFSTAT,Power Profiler Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VALUE,SW can use these bits to timestamp the application"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "MCUSRAMCFG,MCU SRAM configuration"
|
|
hexmask.long 0x00 7.--31. 1. "RESERVED7,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "PARITY_EN,Parity enable0: Parity disabled Parity section available as GPRAM1: Parity enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BM_OFF,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PAGE,Page Mode select0: Page Mode disabled" "Page Mode disabled,Page Mode enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "PGS,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "BM,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "PCH_F,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PCH_L,NOT in use.Writing any other value than the reset value may result in undefined behavior." "0,1"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "RAMRETEN,Memory Retention Control"
|
|
hexmask.long 0x00 4.--31. 1. "RESERVED4,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 3. "RFCULL," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RFC," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "VIMS," "VIMS,VIMS,?..."
|
|
group.long 0x290++0x0B
|
|
line.long 0x00 "OSCIMSC,Oscillator Interrupt Mask Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "HFSRCPENDIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "LFSRCDONEIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "XOSCDLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "XOSCLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RCOSCDLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RCOSCLFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "XOSCHFIM," "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RCOSCHFIM," "0,1"
|
|
line.long 0x04 "OSCRIS,Oscillator Raw Interrupt Status"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 7. "HFSRCPENDRIS,SCLK_HF source switch pending interrupt.After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source change request then the requested SCLK_HF source will be enabled and qualified" "Indicates SCLK_HF source is not ready to be..,Indicates SCLK_HF source is ready to be.."
|
|
newline
|
|
bitfld.long 0x04 6. "LFSRCDONERIS,SCLK_LF source switch done.The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that the SCLK_LF source shall be changed" "Indicates SCLK_LF source switch has not completed,Indicates SCLK_LF source switch has completed.."
|
|
newline
|
|
bitfld.long 0x04 5. "XOSCDLFRIS,The XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF" "XOSCDLF has not been qualified,XOSCDLF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 4. "XOSCLFRIS,The XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator has been qualified with respect to frequency" "XOSCLF has not been qualified,XOSCLF has been qualified Interrupt is qualified.."
|
|
newline
|
|
bitfld.long 0x04 3. "RCOSCDLFRIS,The RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF" "RCOSCDLF has not been qualified,RCOSCDLF has been qualifiedInterrupt is.."
|
|
newline
|
|
bitfld.long 0x04 2. "RCOSCLFRIS,The RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF oscillator has been qualified with respect to frequency" "RCOSCLF has not been qualified,RCOSCLF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 1. "XOSCHFRIS,The XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been qualified for use as a clock source" "XOSC_HF has not been qualified,XOSC_HF has been qualified Interrupt is.."
|
|
newline
|
|
bitfld.long 0x04 0. "RCOSCHFRIS,The RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been qualified for use as a clock source When the RCOSCHFRIS interrupt is high the oscillator is qualified and will be used as a clock source when selected" "RCOSC_HF has not been qualified,RCOSC_HF has been qualifiedInterrupt is.."
|
|
line.long 0x08 "OSCICR,Oscillator Raw Interrupt Clear"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 7. "HFSRCPENDC,Writing 1 to this field clears the HFSRCPEND raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. "LFSRCDONEC,Writing 1 to this field clears the LFSRCDONE raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "XOSCDLFC,Writing 1 to this field clears the XOSCDLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "XOSCLFC,Writing 1 to this field clears the XOSCLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "RCOSCDLFC,Writing 1 to this field clears the RCOSCDLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "RCOSCLFC,Writing 1 to this field clears the RCOSCLF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "XOSCHFC,Writing 1 to this field clears the XOSCHF raw interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "RCOSCHFC,Writing 1 to this field clears the RCOSCHF raw interrupt status" "0,1"
|
|
group.long 0x2B0++0x17
|
|
line.long 0x00 "NVMNSCADDR,NVM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x00 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "BOUNDARY,Non-Secure callable boundary address"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x04 "NVMNSADDR,NVM Non-Secure boundary Address"
|
|
rbitfld.long 0x04 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x04 21.--30. 1. "RESERVED21,Software should not rely on the value of a reserved"
|
|
newline
|
|
rbitfld.long 0x04 20. "BOUNDARY_MSB,Non-Secure boundary address MSBHW controlled." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x04 13.--19. 1. "BOUNDARY,Non-Secure boundary address.Writing this field when BUSSECCFG.VALID is set may result in undefined behavior."
|
|
newline
|
|
hexmask.long.word 0x04 0.--12. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x08 "SRAMNSCADDR,SRAM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x08 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x08 19.--30. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x08 10.--18. 1. "BOUNDARY,Non-Secure callable boundary address"
|
|
newline
|
|
hexmask.long.word 0x08 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "SRAMNSADDR,SRAM Non-Secure Callable boundary Address"
|
|
rbitfld.long 0x0C 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0C 19.--30. 1. "RESERVED19,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.word 0x0C 10.--18. 1. "BOUNDARY,Non-Secure boundary address.Writing this field when BUSSECCFG.VALID is set may result in undefined behavior."
|
|
newline
|
|
hexmask.long.word 0x0C 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x10 "BUSSECCFG,BUS Secuirty Configuration Register"
|
|
bitfld.long 0x10 31. "VALID,Security configuration validRegisters that needs to be followed by VALID before settings being applied are:- NVMNSCADDR- NVMNSADDR- SRAMNSCADDR- SRAMNSADDR- BUSSECCFG- CPULOCK" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x10 8.--30. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "BUS_CFG,Bus interconnect security and firewall configuration"
|
|
line.long 0x14 "CPULOCK,CPU Lock Register"
|
|
rbitfld.long 0x14 31. "PARITY,Register parity bit" "0,1"
|
|
newline
|
|
hexmask.long 0x14 5.--30. 1. "RESERVED5,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x14 4. "LOCKNSVTOR,When set will lock non-secure vector table base addressWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LOCKSVTAIRCR,When set will lock- Secure vector table base address- Secure interrupt priority- Busfault- Hardfault NMI security targetWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "LOCKSAU,When set will lock SAU regionsWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LOCKNSMPU,When set will lock non-secure MPUWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "LOCKSMPU,When set will lock secure MPUWriting this field when BUSSECCFG.VALID is set may result in undefined behavior." "0,1"
|
|
tree.end
|
|
tree "RFC"
|
|
tree "RFC_DBELL"
|
|
base ad:0x40041000
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "CMDR,Doorbell Command Register"
|
|
line.long 0x04 "CMDSTA,Doorbell Command Status Register"
|
|
line.long 0x08 "RFHWIFG,Interrupt Flags From RF Hardware Modules"
|
|
hexmask.long.word 0x08 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x08 19. "RATCH7,Radio timer channel 7 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 18. "RATCH6,Radio timer channel 6 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 17. "RATCH5,Radio timer channel 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. "RATCH4,Radio timer channel 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 15. "RATCH3,Radio timer channel 3 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 14. "RATCH2,Radio timer channel 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 13. "RATCH1,Radio timer channel 1 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 12. "RATCH0,Radio timer channel 0 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 11. "RFESOFT2,RF engine software defined interrupt 2 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. "RFESOFT1,RF engine software defined interrupt 1 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. "RFESOFT0,RF engine software defined interrupt 0 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. "RFEDONE,RF engine command done interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. "TRCTK,Debug tracer system tick interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 5. "MDMSOFT,Modem software defined interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 4. "MDMOUT,Modem FIFO output interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. "MDMIN,Modem FIFO input interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 2. "MDMDONE,Modem command done interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 1. "FSCA,Frequency synthesizer calibration accelerator interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x0C "RFHWIEN,Interrupt Enable For RF Hardware Modules"
|
|
hexmask.long.word 0x0C 20.--31. 1. "RESERVED20,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x0C 19. "RATCH7,Interrupt enable for RFHWIFG.RATCH7" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 18. "RATCH6,Interrupt enable for RFHWIFG.RATCH6" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 17. "RATCH5,Interrupt enable for RFHWIFG.RATCH5" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. "RATCH4,Interrupt enable for RFHWIFG.RATCH4" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 15. "RATCH3,Interrupt enable for RFHWIFG.RATCH3" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 14. "RATCH2,Interrupt enable for RFHWIFG.RATCH2" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 13. "RATCH1,Interrupt enable for RFHWIFG.RATCH1" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 12. "RATCH0,Interrupt enable for RFHWIFG.RATCH0" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 11. "RFESOFT2,Interrupt enable for RFHWIFG.RFESOFT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 10. "RFESOFT1,Interrupt enable for RFHWIFG.RFESOFT1" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. "RFESOFT0,Interrupt enable for RFHWIFG.RFESOFT0" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 8. "RFEDONE,Interrupt enable for RFHWIFG.RFEDONE" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. "TRCTK,Interrupt enable for RFHWIFG.TRCTK" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 5. "MDMSOFT,Interrupt enable for RFHWIFG.MDMSOFT" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 4. "MDMOUT,Interrupt enable for RFHWIFG.MDMOUT" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. "MDMIN,Interrupt enable for RFHWIFG.MDMIN" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 2. "MDMDONE,Interrupt enable for RFHWIFG.MDMDONE" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 1. "FSCA,Interrupt enable for RFHWIFG.FSCA" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x10 "RFCPEIFG,Interrupt Flags For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x10 31. "INTERNAL_ERROR,Interrupt flag 31" "0,1"
|
|
newline
|
|
bitfld.long 0x10 30. "BOOT_DONE,Interrupt flag 30" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "MODULES_UNLOCKED,Interrupt flag 29" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. "SYNTH_NO_LOCK,Interrupt flag 28" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "IRQ27,Interrupt flag 27" "0,1"
|
|
newline
|
|
bitfld.long 0x10 26. "RX_ABORTED,Interrupt flag 26" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "RX_N_DATA_WRITTEN,Interrupt flag 25" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "RX_DATA_WRITTEN,Interrupt flag 24" "0,1"
|
|
newline
|
|
bitfld.long 0x10 23. "RX_ENTRY_DONE,Interrupt flag 23" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "RX_BUF_FULL,Interrupt flag 22" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "RX_CTRL_ACK,Interrupt flag 21" "0,1"
|
|
newline
|
|
bitfld.long 0x10 20. "RX_CTRL,Interrupt flag 20" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "RX_EMPTY,Interrupt flag 19" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "RX_IGNORED,Interrupt flag 18" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "RX_NOK,Interrupt flag 17" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "RX_OK,Interrupt flag 16" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "IRQ15,Interrupt flag 15" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "IRQ14,Interrupt flag 14" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FG_COMMAND_STARTED,Interrupt flag 13" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "COMMAND_STARTED,Interrupt flag 12" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "TX_BUFFER_CHANGED,Interrupt flag 11" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "TX_ENTRY_DONE,Interrupt flag 10" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "TX_RETRANS,Interrupt flag 9" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "TX_CTRL_ACK_ACK,Interrupt flag 8" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "TX_CTRL_ACK,Interrupt flag 7" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "TX_CTRL,Interrupt flag 6" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "TX_ACK,Interrupt flag 5" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "TX_DONE,Interrupt flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "LAST_FG_COMMAND_DONE,Interrupt flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "FG_COMMAND_DONE,Interrupt flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "LAST_COMMAND_DONE,Interrupt flag 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "COMMAND_DONE,Interrupt flag 0" "0,1"
|
|
line.long 0x14 "RFCPEIEN,Interrupt Enable For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x14 31. "INTERNAL_ERROR,Interrupt enable for RFCPEIFG.INTERNAL_ERROR" "0,1"
|
|
newline
|
|
bitfld.long 0x14 30. "BOOT_DONE,Interrupt enable for RFCPEIFG.BOOT_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "MODULES_UNLOCKED,Interrupt enable for RFCPEIFG.MODULES_UNLOCKED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. "SYNTH_NO_LOCK,Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "IRQ27,Interrupt enable for RFCPEIFG.IRQ27" "0,1"
|
|
newline
|
|
bitfld.long 0x14 26. "RX_ABORTED,Interrupt enable for RFCPEIFG.RX_ABORTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "RX_N_DATA_WRITTEN,Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24. "RX_DATA_WRITTEN,Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN" "0,1"
|
|
newline
|
|
bitfld.long 0x14 23. "RX_ENTRY_DONE,Interrupt enable for RFCPEIFG.RX_ENTRY_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. "RX_BUF_FULL,Interrupt enable for RFCPEIFG.RX_BUF_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "RX_CTRL_ACK,Interrupt enable for RFCPEIFG.RX_CTRL_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 20. "RX_CTRL,Interrupt enable for RFCPEIFG.RX_CTRL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "RX_EMPTY,Interrupt enable for RFCPEIFG.RX_EMPTY" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "RX_IGNORED,Interrupt enable for RFCPEIFG.RX_IGNORED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 17. "RX_NOK,Interrupt enable for RFCPEIFG.RX_NOK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. "RX_OK,Interrupt enable for RFCPEIFG.RX_OK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "IRQ15,Interrupt enable for RFCPEIFG.IRQ15" "0,1"
|
|
newline
|
|
bitfld.long 0x14 14. "IRQ14,Interrupt enable for RFCPEIFG.IRQ14" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "FG_COMMAND_STARTED,Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "COMMAND_STARTED,Interrupt enable for RFCPEIFG.COMMAND_STARTED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "TX_BUFFER_CHANGED,Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "TX_ENTRY_DONE,Interrupt enable for RFCPEIFG.TX_ENTRY_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "TX_RETRANS,Interrupt enable for RFCPEIFG.TX_RETRANS" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "TX_CTRL_ACK_ACK,Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "TX_CTRL_ACK,Interrupt enable for RFCPEIFG.TX_CTRL_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "TX_CTRL,Interrupt enable for RFCPEIFG.TX_CTRL" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "TX_ACK,Interrupt enable for RFCPEIFG.TX_ACK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "TX_DONE,Interrupt enable for RFCPEIFG.TX_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LAST_FG_COMMAND_DONE,Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "FG_COMMAND_DONE,Interrupt enable for RFCPEIFG.FG_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LAST_COMMAND_DONE,Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "COMMAND_DONE,Interrupt enable for RFCPEIFG.COMMAND_DONE" "0,1"
|
|
line.long 0x18 "RFCPEISL,Interrupt Vector Selection For Command and Packet Engine Generated Interrupts"
|
|
bitfld.long 0x18 31. "INTERNAL_ERROR,Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 30. "BOOT_DONE,Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 29. "MODULES_UNLOCKED,Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 28. "SYNTH_NO_LOCK,Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 27. "IRQ27,Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 26. "RX_ABORTED,Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 25. "RX_N_DATA_WRITTEN,Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 24. "RX_DATA_WRITTEN,Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 23. "RX_ENTRY_DONE,Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 22. "RX_BUF_FULL,Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 21. "RX_CTRL_ACK,Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 20. "RX_CTRL,Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 19. "RX_EMPTY,Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 18. "RX_IGNORED,Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 17. "RX_NOK,Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 16. "RX_OK,Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 15. "IRQ15,Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 14. "IRQ14,Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 13. "FG_COMMAND_STARTED,Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 12. "COMMAND_STARTED,Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 11. "TX_BUFFER_CHANGED,Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 10. "TX_ENTRY_DONE,Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 9. "TX_RETRANS,Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 8. "TX_CTRL_ACK_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 7. "TX_CTRL_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 6. "TX_CTRL,Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 5. "TX_ACK,Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 4. "TX_DONE,Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 3. "LAST_FG_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 2. "FG_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 1. "LAST_COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
newline
|
|
bitfld.long 0x18 0. "COMMAND_DONE,Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should use" "Associate this interrupt line with INT_RF_CPE0..,Associate this interrupt line with INT_RF_CPE1.."
|
|
line.long 0x1C "RFACKIFG,Doorbell Command Acknowledgement Interrupt Flag"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x1C 0. "ACKFLAG,Interrupt flag for Command ACK" "0,1"
|
|
line.long 0x20 "SYSGPOCTL,RF Core General Purpose Output Control"
|
|
hexmask.long.word 0x20 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x20 12.--15. "GPOCTL3,RF Core GPO control bit 3" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 8.--11. "GPOCTL2,RF Core GPO control bit 2" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 4.--7. "GPOCTL1,RF Core GPO control bit 1" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
newline
|
|
bitfld.long 0x20 0.--3. "GPOCTL0,RF Core GPO control bit 0" "CPE GPO line 0,CPE GPO line 1,CPE GPO line 2,CPE GPO line 3,MCE GPO line 0,MCE GPO line 1,MCE GPO line 2,MCE GPO line 3,RFE GPO line 0,RFE GPO line 1,RFE GPO line 2,RFE GPO line 3,RAT GPO line 0,RAT GPO line 1,RAT GPO line 2,RAT GPO line 3"
|
|
tree.end
|
|
tree "RFC_PWR"
|
|
base ad:0x40040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCLKEN,RF Core Power Management and Clock Enable"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED14,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 13. "DEMOD,Enable clock to the Demodulator" "0,1"
|
|
bitfld.long 0x00 12. "MOD,Enable clock to the Modulator" "0,1"
|
|
bitfld.long 0x00 11. "IQRAM,Enable clock to IQ RAM in coherent demodulator" "0,1"
|
|
bitfld.long 0x00 10. "RFCTRC,Enable clock to the RF Core Tracer (RFCTRC) module" "0,1"
|
|
bitfld.long 0x00 9. "FSCA,Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) module" "0,1"
|
|
bitfld.long 0x00 8. "PHA,Enable clock to the Packet Handling Accelerator (PHA) module" "0,1"
|
|
bitfld.long 0x00 7. "RAT,Enable clock to the Radio Timer (RAT) module" "0,1"
|
|
bitfld.long 0x00 6. "RFERAM,Enable clock to the RF Engine RAM module" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RFE,Enable clock to the RF Engine (RFE) module" "0,1"
|
|
bitfld.long 0x00 4. "MDMRAM,Enable clock to the Modem RAM module" "0,1"
|
|
bitfld.long 0x00 3. "MDM,Enable clock to the Modem (MDM) module" "0,1"
|
|
bitfld.long 0x00 2. "CPERAM,Enable clock to the Command and Packet Engine (CPE) RAM module" "0,1"
|
|
bitfld.long 0x00 1. "CPE,Enable processor clock (hclk) to the Command and Packet Engine (CPE)" "0,1"
|
|
rbitfld.long 0x00 0. "RFC,Enable essential clocks for the RF Core interface" "0,1"
|
|
tree.end
|
|
tree "RFC_RAT"
|
|
base ad:0x40043000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RATCNT,Radio Timer Counter Value"
|
|
group.long 0x80++0x1F
|
|
line.long 0x00 "RATCH0VAL,Timer Channel 0 Capture/Compare Register"
|
|
line.long 0x04 "RATCH1VAL,Timer Channel 1 Capture/Compare Register"
|
|
line.long 0x08 "RATCH2VAL,Timer Channel 2 Capture/Compare Register"
|
|
line.long 0x0C "RATCH3VAL,Timer Channel 3 Capture/Compare Register"
|
|
line.long 0x10 "RATCH4VAL,Timer Channel 4 Capture/Compare Register"
|
|
line.long 0x14 "RATCH5VAL,Timer Channel 5 Capture/Compare Register"
|
|
line.long 0x18 "RATCH6VAL,Timer Channel 6 Capture/Compare Register"
|
|
line.long 0x1C "RATCH7VAL,Timer Channel 7 Capture/Compare Register"
|
|
tree.end
|
|
tree.end
|
|
tree "SMPH"
|
|
base ad:0x40084000
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SMPH$1,MCU SEMAPHORE 0"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is availableReading the register causes it to change value to 0" "Semaphore is taken,Semaphore is availableReading the register.."
|
|
repeat.end
|
|
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "SMPH$1,MCU SEMAPHORE 16"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is availableReading the register causes it to change value to 0" "Semaphore is taken,Semaphore is availableReading the register.."
|
|
repeat.end
|
|
rgroup.long 0x800++0x7F
|
|
line.long 0x00 "PEEK0,MCU SEMAPHORE 0 ALIAS"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x04 "PEEK1,MCU SEMAPHORE 1 ALIAS"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x08 "PEEK2,MCU SEMAPHORE 2 ALIAS"
|
|
hexmask.long 0x08 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x0C "PEEK3,MCU SEMAPHORE 3 ALIAS"
|
|
hexmask.long 0x0C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x0C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x10 "PEEK4,MCU SEMAPHORE 4 ALIAS"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x14 "PEEK5,MCU SEMAPHORE 5 ALIAS"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x18 "PEEK6,MCU SEMAPHORE 6 ALIAS"
|
|
hexmask.long 0x18 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x18 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x1C "PEEK7,MCU SEMAPHORE 7 ALIAS"
|
|
hexmask.long 0x1C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x1C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x20 "PEEK8,MCU SEMAPHORE 8 ALIAS"
|
|
hexmask.long 0x20 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x20 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x24 "PEEK9,MCU SEMAPHORE 9 ALIAS"
|
|
hexmask.long 0x24 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x24 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x28 "PEEK10,MCU SEMAPHORE 10 ALIAS"
|
|
hexmask.long 0x28 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x28 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x2C "PEEK11,MCU SEMAPHORE 11 ALIAS"
|
|
hexmask.long 0x2C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x2C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x30 "PEEK12,MCU SEMAPHORE 12 ALIAS"
|
|
hexmask.long 0x30 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x30 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x34 "PEEK13,MCU SEMAPHORE 13 ALIAS"
|
|
hexmask.long 0x34 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x34 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x38 "PEEK14,MCU SEMAPHORE 14 ALIAS"
|
|
hexmask.long 0x38 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x38 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x3C "PEEK15,MCU SEMAPHORE 15 ALIAS"
|
|
hexmask.long 0x3C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x3C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x40 "PEEK16,MCU SEMAPHORE 16 ALIAS"
|
|
hexmask.long 0x40 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x40 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x44 "PEEK17,MCU SEMAPHORE 17 ALIAS"
|
|
hexmask.long 0x44 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x44 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x48 "PEEK18,MCU SEMAPHORE 18 ALIAS"
|
|
hexmask.long 0x48 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x48 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x4C "PEEK19,MCU SEMAPHORE 19 ALIAS"
|
|
hexmask.long 0x4C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x4C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x50 "PEEK20,MCU SEMAPHORE 20 ALIAS"
|
|
hexmask.long 0x50 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x50 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x54 "PEEK21,MCU SEMAPHORE 21 ALIAS"
|
|
hexmask.long 0x54 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x54 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x58 "PEEK22,MCU SEMAPHORE 22 ALIAS"
|
|
hexmask.long 0x58 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x58 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x5C "PEEK23,MCU SEMAPHORE 23 ALIAS"
|
|
hexmask.long 0x5C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x5C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x60 "PEEK24,MCU SEMAPHORE 24 ALIAS"
|
|
hexmask.long 0x60 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x60 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x64 "PEEK25,MCU SEMAPHORE 25 ALIAS"
|
|
hexmask.long 0x64 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x64 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x68 "PEEK26,MCU SEMAPHORE 26 ALIAS"
|
|
hexmask.long 0x68 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x68 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x6C "PEEK27,MCU SEMAPHORE 27 ALIAS"
|
|
hexmask.long 0x6C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x6C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x70 "PEEK28,MCU SEMAPHORE 28 ALIAS"
|
|
hexmask.long 0x70 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x70 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x74 "PEEK29,MCU SEMAPHORE 29 ALIAS"
|
|
hexmask.long 0x74 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x74 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x78 "PEEK30,MCU SEMAPHORE 30 ALIAS"
|
|
hexmask.long 0x78 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x78 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
line.long 0x7C "PEEK31,MCU SEMAPHORE 31 ALIAS"
|
|
hexmask.long 0x7C 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x7C 0. "STAT,Status when reading:0: Semaphore is taken1: Semaphore is available Used for semaphore debugging" "Semaphore is taken,Semaphore is available Used for semaphore.."
|
|
tree.end
|
|
tree "SPI"
|
|
repeat 4. (list 0. 1. 2. 3. )(list ad:0x40000000 ad:0x40008000 ad:0x40009000 ad:0x4000A000 )
|
|
tree "SPI$1"
|
|
base $2
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "IIDX,This register provides the highest priority enabled interrupt index"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "STAT,Interrupt index status"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMASK,Interrupt Mask"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA_DONE_TX,DMA Done 1 event for TX event mask" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 7. "DMA_DONE_RX,DMA Done 1 event for RX event mask" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 6. "IDLE,SPI Idle event mask" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 5. "TXEMPTY,Transmit FIFO Empty event mask" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 4. "TX,Transmit FIFO event mask" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 3. "RX,Receive FIFO event" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 2. "RTOUT,Enable SPI Receive Time-Out event mask" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 1. "PER,Parity error event mask" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "RXFIFO_OVF,RXFIFO overflow event mask" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RIS,Raw interrupt status"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA_DONE_TX,DMA Done 1 event for TX" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 7. "DMA_DONE_RX,DMA Done 1 event for RX" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "IDLE,SPI has done finished transfers and changed into IDLE mode" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "TXEMPTY,Transmit FIFO Empty interrupt mask" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 4. "TX,Transmit FIFO event" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "RX,Receive FIFO event" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 2. "RTOUT,SPI Receive Time-Out event" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 1. "PER,Parity error event: this bit is set if a Parity error has been detected" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "RXFIFO_OVF,RXFIFO overflow event" "Interrupt did not occur,Interrupt occurred"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MIS,Masked interrupt status"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA_DONE_TX,Masked DMA Done 1 event for TX" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 7. "DMA_DONE_RX,Masked DMA Done 1 event for RX" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "IDLE,Masked SPI IDLE mode event." "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "TXEMPTY,Masked Transmit FIFO Empty event" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 4. "TX,Masked Transmit FIFO event" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "RX,Masked receive FIFO event" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 2. "RTOUT,Masked SPI Receive Time-Out Interrupt" "Clear Interrupt Mask,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 1. "PER,Masked Parity error event: this bit if a Parity error has been detected" "Interrupt did not occur,Interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "RXFIFO_OVF,Masked RXFIFO overflow event" "Interrupt did not occur,Interrupt occurred"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ISET,Interrupt set"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA_DONE_TX,Set DMA Done 1 event for TX" "Writing 0 has no effect,Set Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. "DMA_DONE_RX,Set DMA Done 1 event for RX" "Writing 0 has no effect,Set Interrupt"
|
|
newline
|
|
bitfld.long 0x00 6. "IDLE,Set SPI IDLE mode event." "Writing 0 has no effect,Set Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. "TXEMPTY,Set Transmit FIFO Empty event" "Writing 0 has no effect,Set Interrupt"
|
|
newline
|
|
bitfld.long 0x00 4. "TX,Set Transmit FIFO event" "Writing 0 has no effect,Set Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "RX,Set Receive FIFO event" "Writing 0 has no effect,Set Interrupt"
|
|
newline
|
|
bitfld.long 0x00 2. "RTOUT,Set SPI Receive Time-Out Event" "Writing 0 has no effect,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 1. "PER,Set Parity error event" "Writing 0 has no effect,Set Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "RXFIFO_OVF,Set RXFIFO overflow event" "Writing 0 has no effect,Set Interrupt"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ICLR,Interrupt clear"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 8. "DMA_DONE_TX,Clear DMA Done 1 event for TX" "Writing 0 has no effect,Clear Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. "DMA_DONE_RX,Clear DMA Done 1 event for RX" "Writing 0 has no effect,Clear Interrupt"
|
|
newline
|
|
bitfld.long 0x00 6. "IDLE,Clear SPI IDLE mode event" "Writing 0 has no effect,Clear Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. "TXEMPTY,Clear Transmit FIFO Empty event" "Writing 0 has no effect,Clear Interrupt"
|
|
newline
|
|
bitfld.long 0x00 4. "TX,Clear Transmit FIFO event" "Writing 0 has no effect,Clear Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "RX,Clear Receive FIFO event" "Writing 0 has no effect,Clear Interrupt"
|
|
newline
|
|
bitfld.long 0x00 2. "RTOUT,Clear SPI Receive Time-Out Event" "Writing 0 has no effect,Set Interrupt Mask"
|
|
newline
|
|
bitfld.long 0x00 1. "PER,Clear Parity error event" "Writing 0 has no effect,Clear Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "RXFIFO_OVF,Clear RXFIFO overflow event" "Writing 0 has no effect,Clear Interrupt"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "EVT_MODE,Event mode register"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "The interrupt or event line is disabled.,The interrupt or event line is in software mode..,The interrupt or event line is in hardware mode..,?"
|
|
group.long 0xFC++0x1F
|
|
line.long 0x00 "DESC,This register identifies the peripheral and its exact version"
|
|
hexmask.long.word 0x00 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "FEATUREVER,Feature Set for the module *instance*" "Smallest value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Highest possible value"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "RESERVED8,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "MAJREV,Major rev of the IP" "Smallest value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Highest possible value"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "MINREV,Minor rev of the IP" "Smallest value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Highest possible value"
|
|
line.long 0x04 "CTL0,SPI control register 0"
|
|
hexmask.long.tbyte 0x04 15.--31. 1. "RESERVED15,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 14. "CSCLR,Clear shift register counter on CS inactiveThis bit is relevant only in the slave mode MS=0.0: The shift counter will keep its state when CS goes low1: The shift counter will be clear when CS goes low" "The shift counter will keep its state when CS..,The shift counter will be clear when CS goes low"
|
|
newline
|
|
bitfld.long 0x04 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x04 10.--11. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 9. "SPH,CLKOUT phase (Motorola SPI frame format only)This bit selects the clock edge that captures data and enables it to change state" "1ST_CLK_EDGE,2ND_CLK_EDGE"
|
|
newline
|
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bitfld.long 0x04 8. "SPO,CLKOUT polarity (Motorola SPI frame format only)0h = SPI produces a steady state LOW value on the CLKOUT pin when data is not being transferred.1h = SPI produces a steady state HIGH value on the CLKOUT pin when data is not being transferred" "SPI produces a steady state LOW value on the..,SPI produces a steady state HIGH value on the.."
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newline
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rbitfld.long 0x04 7. "RESERVED7,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x04 5.--6. "FRF,Frame format Select" "Motorola SPI frame format (3 wire mode),Motorola SPI frame format (4 wire mode),TI synchronous serial frame format,National Microwire frame format"
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newline
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bitfld.long 0x04 0.--4. "DSS,Data Size Select.Note: Master mode: Values" "?,?,?,Data Size Select bits: 4,Data Size Select bits: 5,Data Size Select bits: 6,Data Size Select bits: 7,Data Size Select bits: 8,Data Size Select bits: 9,Data Size Select bits: 10,Data Size Select bits: 11,Data Size Select bits: 12,Data Size Select bits: 13,Data Size Select bits: 14,Data Size Select bits: 15,Data Size Select bits: 16,Data Size Select bits: 17,Data Size Select bits: 18,Data Size Select bits: 19,Data Size Select bits: 20,Data Size Select bits: 21,Data Size Select bits: 22,Data Size Select bits: 23,Data Size Select bits: 24,Data Size Select bits: 25,Data Size Select bits: 26,Data Size Select bits: 27,Data Size Select bits: 28,Data Size Select bits: 29,Data Size Select bits: 30,Data Size Select bits: 31,Data Size Select bits: 32"
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line.long 0x08 "CTL1,SPI control register 1"
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rbitfld.long 0x08 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x08 24.--29. "RXTIMEOUT,Receive Timeout (only for Slave mode)Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set.The time is calculated using the control register for the clock selection and divider in the Master mode.." "Smallest value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Highest possible value"
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newline
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hexmask.long.byte 0x08 16.--23. 1. "REPEATTX,Counter to repeat last transfer0: repeat last transfer is disabled.x: repeat the last transfer with the given number.The transfer will be started with writing a data into the TX Buffer"
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newline
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bitfld.long 0x08 10.--15. "RESERVED10,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x08 8.--9. "MODE,SPI Communication Mode SelectNote: Reserved/undefined Modes are identical to Legacy mode" "Legacy Mode,?,multiSPI Mode with 2 Data Bits (not supported),multiSPI Mode with 4 Data Bits (not supported)"
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newline
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bitfld.long 0x08 7. "PBS,Parity Bit Select:Disabled: Bit 0 is used for ParityEnabled: Bit 1 is used for Parity Bit 0 is ignored" "Bit 0 is used for Parity,Bit 1 is used for Parity Bit 0 is ignored"
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newline
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bitfld.long 0x08 6. "PES,Even Parity Select" "Odd Parity mode,Even Parity mode"
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newline
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bitfld.long 0x08 5. "PEN,Parity enableif enabled the last bit will be used as parity to evaluate the right transmission of the previous bits.In case of a parity miss-match the parity error flag RIS.PER will be set" "Disable Parity function ,Enable Parity function "
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newline
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bitfld.long 0x08 4. "MSB,MSB first select" "LSB first,MSB first"
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newline
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bitfld.long 0x08 3. "SOD,Slave-mode: Data output disabledThis bit is relevant only in the slave mode MS=0" "SPI can drive the MISO output in slave mode,SPI cannot drive the MISO output in slave mode"
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newline
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bitfld.long 0x08 2. "MS,Master or slave mode select" "Device configured as slave,Device configured as master"
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newline
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bitfld.long 0x08 1. "LBM,Loop back mode:0: Normal serial port operation enabled.1: Output of transmit serial shifter is connected to input of receive serial shifter internally" "Normal serial port operation enabled,Output of transmit serial shifter is connected.."
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newline
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bitfld.long 0x08 0. "ENABLE,SPI enable0b = Disabled" "Disabled,Enabled"
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line.long 0x0C "CLKCTL,Clock prescaler and divider register"
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bitfld.long 0x0C 28.--31. "DSAMPLE,Delayed sampling" "Smallest value,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Highest possible value"
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newline
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hexmask.long.tbyte 0x0C 10.--27. 1. "RESERVED10,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x0C 0.--9. 1. "SCR,Serial clock divider:This is used to generate the transmit and receive bit rate of the SPI.The SPI bit rate is(SPI's functional clock frequency)/((SCR+1)*2).SCR is a value from 0-1023"
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line.long 0x10 "IFLS,The IFLS register is the interrupt FIFO level select register"
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hexmask.long 0x10 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 3.--5. "RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows" "Reserved,RX FIFO >= 1/4 full,RX FIFO >= 1/2 full (default),RX FIFO >= 3/4 full,Reserved,RX FIFO is full,Reserved,Trigger when RX FIFO contains >= 1 byteShould.."
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newline
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bitfld.long 0x10 0.--2. "TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows" "Reserved,TX FIFO <= 3/4 empty,TX FIFO <= 1/2 empty (default),TX FIFO <= 1/4 empty,Reserved,TX FIFO is empty,Reserved,Trigger when TX FIFO has >= 1 byte freeShould.."
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line.long 0x14 "STAT,Status Register"
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hexmask.long 0x14 5.--31. 1. "RESERVED5,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 4. "BUSY,Busy" "SPI is in idle mode.,SPI is currently transmitting and/or receiving.."
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newline
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bitfld.long 0x14 3. "RNF,Receive FIFO not full" "Receive FIFO is full.,Receive FIFO is not full."
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newline
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bitfld.long 0x14 2. "RFE,Receive FIFO empty" "Receive FIFO is not empty.,Receive FIFO is empty."
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newline
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bitfld.long 0x14 1. "TNF,Transmit FIFI not full" "Transmit FIFO is full.,Transmit FIFO is not full."
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newline
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bitfld.long 0x14 0. "TFE,Transmit FIFO empty" "Transmit FIFO is not empty.,Transmit FIFO is empty."
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line.long 0x18 "CLKDIV2,This register is used to specify module-specific divide ratio of the functional clock.(Only in Core Domain. for ULL use the CLKDIV in IPSTANDARD.)"
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hexmask.long 0x18 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 0.--2. "RATIO,Selects divide ratio of module clock" "Do not divide clock source,Divide clock source by 2,Divide clock source by 3,Divide clock source by 4,Divide clock source by 5,Divide clock source by 6,Divide clock source by 7,Divide clock source by 8"
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line.long 0x1C "DMACR,DMA Control Register"
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hexmask.long 0x1C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 1. "TXDMAE,Transmit DMA enable" "0,1"
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newline
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bitfld.long 0x1C 0. "RXDMAE,Receive DMA enable" "0,1"
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rgroup.long 0x130++0x03
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line.long 0x00 "RXDATA,RXDATA RegisterReading this register returns first value in the FIFO"
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group.long 0x140++0x03
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line.long 0x00 "TXDATA,TXDATA RegisterWriting put the data into the TX FIFOReading this register returns the last written value.Core Domain SPI can use up to 32 bitsULL Domain SPI can use up to 16 bits"
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tree.end
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repeat.end
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tree.end
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tree "SRAM_MMR"
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base ad:0x58035000
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group.long 0x00++0x13
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line.long 0x00 "PER_CTL,Parity Error Control Parity error check controls"
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hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
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bitfld.long 0x00 8. "PER_DISABLE,Parity Status Disable0: A parity error will update PER_CHK.PER_ADDR field1: Parity error does not update PER_CHK.PER_ADDR field" "A parity error will update PER_CHK.PER_ADDR field,Parity error does not update PER_CHK.PER_ADDR.."
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newline
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hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
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bitfld.long 0x00 0. "PER_DEBUG_ENABLE,Parity Error Debug Enable0: Normal operation1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity errors will be generated on reads from within this offset" "Normal operation,An address offset can be written to.."
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line.long 0x04 "PER_CHK,Parity Error CheckParity error check results"
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hexmask.long.byte 0x04 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.tbyte 0x04 0.--23. 1. "PER_ADDR,Parity Error Address OffsetReturns the last address offset which resulted in a parity error during an SRAM"
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line.long 0x08 "PER_DBG,Parity Error DebugParity error check debug address setting"
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hexmask.long.byte 0x08 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
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hexmask.long.tbyte 0x08 0.--23. 1. "PER_DEBUG_ADDR,Debug Parity Error Address OffsetWhen PER_CTL.PER_DEBUG is 1 this field is used to set a parity debug address offset"
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line.long 0x0C "MEM_CTL,Memory ControlControls memory initialization"
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abitfld.long 0x0C 8.--31. "MEM_SEL,Memory Instance SelectThis field is used to enable/disable initialization of each SRAM instance when triggered using MEM_CTL.MEM_CLR_EN" "0x000000=Initialization of instance x is disabled,0x000001=Initialization of instance x is enabled"
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rbitfld.long 0x0C 2.--7. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x0C 1. "MEM_BUSY,Memory Busy status0: Memory accepts transfers1: Memory controller is busy during initialization" "Memory accepts transfers,Memory controller is busy during initialization"
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bitfld.long 0x0C 0. "MEM_CLR_EN,Memory Contents Initialization enableWriting 1 to MEM_CLR_EN will start memory initialization" "0,1"
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line.long 0x10 "MEM_STA,Memory StatusControls memory initialization"
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abitfld.long 0x10 8.--31. "MEM_STA,Memory Instance StatusThis field gives the current status of each SRAM instance" "0x000000=Instance x is in normal mode,0x000001=Instance x is getting initialized"
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hexmask.long.byte 0x10 0.--7. 1. "RESERVED0,Software should not rely on the value of a reserved"
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tree.end
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tree "TRNG"
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base ad:0x58028000
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rgroup.long 0x00++0x3B
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line.long 0x00 "OUT0,Random Number Lower Word Readout Value"
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line.long 0x04 "OUT1,Random Number Upper Word Readout Value"
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line.long 0x08 "IRQFLAGSTAT,Interrupt Status"
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bitfld.long 0x08 31. "NEED_CLOCK," "0,1"
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hexmask.long 0x08 2.--30. 1. "RESERVED2,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 1. "SHUTDOWN_OVF," "0,1"
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bitfld.long 0x08 0. "RDY," "0,1"
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line.long 0x0C "IRQFLAGMASK,Interrupt Mask"
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hexmask.long 0x0C 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x0C 1. "SHUTDOWN_OVF," "0,1"
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newline
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bitfld.long 0x0C 0. "RDY," "0,1"
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line.long 0x10 "IRQFLAGCLR,Interrupt Flag Clear"
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hexmask.long 0x10 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
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bitfld.long 0x10 1. "SHUTDOWN_OVF," "0,1"
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newline
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bitfld.long 0x10 0. "RDY," "0,1"
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line.long 0x14 "CTL,Control"
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|
abitfld.long 0x14 16.--31. "STARTUP_CYCLES,This field determines the number of samples (between 2^8 and 2^24) taken to gather entropy from the FROs during startup" "0x0000=2^24 samples,0x0001=1*2^8 samples,0x0002=2*2^8 samples,0x0003=3*2^8 samples,0x8000=32768*2^8 samples,0xC000=49152*2^8 samples,0xFFFF=65535*2^8 samplesThis field can only be.."
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rbitfld.long 0x14 11.--15. "RESERVED11,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x14 10. "TRNG_EN," "0,1"
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hexmask.long.byte 0x14 3.--9. 1. "RESERVED3,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 2. "NO_LFSR_FB," "0,1"
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bitfld.long 0x14 1. "TEST_MODE," "0,1"
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newline
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bitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x18 "CFG0,Configuration 0"
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abitfld.long 0x18 16.--31. "MAX_REFILL_CYCLES,This field determines the maximum number of samples (between 2^8 and 2^24) taken to re-generate entropy from the FROs after reading out a 64 bits random number" "0x0000=2^24 samples,0x0001=1*2^8 samples,0x0002=2*2^8 samples,0x0003=3*2^8 samples,0x8000=32768*2^8 samples,0xC000=49152*2^8 samples,0xFFFF=65535*2^8 samplesThis field can only be.."
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rbitfld.long 0x18 12.--15. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x18 8.--11. "SMPL_DIV,This field directly controls the number of clock cycles between samples taken from the FROs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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abitfld.long 0x18 0.--7. "MIN_REFILL_CYCLES,This field determines the minimum number of samples (between 2^6 and 2^14) taken to re-generate entropy from the FROs after reading out a 64 bits random number" "0x00=Minimum samples = MAX_REFILL_CYCLES (all..,0x01=1*2^6 samples,0x02=2*2^6 samples,0xFF=255*2^6 samples"
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|
line.long 0x1C "ALARMCNT,Alarm Control"
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|
rbitfld.long 0x1C 30.--31. "RESERVED30,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
bitfld.long 0x1C 24.--29. "SHUTDOWN_CNT,Read-only indicates the number of '1' bits in ALARMSTOP register.The maximum value equals the number of FROs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
newline
|
|
rbitfld.long 0x1C 21.--23. "RESERVED21,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 16.--20. "SHUTDOWN_THR,Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "ALARM_THR,Alarm detection threshold for the repeating pattern detectors on each FRO"
|
|
line.long 0x20 "FROEN,FRO Enable"
|
|
hexmask.long.byte 0x20 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "FRO_MASK,Enable bits for the individual FROs"
|
|
line.long 0x24 "FRODETUNE,FRO De-tune Bit"
|
|
hexmask.long.byte 0x24 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "FRO_MASK,De-tune bits for the individual FROs"
|
|
line.long 0x28 "ALARMMASK,Alarm Event"
|
|
hexmask.long.byte 0x28 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "FRO_MASK,Logging bits for the 'alarm events' of individual FROs"
|
|
line.long 0x2C "ALARMSTOP,Alarm Shutdown"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED24,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "FRO_FLAGS,Logging bits for the 'alarm events' of individual FROs"
|
|
line.long 0x30 "LFSR0,LFSR Readout Value"
|
|
line.long 0x34 "LFSR1,LFSR Readout Value"
|
|
line.long 0x38 "LFSR2,LFSR Readout Value"
|
|
hexmask.long.word 0x38 17.--31. 1. "RESERVED17,Software should not rely on the value of a reserved"
|
|
hexmask.long.tbyte 0x38 0.--16. 1. "LFSR_80_64,Bits [80:64] of the main entropy accumulation LFSR"
|
|
rgroup.long 0x78++0x07
|
|
line.long 0x00 "HWOPT,TRNG Engine Options Information"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 6.--11. "NR_OF_FROS,Number of FROs implemented in this TRNG value 24 (decimal)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "HWVER0,HW Version 0EIP Number And Core Revision"
|
|
bitfld.long 0x04 28.--31. "RESERVED28,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. "HW_MAJOR_VER,4 bits binary encoding of the major hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x04 20.--23. "HW_MINOR_VER,4 bits binary encoding of the minor hardware revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 16.--19. "HW_PATCH_LVL,4 bits binary encoding of the hardware patch level initial release will carry value zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. "EIP_NUM_COMPL,Bit-by-bit logic complement of bits [7:0]"
|
|
hexmask.long.byte 0x04 0.--7. 1. "EIP_NUM,8 bits binary encoding of the module number"
|
|
rgroup.long 0x1FD8++0x03
|
|
line.long 0x00 "IRQSTATMASK,Interrupt Status After Masking"
|
|
hexmask.long 0x00 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 1. "SHUTDOWN_OVF,Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with IRQFLAGMASK.SHUTDOWN_OVF)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RDY,New random value available (result of IRQFLAGSTAT.RDY AND'ed with IRQFLAGMASK.RDY)" "0,1"
|
|
rgroup.long 0x1FE0++0x03
|
|
line.long 0x00 "HWVER1,HW Version 1TRNG Revision Number"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,The revision number of this module is Rev 2.0"
|
|
group.long 0x1FEC++0x07
|
|
line.long 0x00 "IRQSET,Interrupt Set"
|
|
line.long 0x04 "SWRESET,SW Reset Control"
|
|
hexmask.long 0x04 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 0. "RESET,Write '1' to soft reset reset will be low for 4-5 clock cycles" "0,1"
|
|
rgroup.long 0x1FF8++0x03
|
|
line.long 0x00 "IRQSTAT,Interrupt Status"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STAT,TRNG Interrupt status" "0,1"
|
|
tree.end
|
|
tree "UART"
|
|
repeat 4. (list 0. 1. 2. 3. )(list ad:0x40001000 ad:0x4000B000 ad:0x4000C000 ad:0x4000D000 )
|
|
tree "UART$1"
|
|
base $2
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,DataFor words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1). data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0). data is stored in the transmitter holding register (the bottom.."
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hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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rbitfld.long 0x00 11. "OE,UART Overrun Error:This bit is set to 1 if data is received and the receive FIFO is already full" "0,1"
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newline
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rbitfld.long 0x00 10. "BE,UART Break Error:This bit is set to 1 if a break condition was detected indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits).In FIFO mode.." "0,1"
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newline
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rbitfld.long 0x00 9. "PE,UART Parity Error:When set to 1 it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select.In FIFO mode this error is associated with the character at the top of the FIFO (that is the.." "0,1"
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newline
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rbitfld.long 0x00 8. "FE,UART Framing Error:When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).In FIFO mode this error is associated with the character at the top of the FIFO (that is. the oldest received data.." "0,1"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DATA,Data transmitted or received:On writes the transmit data character is pushed into the FIFO.On reads the oldest received data character since the last read is returned"
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line.long 0x04 "RSR,StatusThis register is mapped to the same address as ECR register"
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hexmask.long 0x04 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 3. "OE,UART Overrun Error:This bit is set to 1 if data is received and the receive FIFO is already full" "0,1"
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newline
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bitfld.long 0x04 2. "BE,UART Break Error:This bit is set to 1 if a break condition was detected indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start data parity and stop bits).When a break.." "0,1"
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newline
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bitfld.long 0x04 1. "PE,UART Parity Error:When set to 1 it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select" "0,1"
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newline
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bitfld.long 0x04 0. "FE,UART Framing Error:When set to 1 it indicates that the received character did not have a valid stop bit (a valid stop bit is 1)" "0,1"
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wgroup.long 0x04++0x03
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line.long 0x00 "ECR,Error ClearThis register is mapped to the same address as RSR register"
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hexmask.long 0x00 4.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 3. "OE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
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newline
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bitfld.long 0x00 2. "BE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
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newline
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bitfld.long 0x00 1. "PE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
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newline
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bitfld.long 0x00 0. "FE,The framing (FE) parity (PE) break (BE) and overrun (OE) errors are cleared to 0 by any write to this register" "0,1"
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repeat 5. (list 0. 2. 1. 3. 4. )(list 0x00 0x14 0x44 0x88 0xFC8 )
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rgroup.long ($2+0x08)++0x03
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line.long 0x00 "RESERVED$1,Software should not rely on the value of a reserved"
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repeat.end
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rgroup.long 0x18++0x03
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line.long 0x00 "FR,FlagReads from this register return the UART flags"
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hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x00 7. "TXFE,UART Transmit FIFO Empty:The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled this bit is set when the transmit holding register is empty. - If the FIFO is enabled this bit is set when the transmit FIFO is empty.This.." "0,1"
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newline
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bitfld.long 0x00 6. "RXFF,UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled this bit is set when the receive holding register is full. - If the FIFO is enabled this bit is set when the receive FIFO is full" "0,1"
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newline
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bitfld.long 0x00 5. "TXFF,UART Transmit FIFO Full:Transmit FIFO full" "0,1"
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newline
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bitfld.long 0x00 4. "RXFE,UART Receive FIFO Empty:Receive FIFO empty" "0,1"
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newline
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bitfld.long 0x00 3. "BUSY,UART Busy: If this bit is set to 1 the UART is busy transmitting data" "0,1"
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newline
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bitfld.long 0x00 1.--2. "RESERVED0,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x00 0. "CTS,Clear To Send: This bit is the complement of the active-low UART CTS input pin.That is the bit is 1 when CTS input pin is LOW" "0,1"
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group.long 0x24++0x27
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line.long 0x00 "IBRD,Integer Baud-Rate DivisorIf this register is modified while transmission or reception is on-going. the baud rate will not be updated until transmission or reception of the current character is complete"
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hexmask.long.word 0x00 16.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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hexmask.long.word 0x00 0.--15. 1. "DIVINT,The integer baud rate divisor:The baud rate divisor is calculated using the formula below:Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)Baud rate divisor must be minimum 1 and maximum 65535"
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line.long 0x04 "FBRD,Fractional Baud-Rate DivisorIf this register is modified while trasmission or reception is on-going. the baudrate will not be updated until transmission or reception of the current character is complete"
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hexmask.long 0x04 6.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x04 0.--5. "DIVFRAC,Fractional Baud-Rate Divisor:The baud rate divisor is calculated using the formula below:Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)Baud rate divisor must be minimum 1 and maximum 65535" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x08 "LCRH,Line Control"
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hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x08 7. "SPS,UART Stick Parity Select:0: Stick parity is disabled1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0).This bit has no effect when PEN disables parity checking and.." "Stick parity is disabled,The parity bit is transmitted and checked as.."
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newline
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bitfld.long 0x08 5.--6. "WLEN,UART Word Length:These bits indicate the number of data bits transmitted or received in a frame" "Word Length 5 bits,Word Length 6 bits,Word Length 7 bits,Word Length 8 bits"
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newline
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bitfld.long 0x08 4. "FEN,UART Enable FIFOs" "FIFOs are disabled (character mode) that is the..,Transmit and receive FIFO buffers are enabled.."
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newline
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bitfld.long 0x08 3. "STP2,UART Two Stop Bits Select:If this bit is set to 1 two stop bits are transmitted at the end of the frame" "0,1"
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newline
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bitfld.long 0x08 2. "EPS,UART Even Parity Select" "Odd parity: The UART generates or checks for an..,Even parity: The UART generates or checks for an.."
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newline
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bitfld.long 0x08 1. "PEN,UART Parity EnableThis bit controls generation and checking of parity bit" "Parity is disabled and no parity bit is added to..,Parity checking and generation is enabled."
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newline
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bitfld.long 0x08 0. "BRK,UART Send BreakIf this bit is set to 1 a low-level is continually output on the UARTTXD output pin after completing transmission of the current character" "0,1"
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line.long 0x0C "CTL,Control"
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hexmask.long.word 0x0C 16.--31. 1. "RESERVED16,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x0C 15. "CTSEN,CTS hardware flow control enable" "CTS hardware flow control disabled,CTS hardware flow control enabled"
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newline
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bitfld.long 0x0C 14. "RTSEN,RTS hardware flow control enable" "RTS hardware flow control disabled,RTS hardware flow control enabled"
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newline
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bitfld.long 0x0C 12.--13. "RESERVED12,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x0C 11. "RTS,Request to SendThis bit is the complement of the active-low UART RTS output" "0,1"
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newline
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bitfld.long 0x0C 10. "RESERVED10,Software should not rely on the value of a reserved" "0,1"
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newline
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bitfld.long 0x0C 9. "RXE,UART Receive EnableIf the UART is disabled in the middle of reception it completes the current character before stopping" "UART Receive disabled,UART Receive enabled"
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newline
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bitfld.long 0x0C 8. "TXE,UART Transmit EnableIf the UART is disabled in the middle of transmission it completes the current character before stopping" "UART Transmit disabled,UART Transmit enabled"
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newline
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bitfld.long 0x0C 7. "LBE,UART Loop Back Enable:Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART" "Loop Back disabled,Loop Back enabled"
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newline
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bitfld.long 0x0C 1.--6. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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newline
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bitfld.long 0x0C 0. "UARTEN,UART Enable" "UART disabled,UART enabled"
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line.long 0x10 "IFLS,Interrupt FIFO Level Select"
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hexmask.long 0x10 6.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x10 3.--5. "RXSEL,Receive interrupt FIFO level select:This field sets the trigger points for the receive interrupt" "Receive FIFO becomes >= 1/8 full,Receive FIFO becomes >= 1/4 full,Receive FIFO becomes >= 1/2 full,Receive FIFO becomes >= 3/4 full,Receive FIFO becomes >= 7/8 full,?,?,?"
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newline
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bitfld.long 0x10 0.--2. "TXSEL,Transmit interrupt FIFO level select:This field sets the trigger points for the transmit interrupt" "Transmit FIFO becomes <= 1/8 full,Transmit FIFO becomes <= 1/4 full,Transmit FIFO becomes <= 1/2 full,Transmit FIFO becomes <= 3/4 full,Transmit FIFO becomes <= 7/8 full,?,?,?"
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line.long 0x14 "IMSC,Interrupt Mask Set/Clear"
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hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x14 11. "EOTIM,End of Transmission interrupt mask" "0,1"
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newline
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bitfld.long 0x14 10. "OEIM,Overrun error interrupt mask" "0,1"
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newline
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bitfld.long 0x14 9. "BEIM,Break error interrupt mask" "0,1"
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newline
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bitfld.long 0x14 8. "PEIM,Parity error interrupt mask" "0,1"
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newline
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bitfld.long 0x14 7. "FEIM,Framing error interrupt mask" "0,1"
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newline
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bitfld.long 0x14 6. "RTIM,Receive timeout interrupt mask" "0,1"
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newline
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bitfld.long 0x14 5. "TXIM,Transmit interrupt mask" "0,1"
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newline
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bitfld.long 0x14 4. "RXIM,Receive interrupt mask" "0,1"
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newline
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bitfld.long 0x14 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
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bitfld.long 0x14 1. "CTSMIM,Clear to Send (CTS) modem interrupt mask" "0,1"
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newline
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bitfld.long 0x14 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
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line.long 0x18 "RIS,Raw Interrupt Status"
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hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x18 11. "EOTRIS,End of Transmission interrupt status: This field returns the raw interrupt state of UART's end of transmission interrupt" "0,1"
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newline
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bitfld.long 0x18 10. "OERIS,Overrun error interrupt status: This field returns the raw interrupt state of UART's overrun error interrupt" "0,1"
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newline
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bitfld.long 0x18 9. "BERIS,Break error interrupt status:This field returns the raw interrupt state of UART's break error interrupt" "0,1"
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newline
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bitfld.long 0x18 8. "PERIS,Parity error interrupt status:This field returns the raw interrupt state of UART's parity error interrupt" "0,1"
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newline
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bitfld.long 0x18 7. "FERIS,Framing error interrupt status:This field returns the raw interrupt state of UART's framing error interrupt" "0,1"
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newline
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bitfld.long 0x18 6. "RTRIS,Receive timeout interrupt status:This field returns the raw interrupt state of UART's receive timeout interrupt" "0,1"
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newline
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bitfld.long 0x18 5. "TXRIS,Transmit interrupt status: This field returns the raw interrupt state of UART's transmit interrupt.When FIFOs are enabled (LCRH.FEN = 1) the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the.." "0,1"
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newline
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bitfld.long 0x18 4. "RXRIS,Receive interrupt status:This field returns the raw interrupt state of UART's receive interrupt" "0,1"
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newline
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bitfld.long 0x18 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
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newline
|
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bitfld.long 0x18 1. "CTSRMIS,Clear to Send (CTS) modem interrupt status: This field returns the raw interrupt state of UART's clear to send interrupt" "0,1"
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newline
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bitfld.long 0x18 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
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line.long 0x1C "MIS,Masked Interrupt Status"
|
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hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
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newline
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bitfld.long 0x1C 11. "EOTMIS,End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM" "0,1"
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newline
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bitfld.long 0x1C 10. "OEMIS,Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM" "0,1"
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newline
|
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bitfld.long 0x1C 9. "BEMIS,Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM" "0,1"
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newline
|
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bitfld.long 0x1C 8. "PEMIS,Parity error masked interrupt status:This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM" "0,1"
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newline
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bitfld.long 0x1C 7. "FEMIS,Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM" "0,1"
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newline
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bitfld.long 0x1C 6. "RTMIS,Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt.The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1)" "0,1"
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newline
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bitfld.long 0x1C 5. "TXMIS,Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM" "0,1"
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newline
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bitfld.long 0x1C 4. "RXMIS,Receive masked interrupt status:This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM" "0,1"
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newline
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bitfld.long 0x1C 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x1C 1. "CTSMMIS,Clear to Send (CTS) modem masked interrupt status:This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM" "0,1"
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newline
|
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bitfld.long 0x1C 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x20 "ICR,Interrupt ClearOn a write of 1. the corresponding interrupt is cleared"
|
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hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED12,Software should not rely on the value of a reserved"
|
|
newline
|
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bitfld.long 0x20 11. "EOTIC,End of Transmission interrupt clear:Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS)" "0,1"
|
|
newline
|
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bitfld.long 0x20 10. "OEIC,Overrun error interrupt clear:Writing 1 to this field clears the overrun error interrupt (RIS.OERIS)" "0,1"
|
|
newline
|
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bitfld.long 0x20 9. "BEIC,Break error interrupt clear:Writing 1 to this field clears the break error interrupt (RIS.BERIS)" "0,1"
|
|
newline
|
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bitfld.long 0x20 8. "PEIC,Parity error interrupt clear:Writing 1 to this field clears the parity error interrupt (RIS.PERIS)" "0,1"
|
|
newline
|
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bitfld.long 0x20 7. "FEIC,Framing error interrupt clear:Writing 1 to this field clears the framing error interrupt (RIS.FERIS)" "0,1"
|
|
newline
|
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bitfld.long 0x20 6. "RTIC,Receive timeout interrupt clear:Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS)" "0,1"
|
|
newline
|
|
bitfld.long 0x20 5. "TXIC,Transmit interrupt clear:Writing 1 to this field clears the transmit interrupt (RIS.TXRIS)" "0,1"
|
|
newline
|
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bitfld.long 0x20 4. "RXIC,Receive interrupt clear:Writing 1 to this field clears the receive interrupt (RIS.RXRIS)" "0,1"
|
|
newline
|
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bitfld.long 0x20 2.--3. "RESERVED2,Software should not rely on the value of a reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 1. "CTSMIC,Clear to Send (CTS) modem interrupt clear:Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS)" "0,1"
|
|
newline
|
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bitfld.long 0x20 0. "RESERVED0,Software should not rely on the value of a reserved" "0,1"
|
|
line.long 0x24 "DMACTL,DMA Control"
|
|
hexmask.long 0x24 3.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x24 2. "DMAONERR,DMA on error" "0,1"
|
|
newline
|
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bitfld.long 0x24 1. "TXDMAE,Transmit DMA enable" "0,1"
|
|
newline
|
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bitfld.long 0x24 0. "RXDMAE,Receive DMA enable" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "UDMA0"
|
|
base ad:0x40020000
|
|
rgroup.long 0x00++0x3F
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 28.--31. "TEST," "Controller does not include the integration test..,Controller includes the integration test logic,Undefined,?,?,?,?,?,?,?,?,?,?,?,?,Undefined"
|
|
hexmask.long.byte 0x00 21.--27. 1. "RESERVED21,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TOTALCHANNELS,Register value returns number of available uDMA channels minus one" "Show that the controller is configured to use 1..,Shows that the controller is configured to use 2..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Shows that the controller is configured to use.."
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "STATE,Current state of the control state machine" "Idle,Reading channel controller data,Reading source data end pointer,Reading destination data end pointer,Reading source data,Writing destination data,Waiting for uDMA request to clear,Writing channel controller data,Stalled,Done,Peripheral scatter-gather transition,Undefined,?,?,?,Undefined"
|
|
bitfld.long 0x00 1.--3. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTERENABLE,Shows the enable status of the controller as configured by CFG.MASTERENABLE:0: Controller is disabled1: Controller is enabled" "Controller is disabled,Controller is enabled"
|
|
line.long 0x04 "CFG,Configuration"
|
|
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED8,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 5.--7. "PRTOCTRL,Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows:Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring.Bit [6] Controls HProt[2] to indicate if a bufferable access is.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 1.--4. "RESERVED1,Software should not rely on the value of a reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0. "MASTERENABLE,Enables the controller:0: Disables the controller1: Enables the controller" "Disables the controller,Enables the controller"
|
|
line.long 0x08 "CTRL,Channel Control Data Base Pointer"
|
|
hexmask.long.tbyte 0x08 10.--31. 1. "BASEPTR,This register point to the base address for the primary data structures of each DMA channel"
|
|
hexmask.long.word 0x08 0.--9. 1. "RESERVED0,Software should not rely on the value of a reserved"
|
|
line.long 0x0C "ALTCTRL,Channel Alternate Control Data Base Pointer"
|
|
line.long 0x10 "WAITONREQ,Channel Wait On Request Status"
|
|
line.long 0x14 "SOFTREQ,Channel Software Request"
|
|
line.long 0x18 "SETBURST,Channel Set UseBurst"
|
|
line.long 0x1C "CLEARBURST,Channel Clear UseBurst"
|
|
line.long 0x20 "SETREQMASK,Channel Set Request Mask"
|
|
line.long 0x24 "CLEARREQMASK,Clear Channel Request Mask"
|
|
line.long 0x28 "SETCHANNELEN,Set Channel Enable"
|
|
line.long 0x2C "CLEARCHANNELEN,Clear Channel Enable"
|
|
line.long 0x30 "SETCHNLPRIALT,Channel Set Primary-Alternate"
|
|
line.long 0x34 "CLEARCHNLPRIALT,Channel Clear Primary-Alternate"
|
|
line.long 0x38 "SETCHNLPRIORITY,Set Channel Priority"
|
|
line.long 0x3C "CLEARCHNLPRIORITY,Clear Channel Priority"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ERROR,Error Status and Clear"
|
|
hexmask.long 0x00 1.--31. 1. "RESERVED,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "STATUS,Returns the status of bus error flag in uDMA or clears this bit Read as:0: No bus error detected1: Bus error detectedWrite as:0: No effect status of bus error flag is unchanged.1: Clears the bus error flag" "No effect status of bus error flag is unchanged,Clears the bus error flag"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "REQDONE,Channel Request Done"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "DONEMASK,Channel Request Done Mask"
|
|
tree.end
|
|
tree "VIMS"
|
|
base ad:0x40034000
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "STAT,StatusDisplays current VIMS mode and line buffer status"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 5. "IDCODE_LB_DIS,Icode/Dcode flash line buffer status0: Enabled or in transition to disabled1: Disabled and flushed" "Enabled or in transition to disabled,Disabled and flushed"
|
|
newline
|
|
bitfld.long 0x00 4. "SYSBUS_LB_DIS,Sysbus flash line buffer control0: Enabled or in transition to disabled1: Disabled and flushed" "Enabled or in transition to disabled,Disabled and flushed"
|
|
bitfld.long 0x00 3. "MODE_CHANGING,VIMS mode change status0: VIMS is in the mode defined by MODE1: VIMS is in the process of changing to the mode given in CTL.MODE" "VIMS is in the mode defined by MODE,VIMS is in the process of changing to the mode.."
|
|
newline
|
|
bitfld.long 0x00 2. "INV,This bit is set when invalidation of the cache memory is active / ongoing" "0,1"
|
|
bitfld.long 0x00 0.--1. "MODE,Current VIMS mode" "VIMS GPRAM mode,VIMS Cache mode,?,VIMS Off mode"
|
|
line.long 0x04 "CTL,ControlConfigure VIMS mode and line buffer settings"
|
|
bitfld.long 0x04 31. "STATS_CLR,Set this bit to clear statistic counters" "0,1"
|
|
bitfld.long 0x04 30. "STATS_EN,Set this bit to enable statistic counters" "0,1"
|
|
newline
|
|
bitfld.long 0x04 29. "DYN_CG_EN," "0,1"
|
|
hexmask.long.tbyte 0x04 6.--28. 1. "RESERVED6,Software should not rely on the value of a reserved"
|
|
newline
|
|
bitfld.long 0x04 5. "IDCODE_LB_DIS,Icode/Dcode flash line buffer control0: Enable1: Disable" "Enable,Disable"
|
|
bitfld.long 0x04 4. "SYSBUS_LB_DIS,Sysbus flash line buffer control0: Enable1: Disable" "Enable,Disable"
|
|
newline
|
|
bitfld.long 0x04 3. "ARB_CFG,Icode/Dcode and sysbus arbitation scheme0: Static arbitration (icode/docde > sysbus)1: Round-robin arbitration" "Static arbitration (icode/docde > sysbus),Round-robin arbitration"
|
|
bitfld.long 0x04 2. "PREF_EN,Tag prefetch control0: Disabled1: Enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0.--1. "MODE,VIMS mode request.Write accesses to this field will be blocked while STAT.MODE_CHANGING is set to 1" "VIMS GPRAM mode,VIMS Cache mode,?,VIMS Off mode"
|
|
tree.end
|
|
tree "WDT"
|
|
base ad:0x40080000
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "LOAD,Configuration"
|
|
line.long 0x04 "VALUE,Current Count Value"
|
|
line.long 0x08 "CTL,Control"
|
|
hexmask.long 0x08 3.--31. 1. "RESERVED3,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x08 2. "INTTYPE,WDT Interrupt Type0: WDT interrupt is a standard interrupt" "WDT interrupt is a standard interrupt,WDT interrupt is a non-maskable interrupt"
|
|
newline
|
|
bitfld.long 0x08 1. "RESEN,WDT Reset Enable" "Disabled,Enable the Watchdog.."
|
|
bitfld.long 0x08 0. "INTEN,WDT Interrupt Enable0: Interrupt event disabled" "Interrupt event disabled,Interrupt event enabled"
|
|
line.long 0x0C "ICR,Interrupt Clear"
|
|
line.long 0x10 "RIS,Raw Interrupt Status"
|
|
hexmask.long 0x10 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x10 0. "WDTRIS,This register is the raw interrupt status register" "The WDT has not timed out,A WDT time-out event has occurred"
|
|
line.long 0x14 "MIS,Masked Interrupt Status"
|
|
hexmask.long 0x14 1.--31. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x14 0. "WDTMIS,This register is the masked interrupt status register" "The WDT has not timed out or is masked,An unmasked WDT time-out event has occurred"
|
|
group.long 0x418++0x07
|
|
line.long 0x00 "TEST,Test Mode"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED9,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 8. "STALL,WDT Stall Enable0: The WDT timer continues counting if the CPU is stopped with a debugger.1: If the CPU is stopped with a debugger the WDT stops counting" "The WDT timer continues counting if the CPU is..,If the CPU is stopped with a debugger the WDT.."
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "RESERVED1,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x00 0. "TEST_EN,The test enable bit" "Enable external reset,Disables the generation of an external reset"
|
|
line.long 0x04 "INT_CAUS,Interrupt Cause Test Mode"
|
|
hexmask.long 0x04 2.--31. 1. "RESERVED2,Software should not rely on the value of a reserved"
|
|
bitfld.long 0x04 1. "CAUSE_RESET,Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set)" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. "CAUSE_INTR,Replica of RIS.WDTRIS" "0,1"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "LOCK,Lock"
|
|
tree.end
|
|
endif
|
|
autoindent.off
|
|
newline
|